PCB defect identification method based on YOLOv8 model

Abstract

The invention discloses a PCB defect identification method based on a YOLOv8 model. The method comprises the following steps: S1, obtaining a to-be-identified image set; s2, a YOLOv8 model is improved, wherein the YOLOv8 model comprises a Backbone network, a Neck network and a Head network which are connected in sequence; the improved method is based on a BiFPN bidirectional feature pyramid network, a P2 feature layer is integrated on the basis of the BiFPN bidirectional feature pyramid network so as to improve the detection precision of a small target, and convolution modification network connection suitable for YOLOv8 is adopted; according to the method, a TA (Convolutional Triplet Attention Module) layer is introduced, so that the recognition accuracy of the model is improved; a brand-new CSC module is designed to replace part of C2f modules, model parameter redundancy is reduced, and therefore a target can be located more rapidly and more accurately. S3, training the improved YOLOv8 model by adopting an image set to be recognized; and S4, inputting a to-be-detected image into the improved YOLOv8 model obtained by training to obtain a PCB defect identification result. According to the method, the YOLOv8 model is used as a basic recognition network, the network model structure is improved, and the detection precision of the YOLOv8 model is improved.

Description

Technical Field

[0001] The present invention relates to the field of image technology, and in particular to a PCB defect recognition method based on a YOLOv8 model. Background Art

[0002] As one of the fastest growing branches in the field of image processing, object recognition has been successfully applied to recognition tasks in a variety of scenarios. However, the manufacturing process of printed circuit boards is complex and prone to small but important defects. Therefore, effective detection of PCB defects is particularly necessary. However, the YOLO model performs poorly in detecting small PCB defects and has low defect recognition accuracy. Summary of the invention

[0003] In view of the above-mentioned shortcomings of the prior art, the present invention provides a PCB defect recognition method based on the YOLOv8 model, which uses the YOLOv8 network as the basic recognition network and improves its network model structure, thereby improving the detection accuracy of the YOLOv8 model.

[0004] To achieve the above effects, the technical solution of the present invention is as follows:

[0005] In a first aspect, the present invention provides a PCB defect recognition method based on a YOLOv8 model, comprising the following steps:

[0006] S1: Obtain the image set to be identified;

[0007] S2: improving the YOLOv8 model, wherein the improved YOLOv8 model includes a Backbone network, a Neck network, and a Head network connected in sequence;

[0008] In the Backbone network, the CSC module is used to replace the C2f module, and the P2 layer output is added to the Neck and Head networks of the YOLOv8 model as a small target detection layer; in the feature enhancement stage of the Neck, the small target detection layer performs multi-scale feature fusion with the feature map output by the P3-P5 layers, and the enhanced feature map of 160×160×64 size is input to the Head detection head;

[0009] The CSC module uses the S-Bottlencek module to replace the original Bottleneck module of the YOLOv8 model. Specifically, the CSC module is as follows: the feature map of the Backbone network is divided into a feature map X1 and a feature map X2 of size 1 / 2C along the channel dimension through the split layer. The kernel sizes of the feature map X1 are 3×3 and 5×5 respectively. The feature map X1 passes through the S-Bottleneck module and the BN batch normalization layer respectively, and then is fused through the Concat module, and then passes through the ReLU activation function to obtain the first output feature; the feature map X2 passes through two sequentially connected S-Bottleneck modules to obtain the second output feature; the first output feature and the second output feature are fused and then pass through a 1×1 convolution to obtain the output feature of the CSC module;

[0010] Add a TA layer between the CSC module in the Backbone network and the Neck network;

[0011] S3: Use the image set to be identified to train the improved YOLOv8 model;

[0012] S4: Input the image to be tested into the trained improved YOLOv8 model to obtain the PCB defect recognition result.

[0013] Further, the printed circuit board defect dataset PKU-Market-PCB is preprocessed to obtain a processed printed circuit board defect dataset PKU-Market-PCB, and the printed circuit board defect dataset PKU-Market-PCB is divided into a training set, a test set and a validation set in a ratio of 8:1:1.

[0014] Furthermore, the image preprocessing of the printed circuit board defect dataset PKU-Market-PCB is specifically performed as follows:

[0015] The duplicate images of the printed circuit board defect dataset PKU-Market-PCB are removed, and the remaining printed circuit board defect images are adjusted for brightness, rotation, cropping, translation, and mirroring to obtain the processed printed circuit board defect dataset PKU-Market-PCB.

[0016] Furthermore, the S-Bottleneck module includes a first convolution SCConv and a second convolution SCConv connected in sequence;

[0017] The output features of the first convolution SCConv, the output features of the second convolution SCConv, and the input features of the S-Bottleneck module are element-wise added to form the output features of the S-Bottleneck module.

[0018] Furthermore, the TA layer is specifically:

[0019] Add a TA layer between C2f and Neck network in the Backbone network;

[0020] The TA layer expression is:

[0021] Z-Pool = [AvgPool 0d (x),MaxPool(x)]

[0022] Ms(X1)=σ{f 7×7 [AvgPool(X1);MaxPool(X1)]}

[0023] Ms(X2)=σ{f 7×7 [AvgPool(X2);MaxPool(X2)]}

[0024] Ms(X3)=σ{f 7×7 [AvgPool(X3);MaxPool(X3)]}

[0025]

[0026] X1, X2, and X3 are the input feature maps of the three branches, and Y is the average operation aggregation of the output results.

[0027] Furthermore, step S2 further includes:

[0028] Using the BiFPN module, additional skip connection edges and Concat modules are added to the original PAN structure, links from P3 to P3, P4 to P4, and P5 to P5 are added, and additional information transmission is added between different layers.

[0029] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0030] The present invention improves the YOLOv8 model, integrates the P2 feature layer on the basis of BiFPN to improve the detection accuracy of small targets, adds convolution and modifies the network connection; and adds the TA layer to improve the model recognition accuracy; secondly, designs the CSC module to replace part of the C2f module to reduce the model parameter redundancy, so that the YOLOv8 model can locate PCB defect targets faster and more accurately. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a flow chart of the target recognition method based on the YOLOv8 model of the present invention;

[0032] Figure 2The improved YOLOv8 model structure block diagram provided by the embodiment of the present invention;

[0033] Figure 3 An S-Bottlenck structure diagram provided for an embodiment of the present invention;

[0034] Figure 4 The SCConv layer provided by the example of the present invention;

[0035] Figure 5 A TA layer provided by an embodiment of the present invention;

[0036] Figure 6 A BiFPN module provided by an embodiment of the present invention;

[0037] Figure 7 A CSC structure provided by an embodiment of the present invention;

[0038] Figure 8 mAP_50 curve graphs of the improved YOLOv8 model and the unimproved YOLOv8 model provided in the embodiments of the present invention;

[0039] Fig. 9 A graph of an improved YOLOv8 model and an unimproved YOLOv8 model provided in an embodiment of the present invention; DETAILED DESCRIPTION

[0040] The following will describe the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention, not for limiting the scope of protection of the present invention.

[0041] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0042] Example

[0043] This embodiment proposes a method. Figure 1 , a PCB defect recognition method based on the YOLOv8 model, comprising the following steps:

[0044] S1: Obtain the image set to be identified;

[0045] S2: improving the YOLOv8 model, wherein the improved YOLOv8 model includes a Backbone network, a Neck network, and a Head network connected in sequence;

[0046] In the Backbone network, the CSC module is used to replace the C2f module to reduce model parameter redundancy, thereby locating the target more quickly and accurately; the Conv layer is added before the Backbone network enters the Neck network, and the P2 layer output is added to the Neck and Head networks of the YOLOv8 model as a small target detection layer; in the feature enhancement stage of the Neck neck, the small target detection layer performs multi-scale feature fusion with the feature map output by the P3-P5 layers, and the enhanced feature map of 160×160×64 size is input to the Head detection head;

[0047] like Figure 7 , the CSC module uses the S-Bottlencek module to replace the original Bottleneck module of the YOLOv8 model, and one of the S-Bottlenneck modules is moved to the branch connecting the split layer and Concat. The CSC module is specifically as follows: the feature map of the Backbone network is divided into a feature map X1 and a feature map X2 of size 1 / 2C along the channel dimension through the split layer. The kernel sizes of the feature map X1 are 3×3 and 5×5 respectively. The feature map X1 passes through the S-Bottleneck module and the BN batch normalization layer and is fused through the Concat module, and then passes through the ReLU activation function to obtain the first output feature; the feature map X2 passes through two sequentially connected S-Bottleneck modules to obtain the second output feature; the first output feature and the second output feature are fused and then pass through a 1×1 convolution to obtain the output feature of the CSC module;

[0048] Add a TA layer (Convolutional Triplet Attention Module) between the CSC module in the Backbone network and the Neck network;

[0049] S3: Use the image set to be identified to train the improved YOLOv8 model;

[0050] S4: Input the image to be tested into the trained improved YOLOv8 model to obtain the PCB defect recognition result.

[0051] The improved YOLOv8 model is based on the BiFPN bidirectional feature pyramid network, integrates the P2 feature layer to improve the detection accuracy of small targets, and uses convolutions suitable for YOLOv8 to modify the network connection.

[0052] As a preferred technical solution, in this embodiment, the image set to be identified is a printed circuit board defect data set PKU-Market-PCB, the printed circuit board defect data set PKU-Market-PCB is preprocessed to obtain a processed printed circuit board defect data set PKU-Market-PCB, and the printed circuit board defect data set PKU-Market-PCB is divided into a training set, a test set and a validation set in a ratio of 8:1:1.

[0053] As a preferred technical solution, in this example, the image preprocessing of the printed circuit board defect dataset PKU-Market-PCB is specifically as follows:

[0054] The duplicate images of the printed circuit board defect dataset PKU-Market-PCB are removed, and the remaining printed circuit board defect images are adjusted for brightness, rotation, cropping, translation, and mirroring to obtain the processed printed circuit board defect dataset PKU-Market-PCB.

[0055] It should be noted that, in this embodiment, the defect categories are: missing hole, mouse bite, open circuit, short circuit, spur and spurious copper; the improved YOLOv5 model network is trained in the PyTorch environment, with a learning rate of 0.001, 300 training rounds, and a batch_size value of 8; the final training mAP can reach 0.987, achieving an improvement in the performance of the improved YOLOv8 model.

[0056] As a preferred technical solution, in this embodiment, the S-Bottleneck module includes a first convolution SCConv (i.e., spatial and channel reconstruction convolution) and a second convolution SCConv connected in sequence;

[0057] The output features of the first convolution SCConv, the output features of the second convolution SCConv, and the input features of the S-Bottleneck module are element-wise added to form the output features of the S-Bottleneck module.

[0058] It is understandable that the S-Bottleneck module can promote the model's learning of complex features. On the basis of retaining the original structure, an additional path is added. This new path further promotes the information interaction and fusion between features, enabling the model to more accurately capture features of different scales and levels, thereby significantly enhancing the feature expression ability.

[0059] As a preferred technical solution, in this embodiment, the TA layer is calculated by the following steps:

[0060] Initialize a feature map X with a scale of H*W*C, and transpose the feature map X in three dimensions of H, W, and C to obtain feature maps X1, X2, and X3. The scales of the three feature maps are H*W*C, W*H*C, and C*H*W respectively;

[0061] Input the three feature maps into the processing module and output different feature maps;

[0062] Transpose the output feature maps. The scales of the three feature maps after transposition are all H*W*C.

[0063] The transposed feature maps are multiplied by a coefficient of 1 / 3. The operation process is expressed as:

[0064]

[0065] In the formula, X1, X2, and X3 are the input feature maps of the three branches of the TA layer respectively, Y is the output result of the TA layer (the average operation aggregation of the output results), σ represents the sigmoid activation layer, Represents the processing modules corresponding to the input feature maps X1, X2, and X3.

[0066] Specifically, the TA layer has 3 branches, which calculate the relationship between H and W, H and C, and W and C respectively. Taking one branch as an example, the size of the input X is C×H×W, and the size of the feature map X1 obtained after transposition is W×H×C. The tensor obtained after X1 passes through the function is then element-wise multiplied with the feature map X1. It contains three sub-functions, namely Z-Pool and Convolution-Normalization-Sigmod activation layer. The Z-Pool function operates on the 0th dimension of the input feature map, and the expression is:

[0067] The processing module includes a Z-Pool function, and the expression of Z-Pool is:

[0068] Z-Pool = [AvgPool 0d (x),MaxPool(x)]

[0069] Where Z-Pool represents the concatenation of the Z-Pool function in the first dimension of the input feature map, and AvgPool 0d and MaxPool 0d Represents the average pooling layer and the maximum pooling layer respectively. The maximum pooling layer MaxPool and the average pooling layer AvgPool are respectively

[0070] The two tensors are then concatenated as the output of Z-Pool. Through two pooling operations, the TA layer can obtain rich feature information and significantly reduce the depth of the feature map (C×H×W→2×H×W), with minimal increase in the number of parameters.

[0071] In the TA layer expression:

[0072] Ms(X1)=σ{f 7×7 [AvgPool(X1);MaxPool(X1)]}

[0073] Ms(X2)=σ{f 7×7 [AvgPool(X2);MaxPool(X2)]}

[0074] Ms(X3)=σ{f 7×7 [AvgPool(X3);MaxPool(X3)]}.

[0075] As a preferred technical solution, in this embodiment, step S2 further includes:

[0076] Using the BiFPN module, additional skip connection edges and Concat modules are added to the original PAN structure, links from P3 to P3, P4 to P4, and P5 to P5 are added, and additional information transmission is added between different layers.

[0077] Furthermore, before inputting the images of the to-be-recognized image set into the improved YOLOv8 model for target detection, the method further includes: converting a label file in the .xml format in the to-be-recognized image set into a label file in the .txt format.

[0078] It is understandable that the Triplet mechanism innovatively introduces the concept of cross-dimensional interaction, which significantly improves this shortcoming by capturing the interaction between the input tensor in the spatial dimension and the channel dimension. Different branches can obtain feature representations of different levels and dimensions. Shallow features have more detailed information, while deep features contain more semantic information. In object detection, simple concatenation or summation of feature fusion will lose some detailed information. Comprehensively utilizing the different feature information extracted by the three branches allows the model to have more parameter sharing and constraints, thereby improving the robustness of the model.

[0079] Specifically, the size of the image set to be identified is 640×640×3; the Backbone network includes two Conv layers, a first CSC module, a third Conv layer, a second CSC module, a fourth Conv layer, a third CSC module, a fifth Conv layer, a fourth CSC module, and a first pyramid pooling module SPPF, which are connected in sequence. The output end of the SPPF module is connected to the input end of the fourth convolution CSC module;

[0080] Among them, the CSC module is used to extract features from the printed circuit board image set to be identified to obtain a feature map; the convolution Conv layer performs a convolution operation on the feature image to learn local feature information; the SPPF module (i.e., the receptive field expansion module) is used to expand the receptive field range of the feature map.

[0081] The Neck network includes a first TA module, a sixth Conv layer, a first upsampling module upsample, a second TA module, a seventh Conv layer, a first fusion module concat, a first C2f module, a second upsampling module upsample, a third TA module, an eighth Conv layer, a second fusion module concat, a second C2f module, a third upsampling module upsample, a fourth TA module, a ninth Conv layer, a third fusion module concat, a third C2f module, a tenth Conv layer, a fourth fusion module concat, a fourth C2f module, an eleventh Conv layer, a fifth fusion module concat, a fifth C2f module, a twelfth Conv layer, a sixth fusion module concat, and a sixth C2f module, which are connected in sequence; the third C2f module is connected to the input end of the first Detect module, the output end of the fourth C2f module is connected to the input end of the second Detect module, the output end of the fifth C2f module is connected to the input end of the third Detect module, and the output end of the sixth C2f module is connected to the input end of the fourth Detect module;

[0082] The first upsampling module upsample is used to increase the resolution of input data, amplify low-resolution feature maps or data to higher resolution, extract more detailed information or generate higher-resolution output. The first fusion module concat is used to fuse the feature map output by the seventh Conv layer and the upsampled feature map output by the first upsampling module upsample; the second fusion module concat is used to fuse the feature map output by the eighth Conv layer and the upsampled feature map output by the second upsampling module upsample; the third fusion module concat is used to fuse the feature map output by the ninth Conv layer, the upsampled feature map output by the third upsampling module upsample and the feature map output by the fourth attention mechanism TA; the fourth fusion module concat is used to fuse the feature map output by the tenth Conv layer and the feature map output by the eighth Conv layer; the fifth fusion module concat is used to fuse the feature map output by the eleventh Conv layer and the feature map output by the seventh Conv layer; the fourth fusion module concat is used to fuse the feature map output by the twelfth Conv layer and the feature map output by the sixth Conv layer; the SPPF module can aggregate deep semantic information on a larger receptive field, and can adaptively design and reconstruct the kernel according to the content information on the specific feature map to realize upsampling processing of the feature map. The sizes of the output feature maps of the seventh Conv layer, the first upsampling module upsample, the eighth Conv layer, the second upsampling module upsample, the ninth Conv layer, the third upsampling module upsample, the fourth attention mechanism TA, the tenth Conv layer, the eighth Conv layer, the eleventh Conv layer, the seventh Conv layer, the twelfth Conv layer, and the sixth Conv layer are 40×40×256, 40×40×256, 80×80×128, 80×80×128, 160×160×64, 160×160×64, 160×160×64, 160×160×64, 160×160×64, 80×80×128, 80×80×128, 40×40×256, 40×40×256, 20×20×512, and 20×20×512, respectively.

[0083] The multi-branch CSC module is used to perform deep feature extraction on the feature map; the attention mechanism TA is used to extract the target position information from the feature map.

[0084] like Figure 6, an upsampling process is added to the Neck network of YOLOv8, and the original FPN and PAN structures of the Neck network in YOLOv8 are replaced with BiFPN structures. The improved feature fusion network adds an upsampling process and introduces the weighted bidirectional feature pyramid network (BiFPN) into the Neck network part of the YOLOv8 model, replacing the original Concat module with the BiFPN module; BiFPN is a weighted feature fusion mechanism that assigns a learnable weight to each path, and continuously updates the weight by learning data features to obtain more important information, and further enhances the network feature fusion capability through learnable weights.

[0085] It is worth noting that existing feature fusion methods usually use the same weight to weight feature maps of different scales. When the resolution of the input feature map is different, using the same weight for weighting may lead to uneven output feature maps. BiFPN considers the importance of different input features and uses different weights for feature fusion. By repeatedly applying this structure, feature fusion is enhanced, thereby more effectively processing input feature maps of different resolutions. BiFPN is a bidirectional feature pyramid network. In computer vision, this neural network architecture is widely used in target detection and segmentation tasks. You can refer to Figure 6 , Figure 6 The figure is a schematic diagram of the BiFPN network structure of the present invention. The weighted fusion method in the BiFPN structure adopts fast normalized fusion, which is proposed for the slow training speed. The weight is scaled to the range of 0 to 1. Since the Softmax method is not used, the training speed is very fast. The cross-scale connection is realized by adding a skip connection and a bidirectional path, thus realizing weighted fusion and bidirectional cross-scale connection.

[0086] The Head network includes a branch consisting of a first CBS module and a first Conv2d module and a branch consisting of a second CBS module and a second Conv2d module;

[0087] In order to better describe the performance of the improved YOLOv7 model, the evaluation indicators are composed of Precision (P), Recall (R), Average Precision (AP), Mean Average Precision (mAP) and PR curve.

[0088]

[0089]

[0090] Among them, TP represents the number of target boxes that correctly identify PCB defects, FP represents the number of target boxes that mistakenly identify other categories as PCB defects, FN represents the number of target boxes that mistakenly identify PCB defects as other categories, P represents the ratio of target boxes correctly identified as PCB defects to all target boxes identified as PCB defects, and R represents the ratio of target boxes correctly identified as PCB defects to all target boxes of PCB defects; AP represents the average accuracy of each category, which is calculated by the area enclosed by the curve in the PR curve and the horizontal and vertical coordinates; mAP is obtained by averaging the APs of n categories, where n represents the number of categories; mAP represents the average precision of all categories, which can be used to judge the performance improvement of the improved model.

[0091] Attached Figure 8 : This is the map-50 curve of the improved YOLOv8 model and the YOLOv8 before improvement in this embodiment. It can be seen that the map-50 value of the improved YOLOv8 is increased by 2.9% compared with the YOLOv8 before improvement. Fig. 9 The precision curve of the improved YOLOv8 model in this embodiment and the YOLOv8 before the improvement shows that the precision value of the improved YOLOv8 is improved by 2.2% compared with the YOLOv8 before the improvement.

[0092] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A PCB defect recognition method based on the YOLOv8 model, characterized in that: The following steps are involved: S1: Obtain the image set to be identified; S2: improving the YOLOv8 model, wherein the improved YOLOv8 model includes a Backbone network, a Neck network, and a Head network connected in sequence; In the Backbone network, the CSC module is used to replace the C2f module, and the P2 layer output is added to the Neck and Head networks of the YOLOv8 model as a small target detection layer; in the feature enhancement stage of the Neck, the small target detection layer performs multi-scale feature fusion with the feature map output by the P3-P5 layers, and the enhanced feature map of 160×160×64 size is input to the Head detection head; The CSC module uses the S-Bottlencek module to replace the original Bottleneck module of the YOLOv8 model. The CSC module is specifically as follows: the feature map of the Backbone network is divided into a feature map X1 and a feature map X2 of size 1 / 2C along the channel dimension through the split layer. The kernel sizes of the feature map X1 are 3×3 and 5×5 respectively. The feature map X1 is fused through the Concat module after passing through the S-Bottleneck module and the BN batch normalization layer, and then through the ReLU activation function to obtain the first output feature; The feature map X2 passes through two S-Bottleneck modules connected in sequence to obtain the second output feature; The first output feature is fused with the second output feature and then goes through a 1×1 convolution to obtain the output feature of the CSC module; Add a TA layer between the CSC module in the Backbone network and the Neck network; S3: Use the image set to be identified to train the improved YOLOv8 model; S4: Input the image to be tested into the trained improved YOLOv8 model to obtain the PCB defect recognition result.

2. According to the PCB defect recognition method based on the YOLOv8 model of claim 1, it is characterized in that: The image set to be identified is a printed circuit board defect data set PKU-Market-PCB. The printed circuit board defect data set PKU-Market-PCB is preprocessed to obtain a processed printed circuit board defect data set PKU-Market-PCB. The printed circuit board defect data set PKU-Market-PCB is divided into a training set, a test set and a validation set in a ratio of 8:1:

1.

3. According to the PCB defect recognition method based on the YOLOv8 model described in claim 2, it is characterized in that: The printed circuit board defect dataset PKU-Market-PCB is subjected to image preprocessing, specifically: The duplicate images in the printed circuit board defect dataset PKU-Market-PCB are removed, and the remaining printed circuit board defect images are adjusted in brightness, rotated, cropped, translated and mirrored to obtain the processed printed circuit board defect dataset PKU-Market-PCB.

4. According to the PCB defect recognition method based on the YOLOv8 model of claim 1, it is characterized in that: The S-Bottleneck module includes a first convolution SCConv and a second convolution SCConv connected in sequence; The output features of the first convolution SCConv, the output features of the second convolution SCConv, and the input features of the S-Bottleneck module are element-wise added to form the output features of the S-Bottleneck module.

5. According to the PCB defect recognition method based on the YOLOv8 model of claim 1, it is characterized in that: The TA layer is calculated by the following steps: Initialize a feature map X with a scale of H*W*C, and transpose the feature map X in three dimensions of H, W, and C to obtain feature maps X1, X2, and X3. The scales of the three feature maps are H*W*C, W*H*C, and C*H*W respectively; Input the three feature maps into the processing module and output different feature maps; The feature maps are multiplied by a coefficient of 1 / 3. The operation process is expressed as: In the formula, X1, X2, and X3 are the input feature maps of the three branches of the TA layer respectively, Y is the output result of the TA layer, and σ represents the sigmoid activation layer. Represents the processing modules corresponding to the input feature maps X1, X2, and X3.

6. According to the PCB defect recognition method based on the YOLOv8 model of claim 5, it is characterized in that: The processing module includes a Z-Pool function, and the expression of Z-Pool is: Z-Pool=[AvgPool 0d (x),MaxPool(x)] Where Z-Pool represents the concatenation of the Z-Pool function in the first dimension of the input feature map, and AvgPool 0d and MaxPool 0d They represent the average pooling layer and the maximum pooling layer respectively.

7. According to the PCB defect recognition method based on the YOLOv8 model of claim 1, it is characterized in that: Step S2 also includes: Using the BiFPN module, additional skip connection edges and Concat modules are added to the original PAN structure, links from P3 to P3, P4 to P4, and P5 to P5 are added, and additional information transmission is added between different layers.

Images