Wafer-level line width standard sheet based on electron beam exposure HSQ and preparation method

Abstract

The invention discloses a wafer-level line width standard sheet based on electron beam exposure HSQ and a preparation method thereof, and the method comprises the following steps: firstly, employing a silicon wafer with a polished single surface as a substrate material; secondly, HSQ photoresist is coated on the substrate material obtained in the step S1 in a spin coating mode; thirdly, carrying out electron beam exposure on the HSQ photoresist through an electron beam lithography machine according to preset line widths with different feature sizes and tracking mark patterns; and finally, defining the HSQ photoresist on the silicon wafer through developing and fixing processes to obtain the wafer-level line width standard sheet. According to the wafer-level line width standard sheet based on electron beam exposure HSQ and the preparation method, oxidation resistance, water absorption resistance and high stability are achieved, extra silicon window opening and nesting processes are not needed, a line width structure and a tracking mark pattern can be prepared at the same time, operation is easy, positioning and marking are accurate, the development cost is saved, and the production efficiency is improved. And the problem that wafer-level automatic calibration is difficult to realize by micro-nano detection equipment is effectively solved.

Description

Technical Field

[0001] The invention relates to the technical field of micro-nanometer measuring instrument metrology, and in particular to a wafer-level line width standard sheet based on electron beam exposure HSQ and a preparation method thereof. Background Art

[0002] As the integrated circuit industry continues to advance towards more advanced manufacturing, the requirements for the accuracy and stability of micro-nano detection equipment serving integrated circuits continue to rise. Critical Dimension (CD) refers to a special line pattern that reflects the width of characteristic lines designed to evaluate and control the image processing accuracy of the process in photolithography mask manufacturing and photolithography processes. In short, the critical dimension is the lines of different widths in an integrated circuit, which is an important measure of the level of integrated circuit manufacturing and design.

[0003] The smaller the critical dimension, the higher the integration of the chip. The calibration of critical dimension measuring instruments requires line width standards of different widths, especially for the current advanced process, which requires wafer-level line width standards. Therefore, many research institutions at home and abroad have carried out the development of related line width standards.

[0004] In the prior art, the mainstream line width standard film is prepared by using a multilayer film combined with wet etching. However, this method is mainly used to realize chip-level line width standard films. To realize wafer-level line width standard films, it is necessary to first etch a recessed area on the silicon wafer and then nest the chip line width standard film into it to form a wafer-level line width standard film, but this will introduce new problems such as nesting flatness and firmness. At the same time, the preparation of tracking marks and chip line width standard films and nesting processes need to be carried out step by step, which greatly increases the complexity of the process and increases a lot of costs.

[0005] Therefore, in order to serve the calibration business of wafer-level detection equipment, it is crucial to develop a method that can efficiently and low-costly produce wafer-level line width standards based on the detection efficiency and production environment of integrated circuit production lines. Summary of the invention

[0006] The purpose of the present invention is to provide a wafer-level line width standard sheet and a preparation method based on electron beam exposure HSQ, which has oxidation resistance, water absorption resistance and high stability, does not require additional silicon window opening and nesting processes, can simultaneously prepare line width structures and tracking mark graphics, is simple to operate, has accurate positioning marks, saves research and development costs, and effectively solves the problem that micro-nano detection equipment is difficult to achieve wafer-level automatic calibration.

[0007] To achieve the above object, the present invention provides a method for preparing a wafer-level line width standard film based on electron beam exposure HSQ, comprising the following steps:

[0008] S1, using single-side polished silicon wafer as substrate material;

[0009] S2, coating HSQ photoresist on the substrate material obtained in step S1 by spin coating;

[0010] S3, performing electron beam exposure on the HSQ photoresist by an electron beam lithography machine according to preset line widths and tracking mark patterns of different feature sizes;

[0011] S4. Through the development and fixing processes, the HSQ photoresist is defined on the silicon wafer to obtain a wafer-level line width standard film.

[0012] Preferably, in step S1, the single-side polished silicon wafer is cleaned and dried.

[0013] Preferably, in step S2, the substrate material coated with the HSQ photoresist is baked.

[0014] Preferably, in step S3, the high voltage of the electron beam lithography machine is 50 kV-100 kV, the maximum scanning frequency is 50 MHz-125 MHz, and the beam current range is 1 nA-20 nA.

[0015] Preferably, in step S3, the tracking mark is drawn by three-dimensional drawing software and outputted in a GDS format file.

[0016] Preferably, the three-dimensional drawing software is L-edit software or AutoCAD software.

[0017] Preferably, in step S3, the line widths of the different characteristic sizes are 22 nm, 50 nm, 100 nm and 200 nm.

[0018] Preferably, in step S4, the developing and fixing process is specifically:

[0019] The exposed HSQ photoresist and substrate material are placed in a developer to react, and after the reaction is completed, they are placed in a fixer to react, so that the HSQ photoresist is defined on the silicon wafer.

[0020] Preferably, the developer is a tetramethylammonium hydroxide solution with a concentration of 2.38%-25%.

[0021] To achieve the above objectives, the present invention also provides a wafer-level line width standard based on electron beam exposure HSQ, comprising a silicon wafer and a HSQ photoresist with a preset characteristic dimension line width and tracking mark pattern, wherein the bottom surface of the HSQ photoresist is adhered to the upper surface of the silicon wafer.

[0022] Therefore, the present invention adopts the above-mentioned wafer-level line width standard sheet based on electron beam exposure HSQ and the preparation method, and the beneficial effects are as follows:

[0023] (1) The preparation method of the present invention uses an electron beam lithography machine and HSQ photoresist. As an inorganic photoresist, HSQ photoresist has extremely high resolution and can easily realize a line width structure below 10nm. At the same time, after being acted upon by the electron energy of the electron beam lithography machine, a highly stable silicon oxide structure can be generated, which has strong water absorption and oxidation resistance.

[0024] (2) The present invention uses HSQ photoresist with a silicon oxide structure and a silicon wafer substrate material. Silicon oxide and silicon itself have different optical properties, which can make the line width structure form a sharp contrast with the substrate material, improve the recognition ability of the mark, and help find the line width position, effectively solving the problem that micro-nano detection equipment is difficult to achieve wafer-level automatic calibration.

[0025] (3) The preparation method of the present invention directly prepares standard line width structures with different feature sizes on a silicon wafer by exposing HSQ photoresist through electron beam lithography, without the need for additional silicon window opening and nesting processes, and is simple to operate, further improving production efficiency.

[0026] (4) The preparation method of the present invention presets the tracking mark pattern through three-dimensional software, and can simultaneously prepare the line width structure and the tracking mark pattern, accurately position the mark, reduce the process flow, and save research and development costs.

[0027] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic structural diagram of a substrate material of an embodiment of a wafer-level line width standard sheet and a preparation method based on electron beam exposure HSQ of the present invention;

[0029] Figure 2 It is a schematic structural diagram of a wafer-level line width standard sheet based on electron beam exposure HSQ and a preparation method embodiment of the present invention after spin coating HSQ photoresist and baking;

[0030] Figure 3 It is a schematic structural diagram after exposure and development of a wafer-level line width standard sheet and a preparation method embodiment based on electron beam exposure HSQ of the present invention;

[0031] Figure 4 It is an optical microscope image of a wafer-level line width standard sheet according to an embodiment of a wafer-level line width standard sheet and a preparation method based on electron beam exposure HSQ of the present invention;

[0032] Figure 5It is a scanning electron microscope image of the line width structure of a wafer-level line width standard sheet according to an embodiment of a wafer-level line width standard sheet and a preparation method based on electron beam exposure HSQ of the present invention;

[0033] Figure 6 It is the atomic force microscope determination result of the line width structure of a wafer-level line width standard sheet according to an embodiment of the present invention, which is a wafer-level line width standard sheet based on electron beam exposure HSQ and a preparation method thereof.

[0034] Reference numerals

[0035] 1. Silicon wafer; 2. HSQ photoresist. DETAILED DESCRIPTION

[0036] The technical solution of the present invention is further described below through the accompanying drawings and embodiments.

[0037] Unless otherwise defined, technical or scientific terms used in the present invention shall have the common meanings understood by one having ordinary skills in the field to which the present invention belongs.

[0038] Embodiment 1

[0039] A method for preparing a wafer-level line width standard sheet based on electron beam exposure HSQ comprises the following steps:

[0040] S1. Use a single-sided polished silicon wafer 1 as a substrate material, and clean and dry the single-sided polished silicon wafer 1. During cleaning, an acidic cleaning solution or an alkaline cleaning solution can be selected to remove particles and impurities on the surface of the silicon wafer 1, providing a good foundation for subsequent preparation steps. In this embodiment, an 8-inch single-sided polished silicon wafer 1 is used as a substrate material, and its structure is as follows: Figure 1 shown.

[0041] S2, coating HSQ photoresist 2 on the substrate material obtained in step S1 by spin coating. And, HSQ photoresist 2 needs to cover the upper surface of the substrate material. Then, the coated HSQ photoresist 2 and the substrate material are baked for 3 minutes. In this embodiment, the model of HSQ photoresist 2 is HSQ XR1541-002, the thickness of HSQ photoresist 2 is 40nm, and its structure is as follows Figure 2 shown.

[0042] S3. Electron beam exposure is performed on the HSQ photoresist 2 by an electron beam lithography machine according to preset line widths and tracking mark patterns of different feature sizes.

[0043] In this embodiment, the sample spin-coated with HSQ photoresist 2 is placed in an electron beam lithography machine using electron beam lithography technology to expose a preset pattern. The preset pattern includes tracking marks and a standard line width structure, and the exposure layout of the preset pattern is drawn by L-edit software, and the standard line width structure is 22nm, 50nm, 100nm and 200nm line width, and the GDS format file is output and imported into the electron beam lithography machine. The high voltage of the electron beam lithography machine used is 100kV, the scanning frequency is 125MHz, and the beam current is 2nA.

[0044] S4, through the development and fixing process, the HSQ photoresist 2 is defined on the silicon wafer 1 to obtain a wafer-level line width standard sheet, specifically:

[0045] The exposed HSQ photoresist 2 and the substrate material are placed in a developer for reaction, with a 2.38% tetramethylammonium hydroxide solution as the developer, and the reaction time is 4 minutes. After the reaction is completed, the developer is placed in a fixer for reaction, with a deionized water solution as the fixer, and the reaction time is 30 seconds, so that the HSQ photoresist 2 is defined on the silicon wafer 1, and a wafer-level line width standard sheet with a preset standard line width pattern and a tracking mark structure is successfully obtained. The wafer-level line width standard sheet includes a silicon wafer 1 and a HSQ photoresist 2 with a preset characteristic size line width and a tracking mark pattern. The bottom surface of the HSQ photoresist 2 is adhered to the upper surface of the silicon wafer 1, and its structure is as follows: Figure 3 As shown, the left and right sides are tracking marks, and the middle is a line width structure.

[0046] Experimental Testing

[0047] An optical microscope, a scanning electron microscope and an atomic force microscope were used to verify the line width structure and the tracking marks of the wafer-level line width standard film prepared by the preparation method of the first embodiment.

[0048] like Figure 4 As shown, from the optical microscope image of the wafer-level linewidth standard film, it can be seen that the wafer-level linewidth standard film with a square frame on all sides and triangular tracking marks on the top, bottom, left and right corners, as well as the preset theoretical feature size of 22nm / 50nm / 100nm / 200nm were successfully prepared.

[0049] like Figure 5 As shown, through the scanning electron microscope images of line width structures with different characteristic sizes of wafer-level line width standard films, it can be seen that line width structures with successively decreasing characteristic sizes have been successfully prepared.

[0050] The atomic force microscope was used to measure the atomic force microscope fixed value results of different characteristic size line width structures. Each characteristic size line width structure was measured 6 times, and the uncertainty was calculated, and the results were obtained as follows: Figure 6The fixed value results shown are that the uncertainty of the line width structure with a characteristic size of 22nm is within 4.8nm, the uncertainty of the line width structure with a characteristic size of 50nm is within 3.5nm, the uncertainty of the line width structure with a characteristic size of 100nm is within 5.3nm, and the uncertainty of the line width structure with a characteristic size of 200nm is within 5.7nm, all of which are relatively high standard wafer-level line width standards.

[0051] Therefore, the present invention adopts the above-mentioned wafer-level line width standard sheet and preparation method based on electron beam exposure HSQ, which has anti-oxidation, anti-water absorption and high stability, does not require additional silicon window opening and nesting processes, can simultaneously prepare line width structure and tracking mark graphics, is simple to operate, has accurate positioning marks, saves research and development costs, and effectively solves the problem that micro-nano detection equipment is difficult to achieve wafer-level automatic calibration.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that they can still modify or replace the technical solution of the present invention with equivalents, and these modifications or equivalent replacements cannot cause the modified technical solution to deviate from the spirit and scope of the technical solution of the present invention.

Claims

1. A method for preparing a wafer-level line width standard sheet based on electron beam exposure HSQ, characterized in that: The following steps are involved: S1, using single-side polished silicon wafer as substrate material; S2, coating HSQ photoresist on the substrate material obtained in step S1 by spin coating; S3, performing electron beam exposure on the HSQ photoresist by an electron beam lithography machine according to preset line widths and tracking mark patterns of different feature sizes; S4. Through the development and fixing processes, the HSQ photoresist is defined on the silicon wafer to obtain a wafer-level line width standard film.

2. The method for preparing a wafer-level line width standard sheet based on electron beam exposure HSQ according to claim 1, characterized in that: In step S1, the single-side polished silicon wafer is cleaned and dried.

3. The method for preparing a wafer-level line width standard film based on electron beam exposure HSQ according to claim 1, characterized in that: In step S2, the substrate material coated with the HSQ photoresist is baked.

4. The method for preparing a wafer-level line width standard film based on electron beam exposure HSQ according to claim 1, characterized in that: In step S3, the high voltage of the electron beam lithography machine is 50kV-100kV, the maximum scanning frequency is 50MHz-125MHz, and the beam current range is 1nA-20nA.

5. The method for preparing a wafer-level line width standard film based on electron beam exposure HSQ according to claim 1, characterized in that: In step S3, the tracking mark is drawn by three-dimensional drawing software and outputted in a GDS format file.

6. The method for preparing a wafer-level line width standard film based on electron beam exposure HSQ according to claim 5, characterized in that: The three-dimensional drawing software is L-edit software or AutoCAD software.

7. The method for preparing a wafer-level line width standard film based on electron beam exposure HSQ according to claim 1, characterized in that: In step S3, the line widths of the different feature sizes are 22 nm, 50 nm, 100 nm and 200 nm.

8. The method for preparing a wafer-level line width standard film based on electron beam exposure HSQ according to claim 1, characterized in that: In step S4, the developing and fixing process is specifically as follows: The exposed HSQ photoresist and substrate material are placed in a developer to react, and after the reaction is completed, they are placed in a fixer to react, so that the HSQ photoresist is defined on the silicon wafer.

9. The method for preparing a wafer-level line width standard film based on electron beam exposure HSQ according to claim 8, characterized in that: The developer is a tetramethylammonium hydroxide solution with a concentration of 2.38%-25%.

10. A wafer-level line width standard film prepared by the method for preparing a wafer-level line width standard film based on electron beam exposure HSQ according to any one of claims 1 to 9, characterized in that: The invention comprises a silicon wafer and a HSQ photoresist with a preset characteristic dimension line width and a tracking mark pattern, wherein the bottom surface of the HSQ photoresist is adhered to the upper surface of the silicon wafer.

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