Device and method for monitoring etching depth of groove MOS (Metal Oxide Semiconductor)

Abstract

The invention discloses a device and a method for monitoring the etching depth of a groove MOS (Metal Oxide Semiconductor), a first component and a second component which have the same structure and different characteristics are adopted for comparison test, and the second component is characterized by comprising a plurality of second grooves which are arranged in a matrix in an area surrounded by the first grooves. According to the method, the first component and the second component are subjected to ion implantation, and the total resistance of the first component and the total resistance of the second component after ion implantation are compared, so that the deviation condition of the etching depth of the monitored groove MOS can be quickly obtained, destructive dissection testing does not need to be carried out on a chip, and the etching depth of a specified position area of each wafer can be monitored; compared with a traditional method, the monitoring frequency and range are more perfect.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor detection technology, and in particular to a monitoring device and method for the etching depth of a trench MOS. Background Art

[0002] MOSFET chip is a semiconductor discrete device. According to its physical structure, MOSFET chips can be classified into two categories: planar MOS and trench MOS. The body and source regions of trench MOS are diffusion regions formed by ion implantation and high-temperature annealing. The source region is usually located in the surface layer of the body region. The diffusion depth of the source region is smaller than that of the body region. The doping type of the body region is opposite to that of the substrate and source region. Taking N-channel MOSFET as an example, the doping type of the substrate is N-type, the doping type of the body region is P-type, and the doping type of the source region is N-type.

[0003] The formation process of the polysilicon gate of the trench MOS includes the deposition and etching process of polysilicon, wherein the polysilicon etching process is to remove all the polysilicon outside the trench, and retain the polysilicon in the trench as the gate of the trench MOS. In the practical process, in order to ensure that the polysilicon outside the trench is completely removed, an over-etching method is usually adopted, so the upper surface of the polysilicon retained in the trench is usually lower than the silicon plane, that is, there is a height difference, and this height difference is also the etching depth. The polysilicon etching depth of the trench MOS will affect the doping depth of the source region, and further affect the threshold voltage of the trench MOS.

[0004] The existing etching depth detection of trench MOS adopts sampling and dissecting chips. This method has obvious disadvantages, that is, it needs to perform destructive dissection test on the chip, so it is impossible to monitor every wafer in place, which has great limitations. Summary of the invention

[0005] The purpose of the present invention is to solve the technical problems existing in the background technology and to provide a monitoring device and method for the etching depth of a trench MOS.

[0006] In order to achieve the above technical objectives, the technical solution adopted in the first aspect of the present invention is as follows:

[0007] A monitoring device for the etching depth of a trench MOS comprises a first component and a second component; the second component comprises a body region, a source region, a plurality of contact holes, a first trench and a plurality of second trenches, the source region is stacked on the body region, the plurality of contact holes penetrate into the source region and the body region respectively, the contact holes are filled with metal electrodes, the first trench penetrates into the source region and the body region in sequence to surround and form a first diffusion resistor and a second diffusion resistor in the source region and the body region respectively, the plurality of second trenches are arranged in a matrix manner in the region surrounded by the first trench, the first trench and the second trench are both filled with a first material; wherein the first component has the same structure as the second component and does not include the plurality of second trenches, the first diffusion resistor and the second diffusion resistor in the first component are connected in parallel to obtain a total resistance R1, and the first diffusion resistor and the second diffusion resistor in the second component are connected in parallel to obtain a total resistance R2.

[0008] Preferably, the second grooves are square grooves, and each second groove is equidistant from another.

[0009] Preferably, the number of the second grooves is N 2 and are arranged in a matrix in the form of N rows and N columns in the area surrounded by the first groove, wherein N>1 and N is a positive integer.

[0010] Preferably, the first groove includes a main annular groove and four sub-annular grooves, the four sub-annular grooves are respectively connected to four sides of the main annular groove, and four contact holes are provided, which are respectively connected to the areas surrounded by the four sub-annular grooves.

[0011] Preferably, the area surrounded by the main annular groove is in the shape of a square.

[0012] Preferably, the total resistor R1 and the total resistor R2 are both Van der Pauw resistors.

[0013] Preferably, the first material is polysilicon.

[0014] Preferably, the first trench and the second trench are also filled with a second substance, the second substance is silicon oxide, the silicon oxide covers the inner walls of the first trench and the second trench, and the remaining space in the first trench and the second trench is filled with polysilicon.

[0015] Preferably, the spacing between each second trench is less than twice the source region implantation depth between the second trenches.

[0016] The technical solution adopted in the second aspect of the present invention is as follows:

[0017] A method for monitoring the etching depth of a trench MOS, characterized in that it is applied to the monitoring device for the etching depth of the trench MOS as in the above scheme, and the method for monitoring the etching depth of the trench MOS comprises:

[0018] Using a preset ion implantation process, ion implantation is performed on the first component and the second component respectively;

[0019] After completing the ion implantation process, respectively detecting the total resistance R1 and the total resistance R2 to obtain a first total resistance value and a second total resistance value;

[0020] The difference between the first total resistance value and the second total resistance value is calculated to determine the deviation of the etching depth of the trench MOS.

[0021] Compared with the prior art, the present invention has the following beneficial technical effects: a first component and a second component having the same structure but different characteristics are used for comparative testing, wherein the different characteristic of the second component is that it has a plurality of second grooves arranged in a matrix in an area surrounded by the first groove, ion implantation is performed on the first component and the second component, and the total resistance of the first component and the second component after the ion implantation is compared to quickly obtain the deviation of the etching depth of the monitoring groove MOS, without the need for destructive anatomical testing of the chip, and the etching depth of the specified position area of ​​each wafer can be monitored, and the monitoring frequency and range are more complete than those of the traditional method. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the planar structure of the first component in the monitoring device when R=0 in the first aspect of the embodiment of the present invention;

[0023] Figure 2 A cross-sectional view of a first component in a monitoring device when R=0 in an embodiment of the first aspect of the present invention;

[0024] Figure 3 It is a schematic diagram of the planar structure of the second component in the monitoring device when R=0 in the embodiment of the first aspect of the present invention;

[0025] Figure 4 A cross-sectional view of the monitoring device of the second component in the monitoring device when R=0 in the embodiment of the first aspect of the present invention;

[0026] Figure 5 A cross-sectional view of a monitoring device of a first component in the monitoring device when R>0 is taken in an embodiment of the first aspect of the present invention;

[0027] Figure 6 A cross-sectional view of the monitoring device of the second component in the monitoring device when R>0 is taken in the embodiment of the first aspect of the present invention;

[0028] Figure 7 This is a monitoring flow chart of an embodiment of the second aspect of the present invention.

[0029] Reference numerals: 100 body region, 200 source region, 300 contact hole, 301 metal electrode, 400 first trench, 401 main annular trench, 402 secondary annular trench, 500 second trench, 600 first substance, 700 second substance. DETAILED DESCRIPTION

[0030] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0031] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second", etc. may explicitly or implicitly include one or more features. In the description of the present invention, unless otherwise specified, "several" means two or more.

[0032] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or a specific connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood by specific circumstances.

[0033] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] like Figure 1 as well as Figure 6 As shown, the present invention provides a monitoring device for the etching depth of a trench MOS in a first aspect, comprising a first component and a second component; the second component comprises a body region 100, a source region 200, a plurality of contact holes 300, a first trench 400 and a plurality of second trenches 500; wherein the first component has the same structure as the second component and does not include the plurality of second trenches 500;

[0035] In this embodiment, the monitoring device is actually located in the dicing lane of the wafer. Specifically, during the chip preparation process such as etching the wafer, the preparation of the monitoring device is also included in the process and is carried out synchronously with the wafer etching. For example, the first groove 400, the second groove 500, the body region 100, and the source region 300 in the first component and the second component are all formed synchronously with the groove, body region, and source region of the monitored trench MOS, wherein the first material in the first groove 400 and the second groove 500 is formed synchronously with the control gate in the monitored trench MOS.

[0036] The source region 200 is stacked on the body region 100, a plurality of contact holes 300 penetrate into the source region 200 and the body region 100 respectively, the contact holes 300 are filled with metal electrodes 301, a first trench 400 penetrates into the source region 200 and the body region 100 in sequence, so as to surround and form a first diffusion resistor and a second diffusion resistor in the source region 200 and the body region 100 respectively, a plurality of second trenches 500 are arranged in a matrix manner in the area surrounded by the first trench 400, and the first trench 400 and the second trench 500 are both filled with a first material 600;

[0037] The first diffusion resistor and the second diffusion resistor in the first component are connected in parallel to obtain a total resistance R1, and the first diffusion resistor and the second diffusion resistor in the second component are connected in parallel to obtain a total resistance R2.

[0038] Specifically, the first groove 400 includes a main annular groove 401 and four secondary annular grooves 402. The four secondary annular grooves 402 are respectively connected to the four sides of the main annular groove 401. There are four contact holes 300, which are respectively connected to the areas surrounded by the four secondary annular grooves 402. The area surrounded by the main annular groove 401 is square in shape. As shown in the accompanying drawings, W1 and W2 respectively refer to the side lengths of the main annular groove 401 in the first component and the main annular groove 401 in the second component. In this embodiment, since the structures of the first component and the second component are basically the same, W1=W2.

[0039] The boundary of the source region 200 of the first component and the second component is located on the center line of the width X1, X2 of the first trench 400. It can be understood that the boundary of the first trench 400 shrinks inwardly, and the inner shrinkage distance is half of the width X1, X2 of the first trench 400, and the final result is the source region 200.

[0040] In this embodiment, the specific implementation is as follows: the monitoring device is located in the dicing lane of the wafer. During the chip preparation process such as etching the wafer, the preparation of the monitoring device is also included in the process and is formed synchronously with the chip. A certain current is applied to two adjacent metal electrodes 301 on the first component and the second component, and the voltage of the other two adjacent metal electrodes 301 is detected. The total resistance R1 and the total resistance R2 corresponding to the first component and the second component are obtained by calculation, and the difference between the total resistance R1 and the total resistance R2 is judged to determine the deviation of the etching depth of the trench MOS. After determining that there is no problem with the etching depth of the trench MOS, the slicing process is performed on the dicing lane through a cutting process, and the monitoring device is destroyed together, so as to realize the monitoring of the trench MOS by the monitoring device, without the need for destructive anatomical testing of the chip.

[0041] Furthermore, the second grooves 500 are square grooves, and each second groove 500 is equidistant from each other.

[0042] The number of the second trenches 500 is N. 2 and are arranged in a matrix in the form of N rows and N columns in the area surrounded by the first trench 400 , wherein N>1 and N is a positive integer.

[0043] Specifically, S in the accompanying drawings is the distance between each second groove 500, and S is much smaller than W2. Specifically, the spacing S between each second groove 500 is smaller than 2 times the injection depth of the source region 200 between the second grooves 500. Since ion injection has a certain depth, in actual operation, assuming that the ion injection depth is 0.3μm, and the spacing between the two second grooves 500 is less than or equal to 0.6μm, the ion injection is injected from the side wall between the two second grooves 500. Therefore, at this depth, the injected ions will meet and achieve a more uniform doping. If the spacing between the two second grooves 500 is too large, for example, greater than the above-mentioned 0.6μm, then the ions will not meet during injection, and only affect the range of 0.3μm from the second groove 500, resulting in the area exceeding 0.3μm not affecting the , thereby affecting the detection effect of the monitoring device. It should be noted that the second component is a comparison group of the first component, and the depth J2 of the spacing S between each second groove 500 in the second component will be affected by the etching depth R of the first material in the second groove 500. Once the etching depth R of the first material is greater than 0, the depth of the ion implantation needs to be added with the first material etching depth R. Since the spacing S is fixed in advance, the depth of the ion implantation is also fixed, so that the depth J2 of the spacing S increases to a depth J4, which leads to a decrease in the resistance of the first diffusion resistor in the source region 200. Then, according to the ratio between the total resistance of the second component and the total resistance of the first component and the original ratio, the deviation of the etching depth of the trench MOS can be judged, and the specific etching depth can be judged by the difference in the ratio.

[0044] Furthermore, the total resistance R1 and the total resistance R2 are both Van der Pauw resistances.

[0045] The first material 600 is polysilicon. The first trench 400 and the second trench 500 are also filled with a second material 700. The second material 700 is silicon oxide. The silicon oxide covers the inner walls of the first trench 400 and the second trench 500, and the remaining space in the first trench 400 and the second trench 500 is filled with polysilicon.

[0046] Specifically, silicon oxide is formed synchronously with the gate oxide layer of the monitored trench MOS, polysilicon is formed synchronously with the control gate of the monitored trench MOS, and the etching depth actually monitored is the etching depth of the polysilicon.

[0047] like Figure 7 As shown, the present invention provides a method for monitoring the etching depth of a trench MOS in a second aspect, characterized in that the method is applied to the monitoring device for the etching depth of the trench MOS in the above-mentioned scheme, and the monitoring method for the etching depth of the trench MOS includes:

[0048] S1. Using a preset ion implantation process, ion implantation is performed on the first component and the second component respectively;

[0049] S2, after completing the ion implantation process, respectively detecting the total resistance R1 and the total resistance R2 to obtain a first total resistance value and a second total resistance value;

[0050] S3. Calculate the difference between the first total resistance value and the second total resistance value to determine the deviation of the etching depth of the trench MOS.

[0051] Specifically, the total resistance R1 formed by the second diffusion resistor R11 formed in the body region 100 and the first diffusion resistor R12 formed in the source region 200 in the first component in parallel is R1=R11*R12 / (R11+R12) according to the calculation formula of parallel resistance.

[0052] The total resistance R2 formed by the second diffusion resistor R21 formed in the body region 100 and the first diffusion resistor R22 formed in the source region 200 in the second component in parallel is R2=R21*R22 / (R21+R22) according to the calculation formula of parallel resistance.

[0053] Since the first component and the second component have the same size and the body regions 100 therein are formed simultaneously, the resistance values ​​of the second diffusion resistors in the first component and the second component are equal, that is, R11 = R21.

[0054] When the etching depth of polysilicon is R=0:

[0055] Since the source regions 200 in the first component and the second component are formed simultaneously, the depth J1 is equal to the depth J2, that is, J1=J2, and the resistance values ​​of the two corresponding first diffusion resistors are equal, R12=R22.

[0056] In summary, we can conclude that: since R11=R21 and R12=R22, R1=R2.

[0057] At this time, by detecting that the total resistance of the first component and the second component is the same, that is, there is no difference, it can be determined that there is no deviation in the etching depth of the trench MOS.

[0058] When the etching depth of polysilicon R>0:

[0059] The doped region formed by ion implantation through the silicon surface into the body region 100 has a depth that is not affected by the polysilicon etching depth. Therefore, its depth J3 (eg Figure 5 The depth J1 (shown) corresponds to the etching depth R of polysilicon when R = 0. Figure 2 As shown), they are equal, that is, J3=J1;

[0060] When the source region 200 is doped by ion implantation, in the polysilicon overetched area in the second trench 500 in the second component, the doped material penetrates the silicon oxide and enters the body region 100 from the sidewall of the second trench 500, so the depth J4 ( Figure 6 The depth J2 (shown) is greater than the depth J2 corresponding to the etching depth R of polysilicon = 0. Figure 4 As shown), that is, J4>J2, and J1=J2, J3=J1, so J4>J3.

[0061] Since the diffusion resistance decreases with increasing depth, since J4>J3, therefore, R12>R22.

[0062] In summary, we can conclude that: since R11=R21 and R12>R22, R1>R2.

[0063] It can be concluded that when the polysilicon etching depth is greater than 0, the corresponding ratio of R1 to R2 (R1 / R2) is greater than 1, and the greater the polysilicon etching depth, the greater the ratio.

[0064] It can be seen from this that by detecting the ratio between the total resistance of the second component and the total resistance of the first component and the original ratio, the deviation of the etching depth of the trench MOS can be determined, and the specific etching depth can be determined by the difference in the ratio.

[0065] The above is a monitoring device and method for the etching depth of a trench MOS or multiple implementation methods provided in combination with specific content, and the specific implementation of the present invention is not limited to these descriptions. Any similarity or similarity with the method, structure, etc. of the present invention, or a number of technical deductions or replacements made under the premise of the concept of the present invention, shall be regarded as the protection scope of the present invention.

Claims

1. A monitoring device for etching depth of trench MOS, characterized in that: include: a first component and a second component; The second component comprises: body area (100); A source region (200) stacked on the body region (100); A plurality of contact holes (300) respectively penetrate into the source region (200) and the body region (100), wherein the contact holes (300) are filled with metal electrodes (301); A first trench (400) is sequentially penetrated into the source region (200) and the body region (100) to surround and form a first diffusion resistor and a second diffusion resistor in the source region (200) and the body region (100), respectively; A plurality of second grooves (500) are arranged in a matrix manner in the area surrounded by the first groove (400), and the first groove (400) and the second groove (500) are both filled with a first substance (600); The first component has the same structure as the second component and does not include a plurality of second grooves (500); the first diffusion resistor and the second diffusion resistor in the first component are connected in parallel to obtain a total resistance R1; the first diffusion resistor and the second diffusion resistor in the second component are connected in parallel to obtain a total resistance R2.

2. The device for monitoring the etching depth of a trench MOS according to claim 1, characterized in that: The second grooves (500) are square grooves, and each of the second grooves (500) is equidistant from each other.

3. The device for monitoring the etching depth of a trench MOS according to claim 1, characterized in that: The number of the second grooves (500) is and are arranged in a matrix in the form of N rows and N columns in the area surrounded by the first groove (400), wherein N>1, and N is a positive integer.

4. The device for monitoring the etching depth of a trench MOS according to claim 1, characterized in that: The first groove (400) includes a main annular groove (401) and four secondary annular grooves (402), the four secondary annular grooves (402) are respectively connected to the four sides of the main annular groove (401), and the contact holes (300) are provided with four, and are respectively connected to the areas surrounded by the four secondary annular grooves (402).

5. The device for monitoring the etching depth of a trench MOS according to claim 4, characterized in that: The area surrounded by the main annular groove (401) is in the shape of a square.

6. The device for monitoring the etching depth of a trench MOS according to claim 5, characterized in that: The total resistance R1 and the total resistance R2 are both Van der Pauw resistances.

7. The device for monitoring the etching depth of a trench MOS according to claim 1, characterized in that: The first substance (600) is polycrystalline silicon.

8. The device for monitoring the etching depth of a trench MOS according to claim 7, characterized in that: The first trench (400) and the second trench (500) are also filled with a second substance (700), the second substance (700) being silicon oxide, the silicon oxide covering the inner walls of the first trench (400) and the second trench (500), and the remaining space in the first trench (400) and the second trench (500) is filled with the polysilicon.

9. The device for monitoring the etching depth of a trench MOS according to claim 2, characterized in that: The spacing between each of the second trenches (500) is less than twice the implantation depth of the source region (200) between the second trenches (500).

10. A method for monitoring the etching depth of a trench MOS, characterized in that: The device for monitoring the etching depth of the trench MOS as claimed in claims 1 to 9, wherein the method for monitoring the etching depth of the trench MOS comprises: Using a preset ion implantation process, ion implantation is performed on the first component and the second component respectively; After completing the ion implantation process, respectively detecting the total resistance R1 and the total resistance R2 to obtain a first total resistance value and a second total resistance value; The difference between the first total resistance value and the second total resistance value is calculated to determine the deviation of the etching depth of the trench MOS.

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