Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, and the method comprises the following steps: providing a semiconductor substrate which comprises a top surface and a bottom surface which are oppositely arranged; an annular groove is formed in the substrate in the direction from the top surface to the bottom surface, and a low-resistance silicon column formed by the substrate is located in the middle of the annular groove; first filling is carried out on the annular groove; first filling liquid is provided, and the annular groove is filled with the first filling liquid; curing the first filling liquid to form a first insulating layer; and performing second filling on the annular groove: providing a second filler, and filling the second filler in the annular groove forming the first insulating layer. According to the manufacturing method, the semiconductor with the low-resistance silicon TSV structure and better reliability and integrity can be obtained, the process is simple, and the manufacturing method is suitable for production environments of different scales.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor chips and manufacturing, and relates to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Through Silicon Via (TSV) is a key technology in current 3D circuit packaging. In TSV technology, the selection of filling materials is crucial. It can be divided into metal filling and silicon filling according to different conductivity types, as follows:

[0003] In metal filling technology, the most common filling material is copper (Cu), because of its advantages such as low resistivity and high reliability. However, Cu as a filling material also has some disadvantages. For example, in blind hole electroplating, there is uneven current distribution, which leads to significant differences in electroplating rate at the top and bottom of the hole, which not only affects the quality of the electroplating layer, but also may cause a pinch-off effect; secondly, due to the large difference in thermal expansion coefficients between silicon (Si) and Cu, when the TSV structure undergoes temperature changes, the interface between the two materials will produce significant stress, causing severe deformation or warping of the substrate, thereby affecting the performance and reliability of the entire chip; thirdly, the manufacturing process of Cu column TSV involves multiple precise process steps, which is relatively complex and leads to high manufacturing costs. In short, it still faces many challenges in practical applications, which limits its application in stress-sensitive devices.

[0004] In comparison, silicon filling technology uses a central silicon column directly as the current conduction core, which simplifies the production process and eliminates complex steps such as seed layer deposition, copper column electroplating, and subsequent copper layer polishing. This not only reduces the technical requirements for production equipment, but also significantly reduces production costs. In addition, the use of silicon as a filling material helps to reduce the thermal stress generated between materials when the temperature changes because it matches the thermal expansion coefficient of the silicon substrate, thereby improving the stability and reliability of the chip. However, silicon filling technology also faces certain challenges, especially when dealing with low-resistance silicon TSVs with high aspect ratio structures. Because the annular grooves of these TSVs are complex in shape and deep, it is difficult to achieve complete filling from bottom to top when filling their complex annular grooves, which may cause defects or gaps in the insulating layer, thereby affecting the overall performance and reliability of the TSV.

[0005] In summary, although metal filling technology is mature and reliable, its thermal expansion coefficient does not match that of silicon, which can easily lead to wafer stress warping, and the process is complex and the equipment cost is high; while the traditional low-resistance silicon TSV, although the thermal expansion coefficient matches that of silicon and the process is relatively simple, is difficult to fully fill the complex annular groove of TSV. Therefore, it is urgent to develop a low-resistance silicon TSV filling method with matching thermal expansion coefficient, high temperature compatibility, good filling effect, and good promotion. Summary of the invention

[0006] The purpose of the present invention is to provide a semiconductor structure and a method for manufacturing the same, which effectively solves the technical problem that the existing silicon filling technology is difficult to completely fill the complex annular groove when processing low-resistance silicon TSV with a high aspect ratio structure, thereby improving the overall performance and reliability of TSV. The method includes the following steps:

[0007] Providing a semiconductor substrate, the substrate comprising a top surface and a bottom surface arranged opposite to each other;

[0008] From the top surface to the bottom surface of the substrate, an annular groove is formed in the substrate, and the middle of the annular groove is a low-resistance silicon column formed by the substrate;

[0009] Performing a first filling on the annular groove: providing a first filling liquid, and filling the annular groove with the first filling liquid under a certain negative pressure condition;

[0010] solidifying the first filling liquid to form a first insulating layer;

[0011] Performing a second filling on the annular groove: providing a second filler, and filling the second filler in the annular groove formed with the first insulating layer;

[0012] The second filler is oxidized to form a second insulating layer. The first insulating layer and the second insulating layer constitute an annular insulating layer. The annular insulating layer insulates the low-resistance silicon pillars from each other.

[0013] Optionally, performing the first filling on the annular groove further comprises the following steps:

[0014] heating the first filling liquid so that the first filling liquid solidifies;

[0015] The semiconductor structure is first polished from the top surface to remove the first insulating layer remaining on the top surface.

[0016] Optionally, performing a second filling on the annular groove further comprises the following steps:

[0017] Performing a second polishing on the semiconductor structure from the top surface to remove the second insulating layer remaining on the top surface;

[0018] The semiconductor structure is thinned from the bottom surface until the first insulating layer is exposed.

[0019] Optionally, the first filling liquid is a mixed solution containing tetraethyl silicate, and the concentration of the tetraethyl silicate in the first filling liquid ranges from 15% to 50%.

[0020] Optionally, the height of the annular groove is greater than or equal to 5 times the diameter of the annular groove, and the diameter of the annular groove is less than or equal to 3 / 2 times the diameter of the low-resistance silicon column.

[0021] Optionally, the temperature range for performing the first filling is 50° C. to 200° C., and the pressure range for forming the certain negative pressure condition is -50 kPa to -96 kPa.

[0022] Optionally, the second filler is a solid powder containing nano silicon particles, and the diameter of the nano silicon particles ranges from 20 nm to 1 μm.

[0023] Optionally, the first filling liquid is heated at a temperature ranging from 150° C. to 600° C., and a heating time greater than or equal to 1 hour.

[0024] Optionally, the semiconductor structure is polished a second time from the top surface until the top surface of the semiconductor structure is flat and the roughness of the top surface is within ±1 μm.

[0025] Optionally, the method further includes: cleaning the semiconductor structure; and drying the cleaned semiconductor structure.

[0026] Optionally, the method further includes: forming a metal electrode layer connected to the low-resistance silicon column below the low-resistance silicon column; and forming a third insulating layer between below the annular groove and below the metal electrode layer.

[0027] Another embodiment of the present invention provides a semiconductor structure, comprising:

[0028] A substrate, wherein the substrate is divided into a top surface and a bottom surface;

[0029] A low-resistance silicon TSV structure, comprising a low-resistance silicon column formed on the substrate and an annular insulating layer located around the low-resistance silicon column, wherein the annular insulating layer comprises the first insulating layer and the second insulating layer;

[0030] The support layer is located on the bottom surface of the substrate, and includes a metal electrode layer formed below the low-resistance silicon pillar and a third insulating layer formed between the metal electrode layer below the annular groove and below the metal electrode layer.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] Improve product reliability and stability: Use the first filling liquid and the second filling material to perform two independent fillings, which improves the uniformity and integrity of the insulation layer filling, so that a good interface bonding is formed between the insulation layer and the substrate and the low-resistance silicon column. Filling is performed in two steps, which improves the flexibility of process control and facilitates adjustment and optimization of each step to adapt to different needs and conditions. It can effectively control the maximum temperature that the subsequent low-resistance TSV can withstand, thereby ensuring the reliability of the low-resistance silicon TSV insulation layer filling;

[0033] Easy to operate and widely applicable: The first filling liquid is filled at low temperature, which effectively reduces the temperature requirement of the entire process, reduces the adverse effect of high temperature on the performance of low-resistance silicon TSV, and ensures the filling quality; the second filling can be carried out at room temperature without complex heating equipment, and can be operated manually or automatically, which is flexible and convenient and suitable for production environments of different scales;

[0034] Thermal stress matching, stable and reliable: The thermal expansion coefficient of the obtained insulating layer (such as silicon oxide) is similar to that of silicon, which means that when the temperature changes, the thermal stress mismatch problem between the insulating layer and the silicon substrate is basically eliminated, improving the stability and reliability of the entire structure; through two-step filling, the compatible temperature of low-resistance silicon TSV can be significantly increased to 1000℃ or even higher, expanding its application range in high-temperature environments and meeting the needs of more high-end applications;

[0035] No impurity pollution: The filling liquid is friendly to the silicon substrate and will not introduce impurity elements during the filling process, ensuring the purity of the silicon wafer and device performance, and meeting the production standards of high-quality electronic components. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1a The figure shows a top view of a low-resistance silicon TSV structure in the prior art under an optical microscope.

[0037] Figure 1b A scanning electron microscope image showing a longitudinal cross-section of a low-resistance silicon TSV structure in the prior art.

[0038] Figure 2 This is a flow chart of the steps of the semiconductor structure manufacturing method provided in the first embodiment.

[0039] Figure 3 A schematic diagram of a side view structure showing an annular groove formed in a substrate.

[0040] Figure 4 A schematic top view of a structure showing an annular groove formed in a substrate.

[0041] Figure 5 Display as Figure 2A schematic structural diagram of filling the annular groove with a first filling liquid in the method shown.

[0042] Figure 6 Show as pair Figure 5 The structure shown is heated to form a structural schematic diagram of a first insulating layer.

[0043] Figure 7 Show as pair Figure 6 Schematic diagram of the structure undergoing the first polishing.

[0044] Figure 8 Displayed as Figure 7 The schematic diagram of the structure in which the annular groove is filled with a second filler is shown.

[0045] Fig. 9 Show as pair Figure 8 The structure shown is oxidized to form a schematic diagram of the structure of the second insulating layer.

[0046] Fig.10 Show as pair Fig. 9 Schematic diagram of the structure undergoing a second polishing.

[0047] Fig.11 Display as Fig.10 Schematic diagram of the structure after the bottom surface of the structure is thinned.

[0048] Fig.12a Display as Figure 2 Scanning electron microscope image of the cross section of the low-resistance silicon TSV structure obtained by the method shown.

[0049] Figure 12b Display as Figure 2 Scanning electron microscope image of the longitudinal section of the low-resistance silicon TSV structure obtained by the method shown.

[0050] Fig.13 Shown is a schematic diagram of a semiconductor structure provided by Embodiment 2 of the present invention.

[0051] Reference numerals

[0052] 100, substrate; 101, low-resistance silicon column; 102, annular groove; 103, first filling liquid; 104, first insulating layer; 105, second filling material; 106, second insulating layer; 107, metal electrode layer; 108, third insulating layer; 109, annular insulating layer. DETAILED DESCRIPTION

[0053] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Although the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation, the form, quantity, positional relationship and proportion of each component in actual implementation can be changed at will under the premise of realizing the technical solution of this party, and the component layout form may also be more complicated.

[0055] A common method for manufacturing a semiconductor structure is as follows:

[0056] A semiconductor substrate is provided, and etching is performed along a horizontal direction from the top surface to the bottom surface of the substrate to form a low-resistance silicon TSV structure to be filled, wherein the low-resistance silicon TSV structure includes a plurality of annular grooves.

[0057] A filling liquid is provided, wherein the filling liquid is a mixed solution containing tetraethyl silicate and an organic solvent.

[0058] Filling is performed by applying the filling liquid droplets into the annular groove of the low-resistance silicon TSV structure.

[0059] The low-resistance silicon TSV structure is heated until the filling liquid is completely solidified to form an insulating layer in the annular groove.

[0060] The low-resistance silicon TSV structure is polished, cleaned and dried in sequence.

[0061] In the low-resistance silicon TSV structure manufactured by the above method, defects and gaps may occur in the insulating layer within the annular groove, thereby affecting the performance and reliability of the entire semiconductor structure.

[0062] Specifically, a mixed solution of 56% C2H6O and 38% tetraethyl silicate is used as the filling liquid; the filling needs to be carried out in a negative pressure environment formed under a pressure of -95kPa; the filling time is 35min; heating is carried out by hot plate heating at 180°C for 1h; polishing is carried out by chemical mechanical planarization method, and the polishing time is: 2min.

[0063] For further information, see Figure 1a, which shows a top view of the low-resistance silicon TSV structure obtained by the above method under an optical microscope. It can be seen that the annular ring is the top structure after the annular groove is filled, and there are obvious uneven filling phenomena on these annular rings.

[0064] For further information, see Figure 1b , showing a scanning electron microscope image of a longitudinal section of a low-resistance silicon TSV structure made by the above method. The internal structure of the insulating layer formed in the annular groove can be clearly seen. There are filled sections, gaps, and unfilled or incompletely filled surfaces in this annular groove. These defects will not only increase the resistance of the TSV structure, but may also introduce parasitic capacitance and inductance, thereby affecting the integrity and speed of signal transmission. In addition, gaps and unfilled areas may also become potential reliability problems, such as cracks or failures under thermal cycles or stress.

[0065] In summary, the above-mentioned semiconductor structure manufacturing method has some problems such as incomplete and uneven filling of the insulating layer, which will seriously affect the reliability of the low-resistance silicon TSV structure. Therefore, we need to improve the filling method of the insulating layer of the low-resistance silicon TSV structure, develop a new filling process, and achieve high-quality filling to ensure the performance and reliability of the TSV structure.

[0066] Embodiment 1

[0067] In view of the above-mentioned deficiencies and defects in the method for manufacturing a semiconductor structure in the prior art, this embodiment provides a method for manufacturing a semiconductor structure.

[0068] See also Figure 2 , which shows the process flow of the semiconductor structure manufacturing method of the present invention, comprising the following steps:

[0069] S1: providing a semiconductor substrate, wherein the substrate comprises a top surface and a bottom surface which are oppositely arranged;

[0070] S2: From the top surface to the bottom surface, an annular groove is formed in the substrate, and a low-resistance silicon column formed on the substrate is located in the middle of the annular groove;

[0071] S3: performing a first filling on the annular groove: providing a first filling liquid, and filling the annular groove with the first filling liquid;

[0072] S4: solidifying the first filling liquid to form a first insulating layer;

[0073] S5: performing a second filling on the annular groove: providing a second filler, and filling the second filler into the annular groove forming the first insulating layer;

[0074] S6: oxidizing the second filler to form a second insulating layer, wherein the first insulating layer and the second insulating layer constitute an annular insulating layer, and the annular insulating layer insulates the low-resistance silicon pillars from each other.

[0075] The following will be combined Figure 3 - Figure 12 details the various steps of a semiconductor structure manufacturing method of the present invention.

[0076] See also Figure 3 A semiconductor substrate 100 is provided, wherein the substrate 100 includes a top surface and a bottom surface that are relatively arranged, a low-resistance silicon TSV structure is formed on the substrate, and annular grooves 102 arranged at intervals are formed by etching the substrate 100 along a horizontal direction from the top surface to the bottom surface.

[0077] See also Figure 4 , showing a top view of the annular groove structure. In the middle of the annular groove 102 is a low-resistance silicon column 101 formed by the substrate 100. The outer side of the annular groove 102 is the substrate 100, and the inner side is the low-resistance silicon column 101.

[0078] Figure 3 For along Figure 4 The cross-sectional view at the dotted line is shown. The low-resistance silicon TSV structure includes a low-resistance silicon column 101 and an annular groove 102 formed on a substrate. The annular groove 102 has a high aspect ratio structure. The depth, width and morphology of the annular groove 102 are designed based on actual needs. As an example, the diameter of the annular groove 102 is less than or equal to 3 / 2 times the diameter of the low-resistance silicon column 101, and the height of the annular groove 102 is greater than or equal to 5 times its diameter.

[0079] Generally, the low-resistance silicon TSV substrate can be one of single crystal silicon, polycrystalline silicon or amorphous silicon. The etching method for forming the annular groove 102 includes: dry etching, wet etching, reactive ion etching, deep reactive ion etching or ion beam etching. Specifically, in this embodiment, the substrate 100 is made of single crystal silicon.

[0080] See also Figure 5 , provide a first filling liquid 103, and fill the annular groove 102 with the first filling liquid 103 until all bubbles in the annular groove 102 burst and overflow. Due to the existence of surface tension, the first filling liquid 103 forms a convex smooth curved surface structure in the annular groove 102, and does not completely fill the entire annular groove 102, and the first filling liquid 103 also exists on the top surface of the substrate 100 and the low-resistance silicon pillar 101.

[0081] Generally, the first filling liquid 103 is a mixed solution containing tetraethyl silicate and some organic solvents such as C2H6O, wherein the concentration of tetraethyl silicate ranges from 15% to 50%. The ratio of tetraethyl silicate to organic solvent can be adjusted according to actual needs. Specifically, in this embodiment, the first filling liquid 103 is a mixed solution containing 56% C2H6O + 38% tetraethyl silicate. Generally, the method for performing the first filling includes one or a combination of vacuum filling or spin coating filling. The first filling needs to be performed at a specific process temperature and a negative pressure environment; the process temperature range is 50°C to 200°C, the process pressure range is -50kpa to -96kpa, and the filling time is 30min to 1h. Methods for forming a negative pressure environment include: vacuum chamber vacuum, vacuum pump vacuuming, and other methods such as negative pressure isolation method. Specifically, in this embodiment, the first filling time is 35min.

[0082] See also Figure 6 ,right Figure 5 The low-resistance silicon TSV structure shown is heated to completely solidify the first filling liquid 103 to form the first insulating layer 104 .

[0083] Generally, the heating methods include: oven heating, hot plate heating, furnace tube heating or a combination thereof. The heating temperature range and heating time are affected by the properties of the filling liquid, the size of the TSV structure, process requirements, equipment and other conditions. Generally, the heating temperature range is: 150°C to 600°C, and the heating time is greater than or equal to 1h. Specifically, the heating range is: 1h to 5h. Specifically, in this embodiment, the first filling liquid is heated by a heating plate, the heating plate temperature is 180°C, and the heating time is 1h.

[0084] See also Figure 7 ,right Figure 6 The first polishing of the low-resistance silicon TSV structure shown removes all the first insulating layer 104 remaining on the top surface, including the low-resistance silicon column 101 and the first insulating layer remaining on the top surface of the substrate 100. Generally, the polishing method includes one or a combination of chemical mechanical planarization (CMP) and a grinding process (Griding). The polishing time ranges from 1 min to 10 min. In this embodiment, the first polishing of the low-resistance silicon TSV structure adopts a chemical mechanical planarization method and polishes for 2 minutes. Due to the surface tension of the first filling liquid 103 and some processes such as heating and polishing, the first insulating layer 104 cannot completely fill the entire annular groove 102, and the surface of the first insulating layer 104 in the annular groove 102 is uneven and unevenly filled.

[0085] See also Figure 8 , execute step S5, provide the second filler 105, fill the second filler 105 to Figure 7The annular groove 102 shown is filled with the depression of the first insulating layer 104 in the annular groove 102 to eliminate the uneven surface of the first insulating layer 104 and the uneven filling phenomenon.

[0086] Generally, the second filler 105 is a solid powder containing nano silicon particles, the diameter of the nano silicon particles ranges from 20 nm to 1 μm, and the filling time ranges from 10 min to 1 h.

[0087] Specifically, in this embodiment, the second filler 105 is a solid powder containing nano-silicon particles with a diameter of 30 nm. The filling time is 15 minutes, so that the annular groove 102 is completely filled under a microscope.

[0088] Optionally, the second filling can be carried out at room temperature without other complex environments. The operation is simple and convenient, and the adaptability is wide, which improves the flexibility of the process steps.

[0089] See also Fig. 9 ,right Figure 8 The semiconductor structure is shown to be oxidized to form a second insulating layer 106 .

[0090] Generally, the oxidation method includes dry oxygen oxidation, wet oxygen oxidation, or a combination thereof. In this embodiment, the second insulating layer 106 is formed into a dense SiO2 layer by using the wet oxygen oxidation method. The SiO2 layer can enhance adhesion and reduce filling failure or shedding caused by interface problems; it can also play a protective role and prevent the insulating layer from being corroded or damaged in the subsequent processing. In addition, this SiO2 layer can also improve the chemical stability and thermal stability of the product.

[0091] See also Fig.10 ,right Fig. 9 The top surface of the semiconductor structure shown is polished for the second time until the redundant second insulating layer 106 on the top surface is completely removed and the top surface is flat. After the second polishing, the roughness of the top surface is within ±1 μm.

[0092] Generally, the polishing method includes chemical mechanical planarization (CMP), gridding, or a combination thereof.

[0093] See also Fig.11 ,right Fig.10 The bottom surface of the semiconductor structure shown is thinned until the first insulating layer is exposed. The thinning method includes one or a combination of chemical mechanical planarization (CMP), gridding, and deep silicon etching (DRIE).

[0094] Specifically, the method for manufacturing the semiconductor structure also includes the following steps: rinsing the semiconductor structure and drying it. Cleaning includes high-purity water cleaning, solvent cleaning, brushing or ultrasonic cleaning, and drying includes rotary drying, spin drying, and the like. In this embodiment, a solvent cleaning and spin drying method is adopted, and the cleaning liquid used is deionized water, anhydrous ethanol, and other organic solvents. By cleaning and drying, residual contaminants are removed, thereby improving the cleanliness and reliability of the semiconductor structure.

[0095] Optionally, the semiconductor structure manufacturing method of this embodiment may further include the step of forming a support layer on the bottom surface of the semiconductor structure. Fig.13 , metal electrode layers 107 are formed in the areas corresponding to the low-resistance silicon pillars 101, and a third insulating layer 108 is formed around the metal electrode layer 107. The metal electrode layer 107 is connected to the low-resistance silicon pillars 101 to achieve electrical connectivity between the two. The third insulating layer 108 is located between the metal electrode layers 107 to achieve mutual insulation between the various parts of the electrode layers, thereby ensuring the electrical reliability of the semiconductor structure. Specifically, the material of the metal electrode layer 107 is one or a combination of platinum, molybdenum, gold, silver or aluminum. The material of the third insulating layer 108 can be a combination of one or more of silicon oxide, silicon nitride, titanium oxide, etc.

[0096] For further information, see Fig.12a , which is a scanning electron microscope image of a cross section of a low-resistance silicon TSV structure obtained by the above method. Fig.12a It can be seen that the annular insulating layer 109 includes the first insulating layer 104 and the second insulating layer 106. In the lateral direction of the low-resistance silicon TSV structure, the insulating material in the annular ring (i.e., the top surface of the annular insulating layer 109) is filled evenly without obvious gaps. For further information, please refer to Figure 12b , which is a scanning electron microscope image of a longitudinal section of a low-resistance silicon TSV structure obtained by the above method. Figure 12b It can be seen that the annular insulating layer 109 in the annular groove 102 is filled uniformly without obvious filling sections and gaps, and the annular insulating layer 109 forms a good interface bond with the substrate 100 and the low-resistance silicon pillar 101; the surface is filled completely. The manufacturing method of the semiconductor structure of this embodiment significantly improves the uniformity and integrity of the low-resistance silicon TSV insulating layer filling, and improves the reliability in practical applications.

[0097] Embodiment 2

[0098] This embodiment provides a semiconductor structure, which is manufactured by the method for manufacturing the semiconductor structure described in the first embodiment.

[0099] Specifically, refer to Fig.13The semiconductor structure includes a substrate 100, a low-resistance silicon TSV structure, and a support layer located at the bottom of the low-resistance silicon TSV structure. Also, refer to 3, the substrate 100 includes a top surface and a bottom surface. Also, refer to Fig.12a and Figure 12b The low-resistance silicon TSV structure of this embodiment includes a substrate 100, a low-resistance silicon column 101 formed on the substrate 100, and an annular insulating layer 109 formed around the low-resistance silicon column 101 and wrapping the low-resistance silicon column 101. The annular insulating layer 109 includes a first insulating layer 104 and a second insulating layer 106. The height of the annular insulating layer 109 is greater than or equal to 5 times the diameter length of the annular groove 102, and the diameter length of the annular groove 102 is less than or equal to 3 / 2 times the diameter length of the low-resistance silicon column 101. Please also refer to Fig.13 The supporting layer includes a metal electrode layer 107 located in a region corresponding to the low-resistance silicon pillar 101 and a third insulating layer 108 surrounding the metal electrode layer 107 .

[0100] The low-resistance silicon TSV substrate can be one of single crystal silicon, polycrystalline silicon or amorphous silicon. In this embodiment, single crystal silicon is used as the substrate material; the first filling liquid is a mixed solution containing tetraethyl silicate and an organic solvent, wherein the concentration range of tetraethyl silicate is: 15% to 50%. In this embodiment, the first filling liquid used is a mixed solution containing 56% C2H6O+38% tetraethyl silicate; the second filler is a solid powder containing nano silicon particles, and the diameter range of the nano silicon particles is 20nm to 1μm. In this embodiment, the second filler is a solid powder containing nano silicon particles with a diameter of 30nm; the material of the metal electrode layer is one or a combination of platinum, molybdenum, gold, silver or aluminum.

[0101] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The following steps are involved: Providing a semiconductor substrate, the substrate comprising a top surface and a bottom surface arranged opposite to each other; An annular groove is formed in the substrate from the top surface to the bottom surface, and a low-resistance silicon column formed by the substrate is located in the middle of the annular groove; Performing a first filling on the annular groove: providing a first filling liquid, and filling the annular groove with the first filling liquid under a certain negative pressure condition; solidifying the first filling liquid to form a first insulating layer; Performing a second filling on the annular groove: providing a second filler, and filling the second filler in the annular groove formed with the first insulating layer; The second filler is oxidized to form a second insulating layer. The first insulating layer and the second insulating layer constitute an annular insulating layer. The annular insulating layer wraps the low-resistance silicon pillars so that the low-resistance silicon pillars are insulated from each other.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The first filling of the annular groove further comprises the following steps: heating the first filling liquid so that the first filling liquid solidifies; The semiconductor structure is first polished from the top surface to remove the first insulating layer remaining on the top surface.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: The second filling of the annular groove further comprises the following steps: Performing a second polishing on the semiconductor structure from the top surface to remove the second insulating layer remaining on the top surface; The semiconductor structure is thinned from the bottom surface until the first insulating layer is exposed.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: The first filling liquid is a mixed solution containing tetraethyl silicate, and the concentration of the tetraethyl silicate in the first filling liquid ranges from 15% to 50%.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The height of the annular groove is greater than or equal to 5 times the diameter length of the annular groove, and the diameter length of the annular groove is less than or equal to 3 / 2 times the diameter length of the low-resistance silicon column.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The temperature range for performing the first filling is 50° C. to 200° C., and the pressure range for forming the certain negative pressure condition is -50 kPa to -96 kPa.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The second filler is a solid powder containing nano silicon particles, and the diameter of the nano silicon particles ranges from 20 nm to 1 μm.

8. The method for manufacturing a semiconductor structure according to claim 2, wherein: The first filling liquid is heated at a temperature ranging from 150° C. to 600° C. and a heating time greater than or equal to 1 hour.

9. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: After the semiconductor structure is polished for the second time on the top surface, the roughness of the top surface of the semiconductor structure is within ±1 μm.

10. The method for manufacturing a semiconductor structure according to claim 1, wherein: Also includes: Cleaning the semiconductor structure; The cleaned semiconductor structure is dried.

11. The method for manufacturing a semiconductor structure according to claim 1, wherein: Also includes: forming a metal electrode layer connected to the low-resistance silicon column below the low-resistance silicon column; A third insulating layer is formed between below the annular groove and below the metal electrode layer.

12. A semiconductor structure formed by the semiconductor structure manufacturing method according to any one of claims 1 to 11, characterized in that: include: a substrate, the substrate comprising a top surface and a bottom surface; A low-resistance silicon TSV structure, comprising a low-resistance silicon column formed on the substrate and an annular insulating layer located around the low-resistance silicon column, wherein the annular insulating layer comprises the first insulating layer and the second insulating layer; The support layer is located on the bottom surface of the substrate and includes a metal electrode layer formed below the low-resistance silicon column and a third insulating layer located between below the annular groove and below the metal electrode layer.

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