Power device and method for reducing parasitic PNP effect thereof
By using voltage difference and doped region structure to block hole diffusion in the LDMOS power device, the parasitic PNP effect problem caused by reverse current in the prior art is solved, and the reliability and performance of the device are improved.
Patent Information
- Application Number
- CN202410546102.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-30
- Publication Date
- 2024-12-10
AI Technical Summary
Existing LDMOS power devices may cause parasitic PNP effects due to reverse current when switching, which will damage device performance.
Design K LDMOS structure power devices in P-type substrates. The source of each transistor is in the P-type well and the drain is in the N-type well. The voltage difference is used to block the holes in the P-type well in the N-type well. and a P-type well and an N-type heavily doped region are provided in the N-type well to collect and block holes, and the voltage difference is controlled to reduce the parasitic PNP effect.
It effectively reduces the parasitic PNP effect in power devices, improves the reliability and performance of the device, and avoids damage caused by parasitic PNP effect.
Smart Images
Figure CN119108395A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor devices, and in particular to a power device and a method for reducing the parasitic PNP effect thereof. Background Art
[0002] When the power device is turned on in the switching power supply, half-bridge driver and other chips, the excessive reverse current may turn on its body diode and form a parasitic PNP effect. LDMOS is a commonly used power device in the prior art, such as Figure 1 As shown, it is a simplified structural schematic diagram of an existing LDMOS device, the LDMOS device is made in a P-type substrate Psub, the source S1 of the LDMOS device is made in a P-type well PW, the drain D1 is made in an N-type well NW, the gate G1 is arranged between the source S1 and the drain D1, an N-type buried layer NBL is arranged on the P-type substrate Psub, the P-type well PW and the N-type well NW are arranged on the N-type buried layer NBL; when the voltage between the source S1 and the drain D1 is greater than a certain value so that the body diode of the LDMOS device is turned on, a parasitic PNP ( Figure 1 ), the parasitic PNP effect of the lateral parasitic may affect the performance of the LDMOS device and may even cause destructive damage to the LDMOS device. Figure 2 FIG. 1 is a simplified structural diagram of another LDMOS device in the prior art. The LDMOS device includes two transistors. S1, G1 and D1 constitute transistor 1, S2, G2 and D2 constitute transistor 2, and S1 and S2 share a P-type well PW. Figure 1 In the same principle, when the body diodes in transistor 1 and transistor 2 are turned on, a parasitic PNP is formed. Therefore, it is necessary to improve the problems existing in the prior art to reduce the influence of the parasitic PNP on the LDMOS device. Summary of the invention
[0003] In order to solve the above technical problems, the present invention provides a power device and a method for reducing the parasitic PNP effect thereof.
[0004] According to a first aspect of the present invention, a method for reducing a parasitic PNP effect of a power device is provided, wherein the power device is fabricated in a P-type substrate, the power device comprises K transistors, the K transistors are all LDMOS structures, the source of each transistor is formed in a P-type well, and the drain of each transistor is formed in an N-type well; K is a natural number greater than or equal to 1; and the method is characterized in that:
[0005] When a body diode between a source and a drain of a transistor located at an edge of the power device is turned on, a voltage difference is controlled to exist between a second position and a first position in the N-type well, and diffusion of holes in the P-type well is blocked based on the voltage difference, so as to reduce a parasitic PNP effect in the power device;
[0006] The first position is the position of the drain of the transistor located at the edge of the power device; in the N-type well, the distance between the second position and the edge of the power device is smaller than the distance between the first position and the edge of the power device.
[0007] Optionally, the voltage at the second position is greater than the voltage at the first position.
[0008] Optionally, a first P-type well is provided between the N-type wells at the first position and the second position to collect holes diffused from the P-type well; the first P-type well is connected to the drain of the transistor located at the edge of the power device.
[0009] Optionally, a first N-type heavily doped region is provided at the second position, and the first N-type heavily doped region is connected to the drain of the first transistor, the gate of the first transistor is connected to the gate of the transistor located at the edge of the power device, and the source of the first transistor is connected to the source of the transistor located at the edge of the power device;
[0010] When the body diode between the source and drain of the transistor located at the edge of the power device is turned on, the first transistor is turned on based on the gate control of the first transistor, so that the voltage at the second position is approximately equal to the voltage at the source of the transistor located at the edge of the power device.
[0011] Optionally, the first transistor is of LDMOS structure, and the power device and the first transistor are combined into one device.
[0012] Optionally, an N-type buried layer is provided on the P-type substrate, and the P-type well and the N-type well are all or partially provided on the N-type buried layer; or,
[0013] The N-type well is disposed on the P-type substrate, and the P-type well is disposed on the P-type substrate or in the N-type well.
[0014] Optionally, the first position is spaced apart from the second position by a distance of 1 or 2 interdigitated structures.
[0015] The present invention also provides a power device, which is fabricated in a P-type substrate, and includes K transistors, all of which are LDMOS structures, a source of each transistor is formed in a P-type well, and a drain of each transistor is formed in an N-type well; K is a natural number greater than or equal to 1; and is characterized in that:
[0016] The power device further includes a first transistor; a first N-type heavily doped region is disposed at a second position in the N-type well, and the first N-type heavily doped region is connected to a drain of the first transistor, a gate of the first transistor is connected to a gate of a transistor located at an edge of the power device, and a source of the first transistor is connected to a source of a transistor located at an edge of the power device;
[0017] The first position is the position of the drain of the transistor located at the edge of the power device; in the N-type well, the distance between the second position and the edge of the power device is smaller than the distance between the first position and the edge of the power device.
[0018] Optionally, a first P-type well is further provided between the drain of the transistor located at the edge of the power device and the N-type well where the first N-type heavily doped region is located; the first P-type well is connected to the drain of the transistor located at the edge of the power device.
[0019] Optionally, when the body diode between the source and drain of the transistor located at the edge of the power device is turned on, the first transistor is turned on based on the gate control of the first transistor, so that the voltage at the second position is approximately equal to the voltage at the source of the transistor located at the edge of the power device.
[0020] Optionally, an N-type buried layer is provided on the P-type substrate, and the P-type well and the N-type well are all or partially provided on the N-type buried layer; or,
[0021] The N-type well is disposed on the P-type substrate, and the P-type well is disposed on the P-type substrate or in the N-type well.
[0022] Optionally, the first position is spaced apart from the second position by a distance of 1 or 2 fingers.
[0023] The beneficial effects of the present invention include at least:
[0024] In summary, the power device and the method for reducing the parasitic PNP effect thereof provided by the present invention are fabricated in a P-type substrate, and include K transistors, all of which are LDMOS structures, the source of each transistor is formed in a P-type well, and the drain of each transistor is formed in an N-type well; K is a natural number greater than or equal to 1; when the body diode between the source and the drain of the transistor located at the edge of the power device is turned on, in the N-type well, a voltage difference is controlled between the second position and the first position, and the diffusion of holes in the P-type well is blocked based on the voltage difference to reduce the parasitic PNP effect in the power device; wherein the first position is the position where the drain of the transistor located at the edge of the power device is located; in the N-type well, the distance between the second position and the edge of the power device is less than the distance between the first position and the edge of the power device. The present invention can reduce the parasitic PNP effect in the power device through the above-mentioned setting, and improve the reliability of the power device.
[0025] Furthermore, a first P-type well is provided between the first position and the N-type well where the second position is located to collect holes diffused from the P-type well; the first P-type well is connected to the drain of the transistor located at the edge of the power device. The parasitic PNP effect can be further reduced by providing the first P-type well.
[0026] Furthermore, the first transistor is an LDMOS structure, and the power device and the first transistor can be combined into one device.
[0027] Furthermore, the first position and the second position are arranged at a distance of 1 or 2 fingers apart to avoid increasing the distance between the two so as to make the device larger in size and be disadvantageous for integration.
[0028] Furthermore, the power device provided by the present invention is provided with a first N-type heavily doped region at the second position, and the first N-type heavily doped region is connected to the drain of the first transistor, the gate of the first transistor is connected to the gate of the transistor located at the edge of the power device, and the source of the first transistor is connected to the source of the transistor located at the edge of the power device; by controlling the gate of the first transistor, when the body diode between the source and the drain of the transistor located at the edge of the power device is turned on, the first transistor is controlled to be turned on to be in the on state, so that the voltage at the second position is nearly equal to the voltage at the source of the transistor located at the edge of the power device. By this arrangement, the voltage difference between the second position and the first position is obtained, and then the holes diffused from the P-type well PW where the source is located are blocked to reduce the parasitic PNP effect.
[0029] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1A simplified structural schematic diagram of an LDMOS device in the prior art is shown;
[0031] Figure 2 Another simplified structural schematic diagram of an LDMOS device in the prior art is shown;
[0032] Figure 3 The present invention provides a method for reducing Figure 1 Schematic diagram of the parasitic PNP effect of the LDMOS device structure;
[0033] Figure 4 Another method for reducing the Figure 1 Schematic diagram of the parasitic PNP effect of the LDMOS device structure;
[0034] Figure 5 The present invention provides a method for reducing Figure 2 Schematic diagram of the parasitic PNP effect of the LDMOS device structure;
[0035] Figure 6 Another method for reducing the Figure 2 Schematic diagram of the parasitic PNP effect of the LDMOS device structure;
[0036] Figure 7 A power device provided by the present invention and a schematic diagram for reducing its parasitic PNP effect are shown;
[0037] Figure 8 Another power device provided by the present invention and a schematic diagram for reducing its parasitic PNP effect are shown;
[0038] Fig. 9 A simplified top view of a power device provided by the present invention is shown;
[0039] Fig.10 Another simplified top view of the power device provided by the present invention is shown. DETAILED DESCRIPTION
[0040] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are given in the drawings. However, the present invention can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.
[0041] Figure 1-Figure 2It is just a simple schematic diagram of the structure of an LDMOS device in the prior art. The arrangement of each part of the structure is not limited to the arrangement in the figure. For example, the P-type well PW can also be arranged in the N-type well NW; the N-type buried layer NBL can also be omitted, and a relatively deep N-well can be directly arranged on the P-type substrate, and the LDMOS device can be made in the N-well; another N-type well NW1 can also be made in the NW, and the doping concentration of NW1 can be different from that of NW, and the drain of the LDMOS can be made in NW1. In this article, for the sake of convenience, NW1 and NW are uniformly referred to as N-type wells. Whether NW1 is specifically arranged can be arranged according to actual conditions. In the above modified embodiments, when the body diode of the LDMOS device is turned on, a parasitic PNP will be formed, which will affect the performance of the device.
[0042] The present invention provides a method for reducing the parasitic PNP effect of a power device. When the body diode between the source and the drain of a transistor located at the edge of the power device is turned on, in an N-type well, a voltage difference is set between a second position and a first position, and the voltage at the second position is greater than the voltage at the first position. Based on the voltage difference, the diffusion of holes in the P-type well PW is blocked to reduce the parasitic PNP effect in the power device. The first position is the position where the drain of the transistor located at the edge of the power device is located. In the N-type well, the second position is closer to the edge of the power device than the first position, that is, the distance between the second position and the edge of the power device is less than the distance between the first position and the edge of the power device. The power device is an LDMOS structure.
[0043] Furthermore, a first P-type well is provided between the N-type wells at the first position and the second position, and the first P-type well is connected to the drain of the transistor located at the edge of the power device; the first P-type well is used to absorb holes diffused from the P-type well PW to further reduce the effect of parasitic PNP.
[0044] Specifically, Figure 3 The present invention provides a method for reducing Figure 1 The schematic diagram of the parasitic PNP effect of the LDMOS device in FIG. 1 shows a first N-type heavily doped region in the N-type well. Figure 3In the figure, N+ is used to represent the position where the first N-type heavily doped region is located, and the position where the drain D1 is located is considered as the first position; and a first transistor M0 is provided, the gate of the first transistor M0 is connected to the gate G1 of the LDMOS device, the source of the first transistor M0 is connected to the source S1 of the LDMOS device, and the drain of the first transistor M0 is connected to the first N-type heavily doped region. By controlling the gate of the first transistor M0, when the body diode between the source S1 and the drain D1 of the LDMOS device is turned on due to some external factors, such as reverse current or a certain voltage, the first transistor M0 is controlled to be in the on state. At this time, the voltage V1 on the first N-type heavily doped region is nearly equal to the voltage of the source S1 of the first transistor M0 or the LDMOS device, then the voltage V1 is greater than the voltage on the drain D1 of the LDMOS device, and there is a voltage between the first N-type heavily doped region and the drain D1. Figure 3 The electric field E shown in the figure can block the diffusion of holes in the P-type well PW to the N-type well, thereby reducing the lateral parasitic PNP effect. At the same time, the electric field will also pass through the N-type buried layer NBL, which can also block the diffusion of holes into the N-type buried layer NBL to reduce the lateral parasitic PNP effect. At this time, it will also have a certain inhibitory effect on the vertical parasitic PNP.
[0045] Further, Figure 4 Another method for reducing the Figure 1 The schematic diagram of the parasitic PNP effect of the LDMOS device in Figure 3 The difference is that another P-type well PW1 (which can be regarded as the first P-type well) is provided between the first N-type heavily doped region and the N-type well NW where the drain D1 is located, and the P-type well PW1 is connected to the drain D1. By providing the first P-type well PW1, it can be used to collect holes diffused laterally from the PW, thereby further reducing the lateral parasitic PNP effect. Similarly, based on the voltage difference between the voltage V1 and the drain D1, an electric field can be formed from the N-type well NW where the first N-type heavily doped region is located through the N-type buried layer NBL to the drain D1 to block the diffusion of holes, thereby reducing the lateral parasitic PNP effect, and also has a certain inhibitory effect on the longitudinal parasitic PNP.
[0046] Among them, Figure 3-Figure 4 The first position and the second position can be set at a distance of 1 or 2 forked fingers, and of course, they can also be set to other distances. In this article, they are set to a distance of 1 or 2 forked fingers (a forked finger is also called a finger, which means that the transistor is made into a forked finger shape, which is a common transistor structure in the layout, such as Fig. 9 or Fig.10 L1 in the figure can be regarded as the distance of a fork finger), which can avoid the large distance between the two making the device size larger and not conducive to integration.
[0047] Figure 5 The present invention provides a method for reducing Figure 2 Schematic diagram of the parasitic PNP effect of LDMOS device, Figure 5 The LDMOS device includes transistor 1 and transistor 2, that is, transistor 1 and transistor 2 are equivalent to one LDMOS; for a single transistor 1 or transistor 2, the method for reducing the parasitic PNP effect is the same as Figure 3 The same as in the embodiment, here transistor 1 and transistor 2 share the first transistor M0 to achieve the reduction of parasitic PNP effect.
[0048] Figure 6 Another method for reducing the Figure 2 The schematic diagram of the parasitic PNP effect of the LDMOS device in FIG. 1 is similar to the method of reducing the parasitic PNP effect for a single transistor 1 and transistor 2. Figure 4 The same as in FIG. 1 , here transistor 1 and transistor 2 share the first transistor M0 to achieve the effect of reducing the parasitic PNP.
[0049] Figure 3-Figure 6 The power devices are respectively Figure 1 or Figure 2 The structure in is used as an example to illustrate. Figure 7 FIG. 1 is another schematic diagram of the present invention for reducing the parasitic PNP effect of a power device, which is different from FIG. Figure 3-Figure 6 Here, the power device can be composed of multiple Figure 1 In or Figure 2 The structure of the LDMOS device is composed of multiple transistors equivalent to a power device (when using Figure 2 When the structure is shown in Figure 1, an LDMOS can be considered to include two transistors); Figure 7 The figure shows that the power device includes K transistors, where the specific value of K can be set according to the actual situation. Figure 7 In the figure, transistor 1 and transistor K are used as examples. In the N-type well where the drain D1 of transistor 1 or the drain DK of transistor K is located, a first heavily doped region is provided near the edge of the power device, and transistor 1 and transistor K share a first transistor M0. Figure 7 The principle of reducing the parasitic PNP effect can be referred to the above description and will not be repeated here.
[0050] Figure 8 FIG. 1 is another schematic diagram of the present invention for reducing the parasitic PNP effect in a power device. Figure 7 Here, the power device can be composed of multiple Figure 1In or Figure 2 The structure of the LDMOS device is Figure 7 The difference is that a first P-type well PW1 is provided between the first heavily doped region N+ and the N-type well where the drain D1 of transistor 1 or the drain DK of transistor K is located, and PW1 is provided to absorb holes diffused laterally to further reduce the parasitic PNP effect.
[0051] It should be noted that for Figure 5-Figure 8 For example, as another embodiment of the present invention, the first transistor M0 may not be shared, that is, one M0 is provided for each to respectively reduce the parasitic PNP effect of the transistor at the edge of the power device. In addition, as described above, Figure 3-Figure 8 The arrangement of the various structures in the figure is not limited to the arrangement in the figure. For example, the P-type well PW can also be arranged in the N-type well NW; the N-type buried layer NBL can also be omitted, and a relatively deep N-well can be directly arranged on the P-type substrate, and the LDMOS device can be made in the N-well; another N-type well NW1 can also be made in the NW, and the doping concentration of NW1 can be different from that of NW, and the drain of the LDMOS is made in NW1. At this time, for the sake of convenience, NW1 and NW are uniformly referred to as N-type wells. Whether to set NW1 can be set according to actual conditions; the length of the N-type buried layer NBL can also be set according to actual conditions.
[0052] Fig. 9 FIG. 1 is a top view of a power device provided by the present invention, in which the power device is composed of a plurality of transistors. Figure 1 In or Figure 2 The structure of the LDMOS device in the power device is composed of the following: the specific number can be set according to the actual situation. The LDMOS device is made in a P-type substrate Psub, where the substrate outside the device is represented by Psub. In the N-type well NW at the edge of the power device, a first heavily doped region N+ is set. Here, the first heavily doped region N+ is set in a ring shape and is closer to the edge of the entire device than the drain of the transistor at the edge of the power device. According to the above description, it can be made in the P-type well PW and the N-type well NW. Figure 1 In or Figure 2 The structure of the LDMOS device shown in FIG. The first transistor M0 may also be composed of one or more Figure 1 In or Figure 2 It is equivalent to the structure of the LDMOS device in . Fig. 9 In the figure, a Figure 1 In or one Figure 2The structure of the LDMOS device in the middle is used as the first transistor M0, and the rest are equivalent to another device, which can be used as a power switch device or a device with other functions. Among them, the first transistor M0 is preferably set as an LDMOS device located near the middle position. Fig. 9 It can be seen from the figure that the present invention can combine the first transistor M0 with the power device whose parasitic PNP effect is to be reduced.
[0053] Fig.10 Another top view of the power device provided by the present invention is shown. Fig. 9 The difference is that a first P-type well PW1 is provided between the N-type well NW where the drain of the transistor at the edge of the power device is located and the N-type well NW where the first heavily doped region N+ is located, for absorbing laterally diffused holes to further reduce the parasitic PNP effect.
[0054] In summary, the power device and the method for reducing its parasitic PNP effect provided by the present invention are fabricated in a P-type substrate, and include K transistors, all of which are LDMOS structures, the source of each transistor is formed in a P-type well, and the drain of each transistor is formed in an N-type well; K is a natural number greater than or equal to 1; when the body diode between the source and the drain of the transistor located at the edge of the power device is turned on, in the N-type well, a voltage difference is controlled between the second position and the first position, and the voltage at the second position is greater than the voltage at the first position, and the diffusion of holes in the P-type well is blocked based on the voltage difference to reduce the parasitic PNP effect in the power device; wherein the first position is the position where the drain of the transistor located at the edge of the power device is located; in the N-type well, the distance between the second position and the edge of the power device is less than the distance between the first position and the edge of the power device. The present invention can reduce the parasitic PNP effect in the power device through the above-mentioned setting, and improve the reliability of the power device.
[0055] Furthermore, a first P-type well is provided between the first position and the N-type well where the second position is located to collect holes diffused from the P-type well; the first P-type well is connected to the drain of the transistor located at the edge of the power device. The parasitic PNP effect can be further reduced by providing the first P-type well.
[0056] Furthermore, the first transistor is an LDMOS structure, and the power device and the first transistor can be combined into one device.
[0057] Furthermore, the first position and the second position are arranged at a distance of 1 or 2 fingers apart to avoid increasing the distance between the two so as to make the device larger in size and be disadvantageous for integration.
[0058] Furthermore, the power device provided by the present invention is provided with a first N-type heavily doped region at the second position, and the first N-type heavily doped region is connected to the drain of the first transistor, the gate of the first transistor is connected to the gate of the transistor located at the edge of the power device, and the source of the first transistor is connected to the source of the transistor located at the edge of the power device; by controlling the gate of the first transistor, when the body diode between the source and the drain of the transistor located at the edge of the power device is turned on, the first transistor is controlled to be turned on to be in the on state, so that the voltage at the second position is nearly equal to the voltage at the source of the transistor located at the edge of the power device. By this arrangement, the voltage difference between the second position and the first position is obtained, and then the holes diffused from the P-type well PW where the source is located are blocked to reduce the parasitic PNP effect.
[0059] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present invention.
Claims
1. A method for reducing parasitic PNP effect of a power device, wherein the power device is fabricated in a P-type substrate, the power device comprises K transistors, the K transistors are all LDMOS structures, the source of each transistor is formed in a P-type well, and the drain of each transistor is formed in an N-type well; K is a natural number greater than or equal to 1; characterized in that, When a body diode between a source and a drain of a transistor located at an edge of the power device is turned on, a voltage difference is controlled to exist between a second position and a first position in the N-type well, and diffusion of holes in the P-type well is blocked based on the voltage difference, so as to reduce a parasitic PNP effect in the power device; The first position is the position where the drain of the transistor located at the edge of the power device is located; In the N-type well, a distance between the second position and an edge of the power device is smaller than a distance between the first position and the edge of the power device.
2. The method for reducing parasitic PNP effect of power device according to claim 1, characterized in that: The voltage at the second position is greater than the voltage at the first position.
3. The method for reducing parasitic PNP effect of power device according to claim 1, characterized in that: A first P-type well is provided between the N-type wells at the first position and the second position to collect holes diffused from the P-type well; the first P-type well is connected to the drain of the transistor located at the edge of the power device.
4. The method for reducing parasitic PNP effect of power device according to claim 1, characterized in that: A first N-type heavily doped region is provided at the second position, and the first N-type heavily doped region is connected to the drain of the first transistor, the gate of the first transistor is connected to the gate of the transistor located at the edge of the power device, and the source of the first transistor is connected to the source of the transistor located at the edge of the power device; When the body diode between the source and drain of the transistor located at the edge of the power device is turned on, the first transistor is turned on based on the gate control of the first transistor, so that the voltage at the second position is approximately equal to the voltage at the source of the transistor located at the edge of the power device.
5. The method for reducing parasitic PNP effect of power device according to claim 4, characterized in that: The first transistor is of LDMOS structure, and the power device and the first transistor are combined into one device.
6. The method for reducing parasitic PNP effect of a power device according to any one of claims 1 to 5, characterized in that: An N-type buried layer is disposed on the P-type substrate, and the P-type well and the N-type well are entirely or partially disposed on the N-type buried layer; or, The N-type well is disposed on the P-type substrate, and the P-type well is disposed on the P-type substrate or in the N-type well.
7. The method for reducing parasitic PNP effect of a power device according to any one of claims 1 to 5, characterized in that: The first position is set to be separated from the second position by a distance of 1 or 2 fingers.
8. A power device, wherein the power device is fabricated in a P-type substrate, the power device comprises K transistors, the K transistors are all LDMOS structures, the source of each transistor is formed in a P-type well, and the drain of each transistor is formed in an N-type well; K is a natural number greater than or equal to 1; characterized in that, The power device further includes a first transistor; a first N-type heavily doped region is disposed at a second position in the N-type well, and the first N-type heavily doped region is connected to a drain of the first transistor, a gate of the first transistor is connected to a gate of a transistor located at an edge of the power device, and a source of the first transistor is connected to a source of a transistor located at an edge of the power device; The first position is the position where the drain of the transistor located at the edge of the power device is located; In the N-type well, a distance between the second position and an edge of the power device is smaller than a distance between the first position and the edge of the power device.
9. The power device according to claim 8, characterized in that: A first P-type well is also provided between the drain of the transistor located at the edge of the power device and the N-type well where the first N-type heavily doped region is located; the first P-type well is connected to the drain of the transistor located at the edge of the power device.
10. The power device according to claim 8, characterized in that: When the body diode between the source and drain of the transistor located at the edge of the power device is turned on, the first transistor is turned on based on the gate control of the first transistor, so that the voltage at the second position is approximately equal to the voltage at the source of the transistor located at the edge of the power device.
11. The power device according to any one of claims 8 to 10, characterized in that: An N-type buried layer is disposed on the P-type substrate, and the P-type well and the N-type well are entirely or partially disposed on the N-type buried layer; or, The N-type well is disposed on the P-type substrate, and the P-type well is disposed on the P-type substrate or in the N-type well.
12. The power device according to any one of claims 8 to 10, characterized in that: The first position is spaced apart from the second position by a distance of 1 or 2 fingers.