Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device may be provided including: a substrate including a first region and a second region; a first active pattern extending in a first direction on the first region; a second active pattern extending in the first direction on the second region; a wall structure extending in the first direction between the first region and the second region, and separating the first active pattern and the second active pattern from each other; a first gate structure intersecting the first active pattern on the first region; a first two-dimensional (2D) channel layer between the first active pattern and the first gate structure, including a first transition metal disulfide; a second gate structure intersecting the second active pattern on the second region; and a second 2D channel layer between the second active pattern and the second gate, including a second transition metal dichalcogenide.

Description

[0001] This application claims priority to and all the benefits of Korean Patent Application No. 10-2023-0074150 filed in the Korean Intellectual Property Office on June 9, 2023, and Korean Patent Application No. 10-2023-0136700 filed in the Korean Intellectual Property Office on October 13, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor device and / or a method for manufacturing the semiconductor device, and more particularly, to a semiconductor device using a two-dimensional semiconductor material as a channel and / or a method for manufacturing the semiconductor device. Background Art

[0003] As one of scaling technologies for increasing the density of integrated circuit devices, a multi-gate transistor has been proposed in which a fin-shaped or nanowire-shaped silicon body is formed on a substrate and a gate is formed on a surface of the silicon body.

[0004] Since this multi-gate transistor uses a three-dimensional channel, it is easy to perform scaling. In addition, even if the gate length of the multi-gate transistor is not increased, the current control capability can be improved. In addition, the short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed.

[0005] Meanwhile, as a method of improving the performance of semiconductor devices by improving mobility and short channel effect (SCE), semiconductor devices using a two-dimensional semiconductor material as a channel are being studied. Summary of the invention

[0006] Some example embodiments of the present disclosure provide semiconductor devices with improved performance.

[0007] Some example embodiments of the present disclosure provide methods for manufacturing a semiconductor device having improved performance.

[0008] However, exemplary embodiments of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] According to an example embodiment conceived in the present invention, a semiconductor device includes: a substrate including a first region and a second region; a first active pattern extending along a first direction on the first region; a second active pattern extending along the first direction on the second region; a wall structure extending along the first direction between the first region and the second region and separating the first active pattern and the second active pattern from each other; a first gate structure intersecting the first active pattern on the first region; a first two-dimensional (2D) channel layer between the first active pattern and the first gate structure, including a first transition metal dichalcogenide; a second gate structure intersecting the second active pattern on the second region; and a second 2D channel layer between the second active pattern and the second gate, including a second transition metal dichalcogenide.

[0010] According to an example embodiment of the present invention, a semiconductor device includes: a substrate; a wall structure extending along a first direction on the substrate; a first sheet pattern extending along the first direction on an upper surface of the substrate and a side surface of the wall structure; a second sheet pattern extending along the first direction on an upper surface of the first sheet pattern and a side surface of the wall structure; a seed layer on a side surface of the wall structure between the first sheet pattern and the second sheet pattern and including a transition metal element; a two-dimensional (2D) channel layer extending from the seed layer along a surface of the first sheet pattern and a surface of the second sheet pattern, the 2D channel layer including a transition metal dichalcogenide, the transition metal dichalcogenide including a transition metal element; and a gate structure intersecting the first sheet pattern and the second sheet pattern and the gate structure on the 2D channel layer.

[0011] According to an example embodiment of the inventive concept, a semiconductor device includes: a substrate including a first region and a second region; a first active pattern including a plurality of first bridge patterns sequentially stacked on the first region, spaced apart from each other and respectively extending along a first direction; a second active pattern including a plurality of second bridge patterns sequentially stacked on the second region, spaced apart from each other and respectively extending along the first direction; a wall structure extending along the first direction between the first region and the second region and separating the first active pattern and the second active pattern from each other; a first seed layer including an oxide of a transition metal element on a first side surface of the wall structure between each adjacent pair of each of the plurality of first bridge patterns, a first two-dimensional (2D) channel layer extending from the first seed layer along each of the plurality of first bridge patterns; The invention relates to a first 2D channel layer, comprising a first transition metal dichalcogenide and a transition metal element, wherein the first gate structure intersects each of the plurality of first bridge patterns and is located on the first 2D channel layer; a second seed layer comprises an oxide of the transition metal element on the second side surface of the wall structure between each adjacent pair of the plurality of second bridge patterns; a second 2D channel layer extends from the second seed layer along the surface of each second bridge pattern of the plurality of second bridge patterns, wherein the second 2D channel layer comprises a second transition metal dichalcogenide and the transition metal element; and a second gate structure intersects each of the plurality of second bridge patterns and is located on the second 2D channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects and features of the present disclosure will become more apparent by describing in detail some example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0013] Figure 1 is a layout diagram for describing a semiconductor device according to example embodiments.

[0014] Figure 2 is along Figure 1 A cross-sectional view taken along line AA.

[0015] Figure 3 Is used to describe Figure 2 Magnified view of regions R1 and R2.

[0016] Figure 4 is along Figure 1 A cross-sectional view taken along line BB.

[0017] Figure 5 is along Figure 1 Cross-sectional view taken along line CC.

[0018] Figures 6 to 10is used to describe the Figure 2 Various magnified views of regions R1 and R2.

[0019] Fig.11 and Fig.12 are other various cross-sectional views for describing semiconductor devices according to some example embodiments.

[0020] Figure 13 to Figure 43 are diagrams for describing intermediate steps of a method for manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0021] The terms "first", "second", etc. are used herein to describe various elements or components, but these elements or components are not limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, within the technical spirit of the present disclosure, the first element or component mentioned below can be a second element or component.

[0022] In addition, in this specification, the term "same" is intended to include not only completely the same meaning but also slight differences that may occur due to a margin in a process or the like.

[0023] In other words, although the terms "same", "equal" or "identical" are used in the description of the example embodiments, it should be understood that some imprecision may exist. Therefore, when one element is referred to as being the same as another element, it should be understood that the element or value is the same as the other element within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0024] When the term "about" or "substantially" is used in conjunction with a numerical value in this specification, the associated numerical value is intended to include a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "about" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the tolerance for the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified to "about" or "substantially", it should be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape.

[0025] As used herein, expressions such as "at least one" preceding a list of elements modify the entire list of elements and do not modify the individual elements of the list. Thus, for example, "at least one of A, B, or C" and "at least one of A, B, and C" both mean A, B, C, or any combination thereof. Likewise, A and / or B means A, B, or A and B.

[0026] In the following, reference will be made to Figures 1 to 12 Semiconductor devices according to some example embodiments are described.

[0027] Figure 1 is a layout diagram for describing a semiconductor device according to example embodiments. Figure 2 is along Figure 1 A cross-sectional view taken along line AA. Figure 3 Is used to describe Figure 2 Magnified view of regions R1 and R2. Figure 4 is along Figure 1 A cross-sectional view taken along line BB. Figure 5 is along Figure 1 Cross-sectional view taken along line CC.

[0028] Reference Figures 1 to 5 , a semiconductor device according to example embodiments may include a substrate 100, a first active pattern AP1, a second active pattern AP2, a first insulating pattern 104, a second insulating pattern 204, a field insulating film 106, a wall structure 102, a first seed layer 122, a second seed layer 222, a first two-dimensional (2D) channel layer 124, a second 2D channel layer 224, a first gate structure GS1, a second gate structure GS2, a first gate spacer 140, a second gate spacer 240, a first source / drain pattern 160, a second source / drain pattern 260, an interlayer insulating film 180, a first gate contact CB1, and a second gate contact CB2.

[0029] The substrate 100 may be bulk silicon or silicon on insulator (SOI). Different from this, the substrate 100 may also be a silicon substrate, or may also include other materials, such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In some example embodiments, the substrate 100 may also have an epitaxial layer formed on a base substrate. For ease of explanation, in the following description, the substrate 100 will be described as a silicon substrate.

[0030] The substrate 100 may include a first region I and a second region II. The first region I and the second region II may be regions separated from each other around a wall structure 102 described later. For example, the wall structure 102 may extend in a first direction X parallel to the upper surface of the substrate 100, and the first region I and the second region II may be arranged along a second direction Y intersecting the first direction X with the wall structure 102 as the center. That is, the first region I may be a region of the substrate 100 defined on one side of the wall structure 102, and the second region II may be a region of the substrate 100 defined on the other side of the wall structure 102.

[0031] In some example embodiments, transistors of different conductivity types may be formed in the first region I and the second region II, respectively. As an example, the first region I may be an NFET region, and the second region II may be a PFET region. As another example, the first region I may be a PFET region, and the second region II may be an NFET region. However, the inventive concepts of the present disclosure are not limited thereto, and transistors of the same conductivity type may be formed in the first region I and the second region II.

[0032] The first active pattern AP1 may be formed on the first region I of the substrate 100. The first active pattern AP1 may extend along the first direction X. The first active pattern AP1 may include a plurality of first bridge patterns (e.g., first to fourth sheet patterns 111 to 114) which are sequentially stacked on the upper surface of the substrate 100 and spaced apart from each other to each extend along the first direction X. The first active pattern AP1 may be provided as a channel region of a multi-bridge channel metal oxide semiconductor field effect transistor (MBCFET) including a multi-bridge channel. Although four bridge patterns are shown as included in the first active pattern AP1, this is merely an example, and the number of bridge patterns included in the first active pattern AP1 is not limited thereto.

[0033] In some example embodiments, a first fin pattern 110 may be formed between the substrate 100 and the first active pattern AP1. The first fin pattern 110 may protrude from an upper surface of the substrate 100 and extend in the first direction X. The first fin pattern 110 may also be formed by etching a portion of the substrate 100, or may also be an epitaxial layer grown from the substrate 100. The first bridge patterns 111 to 114 may be sequentially stacked on an upper surface of the first fin pattern 110.

[0034] The second active pattern AP2 may be formed on the second region II of the substrate 100. The second active pattern AP2 may extend in the first direction X. The second active pattern AP2 may include a plurality of second bridge patterns (e.g., the fifth to eighth sheet patterns 211 to 214) sequentially stacked on the upper surface of the substrate 100 and spaced apart from each other to each extend in the first direction X. The second active pattern AP2 may be provided to include a plurality of bridge channels. Although four bridge patterns are shown as included in the second active pattern AP2, this is only an example, and the number of bridge patterns included in the second active pattern AP2 is not limited thereto.

[0035] In some example embodiments, the second fin pattern 210 may be formed between the substrate 100 and the second active pattern AP2. The second fin pattern 210 may protrude from the upper surface of the substrate 100 and extend in the first direction X. The second fin pattern 210 may also be formed by etching a portion of the substrate 100, or may also be an epitaxial layer grown from the substrate 100. The second bridge patterns 211 to 214 may be sequentially stacked on the upper surface of the second fin pattern 210.

[0036] Only in Figure 2 2 shows that the width of the first active pattern AP1 and / or the width of the second active pattern AP2 may be constant in a vertical direction (e.g., a third direction Z) intersecting the upper surface of the substrate 100, but this is only an example. Depending on the characteristics of the etching process (or patterning process) used to form the first active pattern AP1 and the second active pattern AP2, the width of the first active pattern AP1 and / or the width of the second active pattern AP2 may decrease as the distance from the substrate 100 increases.

[0037] Each of the first active pattern AP1 and the second active pattern AP2 may include silicon (Si) or germanium (Ge) as an elemental semiconductor material. In some example embodiments, each of the first active pattern AP1 and the second active pattern AP2 may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. The group IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping carbon (C), silicon (Si), germanium (Ge), and tin (Sn) with a group IV element. The group III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), or indium (In) as a group III element with at least one of phosphorus (P), arsenic (As), or antimony (Sb) as a group V element. For ease of explanation, in the following description, the first active pattern AP1 and the second active pattern AP2 will both be described as silicon (Si) patterns.

[0038] In some example embodiments, the first active pattern AP1 and the second active pattern AP2 may be disposed at the same level as each other. Here, being disposed at the same level means being disposed at the same height as each other relative to the upper surface of the substrate 100. For example, as shown in the figure, each of the first bridge patterns 111 to 114 and the corresponding second bridge pattern of the second bridge patterns 211 to 214 may be disposed at the same height.

[0039] In some example embodiments, the first active pattern AP1 and the second active pattern AP2 may be formed at the same level as each other. In this specification, being formed at the same level means being formed by the same manufacturing process. For example, the first active pattern AP1 and the second active pattern AP2 may be made of the same material and / or the same material composition.

[0040] The first insulating pattern 104 may be interposed between the substrate 100 and the first active pattern AP1. For example, the first insulating pattern 104 may be interposed between the first fin pattern 110 and a bridge pattern (e.g., the first sheet pattern 111) disposed at the lowermost portion among the first bridge patterns 111 to 114. The first insulating pattern 104 may extend along the first direction X. The first active pattern AP1 may be electrically separated from the substrate 100 and / or the first fin pattern 110 by the first insulating pattern 104.

[0041] The second insulating pattern 204 may be interposed between the substrate 100 and the second active pattern AP2. For example, the second insulating pattern 204 may be interposed between the second fin pattern 210 and a bridge pattern (e.g., the fifth sheet pattern 211) disposed at the lowermost portion among the second bridge patterns 211 to 214. The second insulating pattern 204 may extend along the first direction X. The second active pattern AP2 may be electrically separated from the substrate 100 and / or the second fin pattern 210 by the second insulating pattern 204.

[0042] Each of the first insulating pattern 104 and the second insulating pattern 204 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but is not limited thereto. For example, each of the first insulating pattern 104 and the second insulating pattern 204 may include a silicon nitride film.

[0043] In some example embodiments, the first insulation pattern 104 and the second insulation pattern 204 may be disposed at the same level as each other. In some example embodiments, the first insulation pattern 104 and the second insulation pattern 204 may be formed at the same level as each other.

[0044] The field insulating film 106 may be formed on the substrate 100. The field insulating film 106 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but example embodiments are not limited thereto. As an example, the field insulating film 106 may include a silicon oxide film.

[0045] In some example embodiments, the field insulating film 106 may cover at least a portion of a side surface of the first fin pattern 110 and at least a portion of a side surface of the second fin pattern 210 . Figure 2204, only the upper surface of the field insulating film 106 is shown to be disposed on the same plane as the upper surface of the first insulating pattern 104 and the upper surface of the second insulating pattern 204, but this is only an example. According to some example embodiments, the top surface of the field insulating film 106 may also be formed to be lower than the upper surface of the first insulating pattern 104 and the upper surface of the second insulating pattern 204, and may also be formed to be higher than the upper surface of the first insulating pattern 104 and the upper surface of the second insulating pattern 204.

[0046] The wall structure 102 may be between the first region I and the second region II. The wall structure 102 may extend along the first direction X to separate the first active pattern AP1 and the second active pattern AP2. For example, the wall structure 102 may include a first side surface and a second side surface that intersect the second direction Y and are opposite to each other. The first active pattern AP1 may extend along the first direction X on the first side surface of the wall structure 102, and the second active pattern AP2 may extend along the first direction X on the second side surface of the wall structure 102. In some example embodiments, the first active pattern AP1 may be in contact with the first side surface of the wall structure 102, and the second active pattern AP2 may be in contact with the second side surface of the wall structure 102. The first active pattern AP1 and the second active pattern AP2 separated by the wall structure 102 may be set as a channel region of a fork-sheet field effect transistor (fork-sheet FET).

[0047] The wall structure 102 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but example embodiments are not limited thereto. As an example, the wall structure 102 may include a silicon nitride film. Such a wall structure 102 may be provided as an insulating wall in a fork-chip field effect transistor (a so-called dielectric wall scheme (DWS)).

[0048] Figure 2 102 is shown as being constant in the vertical direction (eg, the third direction Z), but this is only an example. Depending on the characteristics of the etching process (or patterning process) used to form the wall structure 102, the width of the wall structure 102 may increase as the distance from the substrate 100 increases.

[0049] It is shown that only the lower surface of the wall structure 102 is disposed on the same plane as the upper surface of the substrate 100, but this is only an example. As another example, the lower surface of the wall structure 102 may also be formed to be lower than the upper surface of the substrate 100, or may also be formed to be higher than the upper surface of the substrate 100. In some example embodiments, the wall structure 102 may extend along the first direction X to separate the first insulating pattern 104 and the second insulating pattern 204. For example, the lower surface of the wall structure 102 may be formed to be lower than the lower surface of the first insulating pattern 104 and the lower surface of the second insulating pattern 204.

[0050] The first seed layer 122 may be formed between the first bridge patterns 111 to 114 and on the side surface of the wall structure 102. As an example, Figure 3 As shown, the first seed layer 122 may be formed on a first portion of the side surface of the wall structure 102 adjacent to the upper surface of the first sheet pattern 111 and a second portion of the side surface of the wall structure 102 adjacent to the lower surface of the second sheet pattern 112 .

[0051] The first seed layer 122 may include a first surface 122S. The first surface 122S is a surface of the first seed layer 122 that is exposed from the first active pattern AP1 and the wall structure 102 (not in contact with the first active pattern AP1 and the wall structure 102). In some example embodiments, the first surface 122S may include a concave curved surface. This may be due to the characteristics of the etching process used to form the first seed layer 122.

[0052] In some example embodiments, the first seed layer 122 may expose a portion of a side surface of the wall structure 102 between each of the respective adjacent pairs of the first bridge patterns 111 to 114. As an example, the first seed layer 122 adjacent to the upper surface of the first sheet pattern 111 and the first seed layer 122 adjacent to the lower surface of the second sheet pattern 112 may be spaced apart from each other in the third direction Z.

[0053] The second seed layer 222 may be formed between the second bridge patterns 211 to 214 and on the side surface of the wall structure 102. As an example, Figure 3 As shown, the second seed layer 222 may be formed on a first portion of the side surface of the wall structure 102 adjacent to the upper surface of the fifth sheet pattern 211 and a second portion of the side surface of the wall structure 102 adjacent to the lower surface of the sixth sheet pattern 212 .

[0054] The second seed layer 222 may include a second surface 222S. The second surface 222S is a surface of the second seed layer 222 that is exposed from the second active pattern AP2 and the wall structure 102 (not in contact with the second active pattern AP2 and the wall structure 102). In some example embodiments, the second surface 222S may include a concave curved surface. This may be due to the characteristics of the etching process used to form the second seed layer 222.

[0055] In some example embodiments, the second seed layer 222 may expose a portion of the side surface of the wall structure 102 between each of the respective adjacent pairs of the second bridge patterns 211 to 214. As an example, the second seed layer 222 adjacent to the upper surface of the fifth sheet pattern 211 and the second seed layer 222 adjacent to the lower surface of the sixth sheet pattern 212 may be spaced apart from each other in the third direction Z.

[0056] Each of the first seed layer 122 and the second seed layer 222 may include a transition metal element. The transition metal element may include, for example, at least one metal element of molybdenum (Mo), tungsten (W), niobium (Nb), vanadium (V), tantalum (Ta), titanium (Ti), zirconium (Zr), hafnium (Hf), technetium (Tc), rhenium (Re), or copper (Cu). In some example embodiments, the first seed layer 122 and the second seed layer 222 may include the same transition metal element. As an example, both the first seed layer 122 and the second seed layer 222 may include molybdenum (Mo). As another example, both the first seed layer 122 and the second seed layer 222 may include tungsten (W).

[0057] In some example embodiments, each of the first seed layer 122 and the second seed layer 222 may include an oxide of a transition metal element. As an example, each of the first seed layer 122 and the second seed layer 222 may include molybdenum dioxide (MoO 2 As another example, each of the first seed layer 122 and the second seed layer 222 may include tungsten dioxide (WO 2 ).

[0058] The first 2D channel layer 124 may extend from the first seed layer 122 along the surface of the first active pattern AP1. Figure 3 As shown, the first 2D channel layer 124 may extend from the first seed layer 122 adjacent to the upper surface of the first sheet pattern 111 along the upper surface of the first sheet pattern 111 , and may extend from the first seed layer 122 adjacent to the lower surface of the second sheet pattern 112 along the lower surface of the second sheet pattern 112 .

[0059] The first 2D channel layer 124 may surround at least a portion of a periphery of each of the first bridge patterns 111 to 114 exposed from the wall structure 102 and / or the first insulation pattern 104. In some example embodiments, the first 2D channel layer 124 may not extend along an upper surface of an uppermost bridge pattern (e.g., the fourth sheet pattern 114) among the first bridge patterns 111 to 114. As an example, Figure 2 As shown, the first 2D channel layer 124 can extend along the side surface and upper surface of the first sheet pattern 111, the lower surface, side surface and upper surface of the second sheet pattern 112, the lower surface, side surface and upper surface of the third sheet pattern 113, and the lower surface and side surface of the fourth sheet pattern 114.

[0060] The first 2D channel layer 124 may include a first transition metal dichalcogenide including the transition metal element of the first seed layer 122. For example, the first transition metal dichalcogenide may include a transition metal element of molybdenum (Mo), tungsten (W), niobium (Nb), vanadium (V), tantalum (Ta), titanium (Ti), zirconium (Zr), hafnium (Hf), technetium (Tc), rhenium (Re), and copper (Cu), and a chalcogen element of sulfur (S), selenium (Se), and tellurium (Te). As an example, when the first seed layer 122 includes molybdenum dioxide (MoO 2 ), the first 2D channel layer 124 may include molybdenum disulfide (MoS 2 As another example, when the first seed layer 122 includes tungsten dioxide (WO 2 ), the first 2D channel layer 124 may include tungsten disulfide (WS 2 ).

[0061] The first 2D channel layer 124 may be formed by a crystal growth method using the first seed layer 122 as a seed layer. For example, the first 2D channel layer 124 may be formed by two-dimensionally growing a crystal from the first surface 122S of the first seed layer 122. In some example embodiments, the first 2D channel layer 124 may have a single crystal structure. In some example embodiments, the first 2D channel layer 124 may expose a portion of the first surface 122S.

[0062] In some example embodiments, the first 2D channel layer 124 may be formed to have a thickness of several nanometers (nm) by two-dimensionally growing crystals. For example, the thickness of the first 2D channel layer 124 (eg, Figure 3 T11 and T12 in the figure can be about 10 nm or less.

[0063] In some example embodiments, a portion of the first 2D channel layer 124 may extend along a side surface of the wall structure 102 between each adjacent pair of the first bridge patterns 111 to 114. Figure 3 As shown, the first 2D channel layer 124 may include a first horizontal portion 124L and a first vertical portion 124V. The first horizontal portion 124L may extend from the first seed layer 122 in a horizontal direction (e.g., in the first direction X and / or in the second direction Y) along a surface of the first active pattern AP1. The first vertical portion 124V may extend from the first seed layer 122 in a vertical direction (e.g., in a third direction Z) along a side surface of the wall structure 102.

[0064] Only the thickness T11 of the first horizontal portion 124L and the thickness T12 of the first vertical portion 124V are shown to be the same as each other, but this is only an example, and the thickness T11 of the first horizontal portion 124L and the thickness T12 of the first vertical portion 124V may be different from each other depending on the conditions of the crystal growth method.

[0065] The second 2D channel layer 224 may extend from the second seed layer 222 along the surface of the second active pattern AP2. Figure 3 As shown, the second 2D channel layer 224 may extend from the second seed layer 222 adjacent to the upper surface of the fifth sheet pattern 211 along the upper surface of the fifth sheet pattern 211 , and may extend from the second seed layer 222 adjacent to the lower surface of the sixth sheet pattern 212 along the lower surface of the sixth sheet pattern 212 .

[0066] The second 2D channel layer 224 may surround at least a portion of a periphery of each of the second bridge patterns 211 to 214 exposed from the wall structure 102 and / or the second insulating pattern 204. In some example embodiments, the second 2D channel layer 224 may not extend along an upper surface of an uppermost bridge pattern (e.g., the eighth sheet pattern 214) among the second bridge patterns 211 to 214. As an example, Figure 2 As shown, the second 2D channel layer 224 can extend along the side surface and upper surface of the fifth sheet pattern 211, the lower surface, side surface and upper surface of the sixth sheet pattern 212, the lower surface, side surface and upper surface of the seventh sheet pattern 213, and the lower surface and side surface of the eighth sheet pattern 214.

[0067] The second 2D channel layer 224 may include a second transition metal dichalcogenide including the transition metal element of the second seed layer 222. For example, the second transition metal dichalcogenide may include a transition metal element of molybdenum (Mo), tungsten (W), niobium (Nb), vanadium (V), tantalum (Ta), titanium (Ti), zirconium (Zr), hafnium (Hf), technetium (Tc), rhenium (Re), and copper (Cu), and a chalcogen element of sulfur (S), selenium (Se), and tellurium (Te). As an example, when the second seed layer 222 includes molybdenum dioxide (MoO 2 ), the second 2D channel layer 224 may include molybdenum disulfide (MoS 2 As another example, when the second seed layer 222 includes tungsten dioxide (WO 2 ), the second 2D channel layer 224 may include tungsten disulfide (WS 2 ).

[0068] The second 2D channel layer 224 may be formed by a crystal growth method using the second seed layer 222 as a seed layer. For example, the second 2D channel layer 224 may be formed by two-dimensionally growing crystals from the second surface 222S of the second seed layer 222. In some example embodiments, the second 2D channel layer 224 may have a single crystal structure. In some example embodiments, the second 2D channel layer 224 may expose a portion of the second surface 222S.

[0069] In some example embodiments, the second 2D channel layer 224 may be formed to have a thickness of several nanometers (nm) by two-dimensionally growing crystals. For example, the thickness of the second 2D channel layer 224 (eg, Figure 3 T11 and T12 in the figure can be about 10 nm or less.

[0070] In some example embodiments, a portion of the second 2D channel layer 224 may extend along a side surface of the wall structure 102 between each adjacent pair of the second bridge patterns 211 to 214. Figure 3 As shown, the second 2D channel layer 224 may include a second horizontal portion 224L and a second vertical portion 224V. The second horizontal portion 224L may extend from the second seed layer 222 in a horizontal direction (e.g., in the first direction X and / or in the second direction Y) along a surface of the second active pattern AP2. The second vertical portion 224V may extend from the second seed layer 222 in a vertical direction (e.g., in a third direction Z) along a side surface of the wall structure 102.

[0071] Only the thickness T21 of the second horizontal portion 224L and the thickness T22 of the second vertical portion 224V are shown to be the same as each other, but this is only an example, and depending on the conditions of the crystal growth method, the thickness T21 of the second horizontal portion 224L and the thickness T22 of the second vertical portion 224V may be different from each other.

[0072] In some example embodiments, the first transition metal dichalcogenide of the first 2D channel layer 124 and the second transition metal dichalcogenide of the second 2D channel layer 224 may be identical to each other. As an example, both the first 2D channel layer 124 and the second 2D channel layer 224 may include molybdenum disulfide (MoS 2 As another example, both the first 2D channel layer 124 and the second 2D channel layer 224 may include tungsten disulfide (WS 2 ).

[0073] However, the exemplary embodiments of the present disclosure are not limited thereto, and the first transition metal dichalcogenide of the first 2D channel layer 124 and the second transition metal dichalcogenide of the second 2D channel layer 224 may also be different from each other. As an example, when the first seed layer 122 and the second seed layer 222 include molybdenum dioxide (MoO2 ), the first 2D channel layer 124 may include molybdenum disulfide (MoS 2 ), and the second 2D channel layer 224 may include molybdenum diselenide (MoSe 2 As another example, when the first seed layer 122 and the second seed layer 222 include tungsten dioxide (WO 2 ), the first 2D channel layer 124 may include tungsten disulfide (WS 2 ), and the second 2D channel layer 224 may include tungsten diselenide (WSe 2 ).

[0074] The first gate structure GS1 may be formed on the first region I of the substrate 100. The first gate structure GS1 may intersect with the first active pattern AP1. For example, the first gate structure GS1 may extend along the second direction Y on the first side surface of the wall structure 102. Each of the first bridge patterns 111 to 114 may extend along the first direction X and penetrate the first gate structure GS1. Therefore, the first gate structure GS1 may surround the periphery of each of the first bridge patterns 111 to 114 exposed from the wall structure 102 and / or the first insulating pattern 104.

[0075] The second gate structure GS2 may be formed on the second region II of the substrate 100. The second gate structure GS2 may intersect with the second active pattern AP2. For example, the second gate structure GS2 may extend along the second direction Y on the second side surface of the wall structure 102. Each of the second bridge patterns 211 to 214 may extend along the first direction X and penetrate the second gate structure GS2. Therefore, the second gate structure GS2 may surround the periphery of each second bridge pattern 211 to 214 exposed from the wall structure 102 and / or the second insulating pattern 204.

[0076] The first gate structure GS1 may include a first gate dielectric film 132 and a first gate electrode 134 , and the second gate structure GS2 may include a second gate dielectric film 232 and a second gate electrode 234 .

[0077] The first gate dielectric film 132 may be stacked on the first 2D channel layer 124. The first 2D channel layer 124 may be interposed between the first active pattern AP1 and the first gate dielectric film 132. The first gate dielectric film 132 may surround the periphery of the first active pattern AP1. When the first 2D channel layer 124 does not extend along the upper surface of the uppermost bridge pattern (e.g., the fourth sheet pattern 114), the first gate dielectric film 132 may contact the upper surface of the uppermost bridge pattern (e.g., the fourth sheet pattern 114). In some example embodiments, the first gate dielectric film 132 may also extend along the upper surface of the field insulating film 106 and the side surface of the wall structure 102.

[0078] The second gate dielectric film 232 may be stacked on the second 2D channel layer 224. The second 2D channel layer 224 may be interposed between the second active pattern AP2 and the second gate dielectric film 232. The second gate dielectric film 232 may surround the periphery of the second active pattern AP2. When the second 2D channel layer 224 does not extend along the upper surface of the uppermost bridge pattern (e.g., the eighth sheet pattern 214), the second gate dielectric film 232 may contact the upper surface of the uppermost bridge pattern (e.g., the eighth sheet pattern 214). In some example embodiments, the second gate dielectric film 232 may also extend along the upper surface of the field insulating film 106 and the side surface of the wall structure 102.

[0079] Each of the first gate dielectric film 132 and the second gate dielectric film 232 may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material may include, for example, hafnium oxide (HfO 2 )、ZrO 2 ), lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Strontium Titanium Oxide (SrTiO 3 ), lanthanum aluminum oxide (LaAlO 3 ), yttrium oxide (Y 2 O 3 ), Hafnium Oxynitride (HfO x N y ), zirconium oxynitride (ZrO x N y ), lanthanum oxynitride (La 2 O x N y ), aluminum oxynitride (Al 2 O x N y ), titanium oxynitride (TiO x N y ), Strontium Titanium Oxynitride (SrTiO x N y ), lanthanum aluminum oxynitride (LaAlO x N y ), yttrium oxynitride (Y 2 O x N y ) or at least one of a combination thereof, but example embodiments are not limited thereto.

[0080] The semiconductor device according to some example embodiments may include a negative capacitance (NC) FET using a negative capacitor.For example, the first gate dielectric film 132 and / or the second gate dielectric film 232 may include a ferroelectric material film having ferroelectric characteristics and a paraelectric material film having paraelectric characteristics.

[0081] The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, when two or more capacitors are connected in series with each other and the capacitance of each capacitor has a positive value, the total capacitance is reduced compared to the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series with each other has a negative value, the total capacitance may be greater than the absolute value of each individual capacitance while having a positive value.

[0082] When a ferroelectric material film having negative capacitance and a paraelectric material film having positive capacitance are connected in series with each other, the total capacitance value of the ferroelectric material film and the paraelectric material film connected in series with each other can be increased. With the increase in the total capacitance value, a transistor including the ferroelectric material film can have a subthreshold swing (SS) of less than 60mV / decade at room temperature.

[0083] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, or lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, hafnium zirconium oxide may also be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0084] The ferroelectric material film may also include a dopant doped with. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr) or tin (Sn). The type of dopant included in the ferroelectric material film may vary depending on the type of ferroelectric material included in the ferroelectric material film.

[0085] When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), or yttrium (Y).

[0086] When the dopant is aluminum (Al), the ferroelectric material film may include about 3 to about 8 atomic % (at %) of aluminum. Here, the ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum.

[0087] When the dopant is silicon (Si), the ferroelectric material film may include about 2 to about 10 atomic % (at%) of silicon. When the dopant is yttrium (Y), the ferroelectric material film may include about 2 to about 10 at% of yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may include about 1 to about 7 at% of gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may include about 50 to about 80 at% of zirconium.

[0088] The paraelectric material film may have paraelectric characteristics. The paraelectric material film may include, for example, at least one of silicon oxide or a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, or aluminum oxide, but example embodiments are not limited thereto.

[0089] The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film may have ferroelectric properties, but the paraelectric material film may not have ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film is different from the crystal structure of the hafnium oxide included in the paraelectric material film.

[0090] The thickness of the ferroelectric material film may have ferroelectric properties. The thickness of the ferroelectric material film may be, for example, about 0.5 to about 10 nm, but is not limited thereto. Since the critical thickness representing the ferroelectric properties may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0091] As an example, the first gate dielectric film 132 and / or the second gate dielectric film 232 may include a ferroelectric material film. As another example, the first gate dielectric film 132 and / or the second gate dielectric film 232 may include a plurality of ferroelectric material films spaced apart from each other. The first gate dielectric film 132 and / or the second gate dielectric film 232 may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0092] The first gate electrode 134 may be stacked on the first gate dielectric film 132. The first gate dielectric film 132 may be interposed between the first active pattern AP1 and the first gate electrode 134.

[0093] The second gate electrode 234 may be stacked on the second gate dielectric film 232. The second gate dielectric film 232 may be interposed between the second active pattern AP2 and the second gate electrode 234.

[0094] Each of the first gate electrode 134 and the second gate electrode 234 may be formed by, for example, a replacement process, but example embodiments are not limited thereto. It is only shown that each of the first gate electrode 134 and the second gate electrode 234 is a single film, but this is only an example. In some example embodiments, each of the first gate electrode 134 and the second gate electrode 234 may be formed by stacking a plurality of conductive layers.

[0095] In some example embodiments, the wall structure 102 may extend along the first direction X to separate the first gate structure GS1 and the second gate structure GS2 from each other. For example, an upper surface of the wall structure 102 may be formed to be higher than upper surfaces of the first gate structure GS1 and the second gate structure GS2.

[0096] The first gate spacer 140 may be formed on the first insulating pattern 104 and the field insulating film 106. The first gate spacer 140 may extend along the side surface of the first gate structure GS1. In some example embodiments, a portion of the first gate dielectric film 132 may be interposed between the first gate electrode 134 and the first gate spacer 140. For example, Figure 4 As shown, the first gate dielectric film 132 may also extend along at least a portion of the inner side surface of the first gate spacer 140. The first gate dielectric film 132 may be formed by a replacement process, but example embodiments are not limited thereto.

[0097] The second gate spacer 240 may be formed on the second insulating pattern 204 and the field insulating film 106. The second gate spacer 240 may extend along the side surface of the second gate structure GS2. In some example embodiments, a portion of the second gate dielectric film 232 may be interposed between the second gate electrode 234 and the second gate spacer 240. For example, Figure 5 As shown, the second gate dielectric film 232 may also extend along at least a portion of the inner side surface of the second gate spacer 240. The second gate dielectric film 232 may be formed by a replacement process, but example embodiments are not limited thereto.

[0098] Each of the first gate spacer 140 and the second gate spacer 240 may include, for example, at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon carbon nitride, silicon carbon oxynitride, or a combination thereof, but example embodiments are not limited thereto. As an example, each of the first gate spacer 140 and the second gate spacer 240 may include a silicon nitride film.

[0099] The first source / drain pattern 160 may be formed on at least one side surface (e.g., both side surfaces) of the first gate structure GS1. The first source / drain pattern 160 may be connected to the first active pattern AP1. For example, each of the first bridge patterns 111 to 114 may penetrate the first gate structure GS1 and the first gate spacer 140, and be connected to the first source / drain pattern 160. The first source / drain pattern 160 may be electrically separated from the first gate electrode 134 by the first gate spacer 140 and / or the first gate dielectric film 132.

[0100] In some example embodiments, the first 2D channel layer 124 may further extend along side surfaces of the first source / drain pattern 160. For example, a portion of the first 2D channel layer 124 may extend along side surfaces of the first source / drain pattern 160 between respective adjacent pairs of the first bridge patterns 111 to 114. A portion of the first 2D channel layer 124 may be interposed between the first gate structure GS1 and the first source / drain pattern 160.

[0101] In some example embodiments, the first source / drain pattern 160 may include an epitaxial layer. For example, the first source / drain pattern 160 may be formed from the first active pattern AP1 by an epitaxial growth method. The first source / drain pattern 160 may be provided as a source / drain region of a field effect transistor (FET) formed on the first region I.

[0102] When the first region I is an NFET region, the first source / drain pattern 160 including an epitaxial layer may include an n-type impurity (e.g., phosphorus (P), antimony (Sb), or arsenic (As)) or an impurity for blocking or preventing diffusion of the n-type impurity. When the first region I is an NFET region, the first source / drain pattern 160 including an epitaxial layer may further include a tensile stress material. As an example, when the first active pattern AP1 is a silicon (Si) pattern, the first source / drain pattern 160 may include a material having a smaller lattice constant than silicon (Si) (e.g., silicon carbide (SiC)).

[0103] In some example embodiments, the first source / drain pattern 160 may include a metal material such as nickel (Ni), palladium (Pd), gold (Au), titanium (Ti), silver (Ag), aluminum (Al), tungsten (W), copper (Cu), manganese (Mn), or zirconium (Zr). The first source / drain pattern 160 may be provided as a source / drain electrode connected to the first 2D channel layer 124 including a 2D semiconductor material.

[0104] The second source / drain pattern 260 may be formed on at least one side surface (e.g., both side surfaces) of the second gate structure GS2. The second source / drain pattern 260 may be connected to the second active pattern AP2. For example, each of the second bridge patterns 211 to 214 may penetrate the second gate structure GS2 and the second gate spacer 240 and be connected to the second source / drain pattern 260. The second source / drain pattern 260 may be electrically separated from the second gate electrode 234 by the second gate spacer 240 and / or the second gate dielectric film 232.

[0105] In some example embodiments, the second 2D channel layer 224 may further extend along side surfaces of the second source / drain pattern 260. For example, a portion of the second 2D channel layer 224 may extend along side surfaces of the second source / drain pattern 260 between respective adjacent pairs of the second bridge patterns 211 to 214. A portion of the second 2D channel layer 224 may be interposed between the second gate structure GS2 and the second source / drain pattern 260.

[0106] In some example embodiments, the second source / drain pattern 260 may include an epitaxial layer. For example, the second source / drain pattern 260 may be formed from the second active pattern AP2 by an epitaxial growth method. The second source / drain pattern 260 may be provided as a source / drain region of a field effect transistor (FET) formed on the second region II.

[0107] When the second region II is a PFET region, the second source / drain pattern 260 including an epitaxial layer may include a p-type impurity (e.g., boron (B), indium (In), gallium (Ga), or aluminum (Al)) or an impurity for blocking or preventing the diffusion of the p-type impurity. When the second region II is a PFET region, the second source / drain pattern 260 including an epitaxial layer may further include a compressive stress material. As an example, when the second active pattern AP2 is a silicon (Si) pattern, the second source / drain pattern 260 may include a material having a larger lattice constant than silicon (Si) (e.g., silicon germanium (SiGe)).

[0108] In some example embodiments, the second source / drain pattern 260 may include a metal material such as nickel (Ni), palladium (Pd), gold (Au), titanium (Ti), silver (Ag), aluminum (Al), tungsten (W), copper (Cu), manganese (Mn), or zirconium (Zr). The second source / drain pattern 260 may be provided as a source / drain electrode connected to the second 2D channel layer 224 including a 2D semiconductor material.

[0109] The interlayer insulating film 180 may be formed on the wall structure 102, the first gate structure GS1, the second gate structure GS2, the first source / drain pattern 160, and the second source / drain pattern 260. For example, the interlayer insulating film 180 may cover the wall structure 102, the first gate structure GS1, the second gate structure GS2, the first source / drain pattern 160, and the second source / drain pattern 260.

[0110] The interlayer insulating film 180 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxynitride, or a low-k material having a dielectric constant less than that of silicon oxide, but example embodiments are not limited thereto. The low-k material may include, for example, at least one of flowable oxide (FOX), troline silitride (TOSZ), undoped quartz glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluoride silicate glass (FSG), carbon-doped silicon oxide (CDO), xerogel, aerogel, amorphous fluorinated carbon, organic silicate glass (OSG), polyparaxylene, bisbenzocyclobutene (BCB), SiLK, polyimide, a porous polymer material, or a combination thereof, but example embodiments are not limited thereto.

[0111] The first gate contact CB1 may be electrically connected to the first gate structure GS1 . For example, the first gate contact CB1 may extend in the third direction Z to penetrate the interlayer insulating film 180 and be connected to the upper surface of the first gate electrode 134 .

[0112] The second gate contact CB2 may be electrically connected to the second gate structure GS2 . For example, the second gate contact CB2 may extend in the third direction Z to penetrate the interlayer insulating film 180 and be connected to the upper surface of the second gate electrode 234 .

[0113] Each of the first gate contact CB1 and the second gate contact CB2 may include, for example, a metal material such as cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), or cobalt tungsten phosphide (CoWP), but example embodiments are not limited thereto. As an example, each of the first gate contact CB1 and the second gate contact CB2 may include cobalt (Co).

[0114] Figures 6 to 10 is used to describe the Figure 2 For ease of explanation, the above reference will be briefly described or omitted. Figures 1 to 5 The parts described overlap.

[0115] Reference Figure 6, in the semiconductor device according to example embodiments, thicknesses T11 and T12 of the first 2D channel layer 124 and thicknesses T21 and T22 of the second 2D channel layer 224 may be different from each other.

[0116] This may be due to the fact that the first 2D channel layer 124 and the second 2D channel layer 224 are formed at different levels. For example, the thickness T11 of the first horizontal portion 124L and the thickness T21 of the second horizontal portion 224L may be different from each other, and / or the thickness T12 of the first vertical portion 124V and the thickness T22 of the second vertical portion 224V may be different from each other.

[0117] It is only shown that the thicknesses T21 and T22 of the second 2D channel layer 224 are respectively greater than the thicknesses T11 and T12 of the first 2D channel layer 124, but this is only an example, and the thicknesses T21 and T22 of the second 2D channel layer 224 may be respectively less than the thicknesses T11 and T12 of the first 2D channel layer 124. The difference between the thicknesses T11 and T12 of the first 2D channel layer 124 and the thicknesses T21 and T22 of the second 2D channel layer 224 may be appropriately adjusted according to purpose or need.

[0118] Reference Figure 7 , in the semiconductor device according to example embodiments, a thickness T13 of the first seed layer 122 and a thickness T23 of the second seed layer 222 may be different from each other.

[0119] This may be due to the fact that the first seed layer 122 and the second seed layer 222 are formed at different levels. The thickness T13 of the first seed layer 122 and the thickness T23 of the second seed layer 222 may both be defined as, for example, a thickness in a vertical direction (e.g., a third direction Z), but this is merely an example. As another example, the thickness T13 of the first seed layer 122 and the thickness T23 of the second seed layer 222 may both be defined as a thickness in a horizontal direction (e.g., a second direction Y). As yet another example, the thickness T13 of the first seed layer 122 may be defined as a maximum distance from a contact point between the first active pattern AP1 and the wall structure 102 to the first surface 122S, and the thickness T23 of the second seed layer 222 may be defined as a maximum distance from a contact point between the second active pattern AP2 and the wall structure 102 to the second surface 222S.

[0120] It is only shown that the thickness T23 of the second seed layer 222 is greater than the thickness T13 of the first seed layer 122, but this is only an example, and the thickness T23 of the second seed layer 222 may be less than the thickness T13 of the first seed layer 122. The difference between the thickness T13 of the first seed layer 122 and the thickness T23 of the second seed layer 222 may be appropriately adjusted according to purpose or need.

[0121] Reference Figure 8 , in the semiconductor device according to example embodiments, a thickness T14 of the first gate dielectric film 132 and a thickness T24 of the second gate dielectric film 232 may be different from each other.

[0122] This may be due to the fact that the first gate dielectric film 132 and the second gate dielectric film 232 are formed at different levels. It is only shown that the thickness T24 of the second gate dielectric film 232 is greater than the thickness T14 of the first gate dielectric film 132, but this is only an example, and the thickness T24 of the second gate dielectric film 232 may be smaller than the thickness T14 of the first gate dielectric film 132. The difference between the thickness T14 of the first gate dielectric film 132 and the thickness T24 of the second gate dielectric film 232 may be appropriately adjusted according to purpose or need.

[0123] Reference Fig. 9 , in the semiconductor device according to example embodiments, the first 2D channel layer 124 may extend along the first surface 122S, or the second 2D channel layer 224 may extend along the second surface 222S.

[0124] For example, the first 2D channel layer 124 may further include a first connection portion 124C extending along the first surface 122S and connecting the first horizontal portion 124L and the first vertical portion 124V. Similarly, the second 2D channel layer 224 may further include a second connection portion 224C extending along the second surface 222S and connecting the second horizontal portion 224L and the second vertical portion 224V.

[0125] Fig. 9 124C completely covers the first surface 122S and the second connection portion 224C completely covers the second surface 222S, but this is only an example. As an example, the first 2D channel layer 124 may expose a portion of the first surface 122S, or the second 2D channel layer 224 may expose a portion of the second surface 222S.

[0126] Reference Fig.10 , in the semiconductor device according to example embodiments, the first 2D channel layer 124 may be spaced apart from the wall structure 102 , or the second 2D channel layer 224 may be spaced apart from the wall structure 102 .

[0127] For example, the first seed layer 122 may completely cover the side surface of the wall structure 102 between each of the respective adjacent pairs of the first bridge patterns 111 to 114. Likewise, the second seed layer 222 may completely cover the side surface of the wall structure 102 between the second bridge patterns 211 to 214.

[0128] exist Fig.101 and 2 , only the first seed layer 122 completely covers the side surface of the wall structure 102 between the first bridge patterns 111 and 112 among the first bridge patterns 111 to 114, and the second seed layer 222 completely covers the side surface of the wall structure 102 between the second bridge patterns 211 and 212 among the second bridge patterns 211 to 214, but this is only an example. As another example, the first seed layer 122 may expose a portion of the side surface of the wall structure 102 between the first bridge patterns 111 to 114, or the second seed layer 222 may expose the side surface of the wall structure 102 between the second bridge patterns 211 to 214.

[0129] Fig.11 and Fig.12 are other various cross-sectional views for describing semiconductor devices according to some example embodiments. Figures 1 to 10 The parts described overlap.

[0130] Reference Fig.11 In a semiconductor device according to example embodiments, an uppermost portion of the first 2D channel layer 124 may be lower than an upper surface of an uppermost bridge pattern (e.g., the fourth sheet pattern 114), and an uppermost portion of the second 2D channel layer 224 may be lower than an upper surface of an uppermost bridge pattern (e.g., the eighth sheet pattern 118).

[0131] For example, the first 2D channel layer 124 may extend from the first seed layer 122 adjacent to the lower surface of the fourth sheet pattern 114 along the lower surface of the fourth sheet pattern 114, and then extend only along a portion of the side surface of the fourth sheet pattern 114. The second 2D channel layer 224 may extend from the second seed layer 222 adjacent to the lower surface of the eighth sheet pattern 214 along the lower surface of the eighth sheet pattern 214, and then extend only along a portion of the side surface of the eighth sheet pattern 214.

[0132] In this example embodiment, the lowermost portion of the first 2D channel layer 124 may be higher than the lower surface of the lowermost bridge pattern (e.g., the first sheet pattern 111), and the lowermost portion of the second 2D channel layer 224 may be higher than the lower surface of the lowermost bridge pattern (e.g., the fifth sheet pattern 211).

[0133] For example, the first 2D channel layer 124 may extend from the first seed layer 122 adjacent to the upper surface of the first sheet pattern 111 along the upper surface of the first sheet pattern 111, and then extend only along a portion of the side surface of the first sheet pattern 111. The second 2D channel layer 224 may extend from the second seed layer 222 adjacent to the upper surface of the fifth sheet pattern 211 along the upper surface of the fifth sheet pattern 211, and then extend only along a portion of the side surface of the fifth sheet pattern 211.

[0134] Reference Fig.12 In the semiconductor device according to example embodiments, the first gate electrode 134 may be formed by stacking a plurality of conductive films, and the second gate electrode 234 may be formed by stacking a plurality of conductive films.

[0135] For example, the first gate electrode 134 may include a first work function adjusting film 134a for adjusting the work function and a first filling conductive film 134b for filling the space formed by the first work function adjusting film 134a. The second gate electrode 234 may include a second work function adjusting film 234a for adjusting the work function and a second filling conductive film 234b for filling the space formed by the second work function adjusting film 234a.

[0136] It is only shown that the first work function adjusting film 134 a and the second work function adjusting film 234 a have the same thickness, but this is only an example, and the first work function adjusting film 134 a and the second work function adjusting film 234 a may also have different thicknesses.

[0137] Each of the first and second work function adjustment films 134a and 234a may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, or a combination thereof. Each of the first and second filling conductive films 134b and 234b may include, for example, W or Al.

[0138] Figure 13 to Figure 43 is an intermediate step diagram for describing a method for manufacturing a semiconductor device according to an example embodiment. For ease of explanation, the above referenced Figures 1 to 12 The parts described overlap.

[0139] Reference Fig.13 and Fig.14 , a first sacrificial film 304, an active film pAP, a second sacrificial film 330 and at least one passivation film 392 or 394 are formed on the substrate 100. For reference, Fig.14 is along Fig.13 A cross-sectional view taken along line AA.

[0140] The first sacrificial film 304 may be formed on the substrate 100. The first sacrificial film 304 may have an etching selectivity with respect to the substrate 100 and the active film pAP. As an example, the substrate 100 and the active film pAP may include silicon (Si), and the first sacrificial film 304 may include silicon germanium (SiGe).

[0141] The active film pAP and the second sacrificial film 330 may be formed on the first sacrificial film 304. The active film pAP and the second sacrificial film 330 may be alternately stacked on the first sacrificial film 304. For example, the active film pAP may include a plurality of sub-active films 311 to 314 sequentially stacked on the first sacrificial film 304. The second sacrificial film 330 may be interposed between each of the adjacent pairs of the sub-active films 311 to 314 so that the sub-active films 311 to 314 are spaced apart from each other in a vertical direction (e.g., in a third direction Z).

[0142] The second sacrificial film 330 may include a transition metal element. The transition metal element may include, for example, at least one metal element of molybdenum (Mo), tungsten (W), niobium (Nb), vanadium (V), tantalum (Ta), titanium (Ti), zirconium (Zr), hafnium (Hf), technetium (Tc), rhenium (Re), or copper (Cu). As an example, the second sacrificial film 330 may include molybdenum (Mo) or tungsten (W).

[0143] In some example embodiments, the second sacrificial film 330 may include an oxide of a transition metal element. As an example, the second sacrificial film 330 may include molybdenum dioxide (MoO 2 ) or tungsten dioxide (WO 2 ).

[0144] At least one passivation film 392 or 394 may be formed on the active film pAP and the second sacrificial film 330. At least one of the passivation films 392 or 394 may include various materials that protect the active film pAP and / or the second sacrificial film 330 in subsequent processes. As an example, a first passivation film 392 including silicon oxide (SiO) and a second passivation film 394 including amorphous silicon (a-Si) may be sequentially stacked on the active film pAP and the second sacrificial film 330.

[0145] Reference Fig.15 and Fig.16 , a first sacrificial pattern 104S, a second sacrificial pattern 204S, a first active pattern AP1, a third sacrificial pattern 331, a second active pattern AP2, and a fourth sacrificial pattern 332 are formed on the substrate 100. For reference, Fig.16 is along Fig.15 A cross-sectional view taken along line AA.

[0146] The first sacrificial pattern 104S, the second sacrificial pattern 204S, the first active pattern AP1, the third sacrificial pattern 331, the second active pattern AP2, and the fourth sacrificial pattern 332 may all extend along the first direction X. For example, Fig.13 and Fig.14The first sacrificial film 304, the active film pAP, the second sacrificial film 330, and the at least one passivation film 392 or 394 are patterned by a patterning process. The first sacrificial film 304 patterned in the first region I may form a first sacrificial pattern 104S, and the first sacrificial film 304 patterned in the second region II may form a second sacrificial pattern 204S. The active film pAP patterned in the first region I may form a first active pattern AP1, and the second sacrificial film 330 patterned in the first region I may form a third sacrificial pattern 331 alternately stacked with the first active pattern AP1. In addition, the active film pAP patterned in the second region II may form a second active pattern AP2, and the second sacrificial film 330 patterned in the second region II may form a fourth sacrificial pattern 332 alternately stacked with the second active pattern AP2.

[0147] In some example embodiments, in the process of etching the first sacrificial film 304 , a portion of the substrate 100 may be etched to form the first fin pattern 110 on the first region I and to form the second fin pattern 210 on the second region II.

[0148] Reference Fig.17 , forming a filling insulating film 302 that performs a filling function.

[0149] The filling insulating film 302 may fill at least a region between the first active pattern AP1 and the second active pattern AP2. For example, the filling insulating film 302 may cover Fig.16 The filling insulating film 302 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but example embodiments are not limited thereto. As an example, the filling insulating film 302 may include a silicon nitride film.

[0150] Reference Fig.18 , exposing the first sacrificial pattern 104S and the second sacrificial pattern 204S.

[0151] For example, a portion of the filling insulating film 302 may be removed to expose side surfaces of the first and second sacrificial patterns 104S and 204S. In some example embodiments, the filling insulating film 302 filling a region between the first and second active patterns AP1 and AP2 may not be removed.

[0152] Reference Fig.19 , the first sacrificial pattern 104S and the second sacrificial pattern 204S are removed.

[0153] Since the first and second sacrificial patterns 104S and 204S may have an etching selectivity with respect to the substrate 100 and the active film pAP, the first and second sacrificial patterns 104S and 204S may be selectively removed. The third and fourth sacrificial patterns 331 and 332 may not be removed.

[0154] Reference Fig. 20 , forming a first insulating pattern 104 and a second insulating pattern 204 .

[0155] The first insulating pattern 104 may fill the region where the first sacrificial pattern 104S is removed, and the second insulating pattern 204 may fill the region where the second sacrificial pattern 204S is removed. Each of the first insulating pattern 104 and the second insulating pattern 204 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but example embodiments are not limited thereto. For example, each of the first insulating pattern 104 and the second insulating pattern 204 may include a silicon nitride film.

[0156] Reference Fig.21 and Fig. 22 , forming a wall structure 102. For reference, Fig. 22 is along Fig.21 A cross-sectional view taken along line AA.

[0157] For example, the filling insulating film 302 on the at least one passivation film 392 or 394 may be removed. Subsequently, the at least one passivation film 392 or 394 may be removed. Thus, the wall structure 102 separating the first active pattern AP1 and the second active pattern AP2 may be formed by at least a portion of the filling insulating film 302 filling the region between the first active pattern AP1 and the second active pattern AP2.

[0158] In some example embodiments, a field insulating film 106 may be formed on the substrate 100. The field insulating film 106 may cover at least a portion of a side surface of the first fin pattern 110 and at least a portion of a side surface of the second fin pattern 210. The field insulating film 106 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but example embodiments are not limited thereto. As an example, the field insulating film 106 may include a silicon oxide film.

[0159] Reference Fig.23 and Fig.24 , a first mask pattern MP1 is formed on the second region II of the substrate 100. For reference, Fig.24 is along Fig.23 A cross-sectional view taken along line AA.

[0160] The first mask pattern MP1 may cover the second region II of the substrate 100. For example, the first mask pattern MP1 may cover the second active pattern AP2 and the fourth sacrificial pattern 332. The first mask pattern MP1 may cover at least a portion of the wall structure 102, but example embodiments are not limited thereto.

[0161] Reference Figure 25 to Figure 27 , a first dummy gate structure DG1 and a first gate spacer 140 are formed on the first region I of the substrate 100. For reference, Fig.26 is along Fig.25 A cross-sectional view taken along line AA of Fig. 27 is along Fig.25 A cross-sectional view taken along line BB.

[0162] The first dummy gate structure DGI may intersect the first active pattern AP1 and the third sacrificial pattern 331. For example, the first dummy gate structure DG1 may extend in the second direction Y on the side surface of the wall structure 102.

[0163] The first dummy gate structure DG1 may include a first dummy gate dielectric film 333 and a first dummy gate electrode 334. For example, a dielectric film and an electrode film sequentially stacked on the first region I of the substrate 100 may be formed. Subsequently, a first gate mask 350 extending in the second direction Y may be formed on the electrode film on the first region I. Subsequently, a patterning process of patterning the dielectric film and the electrode film by using the first gate mask 350 as an etching mask may be performed. The patterned dielectric film may form the first dummy gate dielectric film 333, and the patterned electrode film may form the first dummy gate electrode 334.

[0164] The first dummy gate structure DG1 may have an etch selectivity with respect to the first active pattern AP1. As an example, the first dummy gate electrode 334 may include polysilicon.

[0165] Subsequently, a first gate spacer 140 may be formed on a side surface of the first dummy gate structure DG1. The first gate spacer 140 may extend along a side surface of the first dummy gate structure DG1. The first gate spacer 140 may include, for example, at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon carbon nitride, silicon carbon oxynitride, or a combination thereof, but example embodiments are not limited thereto.

[0166] Reference Fig.28 , an etching process is performed on the first active pattern AP1 and the third sacrificial pattern 331 .

[0167] In the etching process, for example, the first dummy gate structure DG1 and the first gate spacer 140 may be used as an etching mask. When the etching process is performed, a portion of the first active pattern AP1 and a portion of the third sacrificial pattern 331 disposed outside the first dummy gate structure DG1 may be removed to form a first groove 110r. In some example embodiments, the first groove 110r may be defined on the upper surface of the first insulating pattern 104.

[0168] Reference Fig.29 , a first source / drain pattern 160 and an interlayer insulating film 180 are formed.

[0169] The first source / drain pattern 160 may be filled with Fig.28 Thus, a first source / drain pattern 160 connected to the first active pattern AP1 may be formed.

[0170] In some example embodiments, the first source / drain pattern 160 may include an epitaxial layer. For example, the first source / drain pattern 160 may be formed of the first active pattern AP1 by an epitaxial growth method.

[0171] In some example embodiments, the first source / drain pattern 160 may include a metal material such as nickel (Ni), palladium (Pd), gold (Au), titanium (Ti), silver (Ag), aluminum (Al), tungsten (W), copper (Cu), manganese (Mn), or zirconium (Zr). For example, the first source / drain pattern 160 may be formed by a deposition method.

[0172] Subsequently, an interlayer insulating film 180 may be formed covering the first source / drain pattern 160. The interlayer insulating film 180 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxynitride, or a low-k material having a dielectric constant less than that of silicon oxide, but example embodiments are not limited thereto.

[0173] Reference Fig.30 and Fig.31 , remove the first dummy gate structure DG1.

[0174] Since the first dummy gate structure DG1 may have an etching selectivity with respect to the first active pattern AP1, the first dummy gate structure DG1 may be selectively removed. When the first dummy gate structure DG1 is removed, the first active pattern AP1 and the third sacrificial pattern 331 disposed inside the first gate spacer 140 may be exposed.

[0175] Reference Fig.32 and Fig.33 , forming a first seed layer 122 .

[0176] For example, an etching process may be performed on the third sacrificial pattern 331. In the etching process, the third sacrificial pattern 331 may be selectively removed relative to the first active pattern AP1. Thus, a plurality of first bridge patterns 111 to 114 spaced apart from each other and extending in the first direction X may be formed on the first region I of the substrate 100.

[0177] In addition, during the etching process, a portion of the third sacrificial pattern 331 between the first bridge patterns 111 to 114 may not be completely removed due to a narrow space. Thus, the first seed layer 122 remaining between each of the adjacent pairs of the first bridge patterns 111 to 114 and on the side surface of the wall structure 102 may be formed by a portion of the third sacrificial pattern 331.

[0178] Reference Fig.34 and Fig.35 , forming a first 2D channel layer 124 .

[0179] The first 2D channel layer 124 may include a first transition metal dichalcogenide including a transition metal element of the first seed layer 122. The first 2D channel layer 124 may be formed by a crystal growth method using the first seed layer 122 as a seed layer. For example, the first 2D channel layer 124 may be formed by two-dimensionally growing crystals from a surface of the first seed layer 122 exposed from the first active pattern AP1 and the wall structure 102.

[0180] Reference Figure 36 to Figure 38 , forming a first gate structure GS1. As a reference, Fig.37 is along Fig.36 A cross-sectional view taken along line AA of Fig.38 is along Fig.36 A cross-sectional view taken along line BB.

[0181] For example, the first gate dielectric film 132 and the first gate electrode 134 may be sequentially stacked on the first active pattern AP1. Subsequently, a patterning process may be performed on the first gate dielectric film 132 and the first gate electrode 134. Thus, a first gate structure GS1 surrounding the periphery of each of the first bridge patterns 111 to 114 may be formed.

[0182] Reference Fig.39 and Fig.40 , a second mask pattern MP2 is formed on the first region I of the substrate 100. For reference, Fig.40 is along Fig.39 A cross-sectional view taken along line AA.

[0183] The second mask pattern MP2 may cover the first region I of the substrate 100. For example, the second mask pattern MP2 may cover the first active pattern AP1, the first source / drain pattern 160, and the first gate structure GS1. The second mask pattern MP2 may cover at least a portion of the wall structure 102, but example embodiments are not limited thereto.

[0184] Reference Figure 41 to Figure 43 , a second source / drain pattern 260, a second seed layer 222, a second 2D channel layer 224 and a second gate structure GS2 are formed on the second region II of the substrate 100. For reference, Fig.42 is along Fig.41 A cross-sectional view taken along line AA of Fig.43 is along Fig.41 Except for being formed on the second region II of the substrate 100, the formation of the second source / drain pattern 260, the second seed layer 222, the second 2D channel layer 224 and the second gate structure GS2 may be similar to the formation of the first source / drain pattern 160, the first seed layer 122, the first 2D channel layer 124 and the first gate structure GS1, and thus a detailed description thereof will be omitted.

[0185] Then, refer to Figures 1 to 5 , forming a first gate contact CB1 connected to the first gate structure GS1 and a second gate contact CB2 connected to the second gate structure GS2. Thus, the above reference can be manufactured Figures 1 to 5 A semiconductor device is described.

[0186] Meanwhile, as a method of improving the performance of semiconductor devices by improving mobility and short channel effect (SCE), semiconductor devices using two-dimensional semiconductor materials as channels are being studied. However, two-dimensional semiconductor materials have problems such as poor compatibility with commercially available silicon (Si)-based structures and processes due to their material properties, and difficulty in molding due to their very thin thickness.

[0187] In a semiconductor device and a method for manufacturing the same according to some example embodiments, a transition metal material (e.g., a first seed layer 122 and / or a second seed layer 222) remaining between bridge patterns may be used as a seed layer to form a transition metal chalcogenide material (e.g., a first 2D channel layer 124 and / or a second 2D channel layer 224). Thus, a first 2D channel layer 124 and / or a second 2D channel layer 224 including a transition metal chalcogenide material may be formed. In addition, the first 2D channel layer 124 and / or the second 2D channel layer 224 may have a single crystal structure and may have high compatibility with commercially available structures and processes based on silicon (Si). Thus, a semiconductor device with improved performance may be provided using a 2D semiconductor material as a channel region by a simple method.

[0188] Although the present invention has been specifically shown and described with reference to some exemplary embodiments of the present invention, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention as defined in the appended claims. Therefore, it is desired that the present embodiments be considered in all respects as illustrative and not restrictive, with reference to the appended claims rather than the foregoing description to indicate the scope of the present invention.

Claims

1. A semiconductor device, include: A substrate including a first region and a second region; A first active pattern extending along a first direction on the first area; a second active pattern extending along the first direction on the second area; a wall structure extending between the first region and the second region along the first direction and separating the first active pattern and the second active pattern from each other; a first gate structure intersecting the first active pattern on the first region; A first two-dimensional (2D) channel layer, between the first active pattern and the first gate structure, comprising a first transition metal dichalcogenide; a second gate structure intersecting the second active pattern on the second region; as well as A second 2D channel layer, between the second active pattern and the second gate structure, includes a second transition metal dichalcogenide.

2. The semiconductor device according to claim 1, in, The first transition metal dichalcogenide and the second transition metal dichalcogenide include the same transition metal element.

3. The semiconductor device according to claim 1, in, The first active pattern includes a plurality of bridge patterns sequentially stacked on the first region, spaced apart from each other and respectively extending along the first direction.

4. The semiconductor device according to claim 3, further comprising: include: a seed layer including an oxide of a transition metal element on a side surface of the wall structure between each of the respective adjacent pairs of the plurality of bridge patterns, The first 2D channel layer extends from the seed layer along a surface of each bridge pattern of the plurality of bridge patterns.

5. The semiconductor device according to claim 4, in, The first transition metal dichalcogenide includes the transition metal element.

6. The semiconductor device according to claim 3, in, The second 2D channel layer does not extend along an upper surface of an uppermost bridge pattern among the plurality of bridge patterns.

7. The semiconductor device according to claim 1, in, A thickness of the first 2D channel layer and a thickness of the second 2D channel layer are different from each other.

8. The semiconductor device according to claim 1, in, The wall structure further separates the first gate structure and the second gate structure from each other.

9. The semiconductor device according to claim 1, further comprising: include: a first insulating pattern extending along the first direction between the substrate and the first active pattern; as well as A second insulating pattern extends along the first direction between the substrate and the second active pattern.

10. The semiconductor device according to claim 1, in, The first region is an NFET region, and the second region is a PFET region.

11. A semiconductor device, include: substrate; a wall structure extending along a first direction on the substrate; a first sheet-like pattern extending along the first direction on the upper surface of the substrate and the side surface of the wall structure; a second sheet-like pattern extending along the first direction on an upper surface of the first sheet-like pattern and a side surface of the wall structure; a seed layer including a transition metal element on a side surface of the wall structure between the first lamellar pattern and the second lamellar pattern; a two-dimensional 2D channel layer extending from the seed layer along the surface of the first sheet-shaped pattern and the surface of the second sheet-shaped pattern, wherein the 2D channel layer comprises a transition metal dichalcogenide, and the transition metal dichalcogenide comprises the transition metal element; as well as A gate structure intersects the first sheet-shaped pattern and the second sheet-shaped pattern, and the gate structure is on the 2D channel layer.

12. The semiconductor device according to claim 11, in, The 2D channel layer has a single crystal structure.

13. The semiconductor device according to claim 11, in, The transition metal element includes at least one of molybdenum (Mo) or tungsten (W).

14. The semiconductor device according to claim 13, in, The transition metal dichalcogenide includes molybdenum disulfide MoS 2 Or tungsten disulfide WS 2 At least one of .

15. The semiconductor device according to claim 11, in, The gate structure includes a gate dielectric film and a gate electrode sequentially stacked on the 2D channel layer, The 2D channel layer does not extend along the upper surface of the second sheet pattern, and The gate dielectric film extends along an upper surface of the second sheet pattern.

16. A semiconductor device, include: A substrate including a first region and a second region; a first active pattern including a plurality of first bridge patterns sequentially stacked on the first region, spaced apart from each other and respectively extending in a first direction; a second active pattern including a plurality of second bridge patterns sequentially stacked on the second region, spaced apart from each other and respectively extending along the first direction; a wall structure extending along the first direction between the first region and the second region and separating the first active pattern and the second active pattern from each other; a first seed layer including an oxide of a transition metal element on a first side surface of the wall structure between each of the respective adjacent pairs of the plurality of first bridge patterns, a first two-dimensional 2D channel layer extending from the first seed layer along a surface of each of the plurality of first bridge patterns, wherein the first 2D channel layer comprises a first transition metal dichalcogenide, and the first transition metal dichalcogenide comprises the transition metal element; a first gate structure intersecting each of the plurality of first bridge patterns and located on the first 2D channel layer; a second seed layer including an oxide of the transition metal element on a second side surface of the wall structure between each of the respective adjacent pairs of the plurality of second bridge patterns; a second 2D channel layer extending from the second seed layer along a surface of each of the plurality of second bridge patterns, the second 2D channel layer comprising a second transition metal dichalcogenide, wherein the second transition metal dichalcogenide comprises the transition metal element; as well as The second gate structure intersects each of the plurality of second bridge patterns and is located on the second 2D channel layer.

17. The semiconductor device according to claim 16, in, Each of the first 2D channel layer and the second 2D channel layer has a single crystalline structure.

18. The semiconductor device according to claim 16, in, The first 2D channel layer does not extend along an upper surface of a first uppermost bridge pattern among the plurality of first bridge patterns, and The second 2D channel layer does not extend along an upper surface of a second uppermost bridge pattern among the plurality of second bridge patterns.

19. The semiconductor device according to claim 16, in, A thickness of the first 2D channel layer and a thickness of the second 2D channel layer are different from each other.

20. The semiconductor device according to claim 16, in, The first region is an NFET region, and the second region is a PFET region.

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