Semiconductor device

Abstract

The semiconductor device may include: a substrate including an active pattern; a device isolation layer defining an active pattern; a channel pattern on the active pattern; a gate electrode on the channel pattern; and first and second isolation patterns penetrating the gate electrode. The first isolation pattern may extend into the device isolation layer, and the second isolation pattern may be disposed to penetrate the gate electrode and the device isolation layer, and may extend into an upper portion of the substrate. A level of a bottom surface of the second isolation pattern may be lower than a level of a bottom surface of the device isolation layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority of Korean Patent Application No. 10-2023-0073823 filed in the Korean Intellectual Property Office on June 8, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device, and in particular, to a semiconductor device including a field effect transistor. Background Art

[0004] Semiconductor devices include integrated circuits composed of metal oxide semiconductor field effect transistors (MOS-FETs). In order to meet the growing demand for semiconductor devices with small pattern sizes and reduced design rules, MOS-FETs are being significantly reduced. The reduction of MOS-FETs may cause degradation in the operating characteristics of semiconductor devices. Various studies are being conducted to overcome the technical limitations associated with the reduction of semiconductor devices and to achieve high-performance semiconductor devices. Summary of the invention

[0005] Embodiments of the present disclosure provide a semiconductor device with improved reliability.

[0006] Embodiments of the present disclosure provide a semiconductor device having improved electrical characteristics.

[0007] According to an embodiment of the present disclosure, a semiconductor device may include: a substrate including an active pattern; a device isolation layer defining the active pattern; a channel pattern on the active pattern; a gate electrode on the channel pattern; and a first isolation pattern and a second isolation pattern penetrating the gate electrode. The first isolation pattern may extend into the device isolation layer, and the second isolation pattern may be arranged to penetrate the gate electrode and the device isolation layer, and may extend into an upper portion of the substrate. The level of the bottom surface of the second isolation pattern may be lower than the level of the bottom surface of the device isolation layer.

[0008] According to an embodiment of the present disclosure, a semiconductor device may include: a substrate; a device isolation layer filling a trench on the substrate; a first isolation pattern on the device isolation layer; an active contact on the first isolation pattern; and a lower power line disposed below the substrate. The lower power line may include an interconnect and a contact protruding from the interconnect toward the substrate. The contact may be disposed to penetrate the substrate, the device isolation layer, and the first isolation pattern, and may be electrically connected to the active contact.

[0009] According to an embodiment of the present disclosure, a semiconductor device may include: a first gate electrode, a second gate electrode, and a third gate electrode, which are disposed on a substrate, extend in a first direction, and are sequentially arranged in a second direction intersecting the first direction; source / drain patterns, which are respectively disposed between the first gate electrode to the third gate electrode; and an isolation structure, which penetrates the first gate electrode to the third gate electrode. The isolation structure may include: a first isolation pattern, which extends in the second direction to divide the first gate electrode into a pair of gate electrodes spaced apart from each other in the first direction; a second isolation pattern, which extends in the first direction to penetrate the second gate electrode; a third isolation pattern, which extends in the first direction to penetrate the third gate electrode; a first void, which is on a first region where the first isolation pattern and the second isolation pattern intersect each other; and a second void, which is on a second region where the first isolation pattern and the third isolation pattern intersect each other. When viewed in a plan view, the first void may be a cross-shaped region having four curved surfaces, and the second void may be a T-shaped region having two curved surfaces. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 3 is a conceptual diagram illustrating a logic unit of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 4 is a plan view showing a semiconductor device according to an embodiment of the present disclosure.

[0012] FIG. 5A to FIG. 5G is along Figure 4 Cross-sectional views taken along line AA', line BB', line CC', line DD', line EE', FF' and line GG'.

[0013] FIG. 6A to FIG. 6C are along Figure 4 2 is a cross-sectional view taken along line CC′, line FF′, and line GG′ of FIG. 1 , and illustrates a semiconductor device according to an embodiment of the present disclosure.

[0014] Fig. 7A FIG. 2 is a diagram showing a portion of a semiconductor device according to an embodiment of the present disclosure (eg, Figure 4 M) is an enlarged plan view.

[0015] Figure 7B is an enlarged plan view showing a semiconductor device according to another embodiment of the present disclosure.

[0016] Fig. 8A and Figure 8B is along Fig. 7A Cross-sectional views taken along line II' and line II-II'.

[0017] Fig.9A , Fig. 9B , Fig. 9C , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig. 12C , Fig.13A , Fig. 13B , Fig. 13C , Fig.13D , Fig.14A , Fig. 14B , Fig. 14C , Fig.14D , Fig.15A , Fig. 15B , Fig. 15C , Fig.15D , Fig.16A , Fig. 16B , Fig. 16C , Fig.16D , Fig.16E , Fig.16F , Figure 16G , Fig.17A , Fig. 17B , Fig. 17C , Fig.17D , Fig.17E , Fig.17F , Figure 17G , Fig.18A , Fig.18B , Fig. 18C , Fig.18D , Fig.18E , Fig.18F , Figure 18G , Fig.19A , Fig.19B , Fig.19C , Fig.19D , Fig.19E , Fig.19F , Figure 19G , Fig. 20A , Fig. 20B , Fig. 20C , Fig.20D , Fig.20E , Fig.20F and Figure 20G is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] Figures 1 to 3 is a conceptual diagram illustrating a logic unit of a semiconductor device according to an embodiment of the present disclosure.

[0019] Reference Figure 1, a single height cell SHC can be provided. Specifically, a first lower power line VPR1 and a second lower power line VPR2 can be disposed in a lower portion of the substrate 100. The first lower power line VPR1 can be a conduction path provided with a source voltage VSS (e.g., a ground voltage). The second lower power line VPR2 can be a conduction path provided with a drain voltage VDD (e.g., a power supply voltage).

[0020] The single height cell SHC may be defined between the first lower power line VPR1 and the second lower power line VPR2. The single height cell SHC may include one PMOSFET region PR and one NMOSFET region NR. In other words, the single height cell SHC may have a CMOS structure disposed between the first lower power line VPR1 and the second lower power line VPR2.

[0021] Each of the PMOSFET region PR and the NMOSFET region NR may have a width W1 in the first direction D1. The length of the single height cell SHC in the first direction D1 may be defined as a first height HE1. The first height HE1 may be substantially equal to a distance (e.g., a spacing) between the first lower power line VPR1 and the second lower power line VPR2.

[0022] The single height cell SHC may constitute a single logic unit. In this specification, a logic unit may refer to a logic device configured to perform a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). In other words, a logic unit may include transistors constituting the logic device and interconnects connecting the transistors to each other.

[0023] Reference Figure 2 , a double height cell DHC can be provided. Specifically, a first lower power line VPR1, a second lower power line VPR2, and a third lower power line VPR3 can be disposed on the substrate 100. The second lower power line VPR2 can be disposed between the first lower power line VPR1 and the third lower power line VPR3. The third lower power line VPR3 can be a conduction path provided with a source voltage VSS.

[0024] The double height cell DHC may be defined between the first lower power line VPR1 and the third lower power line VPR3. The double height cell DHC may include a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2.

[0025] The first NMOSFET region NR1 may be adjacent to the first lower power line VPR1. The second NMOSFET region NR2 may be adjacent to the third lower power line VPR3. The first PMOSFET region PR1 and the second PMOSFET region PR2 may be adjacent to the second lower power line VPR2. When viewed in a plan view, the second lower power line VPR2 may be disposed between the first PMOSFET region PR1 and the second PMOSFET region PR2.

[0026] The length of the double height unit DHC in the first direction D1 may be defined as a second height HE2. The second height HE2 may be Figure 1 The first PMOSFET region PR1 and the second PMOSFET region PR2 of the double-height cell DHC may be combined to function as a single PMOSFET region. Therefore, the channel size of the PMOS transistor of the double-height cell DHC may be greater than Figure 1 The channel size of the PMOS transistor of the single-height cell SHC.

[0027] For example, the channel size of the PMOS transistor of the double-height cell DHC may be about twice the channel size of the PMOS transistor of the single-height cell SHC. In this case, the double-height cell DHC may operate at a higher speed than the single-height cell SHC. In an embodiment, Figure 2 The double height cell DHC shown may be defined as a multi-height cell. Although not shown, the multi-height cell may include a triple height cell having a cell height approximately three times that of a single height cell SHC.

[0028] Reference Figure 3 , the first single height cell SHC1, the second single height cell SHC2, and the double height cell DHC may be two-dimensionally arranged on the substrate 100. The first single height cell SHC1 may be disposed between the first lower power line VPR1 and the second lower power line VPR2. The second single height cell SHC2 may be disposed between the second lower power line VPR2 and the third lower power line VPR3. The second single height cell SHC2 may be adjacent to the first single height cell SHC1 in the first direction D1.

[0029] The double height cell DHC may be disposed between the first lower power line VPR1 and the third lower power line VPR3. The double height cell DHC may be adjacent to the first single height cell SHC1 and the second single height cell SHC2 in the second direction D2.

[0030] The partition structure pattern SDB may be disposed between the first single height cell SHC1 and the double height cell DHC and between the second single height cell SHC2 and the double height cell DHC. The active region of the double height cell DHC may be electrically separated from the active region of each of the first single height cell SHC1 and the second single height cell SHC2 by the partition structure pattern SDB.

[0031] Figure 4 is a plan view showing a semiconductor device according to an embodiment of the present disclosure. FIG. 5A to FIG. 5G is along Figure 4 Cross-sectional views taken along line AA', line BB', line CC', line D-D', line EE', FF' and line GG'. Figure 4 as well as FIG. 5A to FIG. 5G Shows Figure 3 An example of a detailed structure of the first single-height cell SHC1 and the second single-height cell SHC2.

[0032] Reference Figure 4 and FIG. 5A to FIG. 5G , the edge cell SHC_P may be disposed on the substrate 100. The logic transistor constituting the logic circuit may be disposed on the edge cell SHC_P. The substrate 100 may be a semiconductor substrate formed of or including silicon, germanium, silicon germanium, a compound semiconductor material, etc. In an embodiment, the substrate 100 may be a silicon wafer.

[0033] The substrate 100 may include a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2. Each of the first PMOSFET region PR1, the second PMOSFET region PR2, the first NMOSFET region NR1, and the second NMOSFET region NR2 may extend along a second direction D2. The edge cell SHC_P may include a first NMOSFET region NR1 and a first PMOSFET region PR1.

[0034] The first active pattern AP1 and the second active pattern AP2 may be defined by a trench TR formed in an upper portion of the substrate 100. The first active pattern AP1 may be disposed on each of the first PMOSFET region PR1 and the second PMOSFET region PR2. The second active pattern AP2 may be disposed on each of the first NMOSFET region NR1 and the second NMOSFET region NR2. The first active pattern AP1 and the second active pattern AP2 may extend in the second direction D2. Each of the first active pattern AP1 and the second active pattern AP2 may be a vertical protrusion of the substrate 100.

[0035] The device isolation layer ST may be disposed on the substrate 100. The device isolation layer ST may be disposed to fill the trench TR. The device isolation layer ST may be formed of or include silicon oxide. The device isolation layer ST may not cover the first channel pattern CH1 and the second channel pattern CH2 to be described below.

[0036] The first channel pattern CH1 may be disposed on the first active pattern AP1. The second channel pattern CH2 may be disposed on the second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked sequentially. The first to third semiconductor patterns SP1, SP2, and SP3 may be spaced apart from each other in a vertical direction (i.e., a third direction D3).

[0037] Each of the first to third semiconductor patterns SP1, SP2, and SP3 may be formed of or include silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, each of the first to third semiconductor patterns SP1, SP2, and SP3 may be formed of or include crystalline silicon.

[0038] A plurality of first source / drain patterns SD1 may be disposed on the first active pattern AP1. A plurality of first grooves RS1 may be formed in an upper portion of the first active pattern AP1. The first source / drain patterns SD1 may be disposed in the first grooves RS1, respectively. The first source / drain patterns SD1 may be impurity regions of a first conductivity type (e.g., n-type). The first channel pattern CH1 may be between each pair of first source / drain patterns SD1. In other words, each pair of first source / drain patterns SD1 may be connected to each other through the stacked first to third semiconductor patterns SP1, SP2, and SP3.

[0039] A plurality of second source / drain patterns SD2 may be disposed on the second active pattern AP2. A plurality of second grooves RS2 may be formed in an upper portion of the second active pattern AP2. The second source / drain patterns SD2 may be disposed in the second grooves RS2, respectively. The second source / drain pattern SD2 may be an impurity region of a second conductivity type (e.g., p-type). The second channel pattern CH2 may be between each pair of second source / drain patterns SD2. In other words, each pair of second source / drain patterns SD2 may be connected to each other through the stacked first to third semiconductor patterns SP1, SP2, and SP3.

[0040] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be epitaxial patterns formed by a selective epitaxial growth (SEG) process. In an embodiment, each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a top surface higher than a top surface of the third semiconductor pattern SP3. In another embodiment, a top surface of at least one of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be located at substantially the same level as a top surface of the third semiconductor pattern SP3.

[0041] The first source / drain pattern SD1 may include a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the substrate 100. In this case, the pair of first source / drain patterns SD1 may apply compressive stress to the first channel pattern CH1 located therebetween. The second source / drain pattern SD2 may be formed of or include the same semiconductor material (e.g., Si) as the substrate 100.

[0042] Each of the first source / drain patterns SD1 may include a buffer layer BFL and a main layer MAL on the buffer layer BFL. Figure 5A , the buffer layer BFL may cover the inner surface of the first groove RS1. In an embodiment, the buffer layer BFL may have a substantially conformal thickness. For example, the thickness of the buffer layer BFL measured along the third direction D3 on the bottom of the first groove RS1 may be substantially equal to the thickness of the buffer layer BFL measured along the second direction D2 at the top level of the first groove RS1.

[0043] In an embodiment, the buffer layer BFL may have a thickness that decreases in an upward direction. For example, the thickness of the buffer layer BFL measured along the third direction D3 at the bottom of the first groove RS1 may be greater than the thickness of the buffer layer BFL measured along the second direction D2 at the top level of the first groove RS1. In addition, the buffer layer BFL may have a "U"-shaped cross-section corresponding to the profile of the first groove RS1.

[0044] The main layer MAL may fill most of the unfilled area of ​​the first groove RS1 covered with the buffer layer BFL. The volume of the main layer MAL may be greater than the volume of the buffer layer BFL. Each of the buffer layer BFL and the main layer MAL may be formed of or include silicon germanium (SiGe). Specifically, the buffer layer BFL may contain a relatively low concentration of germanium (Ge). In another embodiment, the buffer layer BFL may contain only silicon (Si) without germanium (Ge). The germanium concentration of the buffer layer BFL may be in the range of 0at% to 10at%.

[0045] The main layer MAL may include a relatively high concentration of germanium. In an embodiment, the germanium concentration of the main layer MAL may be in a range of 30 at % to 70 at %. The germanium concentration of the main layer MAL may increase in the third direction D3. For example, a portion of the main layer MAL adjacent to the buffer layer BFL may have a germanium concentration of about 40 at %, and an upper portion of the main layer MAL may have a germanium concentration of about 60 at %.

[0046] Each of the buffer layer BFL and the main layer MAL may contain an impurity (eg, boron, gallium, or indium) that allows the first source / drain pattern SD1 to have p-type conductivity. The impurity concentration of each of the buffer layer BFL and the main layer MAL may be within 1.0×10 18 atom / cm 3 Up to 5.0×10 22 atom / cm 3 The impurity concentration of the main layer MAL may be higher than the impurity concentration of the buffer layer BFL.

[0047] The buffer layer BFL may prevent stacking faults between the substrate 100 (i.e., the first active pattern AP1) and the main layer MAL and between the first to third semiconductor patterns SP1, SP2, and SP3 and the main layer MAL. Stacking faults may cause an increase in channel resistance. The buffer layer BFL may protect the main layer MAL in a process of replacing the second semiconductor layer SAL with the first to third portions PO1, PO2, and PO3 of the gate electrode GE, as will be described below. In other words, the buffer layer BFL may prevent an etchant material used to remove the second semiconductor layer SAL from entering and etching the main layer MAL.

[0048] Each second source / drain pattern SD2 may be formed of or include silicon (Si). The second source / drain pattern SD2 may further include an impurity (e.g., phosphorus, arsenic, or antimony) that allows the second source / drain pattern SD2 to have n-type conductivity. The impurity concentration of the second source / drain pattern SD2 may be within a range of 1.0×10 18 atom / cm 3 Up to 5.0×10 22 atom / cm 3 within the range.

[0049] The gate electrodes GE may be disposed to extend in the first direction D1 and cross the first and second channel patterns CH1 and CH2. The gate electrodes GE may be arranged at a first interval along the second direction D2. Each of the gate electrodes GE may vertically overlap the first and second channel patterns CH1 and CH2.

[0050] The gate electrode GE may include a first portion PO1 between the active pattern AP1 or AP2 and the first semiconductor pattern SP1, a second portion PO2 between the first and second semiconductor patterns SP1 and SP2, a third portion PO3 between the second and third semiconductor patterns SP2 and SP3, and a fourth portion PO4 on the third semiconductor pattern SP3.

[0051] Return to reference Figure 5D , the gate electrode GE may be disposed on the top surface TS, the bottom surface BS, and the opposite side surface SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. That is, the transistor according to the present embodiment may be a three-dimensional field effect transistor (e.g., MBCFET or GAAFET) in which the gate electrode GE is disposed to three-dimensionally surround the channel pattern.

[0052] The first isolation pattern RIS_P1 of the isolation structure RIS may be disposed on the boundary of the edge cell SHC_P. The first isolation pattern RIS_P1 may overlap the gate electrode GE, respectively. The first isolation pattern RIS_P1 may be formed of or include an insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof).

[0053] The gate electrode GE on the edge cell SHC_P can be separated from the gate electrode GE on the single height cell placed around the edge cell SHC_P by the first isolation pattern RIS_P1. That is, the gate electrode GE extending along the first direction D1 can be divided into a plurality of gate electrodes GE by the first isolation pattern RIS_P1. The first isolation pattern RIS_P1 will be described in more detail below.

[0054] Return to reference Figure 4 as well as FIG. 5A to FIG. 5G , a pair of gate spacers GS may be respectively disposed on opposite side surfaces of the fourth portion PO4 of the gate electrode GE. The gate spacer GS may extend along the gate electrode GE and in the first direction D1. The top surface of the gate spacer GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacer GS may be coplanar with the top surface of the first interlayer insulating layer 110 to be described below. The gate spacer GS may be formed of at least one of SiCN, SiCON, or SiN, or may include at least one of SiCN, SiCON, or SiN. In an embodiment, the gate spacer GS may be a multilayer structure including at least two different materials selected from SiCN, SiCON, and SiN.

[0055] Although not shown, a gate capping pattern may be disposed on the gate electrode GE. The gate capping pattern may extend along the gate electrode GE and in the first direction D1. The gate capping pattern may be formed of a material having an etching selectivity with respect to a first interlayer insulating layer 110 and a second interlayer insulating layer 120 to be described below, or may include the material. In detail, the gate capping pattern may be formed of at least one of SiON, SiCN, SiCON, or SiN, or may include at least one of SiON, SiCN, SiCON, or SiN.

[0056] The gate insulating layer GI may be interposed between the gate electrode GE and the first channel pattern CH1 and between the gate electrode GE and the second channel pattern CH2. The gate insulating layer GI may cover the top surface TS, the bottom surface BS, and the opposite side surfaces SW1 and SW2 of each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating layer GI may cover the top surface of the device isolation layer ST under the gate electrode GE.

[0057] In an embodiment, the gate insulating layer GI may include a silicon oxide layer, a silicon oxynitride layer and / or a high-k dielectric layer. The high-k dielectric layer may be formed of at least one of a high-k dielectric material having a dielectric constant higher than that of silicon oxide, or may include at least one of such high-k dielectric materials. For example, the high-k dielectric material may include at least one of the following items: hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium oxide silicon, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0058] In another embodiment, the semiconductor device may include a negative capacitance (NC) FET using a negative capacitor. For example, the gate insulating layer GI may include a ferroelectric layer exhibiting ferroelectric characteristics and a paraelectric layer exhibiting paraelectric characteristics.

[0059] The ferroelectric layer may have a negative capacitance, and the paraelectric layer may have a positive capacitance. In the case where two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance may be reduced to a value less than the capacitance of each capacitor. Conversely, in the case where at least one of the capacitors connected in series has a negative capacitance, the total capacitance of the capacitors connected in series may have a positive value and may be greater than the absolute value of each capacitance.

[0060] In the case where a ferroelectric layer having negative capacitance and a paraelectric layer having positive capacitance are connected in series, the total capacitance of the ferroelectric layer and the paraelectric layer connected in series can be increased. Due to this increase in total capacitance, a transistor including the ferroelectric layer can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0061] The ferroelectric layer may have ferroelectric properties. The ferroelectric layer may be formed of, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide and / or lead zirconium titanium oxide or include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide and / or lead zirconium titanium oxide. Here, hafnium zirconium oxide may be hafnium oxide doped with zirconium (Zr). Alternatively, hafnium zirconium oxide may be a compound composed of hafnium (Hf), zirconium (Zr) and / or oxygen (O).

[0062] The ferroelectric layer may further include a dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr) and / or tin (Sn). The type of dopant in the ferroelectric layer may vary depending on the ferroelectric material included in the ferroelectric layer.

[0063] In the case where the ferroelectric layer includes hafnium oxide, the dopant in the ferroelectric layer may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and / or yttrium (Y).

[0064] In the case where the dopant is aluminum (Al), the content of aluminum in the ferroelectric layer may be in the range of 3 at% to 8 at% (atomic percentage). Here, the content of the dopant (eg, aluminum atoms) may be the ratio of the number of aluminum atoms to the number of hafnium atoms and aluminum atoms.

[0065] In the case where the dopant is silicon (Si), the content of silicon in the ferroelectric layer can be in the range of 2at% to 10at%. In the case where the dopant is yttrium (Y), the content of yttrium in the ferroelectric layer can be in the range of 2at% to 10at%. In the case where the dopant is gadolinium (Gd), the content of gadolinium in the ferroelectric layer can be in the range of 1at% to 7at%. In the case where the dopant is zirconium (Zr), the content of zirconium in the ferroelectric layer can be in the range of 50at% to 80at%.

[0066] The paraelectric layer may have paraelectric properties. The paraelectric layer may be formed of or include, for example, at least one of silicon oxide and / or a high-k metal oxide. Metal oxides that may be used as paraelectric layers may include, for example, at least one of hafnium oxide, zirconium oxide, and / or aluminum oxide, but the present disclosure is not limited to these examples.

[0067] The ferroelectric layer and the paraelectric layer may be formed of or include the same material. The ferroelectric layer may have ferroelectric properties, but the paraelectric layer may not have ferroelectric properties. For example, in the case where the ferroelectric layer and the paraelectric layer contain hafnium oxide, the crystal structure of the hafnium oxide in the ferroelectric layer may be different from the crystal structure of the hafnium oxide in the paraelectric layer.

[0068] The ferroelectric layer can exhibit ferroelectric properties only when the thickness of the ferroelectric layer is within a specific range. In an embodiment, the thickness of the ferroelectric layer can be in the range of 0.5nm to 10nm, but the present disclosure is not limited to this example. Since the critical thickness associated with the appearance of ferroelectric properties varies depending on the type of ferroelectric material, the thickness of the ferroelectric layer can be changed according to the type of ferroelectric material.

[0069] As an example, the gate insulating layer GI may include a single ferroelectric layer. As another example, the gate insulating layer GI may include a plurality of ferroelectric layers spaced apart from each other. The gate insulating layer GI may have a multilayer structure in which a plurality of ferroelectric layers and a plurality of paraelectric layers are alternately stacked.

[0070] The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate insulating layer GI and may be adjacent to the first to third semiconductor patterns SP1, SP2, and SP3. The first metal pattern may include a work function metal, which may be used to adjust the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, a transistor with a desired threshold voltage may be realized. For example, the first to third portions PO1, PO2, and PO3 of the gate electrode GE may be composed of a first metal pattern including a work function metal.

[0071] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include a layer composed of at least one metal material selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), molybdenum (Mo) and nitrogen (N). In an embodiment, the first metal pattern may further include carbon (C). The first metal pattern may include a plurality of stacked work function metal layers.

[0072] The second metal pattern may be formed of or include a metal material having a lower resistance than that of the first metal pattern. For example, the second metal pattern may include at least one metal material selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the fourth portion PO4 of the gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern.

[0073] Return to reference Figure 5B, the internal spacer IP may be disposed on the first NMOSFET region NR1 and the second NMOSFET region NR2. In other words, the internal spacer IP may be disposed on the second active pattern AP2. The internal spacer IP may be respectively interposed between the first to third portions PO1, PO2, and PO3 of the gate electrode GE and the second source / drain pattern SD2. The internal spacer IP may be in direct contact with the second source / drain pattern SD2. Each of the first to third portions PO1, PO2, and PO3 of the gate electrode GE may be spaced apart from the second source / drain pattern SD2 by the internal spacer IP.

[0074] The first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. The top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surface of the gate electrode GE and the top surface of the gate spacer GS. Although not shown, the top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surface of the gate capping pattern and the top surface of the gate spacer GS. The second interlayer insulating layer 120 may be disposed on the first interlayer insulating layer 110. The third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. The fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. In an embodiment, at least one of the first to fourth interlayer insulating layers 110 to 140 may include a silicon oxide layer.

[0075] The isolation structure RIS may include a second isolation pattern RIS_P2 and a third isolation pattern RIS_P3 disposed at one side of the edge cell SHC_P and extending along the first direction D1. For example, the second isolation pattern RIS_P2 may be disposed on a boundary of the edge cell SHC_P. The third isolation pattern RIS_P3 may be spaced apart from the second isolation pattern RIS_P2, with the first source / drain pattern SD1 and the second source / drain pattern SD2 interposed therebetween.

[0076] The second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may extend in the first direction D1 to be parallel to the gate electrode GE. A spacing between the second isolation pattern RIS_P2 and the gate electrode GE adjacent to each other or a spacing between the second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may be equal to the first spacing. The second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may be formed of or include an insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof).

[0077] The second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may be provided to penetrate the gate electrode GE and may extend into the first active pattern AP1 and the second active pattern AP2. The second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may be provided to penetrate the first active pattern AP1 and the second active pattern AP2 and may extend into the upper portion of the substrate 100. Each of the second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may electrically separate the active region of each single-height cell from the active region of an adjacent cell. The second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 will be described in more detail below.

[0078] The active contact AC may be disposed to penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. A pair of active contact portions AC may be disposed at both sides of the gate electrode GE, respectively. When viewed in a plan view, the active contact portion AC may be a stripe pattern extending along the first direction D1.

[0079] The active contact AC may be a self-aligned contact. In other words, the active contact AC may be formed by a self-aligned process using the gate spacer GS. For example, the active contact AC may cover at least a portion of the side surface of the gate spacer GS. Although not shown, the active contact AC may be provided to cover a portion of the top surface of the gate capping pattern.

[0080] The metal-semiconductor compound layer SC (e.g., a silicide layer) may be interposed between the active contact AC and the first source / drain pattern SD1 and between the active contact AC and the second source / drain pattern SD2, respectively. The active contact AC may be electrically connected to the source / drain pattern SD1 or SD2 through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC may be formed of at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or cobalt silicide, or may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or cobalt silicide.

[0081] The gate contacts GC may be disposed to penetrate the second interlayer insulating layer 120 and may be electrically connected to the gate electrodes GE, respectively. When viewed in a plan view, the two gate contacts GC on the edge cell SHC_P may be disposed on and overlap the first PMOSFET region PR1. In other words, the two gate contacts GC on the edge cell SHC_P may be disposed on the first active pattern AP1 (see, for example, Figure 5A). When viewed in a plan view, one gate contact GC on the edge cell SHC_P may be disposed on and overlap the first NMOSFET region NR1. In other words, the gate contact GC on the edge cell SHC_P may be disposed on the second active pattern AP2 (eg, see Figure 5B ).

[0082] The gate contact GC can be freely disposed on the gate electrode GE without any restriction on its position. For example, the gate contact GC can be disposed on the second PMOSFET region PR2, the second NMOSFET region NR2, and the device isolation layer ST filling the trench TR (see, for example, Figure 4 ).

[0083] In an embodiment, reference is made to Figure 5A , Figure 5B and Figure 5E , the upper portion of the active contact AC adjacent to the gate contact GC may be filled with an upper insulating pattern UIP. The bottom surface of the upper insulating pattern UIP may be lower than the bottom surface of the gate contact GC. In other words, the top surface of the active contact AC adjacent to the gate contact GC may be formed at a level lower than the bottom surface of the gate contact GC by the upper insulating pattern UIP. Therefore, the gate contact GC and the active contact AC adjacent to each other may be prevented from contacting each other, thereby preventing a short circuit problem from occurring between them.

[0084] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may be formed of at least one of a metal material (e.g., aluminum, copper, tungsten, molybdenum, and cobalt) or include at least one of a metal material (e.g., aluminum, copper, tungsten, molybdenum, and cobalt). The barrier pattern BM may be provided to cover the side surface and the bottom surface of the conductive pattern FM. In an embodiment, the barrier pattern BM may include a metal layer and a metal nitride layer. The metal layer may be formed of at least one of titanium, tantalum, tungsten, nickel, cobalt, or platinum or include at least one of titanium, tantalum, tungsten, nickel, cobalt, or platinum. The metal nitride layer may be formed of at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN), or may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN).

[0085] Return to reference Figure 4 , Figure 5C and Figure 5E, the first lower power line VPR1 and the second lower power line VPR2 may be disposed under the substrate 100. The first lower power line VPR1 and the second lower power line VPR2 may extend in the second direction D2 to be parallel to each other. The first lower power line VPR1 and the second lower power line VPR2 may be disposed on a boundary of the edge cell SHC_P.

[0086] Return to reference Figure 5C and Figure 5E , the second lower power line VPR2 may be electrically connected to at least one active contact AC. The second lower power line VPR2 may include an interconnection and a contact, the interconnection being a linear pattern extending along the second direction D2, and the contact extending from the interconnection to protrude along the third direction D3. Specifically, the contact may be arranged to penetrate the substrate 100, the device isolation layer ST, and the first isolation pattern RIS_P1 and to contact the active contact AC. The width of the contact may decrease as the distance to the active contact AC in the third direction D3 decreases. As a result, in the semiconductor device according to the present embodiment, the lower power lines VPR1 and VPR2 may be electrically connected to the source / drain patterns SD1 and SD2 through the active contact AC.

[0087] The first lower power line VPR1 and the second lower power line VPR2 may include a conductive pattern FM and a blocking pattern BM. For example, the conductive pattern may be formed of at least one of a metal material (e.g., aluminum, copper, tungsten, molybdenum, and cobalt) or include at least one of a metal material (e.g., aluminum, copper, tungsten, molybdenum, and cobalt). In an embodiment, the blocking pattern BM may include a metal layer and a metal nitride layer. The metal layer may be formed of at least one of titanium, tantalum, tungsten, nickel, cobalt, or platinum or include at least one of titanium, tantalum, tungsten, nickel, cobalt, or platinum. The metal nitride layer may be formed of at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN), or may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN).

[0088] The bottom surface of the interconnection may be coplanar with the bottom surface 100b of the substrate 100. The power delivery network layer PDN may be disposed on the bottom surface 100b of the substrate 100. The power delivery network layer PDN may include a plurality of lower interconnection lines electrically connected to the first lower power line VPR1 and the second lower power line VPR2. As an example, the power delivery network layer PDN may include a wiring network for applying a source voltage VSS to the first lower power line VPR1. The power delivery network layer PDN may include a wiring network for applying a drain voltage VDD to the second lower power line VPR2.

[0089] The first metal layer M1 may be disposed in the third interlayer insulating layer 130. The first metal layer M1 may include first interconnection lines M1_I. The first interconnection lines M1_I of the first metal layer M1 may extend in the second direction D2 to be parallel to each other.

[0090] According to an embodiment of the present disclosure, the lower power lines VPR1 and VPR2 disposed under the substrate 100 may be used as power lines for supplying power to the single-height cells. Therefore, the power lines may be omitted from the first metal layer M1. The first interconnect lines M1_I for signal transmission may be disposed in the first metal layer M1. The first interconnect lines M1_I may be arranged at a second pitch along the first direction D1. The second pitch may be smaller than the first pitch.

[0091] The first metal layer M1 may further include first vias VI1. The first vias VI1 may be respectively disposed under the first interconnection lines M1_I of the first metal layer M1. The first interconnection lines M1_I of the first metal layer M1 may be electrically connected to the active contact AC through the first vias VI1. The first interconnection lines M1_I of the first metal layer M1 may be electrically connected to the gate contact GC through the first vias VI1.

[0092] The first interconnection line M1_I of the first metal layer M1 and the first via hole VI1 thereunder may be formed separately by different processes. That is, each of the first interconnection line M1_I and the first via hole VI1 of the first metal layer M1 may be formed by a single damascene process. The semiconductor device according to the present embodiment may be manufactured using a sub-20 nm process.

[0093] The second metal layer M2 may be disposed in the fourth interlayer insulating layer 140. The second metal layer M2 may include a plurality of second interconnection lines M2_I. Each second interconnection line M2_I of the second metal layer M2 may be a linear or stripe pattern extending along the first direction D1. In other words, the second interconnection lines M2_I may extend along the first direction D1 to be parallel to each other.

[0094] The second metal layer M2 may further include second vias VI2 respectively disposed under the second interconnects M2_I. The first interconnects M1_I of the first metal layer M1 and the second interconnects M2_I of the second metal layer M2 may be electrically connected to each other through the second vias VI2. In an embodiment, the second interconnects M2_I of the second metal layer M2 and the second vias VI2 thereunder may be formed by a dual damascene process.

[0095] The first interconnection line M1_I of the first metal layer M1 and the second interconnection line M2_I of the second metal layer M2 may be formed of the same conductive material or different conductive materials, or may include the same conductive material or different conductive materials. For example, the first interconnection line M1_I of the first metal layer M1 and the second interconnection line M2_I of the second metal layer M2 may be formed of at least one of metal materials (e.g., aluminum, copper, tungsten, molybdenum, ruthenium, and cobalt), or may include at least one of metal materials (e.g., aluminum, copper, tungsten, molybdenum, ruthenium, and cobalt). Although not shown, a plurality of metal layers (e.g., M3, M4, M5, etc.) may be additionally stacked on the fourth interlayer insulating layer 140. Each stacked metal layer may include an interconnection line used as a routing path between units.

[0096] Return to reference Figure 4 and FIG. 5A to FIG. 5G , the isolation structure RIS may be disposed on the boundary of the edge cell SHC_P. The isolation structure RIS may be disposed to cut the plurality of gate electrodes GE extending along the first direction D1. The isolation structure RIS may be disposed to penetrate the gate electrode GE and the active patterns AP1 and AP2. In other words, the isolation structure RIS may electrically separate the active area of ​​the single height cell from the active area of ​​the adjacent cell.

[0097] The isolation structure RIS may include a first isolation pattern RIS_P1, a second isolation pattern RIS_P2, and a third isolation pattern RIS_P3. The first isolation pattern RIS_P1 may extend in the second direction D2. The first isolation pattern RIS_P1 may divide one gate electrode GE into a pair of gate electrodes GE spaced apart from each other in the first direction D1. The second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may extend in the first direction D1. The second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may be provided to penetrate the gate electrode GE.

[0098] Reference Figure 4 , Figure 5C and Figure 5D The first isolation pattern RIS_P1 may be disposed on the substrate 100 between the first PMOSFET region PR1 and the second PMOSFET region PR2, between the first NMOSFET region NR1 and the second NMOSFET region NR2, or between the first PMOSFET region PR1 and the first NMOSFET region NR1.

[0099] The first isolation pattern RIS_P1 may be arranged to penetrate the gate electrode GE and the gate insulating layer GI, and may extend to the device isolation layer ST. Specifically, the first isolation pattern RIS_P1 may extend into the device isolation layer ST. The level LV1 of the bottom surface of the first isolation pattern RIS_P1 may be higher than the level LV_ST of the bottom surface of the device isolation layer ST. The top surface of the first isolation pattern RIS_P1 may be substantially coplanar with the top surface of the gate electrode GE. In an embodiment, the top surface of the first isolation pattern RIS_P1 may be higher than the top surface of the gate electrode GE. In other words, the top surface of the first isolation pattern RIS_P1 may be located at a level equal to or higher than the top surface of the gate electrode GE.

[0100] In an embodiment, although not shown, a gate capping pattern may be disposed on the gate electrode GE. A top surface of the first isolation pattern RIS_P1 may be located at the same level as a top surface of the gate capping pattern. A top surface of the first isolation pattern RIS_P1 may be located at a level higher than a top surface of the gate capping pattern.

[0101] The first isolation pattern RIS_P1 may be a single layer including at least one of silicon oxide, silicon nitride, or silicon oxynitride. That is, the first isolation pattern RIS_P1 may be a single layer including an insulating material. The first isolation pattern RIS_P1 may further include a void formed near its top surface. The void will be described in more detail below.

[0102] The first isolation pattern RIS_P1 may have a first height P1H. The first height P1H may be defined as a vertical distance from a bottom surface of the first isolation pattern RIS_P1 to an uppermost surface of the first isolation pattern RIS_P1. For example, the first height P1H may be in a range of 90 nm to 130 nm.

[0103] Reference Figure 4 , Figure 5A , Figure 5B , Fig. 5F and Figure 5G , the second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may be disposed on the first PMOSFET region PR1 or the first NMOSFET region NR1. The second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 on the first PMOSFET region PR1 may be spaced apart from each other, with the first source / drain pattern SD1 interposed therebetween. The second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 on the first NMOSFET region NR1 may be spaced apart from each other, with the second source / drain pattern SD2 interposed therebetween.

[0104] The second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may be disposed to penetrate the gate electrode GE, the gate insulating layer GI, and the device isolation layer ST, and may extend to the substrate 100. In detail, the second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may extend into the upper portion of the substrate 100. The level LV2 of the bottom surface of the second isolation pattern RIS_P2 may be lower than the level LV_ST of the bottom surface of the device isolation layer ST. The level LV3 of the bottom surface of the third isolation pattern RIS_P3 may be lower than the level LV_ST of the bottom surface of the device isolation layer ST.

[0105] The top surface of each of the second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may be substantially coplanar with the top surface of the gate electrode GE. In an embodiment, the top surface of each of the second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may be higher than the top surface of the gate electrode GE. In other words, the top surface of each of the second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may be located at a level equal to or higher than the top surface of the gate electrode GE.

[0106] In an embodiment, although not shown, a gate capping pattern may be disposed on the gate electrode GE. A top surface of each of the second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may be located at the same level as a top surface of the gate capping pattern. A top surface of each of the second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may be located at a level higher than a top surface of the gate capping pattern.

[0107] Each of the second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may be composed of a single layer including at least one of silicon oxide, silicon nitride, or silicon oxynitride. In other words, each of the second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may be a single layer including an insulating material. Each of the second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may further include a void formed near a top surface thereof. The void will be described in more detail below.

[0108] The second isolation pattern RIS_P2 may have a second height P2H, and the third isolation pattern RIS_P3 may have a third height P3H. The second height P2H may be defined as a vertical distance from the bottom surface of the second isolation pattern RIS_P2 to the uppermost surface of the second isolation pattern RIS_P2. The third height P3H may be defined as a vertical distance from the bottom surface of the third isolation pattern RIS_P3 to the uppermost surface of the third isolation pattern RIS_P3. The second height P2H and the third height P3H may be equal to each other. For example, both the second height P2H and the third height P3H may be in the range of 140nm to 180nm.

[0109] Return to reference Fig. 5F , the second isolation pattern RIS_P2 may include a first portion and a second portion. The first portion may be configured to penetrate the gate electrode GE and the gate insulating layer GI, and may extend into the device isolation layer ST. The first portion may have a first depth P2H_F. The first depth P2H_F may be defined as a vertical distance from the top surface of the device isolation layer ST to the bottom surface of the second interlayer insulating layer 120. The first depth P2H_F may be equal to Figure 5C For example, the first depth P2H_F may be in the range of 90 nm to 130 nm.

[0110] The second portion may be disposed to penetrate the gate electrode GE, the gate insulating layer GI, and the active pattern, and may extend into the upper portion of the substrate 100. The second portion may have a second depth P2H_V. The second depth P2H_V may be defined as a vertical distance from the lowermost surface of the second isolation pattern RIS_P2 to the bottom surface of the second interlayer insulating layer 120. The second depth P2H_V may be equal to Figure 5A For example, the second depth P2H_V may be in the range of 140 nm to 180 nm.

[0111] Return to reference Figure 5G , the third isolation pattern RIS_P3 may include a third portion and a fourth portion. The third portion may be configured to penetrate the gate electrode GE and the gate insulating layer GI, and may extend into the device isolation layer ST. The third portion may have a third depth P3H_F. The third depth P3H_F may be defined as a vertical distance from the top surface of the device isolation layer ST to the bottom surface of the second interlayer insulating layer 120. The third depth P3H_F may be equal to Figure 5C For example, the third depth P3H_F may be in the range of 90 nm to 130 nm.

[0112] The fourth portion may be disposed to penetrate the gate electrode GE, the gate insulating layer GI, and the active pattern AP1 or AP2, and may extend into the upper portion of the substrate 100. The fourth portion may have a fourth depth P3H_V. The fourth depth P3H_V may be defined as a vertical distance from the lowermost surface of the third isolation pattern RIS_P3 to the bottom surface of the second interlayer insulating layer 120. The fourth depth P3H_V may be equal to Figure 5A For example, the fourth depth P3H_V may be in the range of 140 nm to 180 nm.

[0113] In other words, the second isolation pattern RIS_P2 may include a first portion and a second portion having vertical lengths different from each other, and the third isolation pattern RIS_P3 may include a third portion and a fourth portion having vertical lengths different from each other. This may be because there may be a difference in etching rate or etching selectivity between the device isolation layer ST and the active patterns AP1 and AP2 under an etching gas or an etchant material used in a subsequent etching process of the manufacturing process.

[0114] The level LV1 of the bottom surface of the first isolation pattern RIS_P1 may be higher than the level LV_ST of the bottom surface of the device isolation layer ST, and the level LV3 of the bottom surface of the third isolation pattern RIS_P3 may be lower than the level LV_ST of the bottom surface of the device isolation layer ST. In other words, the level LV_ST of the bottom surface of the device isolation layer ST may be placed between the level LV1 of the bottom surface of the first isolation pattern RIS_P1 and the level LV3 of the bottom surface of the third isolation pattern RIS_P3.

[0115] In an embodiment, the above structures of the isolation structure RIS may be formed simultaneously. In other words, the first to third isolation patterns RIS_P1, RIS_P2, and RIS_P3 of the isolation structure RIS may be formed as a single object. Since the first to third isolation patterns RIS_P1, RIS_P2, and RIS_P3 are formed simultaneously, Figure 5C The first height P1H, Fig. 5F The first depth P2H_F and Figure 5G The third depths P3H_F of the semiconductor device may be substantially equal to each other. In addition, the number of photomasks used to form the first to third isolation patterns RIS_P1, RIS_P2, and RIS_P3 as a single object may be reduced, thereby reducing the manufacturing cost of the semiconductor device. As a result, the efficiency of the manufacturing process of the semiconductor device and the reliability of the semiconductor device may be improved.

[0116] Below, various embodiments of the present disclosure will be described. In the following description of these embodiments, for the sake of simplicity, the previous reference Figure 4 and FIG. 5A to FIG. 5GDescribed elements may be identified by the same reference numerals without repeating their overlapping descriptions. FIG. 6A to FIG. 6C is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure. Fig. 6A , Figure 6B and Figure 6C are along Figure 4 Cross-sectional views taken along lines CC', F-F' and G-G'.

[0117] Reference FIG. 6A to FIG. 6C , the first isolation pattern RIS_P1 may have a fourth height P1H'. The fourth height P1H' may be defined as a vertical distance from the bottom surface of the first isolation pattern RIS_P1 to the uppermost surface of the first isolation pattern RIS_P1. In other words, the first isolation pattern RIS_P1 may be disposed to penetrate the gate electrode GE, the gate insulating layer GI, and the device isolation layer ST, and may extend to the upper portion of the substrate 100.

[0118] The second isolation pattern RIS_P2 may have a fifth height P2H'. The fifth height P2H' may be defined as a vertical distance from the bottom surface of the second isolation pattern RIS_P2 to the uppermost surface of the second isolation pattern RIS_P2. The bottom surface of the second isolation pattern RIS_P2 may be located at the same level as the bottom surface of the first isolation pattern RIS_P1.

[0119] The third isolation pattern RIS_P3 may have a sixth height P3H'. The sixth height P3H' may be defined as a vertical distance from the bottom surface of the third isolation pattern RIS_P3 to the uppermost surface of the third isolation pattern RIS_P3. The bottom surface of the third isolation pattern RIS_P3 may be located at the same level as the bottom surfaces of the first isolation pattern RIS_P1 and the second isolation pattern RIS_P2.

[0120] The top surface of each of the first isolation pattern RIS_P1, the second isolation pattern RIS_P2, and the third isolation pattern RIS_P3 may be substantially coplanar with the top surface of the gate electrode GE. In an embodiment, the top surface of each of the first isolation pattern RIS_P1, the second isolation pattern RIS_P2, and the third isolation pattern RIS_P3 may be higher than the top surface of the gate electrode GE. Since the first to third isolation patterns RIS_P1, RIS_P2, and RIS_P3 have top surfaces at the same level and bottom surfaces at the same level, the fourth height P1H', the fifth height P2H', and the sixth height P3H' may be equal to each other.

[0121] Return to reference Figure 6C, the level LV1 of the bottom surface of the first isolation pattern RIS_P1 may be equal to the level LV3 of the bottom surface of the third isolation pattern RIS_P3. The level LV1 of the bottom surface of the first isolation pattern RIS_P1 and the level LV3 of the bottom surface of the third isolation pattern RIS_P3 may be lower than the level LV_ST of the bottom surface of the device isolation layer ST. In other words, the bottom surface of the first isolation pattern RIS_P1 and the bottom surface of the third isolation pattern RIS_P3 may be located at a level lower than the bottom surface of the device isolation layer ST. Since the bottom surface of the second isolation pattern RIS_P2 is located at the same level as the bottom surface of the first isolation pattern RIS_P1 and the bottom surface of the third isolation pattern RIS_P3, the level of the bottom surface of the second isolation pattern RIS_P2 may be lower than the level LV_ST of the bottom surface of the device isolation layer ST.

[0122] According to an embodiment of the present disclosure, an etchant material for etching the metal material in the gate electrode GE may be selected to etch silicon oxide or silicon with the same etching selectivity. In this case, the device isolation layer ST and the active patterns AP1 and AP2 may be uniformly etched, and therefore, the first to third isolation patterns RIS_P1, RIS_P2, and RIS_P3 may have the same vertical length. In other words, the fourth height P1H', the fifth height P2H', and the sixth height P3H' may be equal to each other.

[0123] In the following description, for the sake of simplicity, the previous reference Figure 4 , FIG. 5A to FIG. 5G as well as FIG. 6A to FIG. 6C Described elements may be identified by the same reference numerals without repeating their overlapping descriptions. Fig. 7A FIG. 2 is a diagram showing a portion of a semiconductor device according to an embodiment of the present disclosure (eg, Figure 4 M) is an enlarged plan view, and Figure 7B is an enlarged plan view showing a semiconductor device according to another embodiment of the present disclosure. Fig. 8A and Figure 8B is along Fig. 7A Cross-sectional views taken along line II' and line II-II'.

[0124] Reference Figure 4 and Fig. 7A , a plurality of gate electrodes GE may be disposed on the substrate 100 to extend along the first direction D1. The gate electrodes GE may be sequentially arranged along the second direction D2. The sequentially arranged gate electrodes GE may include a first gate electrode, a second gate electrode, and a third gate electrode.

[0125] The source / drain patterns may be disposed between the first to third gate electrodes, respectively. The source / drain patterns may be disposed on the first and second PMOSFET regions PR1 and PR2 and the first and second NMOSFET regions NR1 and NR2.

[0126] The isolation structure RIS may include a first isolation pattern RIS_P1 extending in the second direction D2, and second and third isolation patterns RIS_P2 and RIS_P3 extending in the first direction D1. In detail, when viewed in a plan view, the first isolation pattern RIS_P1 spaced apart from each other in the first direction D1, and the second and third isolation patterns RIS_P2 and RIS_P3 spaced apart from each other in the second direction D2 may have a closed loop shape or a closed circular ring shape.

[0127] The isolation structure RIS may be arranged to penetrate the first gate electrode to the third gate electrode. Specifically, the first isolation pattern RIS_P1 may be arranged to penetrate the first gate electrode and divide each first gate electrode into a pair of gate electrodes spaced apart from each other in the first direction D1. The second isolation pattern RIS_P2 may be arranged to penetrate the second gate electrode, and the third isolation pattern RIS_P3 may be arranged to penetrate the third gate electrode. For example, the second isolation pattern RIS_P2 may be arranged to penetrate the entire second gate electrode, and the third isolation pattern RIS_P3 may be arranged to penetrate a portion of the third gate electrode.

[0128] Return to reference Fig. 7A , the isolation structure RIS may include a first region CR1 and a second region CR2, in which the first isolation pattern RIS_P1 and the second isolation pattern RIS_P2 intersect each other, and in which the first isolation pattern RIS_P1 and the third isolation pattern RIS_P3 intersect each other. The isolation structure RIS may further include a void portion VDE adjacent to a top surface thereof. The void portion VDE may include a first void VD1 on the first region CR1 and a second void VD2 on the second region CR2.

[0129] When viewed in a plan view, the first void VD1 may be a cross-shaped empty region including four curved surfaces CS1 to CS4. When viewed in a plan view, the second void VD2 may be a T-shaped empty region including two curved surfaces CS5 and CS6.

[0130] Fig. 8A and Figure 8B is along Fig. 7A The cross-sectional view taken along line II' and line II-II'. Fig. 7AAs shown, line II' and line II-II' are selected to be parallel to the fourth direction D4 and the fifth direction D5, respectively. The fourth direction D4 may be defined to intersect both the first direction D1 and the second direction D2. The fifth direction D5 may be defined to be orthogonal to the fourth direction D4.

[0131] Reference Fig. 8A and Figure 8B , the isolation structure RIS may be a single layer deposited by a chemical vapor deposition (CVD) process. The single layer may include a first isolation layer RISL1 extending from the bottom surface of the isolation trench RIS_TR to the side surface thereof, a second isolation layer RISL2 on the first isolation layer RISL1, and a third isolation layer RISL3 on the second isolation layer RISL2. The single layer may be a layer formed by sequentially depositing the first isolation layer RISL1, the second isolation layer RISL2, and the third isolation layer RISL3.

[0132] In a single layer of a semiconductor device according to an embodiment of the present disclosure, there may be no observable interface between the first isolation layer RISL1 and the second isolation layer RISL2 and / or between the second isolation layer RISL2 and the third isolation layer RISL3. In other words, the isolation structure RIS may be a single layer in which the first to third isolation layers RISL1, RISL2, and RISL3 are connected to each other without any observable interface.

[0133] The first void VD1 may be adjacent to the top surface of the isolation structure RIS. The first void VD1 may be surrounded by the second curved surface CS2 and the third curved surface CS3 opposite to each other in the fourth direction D4, and the first curved surface CS1 and the fourth curved surface CS4 opposite to each other in the fifth direction D5. In an embodiment, the first void VD1 may have a hemispherical shape recessed in a downward direction.

[0134] Return to reference Figure 7B , the isolation structure RIS may be a double layer deposited by a chemical vapor deposition (CVD) process. In detail, each of the first to third isolation patterns RIS_P1, RIS_P2, and RIS_P3 (eg, Fig. 7A The first sub-isolation pattern RIS_N may be formed of or include a first sub-isolation pattern RIS_N and a second sub-isolation pattern RIS_O on the first sub-isolation pattern RIS_N. The first sub-isolation pattern RIS_N may be formed of or include silicon nitride or silicon oxynitride. The second sub-isolation pattern RIS_O may be formed of or include silicon oxide.

[0135] The isolation structure RIS may include a first region CR1 and a second region CR2. Fig. 7A The first isolation pattern RIS_P1 and the second isolation pattern RIS_P2 cross each other in the second region CR2. Fig. 7A The first isolation pattern RIS_P1 and the third isolation pattern RIS_P3 of the isolation structure RIS may cross each other. The isolation structure RIS may further include a void portion VDE adjacent to a top surface thereof. Specifically, the void portion VDE may be between the second sub-isolation patterns RIS_O. The void portion VDE may include a first void disposed on the first region CR1 and having a cross-shaped form and a second void VD2 disposed on the second region CR2 and having a T-shaped form.

[0136] Below, various embodiments of the present disclosure will be described. In the following description of these embodiments, for the sake of simplicity, the previous reference Figure 4 and FIG. 5A to FIG. 5G Described elements may be identified by the same reference numerals without repeating their overlapping descriptions. FIG. 6A to FIG. 6C is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure. Fig. 6A , Figure 6B and Figure 6C are respectively along Figure 4 Cross-sectional views taken along lines CC', F-F' and G-G'.

[0137] Reference FIG. 6A to FIG. 6C , the first isolation pattern RIS_P1 may have a fourth height P1H'. The fourth height P1H' may be defined as a vertical distance from the bottom surface of the first isolation pattern RIS_P1 to the uppermost surface of the first isolation pattern RIS_P1. In other words, the first isolation pattern RIS_P1 may be disposed to penetrate the gate electrode GE, the gate insulating layer GI, and the device isolation layer ST, and may extend to the upper portion of the substrate 100.

[0138] The second isolation pattern RIS_P2 may have a fifth height P2H'. The fifth height P2H' may be defined as a vertical distance from the bottom surface of the second isolation pattern RIS_P2 to the uppermost surface of the second isolation pattern RIS_P2. The bottom surface of the second isolation pattern RIS_P2 may be located at the same level as the bottom surface of the first isolation pattern RIS_P1.

[0139] The third isolation pattern RIS_P3 may have a sixth height P3H'. The sixth height P3H' may be defined as a vertical distance from the bottom surface of the third isolation pattern RIS_P3 to the uppermost surface of the third isolation pattern RIS_P3. The bottom surface of the third isolation pattern RIS_P3 may be located at the same level as the bottom surfaces of the first isolation pattern RIS_P1 and the second isolation pattern RIS_P2.

[0140] The top surface of each of the first isolation pattern RIS_P1, the second isolation pattern RIS_P2, and the third isolation pattern RIS_P3 may be substantially coplanar with the top surface of the gate electrode GE. In an embodiment, the top surface of each of the first isolation pattern RIS_P1, the second isolation pattern RIS_P2, and the third isolation pattern RIS_P3 may be higher than the top surface of the gate electrode GE. Since the first to third isolation patterns RIS_P1, RIS_P2, and RIS_P3 have top surfaces at the same level and bottom surfaces at the same level, the fourth height P1H', the fifth height P2H', and the sixth height P3H' may be equal to each other.

[0141] Return to reference Figure 6C , the level LV1 of the bottom surface of the first isolation pattern RIS_P1 may be equal to the level LV3 of the bottom surface of the third isolation pattern RIS_P3. The level LV1 of the bottom surface of the first isolation pattern RIS_P1 and the level LV3 of the bottom surface of the third isolation pattern RIS_P3 may be lower than the level LV_ST of the bottom surface of the device isolation layer ST. In other words, the bottom surface of the first isolation pattern RIS_P1 and the bottom surface of the third isolation pattern RIS_P3 may be located at a level lower than the bottom surface of the device isolation layer ST. Since the bottom surface of the second isolation pattern RIS_P2 is located at the same level as the bottom surface of the first isolation pattern RIS_P1 and the bottom surface of the third isolation pattern RIS_P3, the level of the bottom surface of the second isolation pattern RIS_P2 may be lower than the level LV_ST of the bottom surface of the device isolation layer ST.

[0142] According to an embodiment of the present disclosure, an etchant material for etching the metal material in the gate electrode GE may be selected to etch silicon oxide or silicon with the same etching selectivity. In this case, the device isolation layer ST and the active patterns AP1 and AP2 may be uniformly etched, and therefore, the first to third isolation patterns RIS_P1, RIS_P2, and RIS_P3 may have the same vertical length. In other words, the fourth height P1H', the fifth height P2H', and the sixth height P3H' may be equal to each other.

[0143] In the following description, for the sake of simplicity, the previous reference Figure 4 , FIG. 5A to FIG. 5G as well as FIG. 6A to FIG. 6C Described elements may be identified by the same reference numerals without repeating their overlapping descriptions. Fig. 7A FIG. 2 is a diagram showing a portion of a semiconductor device according to an embodiment of the present disclosure (eg, Figure 4 M) is an enlarged plan view, and Figure 7Bis an enlarged plan view showing a semiconductor device according to another embodiment of the present disclosure. Fig. 8A and Figure 8B is along Fig. 7A Cross-sectional views taken along line II' and line II-II'.

[0144] Reference Figure 4 and Fig. 7A , a plurality of gate electrodes GE may be disposed on the substrate 100 to extend along the first direction D1. The gate electrodes GE may be sequentially arranged along the second direction D2. The sequentially arranged gate electrodes GE may include a first gate electrode, a second gate electrode, and a third gate electrode.

[0145] The source / drain patterns may be disposed between the first to third gate electrodes, respectively. The source / drain patterns may be disposed on the first and second PMOSFET regions PR1 and PR2 and the first and second NMOSFET regions NR1 and NR2.

[0146] The isolation structure RIS may include a first isolation pattern RIS_P1 extending in the second direction D2, and second and third isolation patterns RIS_P2 and RIS_P3 extending in the first direction D1. In detail, when viewed in a plan view, the first isolation pattern RIS_P1 spaced apart from each other in the first direction D1, and the second and third isolation patterns RIS_P2 and RIS_P3 spaced apart from each other in the second direction D2 may be connected to each other to have a closed loop shape or a closed circular ring shape.

[0147] The isolation structure RIS may be arranged to penetrate the first gate electrode to the third gate electrode. Specifically, the first isolation pattern RIS_P1 may be arranged to penetrate the first gate electrode and divide each first gate electrode into a pair of gate electrodes spaced apart from each other in the first direction D1. The second isolation pattern RIS_P2 may be arranged to penetrate the second gate electrode, and the third isolation pattern RIS_P3 may be arranged to penetrate the third gate electrode. For example, the second isolation pattern RIS_P2 may be arranged to penetrate the entire second gate electrode, and the third isolation pattern RIS_P3 may be arranged to penetrate a portion of the third gate electrode.

[0148] Return to reference Fig. 7A , the isolation structure RIS may include a first region CR1 and a second region CR2, in which the first isolation pattern RIS_P1 and the second isolation pattern RIS_P2 intersect each other, and in which the first isolation pattern RIS_P1 and the third isolation pattern RIS_P3 intersect each other. The isolation structure RIS may further include a void portion VDE adjacent to a top surface thereof. The void portion VDE may include a first void VD1 on the first region CR1 and a second void VD2 on the second region CR2.

[0149] When viewed in a plan view, the first void VD1 may be a cross-shaped empty region including four curved surfaces CS1 to CS4. When viewed in a plan view, the second void VD2 may be a T-shaped empty region including two curved surfaces CS5 and CS6.

[0150] Fig. 8A and Figure 8B is along Fig. 7A The cross-sectional view taken along line II' and line II-II'. Fig. 7A As shown, line II' and line II-II' are selected to be parallel to the fourth direction D4 and the fifth direction D5, respectively. The fourth direction D4 may be defined to intersect both the first direction D1 and the second direction D2. The fifth direction D5 may be defined to be orthogonal to the fourth direction D4.

[0151] Reference Fig. 8A and Figure 8B , the isolation structure RIS may be a single layer deposited by a chemical vapor deposition (CVD) process. The single layer may include a first isolation layer RISL1 extending from the bottom surface of the isolation trench RIS_TR to the side surface thereof, a second isolation layer RISL2 on the first isolation layer RISL1, and a third isolation layer RISL3 on the second isolation layer RISL2. The single layer may be a layer formed by sequentially depositing the first isolation layer RISL1, the second isolation layer RISL2, and the third isolation layer RISL3.

[0152] In a single layer of a semiconductor device according to an embodiment of the present disclosure, there may be no observable interface between the first isolation layer RISL1 and the second isolation layer RISL2 and / or between the second isolation layer RISL2 and the third isolation layer RISL3. In other words, the isolation structure RIS may be a single layer in which the first to third isolation layers RISL1, RISL2, and RISL3 are connected to each other without any observable interface.

[0153] The first void VD1 may be adjacent to the top surface of the isolation structure RIS. The first void VD1 may be surrounded by the second curved surface CS2 and the third curved surface CS3 opposite to each other in the fourth direction D4, and the first curved surface CS1 and the fourth curved surface CS4 opposite to each other in the fifth direction D5. In an embodiment, the first void VD1 may have a hemispherical shape recessed in a downward direction.

[0154] Return to reference Figure 7B , the isolation structure RIS may be a double layer deposited by a chemical vapor deposition (CVD) process. In detail, Fig. 7AEach of the first to third isolation patterns RIS_P1, RIS_P2, and RIS_P3 may include a first sub-isolation pattern RIS_N and a second sub-isolation pattern RIS_O on the first sub-isolation pattern RIS_N. The first sub-isolation pattern RIS_N may be formed of or include silicon nitride or silicon oxynitride. The second sub-isolation pattern RIS_O may be formed of or include silicon oxide.

[0155] The isolation structure RIS may include a first region CR1 and a second region CR2. Fig. 7A The first isolation pattern RIS_P1 and the second isolation pattern RIS_P2 cross each other in the second region CR2. Fig. 7A The first isolation pattern RIS_P1 and the third isolation pattern RIS_P3 of the isolation structure RIS may cross each other. The isolation structure RIS may further include a void portion VDE adjacent to a top surface thereof. Specifically, the void portion VDE may be between the second sub-isolation patterns RIS_O. The void portion VDE may include a first void disposed on the first region CR1 and having a cross-shaped form and a second void VD2 disposed on the second region CR2 and having a T-shaped form.

[0156] FIG. 9A to FIG. 20G is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. In detail, Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A and Fig. 20A is corresponding to Figure 4 A cross-sectional view along line AA'. Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B and Fig. 20B is corresponding to Figure 4 Cross-sectional view along line BB'. Fig. 9B , Fig. 10B , Fig. 13C , Fig. 14C , Fig. 15C , Fig. 16C , Fig. 17C , Fig. 18C , Fig.19C and Fig. 20C is corresponding to Figure 4 Cross-sectional view along line CC'. Fig. 9C , Fig. 10C , Fig.14D , Fig.15D , Fig.16D , Fig.17D , Fig.18D , Fig.19D and Fig.20D is corresponding to Figure 4 Cross-sectional view along line D-D'. Fig. 11C , Fig. 12C , Fig.13D , Fig.16E , Fig.17E , Fig.18E , Fig.19E and Fig.20E is corresponding to Figure 4 Cross-sectional view along line EE'. Fig.16F , Fig.17F , Fig.18F , Fig.19F and Fig.20F is corresponding to Figure 4 Cross-sectional view along line F-F'. Figure 16G , Figure 17G , Figure 18G , Figure 19G and Figure 20G is corresponding to Figure 4 Cross-sectional view along line G-G'.

[0157] Reference 9A to 9C , a substrate 100 including first and second PMOSFET regions PR1 and PR2 and first and second NMOSFET regions NR1 and NR2 may be provided. First semiconductor layers ACL and second semiconductor layers SAL may be formed on the substrate 100 to be alternately stacked on top of each other. Each of the first semiconductor layers ACL and the second semiconductor layers SAL may be formed of or include at least one of silicon (Si), germanium (Ge), or silicon-germanium (SiGe), but the first semiconductor layers ACL and the second semiconductor layers SAL may be formed of materials different from each other.

[0158] The second semiconductor layer SAL may be formed of or include a material having an etching selectivity relative to the first semiconductor layer ACL. For example, the first semiconductor layer ACL may be formed of or include silicon (Si), and the second semiconductor layer SAL may be formed of or include silicon-germanium (SiGe). The germanium concentration of each second semiconductor layer SAL may be in the range of 10 at % to 30 at %.

[0159] Mask patterns may be formed on the first and second PMOSFET regions PR1 and PR2 and the first and second NMOSFET regions NR1 and NR2 of the substrate 100, respectively. The mask patterns may be line or stripe patterns extending in the second direction D2.

[0160] A patterning process using the mask pattern as an etching mask may be performed to form trenches TR defining first active patterns AP1 and second active patterns AP2. The first active pattern AP1 may be formed on each of the first PMOSFET region PR1 and the second PMOSFET region PR2. The second active pattern AP2 may be formed on each of the first NMOSFET region NR1 and the second NMOSFET region NR2. When viewed in a plan view, the first active pattern AP1 and the second active pattern AP2 may be linear patterns extending in the second direction D2 to be parallel to each other.

[0161] A stack pattern STP may be formed on each of the first active pattern AP1 and the second active pattern AP2. The stack pattern STP may include first semiconductor layers ACL and second semiconductor layers SAL that are alternately stacked. During the patterning process, the stack pattern STP may be formed together with the first active pattern AP1 and the second active pattern AP2. The stack pattern STP may not be formed on the substrate 100 between the first PMOSFET region PR1 and the second PMOSFET region PR2 and between the first NMOSFET region NR1 and the second NMOSFET region NR2.

[0162] The device isolation layer ST may be provided to fill the trench TR. Specifically, an insulating layer may be formed on the substrate 100 to cover the first and second active patterns AP1 and AP2 and the stack pattern STP. The device isolation layer ST may be formed by recessing the insulating layer until the stack pattern STP is exposed.

[0163] The device isolation layer ST may be formed of an insulating material (e.g., silicon oxide) or include an insulating material (e.g., silicon oxide). The stack pattern STP may be placed at a level higher than the device isolation layer ST and may be exposed to the outside of the device isolation layer ST. In other words, the stack pattern STP may protrude vertically above the device isolation layer ST.

[0164] Reference FIG. 10A to FIG. 10C , sacrificial patterns PP may be formed on the substrate 100 to cross the stacked patterns STP. Each of the sacrificial patterns PP may be a line or stripe pattern extending along the first direction D1. The sacrificial patterns PP may be arranged at a first pitch along the second direction D2.

[0165] Specifically, on each of the first PMOSFET region PR1 and the second PMOSFET region PR2 and the first NMOSFET region NR1 and the second NMOSFET region NR2, the sacrificial patterns PP on the stacked pattern STP may be formed to be spaced apart from each other in the second direction D2. The sacrificial patterns PP may be formed on portions of the device isolation layer ST disposed between the first PMOSFET region PR1 and the second PMOSFET region PR2 and between the first NMOSFET region NR1 and the second NMOSFET region NR2 to be spaced apart from each other in the second direction D2.

[0166] The formation of the sacrificial pattern PP may include forming a sacrificial layer on the substrate 100, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etch mask. The sacrificial layer may be formed of or include polysilicon.

[0167] A pair of gate spacers GS may be formed on opposite side surfaces of each sacrificial pattern PP. The formation of the gate spacer GS may include conformally forming a gate spacer layer on the substrate 100 and anisotropically etching the gate spacer layer. The gate spacer layer may be formed of or include at least one of SiCN, SiCON, or SiN. In an embodiment, the gate spacer layer may be a multilayer structure including at least two of SiCN, SiCON, or SiN.

[0168] Reference FIG. 11A to FIG. 11C , a first recess RS1 may be formed in the stack pattern STP on the first active pattern AP1. A second recess RS2 may be formed in the stack pattern STP on the second active pattern AP2. During the formation of the first recess RS1 and the second recess RS2, the device isolation layer ST may also be recessed at both sides of each of the first active pattern AP1 and the second active pattern AP2 (for example, see Fig. 9C ).

[0169] Specifically, the first recess RS1 may be formed by etching the stacked pattern STP on the first active pattern AP1 using the hard mask pattern MP and the gate spacer GS as an etching mask. The first recess RS1 may be formed between a pair of sacrificial patterns PP. The second recess RS2 in the stacked pattern STP on the second active pattern AP2 may be formed by the same method as that of the first recess RS1.

[0170] The first to third semiconductor patterns SP1, SP2, and SP3 sequentially stacked between adjacent first recesses in the first recess RS1 may be formed of the first semiconductor layer ACL, respectively. The first to third semiconductor patterns SP1, SP2, and SP3 sequentially stacked between adjacent second recesses in the second recess RS2 may be formed of the first semiconductor layer ACL, respectively. The first to third semiconductor patterns SP1, SP2, and SP3 between adjacent first recesses RS1 may constitute a first channel pattern CH1. The first to third semiconductor patterns SP1, SP2, and SP3 between adjacent second recesses RS2 may constitute a second channel pattern CH2.

[0171] Reference FIG. 12A to FIG. 12C , first source / drain patterns SD1 may be formed in the first recess RS1, respectively. Specifically, the buffer layer BFL may be formed by a first SEG process using an inner surface of the first recess RS1 as a seed layer. The buffer layer BFL may be grown using the first to third semiconductor patterns SP1, SP2, and SP3 and the substrate 100 exposed by the first recess RS1 as a seed layer. As an example, the first SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0172] The buffer layer BFL may include a semiconductor material (e.g., SiGe) whose lattice constant is greater than that of the semiconductor material of the substrate 100. The buffer layer BFL may include a relatively low concentration of germanium (Ge). In another embodiment, the buffer layer BFL may include only silicon (Si) without germanium (Ge). The germanium concentration of the buffer layer BFL may be in the range of 0 at % to 10 at %.

[0173] A second SEG process may be performed on the buffer layer BFL to form a main layer MAL. The main layer MAL may be formed to completely or almost completely fill the first recess RS1. The main layer MAL may contain a relatively high concentration of germanium. In an embodiment, the germanium concentration of the main layer MAL may be in a range of 30 at % to 70 at %.

[0174] In an embodiment, a third SEG process may be performed on the main layer MAL to form a capping layer. The capping layer may be formed of or include silicon (Si). The silicon concentration of the capping layer may be in the range of 98 at % to 100 at %.

[0175] The first source / drain pattern SD1 may be in-situ doped with p-type impurities (eg, boron, gallium, or indium) during the formation of the buffer layer BFL and the main layer MAL. Alternatively, impurities may be implanted into the first source / drain pattern SD1 after the first source / drain pattern SD1 is formed.

[0176] A second source / drain pattern SD2 may be formed in the second recess RS2, respectively. Specifically, the second source / drain pattern SD2 may be formed by a SEG process, wherein the inner surface of the second recess RS2 serves as a seed layer. In an embodiment, the second source / drain pattern SD2 may be formed of or include the same semiconductor material (e.g., Si) as the substrate 100.

[0177] During the formation of the second source / drain pattern SD2 , the second source / drain pattern SD2 may be in-situ doped with n-type impurities (eg, phosphorus, arsenic, or antimony) Alternatively, after the second source / drain pattern SD2 is formed, impurities may be implanted into the second source / drain pattern SD2 .

[0178] In an embodiment, before forming the second source / drain pattern SD2, inner spacers IP may be formed by replacing portions of the second semiconductor layer SAL exposed by the second recess RS2 with an insulating material. As a result, inner spacers IP may be formed between the second source / drain pattern SD2 and the second semiconductor layer SAL, respectively.

[0179] Reference FIG. 13A to FIG. 13D , a first interlayer insulating layer 110 may be formed to cover the first and second source / drain patterns SD1 and SD2 , the hard mask pattern MP, the gate spacer GS, and the device isolation layer ST. In an embodiment, the first interlayer insulating layer 110 may include a silicon oxide layer.

[0180] The first interlayer insulating layer 110 may be planarized to expose the top surface of the sacrificial pattern PP. The planarization of the first interlayer insulating layer 110 may be performed using an etch-back process or a chemical mechanical polishing (CMP) process. During the planarization process, all of the hard mask pattern MP may be removed. As a result, the top surface of the first interlayer insulating layer 110 may be coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0181] Reference FIG. 14A to FIG. 14D , a photolithography process may be performed to selectively open a region of the sacrificial pattern PP. For example, a region of the sacrificial pattern PP on a boundary of the edge cell SHC_P may be selectively opened. The opened region of the sacrificial pattern PP may be selectively etched and removed.

[0182] The exposed sacrificial pattern PP may be selectively removed. As a result of the removal of the sacrificial pattern PP, an outer region ORG may be formed to expose the first channel pattern CH1 and the second channel pattern CH2 (eg, see Fig.14D ). The removal of the sacrificial pattern PP may include a wet etching process performed using an etching solution capable of selectively etching polysilicon.

[0183] Reference Fig. 14C , a wet etching process may be performed to selectively remove the sacrificial pattern PP through the opening region. In the wet etching process, the gate spacer GS and the device isolation layer ST may have a lower etching rate than the sacrificial pattern PP, and in this case, the wet etching process may not etch the gate spacer GS and the device isolation layer ST. As a result, the sacrificial pattern PP may be selectively removed to expose the top surface of the device isolation layer ST.

[0184] The second semiconductor layer SAL exposed through the outer region ORG may be selectively removed to form an inner region IRG (eg, see Fig.14D ). Specifically, an etching process for selectively etching the second semiconductor layer SAL may be performed to leave the first to third semiconductor patterns SP1, SP2, and SP3 and remove only the second semiconductor layer SAL. An etching recipe for the etching process may be selected so as to etch a layer formed to have a relatively high germanium concentration (e.g., a silicon germanium layer) at a high etching rate. For example, the etching process may be selected to have a high etching rate for a silicon germanium layer having a germanium concentration higher than 10 at%.

[0185] During the etching process, the second semiconductor layer SAL may be completely removed from the first PMOSFET region PR1 and the second PMOSFET region PR2 and the first NMOSFET region NR1 and the second NMOSFET region NR2. The etching process may be a wet etching process. The etchant material used in the etching process may be selected to quickly remove the second semiconductor layer SAL having a relatively high germanium concentration. At the same time, the first source / drain pattern SD1 on the first PMOSFET region PR1 and the second PMOSFET region PR2 may be protected from the etching process by the buffer layer BFL having a relatively low germanium concentration.

[0186] Return to reference Fig.14D As a result of the selective removal of the second semiconductor layer SAL, the stacked first to third semiconductor patterns SP1, SP2, and SP3 may remain on each of the first active pattern AP1 and the second active pattern AP2. Empty regions formed by removing the second semiconductor layer SAL may be used as first to third inner regions IRG1, IRG2, and IRG3, respectively.

[0187] In detail, the first inner region IRG1 may be formed between the active pattern AP1 or AP2 and the first semiconductor pattern SP1 , the second inner region IRG2 may be formed between the first and second semiconductor patterns SP1 and SP2 , and the third inner region IRG3 may be formed between the second and third semiconductor patterns SP2 and SP3 .

[0188] Reference FIG. 15A to FIG. 15D , a gate insulating layer GI may be conformally formed on the exposed first to third semiconductor patterns SP1, SP2, and SP3. A gate electrode GE may be formed on the gate insulating layer GI. The gate electrode GE may include first to third internal electrodes PO1, PO2, and PO3 formed in the first to third internal regions IRG1, IRG2, and IRG3, respectively, and an external electrode PO4 formed in the external region ORG. Although not shown, a gate capping pattern may be formed on the gate electrode GE.

[0189] Reference Fig. 15C , the gate insulating layer GI may be formed on the exposed top surface of the device isolation layer ST and the exposed side surface of the gate spacer GS. A gate electrode GE may be formed on the gate insulating layer GI. The gate electrode GE formed on the device isolation layer ST may be used as a dummy gate electrode. The top surface of the gate electrode GE may be coplanar with the top surface of the gate spacer GS, the top surface of the gate insulating layer GI, and the top surface of the first interlayer insulating layer 110.

[0190] Reference Fig.15D , the gate insulating layer GI may be conformally formed on the exposed first to third semiconductor patterns SP1, SP2, and SP3. Specifically, the gate insulating layer GI may surround the top surface TS, the bottom surface BS, and the opposite side surface SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. The first internal electrode PO1 may be between the first active pattern AP1 and the first semiconductor pattern SP1. The second internal electrode PO2 may be between the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The third internal electrode PO3 may be between the second semiconductor pattern SP2 and the third semiconductor pattern SP3. The external electrode PO4 may be disposed on the third semiconductor pattern SP3.

[0191] Reference FIG. 16A to FIG. 16G , a first mask layer HMO1 may be formed on the gate electrode GE and the first interlayer insulating layer 110. A second mask layer HMN1 may be formed on the first mask layer HMO1. A first mask structure MST1 may be formed on the second mask layer HMN1.

[0192] The first mask structure MST1 may include a third mask layer SOHP on the second mask layer HMN1 and a fourth mask layer HMNP on the third mask layer SOHP.

[0193] The first mask layer HMO1 may be formed of or include silicon oxide. The first mask layer HMO1 may be a silicon oxide layer deposited by an atomic layer deposition (ALD) process. For example, the thickness of the first mask layer HMO1 may be 1000 Å. to within the range.

[0194] The second mask layer HMN1 may be formed of or include a material having an etching selectivity with respect to the first mask layer HMO1. The second mask layer HMN1 may be formed of or include silicon nitride. The second mask layer HMN1 may be a silicon nitride layer deposited by a chemical vapor deposition (CVD) process. For example, the second mask layer HMN1 may be formed of or include plasma enhanced silicon nitride (PE-SiN). The thickness of the second mask layer HMN1 may be 1000 Å. to within the range.

[0195] The third mask layer SOHP may be formed of or include a material having an etch selectivity with respect to the second mask layer HMN1. The third mask layer SOHP may be formed of or include at least one of a spin-on hard mask (SOH) material. Fig. 16C , Fig.16D , Fig.16F and Figure 16G , the third mask layer SOHP may include a recessed region formed between the first PMOSFET region PR1 and the second PMOSFET region PR2 and between the first PMOSFET region PR1 and the NMOSFET region NR1 by a first photolithography process. Fig.16E , the third mask layer SOHP may include a recessed region formed between the first PMOSFET region PR1 and the second PMOSFET region PR2 by the first photolithography process. In other words, the third mask layer SOHP may be a pattern including recessed regions extending along the second direction D2 and spaced apart from each other in the first direction D1.

[0196] The fourth mask layer HMNP may be formed of or include a material having an etching selectivity relative to the third mask layer SOHP. The fourth mask layer HMNP may be formed of or include silicon oxynitride. For example, the fourth mask layer HMNP may be formed of or include silicon (Si) or silicon oxynitride (SiON). The thickness of the fourth mask layer HMNP may be 200 Å / s. to within the range.

[0197] The fourth mask layer HMNP may be a pattern formed based on a layout design rule. Fig. 16C, Fig.16D , Fig.16F and Figure 16G , the fourth mask layer HMNP may be a pattern formed to have an opening region between the first PMOSFET region PR1 and the second PMOSFET region PR2 and an opening region between the first PMOSFET region PR1 and the NMOSFET region NR1. Fig.16E , the fourth mask layer HMNP may be a pattern including an opening region between the first PMOSFET region PR1 and the second PMOSFET region PR2 .

[0198] Specifically, forming the first mask structure MST1 may include: forming a first preliminary mask layer on the second mask layer HMN1; forming a fourth mask layer HMNP on the first preliminary mask layer; and performing a first photolithography process on the first preliminary mask layer through an opening region of the fourth mask layer HMNP.

[0199] The first photolithography process may include performing a pre-cleaning process on the first preliminary mask layer and the fourth mask layer HMNP and performing an exposure and development process on the first preliminary mask layer. For example, the exposure process may be an extreme ultraviolet (EUV) exposure process. As a result of the development process, the first preliminary mask layer may be formed into a third mask layer SOHP.

[0200] Reference FIG. 17A to FIG. 17G , the first mask layer HMO1 and the second mask layer HMN1 may be subjected to Fig.16D The first etching process may be an anisotropic dry etching process. An etching gas or an etchant material may be selected for the first etching process to etch the first mask layer HMO1 and the second mask layer HMN1. For example, an etching gas or an etchant material may be selected to etch silicon oxide and silicon nitride.

[0201] As a result of the first etching process, the first mask layer HMO1 and the second mask layer HMN1 may be formed to include a first etch recess region HM_RS1. The first etch recess region HM_RS1 may correspond to the reference Fig.16D The opening area of ​​the first mask structure MST1 is described. Fig. 17C , Fig.17D , Fig.17F and Figure 17G , the first etch recessed region HM_RS1 may be located between the first PMOSFET region PR1 and the second PMOSFET region PR2 and between the first PMOSFET region PR1 and the first NMOSFET region NR1. Fig.17E , the first etch recess region HM_RS1 may be disposed between the first PMOSFET region PR1 and the second PMOSFET region PR2 .

[0202] Reference FIG. 18A to FIG. 18G , a second mask structure MST2 may be formed on the substrate 100. The second mask structure MST2 may include a fifth mask layer SOHP2 on the second mask layer HMN1 and a sixth mask layer HMNP2 on the fifth mask layer SOHP2.

[0203] The fifth mask layer SOHP2 may be formed of or include a material having an etch selectivity with respect to the second mask layer HMN1. The fifth mask layer SOHP2 may be formed of or include at least one of a spin-on hard mask (SOH) material. Fig.18A , Fig.18B , Fig. 18C , Fig.18F and Figure 18G , the fifth mask layer SOHP2 may include a recessed region formed on the gate electrode GE of the first PMOSFET region PR1 by the second photolithography process. In addition, the fifth mask layer SOHP2 may include a recessed region formed on the gate electrode GE of the first NMOSFET region NR1 by the second photolithography process. In other words, the fifth mask layer SOHP2 may be a pattern including recessed regions extending along the first direction D1 and spaced apart from each other in the second direction D2.

[0204] The sixth mask layer HMNP2 may be formed of or include a material having an etching selectivity relative to the fifth mask layer SOHP2. The sixth mask layer HMNP2 may be formed of or include silicon oxynitride. For example, the sixth mask layer HMNP2 may be formed of or include silicon (Si) or silicon oxynitride (SiON).

[0205] The sixth mask layer HMNP2 may be a pattern formed based on a layout design rule. Fig.18A , Fig.18B , Fig. 18C , Fig.18F and Figure 18G , the sixth mask layer HMNP2 may be a pattern formed to have an opening region on the gate electrode GE of the first PMOSFET region PR1 and an opening region on the gate electrode GE of the first NMOSFET region NR1 .

[0206] Specifically, forming the second mask structure MST2 may include: forming a second preliminary mask layer on the second mask layer HMN1; forming a sixth mask layer HMNP2 on the second preliminary mask layer; and performing a second photolithography process on the second preliminary mask layer through the opening region of the sixth mask layer HMNP2.

[0207] The second photolithography process may include: performing a pre-cleaning process on the second preliminary mask layer and the sixth mask layer HMNP2; and performing an exposure and development process on the second preliminary mask layer. For example, the exposure process may be an ArF exposure process. As a result of the development process, the second preliminary mask layer may be formed into the fifth mask layer SOHP2.

[0208] Reference FIG. 19A to FIG. 19G , the first mask layer HMO1 and the second mask layer HMN1 may be subjected to Fig.18A The second etching process using the second mask structure MST2 as an etching mask. The second etching process may be an anisotropic dry etching process. An etching gas or an etchant material for the second etching process may be selected to etch both the first mask layer HMO1 and the second mask layer HMN1. For example, an etching gas or an etchant material may be selected to etch silicon oxide and silicon nitride.

[0209] As a result of the second etching process, the first mask layer HMO1 and the second mask layer HMN1 may be formed to include a second etch recessed region HM_RS2. The second etch recessed region HM_RS2 may correspond to the reference Fig.18A The opening area of ​​the second mask structure MST2 is described. Fig.19A , Fig.19B , Fig.19C , Fig.19E , Fig.19F and Figure 19G , the second etch recess region HM_RS2 may be disposed on the gate electrode GE of the first PMOSFET region PR1 and on the gate electrode GE of the first NMOSFET region NR1 .

[0210] A first photolithography process, a first etching process, a second photolithography process, and a second etching process may be performed to form a third mask structure MST3. The third mask structure MST3 may include a first hard mask pattern HP1 and a second hard mask pattern HP2 on the first hard mask pattern HP1. Each of the first hard mask pattern HP1 and the second hard mask pattern HP2 may include Fig.17D The first etched recessed region HM_RS1 and the second etched recessed region HM_RS2 are formed.

[0211] Return to reference FIG. 5A to FIG. 5G , an isolation structure RIS can be formed. Forming the isolation structure RIS may include: using Fig.19AThe third mask structure MST3 is used as an etching mask to perform a third etching process; and an isolation structure RIS is deposited on the area recessed by the third etching process. In an embodiment, the isolation structure RIS can be deposited by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process.

[0212] Specifically, the gate electrode GE may be subjected to Fig.19A The third etching process of the gate electrode GE, the gate insulating layer GI and the device isolation layer ST may be selected. For example, the etchant material may be selected to etch the metal material (e.g., tungsten (W)) and silicon oxide included in the gate electrode GE.

[0213] In the manufacturing method according to the embodiment of the present disclosure, an etchant material may be selected to etch metal materials, silicon and silicon oxide. In the embodiment, the etchant material may exhibit an etching rate different from that of the metal material, silicon and silicon oxide. For example, under the etchant material, the etching rate of the metal material may be higher than the etching rate of silicon. Under the etchant material, the etching rate of silicon may be higher than the etching rate of silicon oxide. Return to reference Fig. 5F and Figure 5G Due to a difference in etching selectivity under an etchant material, each of the second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may include a first portion and a second portion formed to have vertical lengths different from each other.

[0214] The third etching process may be optimized to form a region on the substrate 100 in which the isolation structure RIS will be formed simultaneously or as a single region. For example, an etchant material for the third etching process may be selected to selectively etch the gate electrode GE and the semiconductor patterns SP1, SP2, and SP3, but not to etch the first source / drain pattern SD1. This may be because the etchant material is selected to etch metal materials at a high etching rate compared to silicon germanium (SiGe). Therefore, the loss of the first source / drain pattern SD1 adjacent to the second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may be reduced, thereby minimizing pattern defects. As a result, the semiconductor device manufactured by the manufacturing method may have improved electrical characteristics and reliability characteristics.

[0215] The deposited isolation structure RIS may include a first isolation pattern RIS_P1, a second isolation pattern RIS_P2, and a third isolation pattern RIS_P3. A top surface of the first isolation pattern RIS_P1 may be substantially coplanar with a top surface of the gate electrode GE. A top surface of each of the second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may be substantially coplanar with a top surface of the first interlayer insulating layer 110 and a top surface of the gate spacer GS.

[0216] A second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may include a silicon oxide layer. An active contact AC may be formed to penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110 and may be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. A gate contact GC may be formed to penetrate the second interlayer insulating layer 120 and may be electrically connected to the gate electrode GE.

[0217] Although not shown, in the case where the gate capping pattern is disposed on the gate electrode GE, a gate contact may be formed to penetrate the second interlayer insulating layer 120 and the gate capping pattern and may be electrically connected to the gate electrode GE.

[0218] Forming each of the active contact AC and the gate contact GC may include: forming a barrier pattern BM; and forming a conductive pattern FM on the barrier pattern BM. The barrier pattern BM may be conformally formed and may include a metal layer and / or a metal nitride layer. The conductive pattern FM may be formed of or include a low resistance metal.

[0219] Return to reference Figure 4 and FIG. 5A to FIG. 5G , a third interlayer insulating layer 130 may be formed on the active contact AC and the gate contact GC. A first metal layer M1 may be formed in the third interlayer insulating layer 130. A fourth interlayer insulating layer 140 may be formed on the third interlayer insulating layer 130. A second metal layer M2 may be formed in the fourth interlayer insulating layer 140.

[0220] Lower power lines VPR1 and VPR2 may be formed under the substrate 100. Each of the lower power lines VPR1 to VPR3 may be electrically connected to the active contact AC through the upper contact UCT. A power delivery network layer PDN may be formed on the bottom surface 100b of the substrate 100. The power delivery network layer PDN may be formed to apply a source voltage or a drain voltage to the lower power lines VPR1 and VPR2.

[0221] Forming the lower power lines VPR1 and VPR2 may include: performing a BEOL process on the substrate 100; inverting the substrate 100; performing a planarization process on the bottom surface 100b of the inverted substrate 100; forming an insulating layer 105 on the bottom surface 100b of the substrate 100; and performing a patterning process on the insulating layer 105. The patterning process may be, for example, a single damascene process or a dual damascene process.

[0222] Specifically, the patterning process may include forming a barrier pattern BM and forming a conductive pattern FM on the barrier pattern BM. The barrier pattern BM may be conformally formed and may include a metal layer and / or a metal nitride layer. The conductive pattern FM may be formed of or include a low resistance metal.

[0223] Next, a manufacturing method according to another embodiment of the present disclosure will be described. In the following description, for the sake of simplicity, the previous reference Figure 4 to Figure 5G as well as FIG. 9A to FIG. 19G Described elements may be identified by the same reference numerals without repeating their overlapping descriptions. FIG. 20A to FIG. 20G is a cross-sectional view showing a semiconductor device manufactured using another etchant material in a fourth etching process.

[0224] Reference FIG. 6A to FIG. 6C and FIG. 20A to FIG. 20G , the isolation structure RIS may be formed such that the fourth height P1H', the fifth height P2H', and the sixth height P3H' have the same value. Forming the isolation structure RIS may include: using Fig.19A A fourth etching process is performed using the third mask structure MST3 as an etching mask; and an isolation structure RIS is deposited on a region recessed by the fourth etching process.

[0225] Specifically, the gate electrode GE may be subjected to Fig.19A The fourth etching process may be an anisotropic dry etching process.

[0226] The etchant material used for the fourth etching process can be selected to etch the metal material, silicon and silicon oxide. The etching rates of the metal material, silicon and silicon oxide under the etchant material can be similar or equal to each other. Therefore, the depth of the recessed area where the isolation structure RIS will be formed can be controlled to a target depth. The target depth can be the fourth height P1H', the fifth height P2H' and the sixth height P3H' mentioned above. For example, the target depth can be in the range of 140nm to 180nm. Return to reference FIG. 6A to FIG. 6C , by adjusting the process time of the fourth etching process, the isolation structures RIS can be formed to have the same vertical distance.

[0227] The fourth etching process may be optimized to form a region on the substrate 100 in which the isolation structure RIS is to be formed simultaneously or as a single region. For example, an etchant material for the fourth etching process may be selected to etch the gate electrode GE and the semiconductor patterns SP1, SP2, and SP3, but not to etch the first source / drain pattern SD1. Therefore, the loss of the first source / drain pattern SD1 adjacent to the second isolation pattern RIS_P2 and the third isolation pattern RIS_P3 may be reduced, thereby minimizing pattern defects. As a result, the semiconductor device manufactured by the manufacturing method may have improved electrical characteristics and reliability characteristics.

[0228] According to an embodiment of the present disclosure, a three-dimensional field effect transistor may include a first isolation pattern, a second isolation pattern, and a third isolation pattern formed simultaneously or as a single object. Therefore, the first isolation pattern, the second isolation pattern, and the third isolation pattern may be formed to have a top surface located at the same level or having the same height, and in this case, the cost of manufacturing a photomask may be reduced. In addition, the first isolation pattern to the third isolation pattern may be formed by an optimized etching process that can prevent the loss of the source / drain pattern adjacent thereto. Therefore, semiconductor devices may be efficiently manufactured and defects may be prevented from occurring in the source / drain pattern adjacent to the first isolation pattern to the third isolation pattern. As a result, the electrical characteristics and reliability characteristics of the semiconductor device may be improved.

[0229] While example embodiments of the present disclosure have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made without departing from the spirit and scope of the following claims.

Claims

1. A semiconductor device, include: a substrate including an active pattern; A device isolation layer, defining the active pattern; a channel pattern on the active pattern; a gate electrode on the channel pattern; as well as a first isolation pattern and a second isolation pattern penetrating the gate electrode, wherein the first isolation pattern extends into the device isolation layer, wherein the second isolation pattern penetrates the gate electrode and the device isolation layer and extends into the upper portion of the substrate, and The level of the bottom surface of the second isolation pattern is lower than or equal to the level of the bottom surface of the device isolation layer.

2. The semiconductor device according to claim 1, in, A level of a bottom surface of the second isolation pattern is equal to a level of a bottom surface of the device isolation layer.

3. The semiconductor device according to claim 1, in, A bottom surface of the first isolation pattern is at a level higher than a bottom surface of the device isolation layer.

4. The semiconductor device according to claim 1, in, The first isolation pattern and the second isolation pattern define a single object.

5. The semiconductor device according to claim 1, in, The first isolation pattern penetrates the device isolation layer and extends into an upper portion of the substrate, and The level of the bottom surface of the first isolation pattern is equal to the level of the bottom surface of the second isolation pattern.

6. The semiconductor device according to claim 5, in, A top surface of the first isolation pattern and a top surface of the second isolation pattern are located at a level equal to or higher than a top surface of the gate electrode, and A bottom surface of the first isolation pattern and a bottom surface of the second isolation pattern are located at a level lower than a bottom surface of the device isolation layer.

7. The semiconductor device according to claim 1, in, The second isolation pattern comprises: A first portion extending into the device isolation layer; and a second portion extending into an upper portion of the substrate, and Wherein, a first depth of the first portion is smaller than a second depth of the second portion.

8. The semiconductor device according to claim 7, in, The second depth is in the range of 140 nm to 180 nm.

9. The semiconductor device according to claim 7, in, The first depth of the first portion is equal to a first height of the first isolation pattern.

10. The semiconductor device according to claim 1, in, Each of the first isolation pattern and the second isolation pattern is a single layer including at least one of silicon oxide, silicon nitride, or silicon oxynitride.

11. The semiconductor device according to claim 1, in, Each of the first isolation pattern and the second isolation pattern defines a void adjacent to a top surface of each of the first isolation pattern and the second isolation pattern.

12. The semiconductor device according to claim 1, further comprising a gate capping pattern on the gate electrode, in, Top surfaces of the first isolation pattern and the second isolation pattern are located at a level equal to or higher than a top surface of the gate capping pattern.

13. The semiconductor device according to claim 1, in, Each of the first isolation pattern and the second isolation pattern includes a first sub-isolation pattern and a second sub-isolation pattern on the first sub-isolation pattern.

14. The semiconductor device according to claim 13, in, The first sub-isolation pattern includes silicon nitride or silicon oxynitride, and Wherein, the second sub-isolation pattern comprises silicon oxide.

15. The semiconductor device according to claim 13, in, The first isolation pattern and the second isolation pattern define a gap between the second sub-isolation pattern of the first isolation pattern and the second sub-isolation pattern of the second isolation pattern.

16. A semiconductor device, include: substrate; A device isolation layer filling the trench on the substrate; a first isolation pattern, on the device isolation layer; an active contact portion on the first isolation pattern; as well as a lower power line disposed below the substrate, wherein the lower power line comprises an interconnection portion and a contact portion protruding from the interconnection portion toward the substrate, and The contact portion penetrates the substrate, the device isolation layer, and the first isolation pattern, and is electrically connected to the active contact portion.

17. The semiconductor device according to claim 16, in, The width of the contact portion decreases as the distance from the interconnect portion increases in a direction toward the active contact portion.

18. A semiconductor device, include: A first gate electrode, a second gate electrode and a third gate electrode are disposed on the substrate, extend along a first direction, and are sequentially arranged along a second direction intersecting the first direction; source / drain patterns, respectively disposed between the first gate electrode, the second gate electrode and the third gate electrode; as well as an isolation structure penetrating the first gate electrode, the second gate electrode and the third gate electrode, Wherein, the isolation structure comprises: a first isolation pattern extending along the second direction and dividing the first gate electrode into a pair of gate electrodes, the pair of gate electrodes being spaced apart from each other in the first direction; a second isolation pattern extending along the first direction and penetrating the second gate electrode; a third isolation pattern extending along the first direction and penetrating the third gate electrode; a first gap at a first region where the first isolation pattern and the second isolation pattern cross each other; and a second gap, at a second region where the first isolation pattern and the third isolation pattern intersect each other, wherein the first gap comprises a cross-shaped region having four curved surfaces when viewed in a plan view of the semiconductor device, wherein the plan view faces a vertical direction orthogonal to the first direction and the second direction, and Wherein, when viewed in the plan view of the semiconductor device, the second gap is a T-shaped region having two curved surfaces.

19. The semiconductor device according to claim 18, in, The first isolation pattern, the second isolation pattern and the third isolation pattern are formed simultaneously, and Each of the first isolation pattern, the second isolation pattern and the third isolation pattern includes at least one of silicon oxide, silicon nitride or silicon oxynitride.

20. The semiconductor device according to claim 19, in, Each of the first isolation pattern, the second isolation pattern, and the third isolation pattern includes a first sub-isolation pattern and a second sub-isolation pattern on the first sub-isolation pattern, Wherein, the first sub-isolation pattern comprises silicon nitride or silicon oxynitride, and Wherein, the second sub-isolation pattern comprises silicon oxide.

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