Semiconductor device

Abstract

A semiconductor device includes: a first lower active pattern and a second lower active pattern; a first upper active pattern and a second upper active pattern; a first gate electrode overlapping the first lower active pattern and the first upper active pattern; a second gate electrode spaced apart from the first gate electrode; a third gate electrode spaced apart from the first gate electrode; a fourth gate electrode spaced apart from the third gate electrode; a first lower source / drain contact electrically connected to the first lower active pattern; a first upper source / drain contact electrically connected to the second upper active pattern; a lower shared contact in the lower region; and an upper shared contact in the upper region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0072747 filed in the Korean Intellectual Property Office on June 7, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including stacked multi-gate transistors. Background Art

[0004] As one of scaling technologies for increasing the density of integrated circuit devices, a multi-gate transistor for forming a fin-shaped or nanowire-shaped silicon body on a substrate and forming a gate on a surface of the silicon body has been proposed.

[0005] Since the multi-gate transistor uses a three-dimensional channel, it is easy to scale the multi-gate transistor. In addition, even if the gate length of the multi-gate transistor is not increased, the current control capability can be improved. In addition, the short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed. Summary of the invention

[0006] An object of the present disclosure is to provide a semiconductor device having improved design freedom and integration.

[0007] The objects of the present disclosure are not limited to those described above, and additional objects of the present disclosure not mentioned herein will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0008] According to aspects of the present disclosure, a semiconductor device includes a lower region and an upper region on a substrate, and the semiconductor device may further include: a first lower active pattern and a second lower active pattern, extending in a first direction, extending in the lower region, and spaced apart from each other in a second direction intersecting the first direction; a first upper active pattern and a second upper active pattern, extending in the first direction, extending in the upper region, and spaced apart from each other in the second direction; a first gate electrode, overlapping the first lower active pattern and the first upper active pattern; a second gate electrode, spaced apart from the first gate electrode in the second direction, wherein the second gate electrode overlaps at least one of the second lower active pattern and the second upper active pattern; and a third gate electrode, spaced apart from the first gate electrode in the first direction. The first gate electrode and the second gate electrode are separated in the second direction, wherein the third gate electrode overlaps with at least one of the first lower active pattern and the first upper active pattern; the fourth gate electrode is spaced apart from the third gate electrode in the second direction, wherein the fourth gate electrode overlaps with the second lower active pattern and the second upper active pattern; the first lower source / drain contact is electrically connected to the first lower active pattern and is between the first gate electrode and the third gate electrode; the first upper source / drain contact is electrically connected to the second upper active pattern and is between the second gate electrode and the fourth gate electrode; the lower shared contact is in the lower region, wherein the lower shared contact is electrically connected to the first lower source / drain contact and the fourth gate electrode; and the upper shared contact is in the upper region, wherein the upper shared contact is electrically connected to the first upper source / drain contact and the first gate electrode.

[0009] According to aspects of the present disclosure, a semiconductor device may include a lower region and an upper region on a substrate, and the semiconductor device may also include: a first lower active pattern and a second lower active pattern, extending in a first direction, extending in the lower region, and spaced apart from each other in a second direction intersecting the first direction; a first upper active pattern and a second upper active pattern, extending in the first direction, extending in the upper region, and spaced apart from each other in the second direction; a first gate electrode, overlapping the first lower active pattern and the first upper active pattern; a second gate electrode, overlapping the second lower active pattern and the second upper active pattern, wherein the second gate electrode does not overlap with the first gate electrode in the second direction; a first lower source / drain contact, electrically connected to the first source / drain contact; connected to the first lower active pattern and between the first gate electrode and the second gate electrode; a first upper source / drain contact, electrically connected to the first upper active pattern and on the first lower source / drain contact; a second lower source / drain contact, spaced apart from the first lower source / drain contact in the second direction and electrically connected to the second lower active pattern; a second upper source / drain contact, spaced apart from the first upper source / drain contact in the second direction and electrically connected to the second upper active pattern; a lower shared contact, in the lower region, wherein the lower shared contact is electrically connected to the first lower source / drain contact and the second gate electrode; and an upper shared contact, in the upper region, wherein the upper shared contact is electrically connected to the second upper source / drain contact and the first gate electrode.

[0010] According to aspects of the present disclosure, a semiconductor device may include: a substrate; a first active pattern, the first active pattern may include a first lower active pattern and a first upper active pattern, the first lower active pattern and the first upper active pattern are on the substrate, spaced apart from each other, and extend in a first direction; a second active pattern, the second active pattern may include a second lower active pattern and a second upper active pattern, the second lower active pattern and the second upper active pattern are on the substrate, spaced apart from each other, and extend in the first direction, wherein the second active pattern is spaced apart from the first active pattern in a second direction intersecting the first direction; a cutting pattern extending in the first direction and between the first active pattern and the second active pattern; a first gate structure extending in the second direction, the first gate structure may include a first gate electrode overlapping the first active pattern and a second gate electrode overlapping the second active pattern, wherein the first gate electrode and the second gate electrode are separated by the cutting pattern; and a second gate structure Spaced apart and extending in the second direction, the second gate structure may include a third gate electrode overlapping the first active pattern and a fourth gate electrode overlapping the second active pattern, wherein the third gate electrode and the fourth gate electrode are separated by a cutting pattern; a first lower source / drain contact electrically connected to the first lower active pattern and between the first gate electrode and the third gate electrode; a first upper source / drain contact electrically connected to the first lower source / drain contact and the first upper active pattern and on the first lower source / drain contact; a second lower source / drain contact electrically connected to the second lower active pattern and between the second gate electrode and the fourth gate electrode; a second upper source / drain contact electrically connected to the second lower source / drain contact and the second upper active pattern and on the second lower source / drain contact; a lower shared contact extending in the first direction and electrically connected to the first lower source / drain contact and the fourth gate electrode; and an upper shared contact extending in the first direction and electrically connected to the second upper source / drain contact and the first gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0012] Figure 1 is an example circuit diagram illustrating a semiconductor device according to some embodiments of the present disclosure.

[0013] Figure 2 is a diagram showing an example layout of a semiconductor device according to some embodiments of the present disclosure.

[0014] Figure 3 is along Figure 2 A schematic cross-sectional view taken along line AA.

[0015] Figure 4 is along Figure 2A schematic cross-sectional view taken along line BB of FIG.

[0016] Figure 5 is along Figure 2 Schematic cross-sectional view taken along line CC.

[0017] Figure 6 It shows Figure 2 A schematic perspective view of a semiconductor device.

[0018] Figure 7 is a diagram showing an example layout of a semiconductor device according to some embodiments of the present disclosure.

[0019] Figure 8 It shows Figure 7 A schematic perspective view of a semiconductor device.

[0020] Fig. 9 is a diagram showing an example layout of a semiconductor device according to some embodiments of the present disclosure.

[0021] Fig.10 It shows Fig. 9 A schematic perspective view of a semiconductor device.

[0022] Fig.11 is a diagram showing an example layout of a semiconductor device according to some embodiments of the present disclosure.

[0023] Fig.12 It shows Fig.11 A schematic perspective view of a semiconductor device.

[0024] Fig.13 is a diagram showing an example layout of a semiconductor device according to some embodiments of the present disclosure.

[0025] Fig.14 It shows Fig.13 A schematic perspective view of a semiconductor device.

[0026] Fig.15 is an example circuit diagram illustrating a semiconductor device according to some embodiments of the present disclosure.

[0027] Fig.16 and Fig.17 are various example layout diagrams illustrating semiconductor devices according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0028] In order to clarify the present disclosure, parts not related to the description will be omitted, and the same elements or equivalents are referred to by the same reference numerals throughout the specification. In addition, since the sizes and thicknesses of the constituent members shown in the drawings are arbitrarily given for better understanding and ease of description, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are excessively shown for better understanding and ease of description.

[0029] It will be understood that when an element (e.g., layer, film, region, or substrate) is mentioned as being "on" another element, the element may be directly on the other element, or there may be an intermediate element. On the contrary, when an element is mentioned as being "directly above" another element, there is no intermediate element. In addition, for ease of description, spatial relative terms (e.g., "below," "under," "below," "above," "on," etc.) may be used herein to describe the relationship of an element or feature relative to another element or feature as shown in the accompanying drawings. It will be understood that spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientations shown in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, the element described as being "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, the term "below" may include both the orientations above and below. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0030] In addition, unless explicitly described to the contrary, the word "include" and variants such as "contain" or "comprise" will be understood to mean including the elements described, but not excluding any other elements. As used herein, the phrase "at least one of A, B and C" refers to the logic (A or B or C) using the non-exclusive logic "or", and should not be interpreted as representing "at least one of A, at least one of B and at least one of C". As used herein, the singular forms "one", "one" and "the" are also intended to include plural forms, unless the context clearly states otherwise. It will also be understood that the terms "include", "contain", "include" and / or "have" when used herein represent the presence of the features, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or combinations thereof. The term "and / or" includes any and all combinations of one or more items listed in association. The term "connection" can be used herein to refer to physical and / or electrical connections, and can refer to direct or indirect physical and / or electrical connections.

[0031] As used herein, "element A is at a higher height than element B" or "element A is at a lower height than element B" means that at least one surface of element A is not coplanar with at least one surface of element B and / or at least one surface of element A is spaced apart from a reference element at a different distance than element B is from the reference element. As an example, "element A is at a higher height than element B" means that element A is spaced apart from the reference element at a greater distance than element B is from the reference element. Components or layers described with reference to "overlapping" in a particular direction may at least partially obscure each other when viewed along a line extending in the particular direction or in a plane perpendicular to the particular direction.

[0032] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements or components, these elements or components should not be limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, without departing from the technical spirit of the present disclosure, the first element or component discussed below may be referred to as the second element or component.

[0033] In the following, reference will be made to Figures 1 to 17 A semiconductor device according to an example embodiment is described. The embodiments disclosed below will be described based on a static random access memory (SRAM) device as a semiconductor device, but the present disclosure is not limited thereto. A person skilled in the art will understand that the technical spirit of the present disclosure can be applied to various semiconductor devices such as logic devices and SRAM devices.

[0034] Figure 1 is an example circuit diagram illustrating a semiconductor device according to some embodiments of the present disclosure. Figure 2 is a diagram showing an example layout of a semiconductor device according to some embodiments of the present disclosure. Figure 3 is along Figure 2 A schematic cross-sectional view taken along line AA. Figure 4 is along Figure 2 A schematic cross-sectional view taken along line BB of FIG. Figure 5 is along Figure 2 Schematic cross-sectional view taken along line CC. Figure 6 It shows Figure 2 A schematic perspective view of a semiconductor device.

[0035] Reference Figure 1 , according to some embodiments, the semiconductor device includes a DD and ground node V SS A pair of inverters INV1 and INV2 therebetween, and a first pass transistor PS1 and a second pass transistor PS2 connected to output nodes of the inverters INV1 and INV2, respectively.

[0036] The first pass transistor PS1 may be connected to a bit line BL, and the second pass transistor PS2 may be connected to a complementary bit line / BL. A gate of the first pass transistor PS1 and a gate of the second pass transistor PS2 may be connected to a word line WL.

[0037] In order to configure a latch circuit, an input node of the first inverter INV1 may be connected to an output node of the second inverter INV2, and an input node of the second inverter INV2 may be connected to an output node of the first inverter INV1.

[0038] The first inverter INV1 may include a first pull-up transistor PU1 and a first pull-down transistor PD1 connected in series, and the second inverter INV2 may include a second pull-up transistor PU2 and a second pull-down transistor PD2 connected in series. The first pull-up transistor PU1 and the second pull-up transistor PU2 may be PFETs, and the first pull-down transistor PD1 and the second pull-down transistor PD2 may be NFETs.

[0039] Reference Figures 1 to 6 , a semiconductor device according to some embodiments may include a lower region I, an upper region II, and a wiring region III.

[0040] The lower region I, the upper region II, and the wiring region III may be sequentially stacked on the substrate 100. In the following description, the first pull-up transistor PU1 and the second pull-up transistor PU2 are part of the lower region I, and the first pull-down transistor PD1 and the second pull-down transistor PD2 are part of the upper region II, but the present disclosure is not limited thereto. A person of ordinary skill in the art will understand that the first pull-down transistor PD1 and the second pull-down transistor PD2 may be part of the lower region I, and the first pull-up transistor PU1 and the second pull-up transistor PU2 may be part of the upper region II. In addition, the following description will be based on an example embodiment in which the first transfer transistor PS1 and the second transfer transistor PS2 are part of the upper region II, but the present disclosure is not limited thereto. A person of ordinary skill in the art will understand that the first transfer transistor PS1 and the second transfer transistor PS2 may be part of the lower region I.

[0041] The semiconductor device according to some embodiments may include a substrate 100, a field insulation layer 105, first active patterns 110A and 110B, second active patterns 210A and 210B, first gate structures 131A, 131B, 132A and 132B, second gate structures 231A, 231B, 232A and 232B, a cutting pattern CT, a gate dielectric layer 120, a gate spacer 140, a lower source / drain region 160A, an upper source / drain region 160B, lower source / drain contacts 171A to 174A, upper source / drain contacts 171B to 174B, 175 and 176, wiring patterns MA1, MA2, MB, MC1, MC2, MD1 and MD2, a lower shared contact SC1, and an upper shared contact SC2.

[0042] The substrate 100 may be bulk silicon or silicon on insulator (SOI). In a variation, the substrate 100 may be a silicon substrate, or may include, for example, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate 100 may be an epitaxial layer formed on a base substrate. For ease of description, the substrate 100 will be described as a silicon substrate.

[0043] The first active patterns 110A and 110B and the second active patterns 210A and 210B may be spaced apart from each other and extend in parallel in the first direction Y. For example, the first active patterns 110A and 110B and the second active patterns 210A and 210B may extend longer in the first direction Y and may be spaced apart from each other in a second direction X intersecting the first direction Y. The first active patterns 110A and 110B and the second active patterns 210A and 210B may include lower active patterns 110A and 210A disposed in the lower region I, and upper active patterns 110B and 210B disposed in the upper region II.

[0044] The first active patterns 110A and 110B may include a first lower active pattern 110A in the lower region I, and a first upper active pattern 110B in the upper region II. For example, the substrate 100, the first lower active pattern 110A, and the first upper active pattern 110B may be sequentially arranged along a third direction Z intersecting the upper surface of the substrate 100. The first lower active pattern 110A may extend along a first direction Y on the substrate 100. The first upper active pattern 110B may be spaced apart from the first lower active pattern 110A and may extend in the first direction Y.

[0045] In some embodiments, the first lower active pattern 110A may include a plurality of bridge patterns (e.g., a first bridge pattern 112 and a second bridge pattern 113) sequentially stacked on the substrate 100 and spaced apart from each other. In some embodiments, the first upper active pattern 110B may include a plurality of bridge patterns (e.g., a third bridge pattern 116 and a fourth bridge pattern 117) sequentially stacked on the first lower active pattern 110A and spaced apart from each other. The first active patterns 110A and 110B may be used as a plurality of bridge channels including a plurality of bridge channels. The number of bridge patterns included in the first active patterns 110A and 110B is merely an example and is not limited to the illustrated example.

[0046] In some embodiments, a first fin pattern 111 may be formed between the substrate 100 and the first bridge pattern 112. The first fin pattern 111 may protrude from the upper surface of the substrate 100 and extend in the first direction Y. The first fin pattern 111 may be formed by etching a portion of the substrate 100, or may be an epitaxial layer grown from the substrate 100.

[0047] The second active patterns 210A and 210B may include a second lower active pattern 210A in the lower region I, and a second upper active pattern 210B in the upper region II. For example, the substrate 100, the second lower active pattern 210A, and the second upper active pattern 210B may be sequentially arranged along the third direction Z. The second lower active pattern 210A may extend along the first direction Y on the substrate 100. The second upper active pattern 210B may be spaced apart from the second lower active pattern 210A and extend in the first direction Y.

[0048] In some embodiments, the second lower active pattern 210A may include a plurality of bridge patterns (e.g., a fifth bridge pattern 212 and a sixth bridge pattern 213) sequentially stacked on the substrate 100 and spaced apart from each other. In some embodiments, the second upper active pattern 210B may include a plurality of bridge patterns (e.g., a seventh bridge pattern 216 and an eighth bridge pattern 217) sequentially stacked on the second lower active pattern 210A and spaced apart from each other. The second active patterns 210A and 210B may be used as a substrate including a multi-bridge channel. The number of bridge patterns included in the second active patterns 210A and 210B is only an example and is not limited thereto.

[0049] In some embodiments, the second fin pattern 211 may be formed between the substrate 100 and the fifth bridge pattern 212. The second fin pattern 211 may protrude from the upper surface of the substrate 100 and extend in the first direction Y. The second fin pattern 211 may be formed by etching a portion of the substrate 100, or may be an epitaxial layer grown from the substrate 100.

[0050] Each of the first active patterns 110A and 110B and the second active patterns 210A and 210B may include silicon (Si) or germanium (Ge) as an elemental semiconductor material. Alternatively, each of the first active patterns 110A and 110B and the second active patterns 210A and 210B may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. The group IV-IV compound semiconductor may be a binary compound or a ternary compound including at least two of carbon (C), silicon (Si), germanium (Ge), or tin (Sn), or a compound including at least two of carbon (C), silicon (Si), germanium (Ge), or tin (Sn) doped with a group IV element. The group III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by a combination of at least one of aluminum (Al), gallium (Ga), or indium (In) as a group III element and at least one of phosphorus (P), arsenic (As), or antimony (Sb) as a group V element.

[0051] In some embodiments, the isolation patterns 115 and 215 may be formed between the lower active patterns 110A and 210A and the upper active patterns 110B and 210B. For example, the lower active patterns 110A and 210A, the isolation patterns 115 and 215, and the upper active patterns 110B and 210B may be sequentially arranged along the third direction Z. The isolation patterns 115 and 215 may be spaced apart from the lower active patterns 110A and 210A, and the upper active patterns 110B and 210B may be spaced apart from the isolation patterns 115 and 215.

[0052] The isolation patterns 115 and 215 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon carbon nitride, silicon carbon oxynitride, or a combination thereof, but are not limited thereto. In some other embodiments, the isolation patterns 115 and 215 may be omitted.

[0053] The field insulating layer 105 may be disposed on the substrate 100. In some embodiments, the field insulating layer 105 may cover at least a portion of a side of the first fin pattern 111 and at least a portion of a side of the second fin pattern 211, or overlap at least a portion of a side of the first fin pattern 111 and at least a portion of a side of the second fin pattern 211. The field insulating layer 105 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof, but is not limited thereto.

[0054] The first gate structures 131A, 131B, 132A, and 132B and the second gate structures 231A, 231B, 232A, and 232B may be formed on the substrate 100 and the field insulating layer 105. The first gate structures 131A, 131B, 132A, and 132B and the second gate structures 231A, 231B, 232A, and 232B may be spaced apart from each other and extend in parallel in the second direction X. For example, the first gate structures 131A, 131B, 132A, and 132B and the second gate structures 231A, 231B, 232A, and 232B may extend longer in the second direction X and may be spaced apart from each other in the first direction Y. In addition, the first gate structures 131A, 131B, 132A and 132B and the second gate structures 231A, 231B, 232A and 232B may include lower gate electrodes 131A, 132A, 231A and 232A disposed in the lower region I and upper gate electrodes 131B, 132B, 231B and 232B disposed in the upper region II.

[0055] The first gate structures 131A, 131B, 132A, and 132B and the second gate structures 231A, 231B, 232A, and 232B may overlap the first active patterns 110A and 110B and the second active patterns 210A and 210B. The first gate structures 131A, 131B, 132A, and 132B and the second gate structures 231A, 231B, 232A, and 232B may surround the periphery of the first active patterns 110A and 110B and the periphery of the second active patterns 210A and 210B. For example, the first active patterns 110A and 110B and the second active patterns 210A and 210B may extend in the first direction Y to extend through the first gate structures 131A, 131B, 132A, and 132B and the second gate structures 231A, 231B, 232A, and 232B.

[0056] Cutting patterns CT may be formed on the substrate 100 and the field insulating layer 105. The cutting patterns CT may extend longer in the first direction Y between the first active patterns 110A and 110B and the second active patterns 210A and 210B to cut the first gate structures 131A, 131B, 132A, and 132B and the second gate structures 231A, 231B, 232A, and 232B.

[0057] For example, the first gate structure 131A, 131B, 132A, and 132B may include first gate electrodes 131A and 131B and second gate electrodes 132A and 132B separated from each other by the cutting pattern CT. The first gate electrodes 131A and 131B and the second gate electrodes 132A and 132B may be spaced apart from each other in the second direction X by the cutting pattern CT. The first gate electrodes 131A and 131B may extend from one side of the cutting pattern CT along the second direction X to overlap with the first active patterns 110A and 110B. The second gate electrodes 132A and 132B may extend from the other side of the cutting pattern CT along the second direction X to overlap with the second active patterns 210A and 210B.

[0058] In addition, for example, the second gate structure 231A, 231B, 232A, and 232B may include third gate electrodes 231A and 231B and fourth gate electrodes 232A and 232B separated from each other by the cutting pattern CT. The third gate electrodes 231A and 231B and the fourth gate electrodes 232A and 232B may be spaced apart from each other in the second direction X by the cutting pattern CT. The third gate electrodes 231A and 231B may extend from one side of the cutting pattern CT along the second direction X to overlap with the first active patterns 110A and 110B. The fourth gate electrodes 232A and 232B may extend from the other side of the cutting pattern CT along the second direction X to overlap with the second active patterns 210A and 210B.

[0059] The cutting pattern CT may include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon carbonitride, silicon carbon oxynitride, or a combination thereof, but is not limited thereto.

[0060] In some embodiments, the cutting pattern CT may define both ends of each of the gate electrodes 131A, 131B, 132A, 132B, 231A, 231B, 232A, and 232B. According to the cutting of the cutting pattern CT, the length of the first gate electrodes 131A and 131B extending in the second direction X may be the same as the length of the third gate electrodes 231A and 231B extending in the second direction X. In addition, the length of the second gate electrodes 132A and 132B extending in the second direction X may be the same as the length of the fourth gate electrodes 232A and 232B extending in the second direction X. In the present disclosure, the term "same" includes not only being completely identical, but also includes slight differences that may occur due to process margins, etc.

[0061] The first gate electrodes 131A and 131B may include a first lower gate electrode 131A in the lower region I and a first upper gate electrode 131B in the upper region II. The first lower gate electrode 131A may overlap the first lower active pattern 110A. The first upper gate electrode 131B may overlap the first upper active pattern 110B on the first lower gate electrode 131A. The first upper gate electrode 131B may contact the first lower gate electrode 131A. That is, the first lower gate electrode 131A and the first upper gate electrode 131B may be electrically connected to each other.

[0062] The first gate electrodes 131A and 131B may be provided as gate electrodes of the first inverter INV1. For example, the first lower active pattern 110A overlapping the first lower gate electrode 131A may be provided as a channel region of the first pull-up transistor PU1, and the first upper active pattern 110B overlapping the first upper gate electrode 131B may be provided as a channel region of the first pull-down transistor PD1.

[0063] The second gate electrodes 132A and 132B may include a second lower gate electrode 132A in the lower region I and a second upper gate electrode 132B in the upper region II. The second lower gate electrode 132A may intersect the second lower active pattern 210A. The second upper gate electrode 132B may intersect the second upper active pattern 210B on the second lower gate electrode 132A. The second upper gate electrode 132B may contact the second lower gate electrode 132A. That is, the second lower gate electrode 132A and the second upper gate electrode 132B may be electrically connected to each other.

[0064] In some embodiments, the second gate electrodes 132A and 132B may overlap at least one of the second lower active pattern 210A and the second upper active pattern 210B. For example, in one variation, one of the second lower gate electrode 132A and the second upper gate electrode 132B may be omitted.

[0065] The second gate electrodes 132A and 132B may be provided as gate electrodes of the second transfer transistor PS2. For example, the second upper active pattern 210B overlapping the second upper gate electrode 132B may be provided as the channel region of the second transfer transistor PS2. In this case, as shown in the figure, the second transfer transistor PS2 may be provided as an NFET in the upper region II. For another example, the second lower active pattern 210A overlapping the second lower gate electrode 132A may be provided as the channel region of the second transfer transistor PS2. In this case, unlike the example shown, the second transfer transistor PS2 may be provided as a PFET in the lower region I.

[0066] The third gate electrodes 231A and 231B may include a third lower gate electrode 231A in the lower region I and a third upper gate electrode 231B in the upper region II. The third lower gate electrode 231A may overlap the first lower active pattern 110A. The third upper gate electrode 231B may overlap the first upper active pattern 110B on the third lower gate electrode 231A. The third upper gate electrode 231B may contact the third lower gate electrode 231A. That is, the third lower gate electrode 231A and the third upper gate electrode 231B may be electrically connected to each other.

[0067] In some embodiments, the third gate electrodes 231A and 231B may overlap at least one of the first lower active pattern 110A or the first upper active pattern 110B. For example, in one variation, one of the third lower gate electrode 231A and the third upper gate electrode 231B may be omitted.

[0068] The third gate electrodes 231A and 231B may be provided as gate electrodes of the first transfer transistor PS1. For example, the first upper active pattern 110B overlapping the third upper gate electrode 231B may be provided as a channel region of the first transfer transistor PS1. In this case, as shown in the figure, the first transfer transistor PS1 may be provided as an NFET in the upper region II. For another example, the first lower active pattern 110A overlapping the third lower gate electrode 231A may be provided as a channel region of the first transfer transistor PS1. In this case, unlike the example shown, the first transfer transistor PS1 may be provided as a PFET in the lower region I.

[0069] The fourth gate electrodes 232A and 232B may include a fourth lower gate electrode 232A in the lower region I and a fourth upper gate electrode 232B in the upper region II. The fourth lower gate electrode 232A may intersect the second lower active pattern 210A. The fourth upper gate electrode 232B may intersect the second upper active pattern 210B on the fourth lower gate electrode 232A. The fourth upper gate electrode 232B may contact the fourth lower gate electrode 232A. That is, the fourth lower gate electrode 232A and the fourth upper gate electrode 232B may be electrically connected to each other.

[0070] The fourth gate electrodes 232A and 232B may be provided as gate electrodes of the second inverter INV2. For example, the second lower active pattern 210A overlapping the fourth lower gate electrode 232A may be provided as a channel region of the second pull-up transistor PU2, and the second upper active pattern 210B overlapping the fourth upper gate electrode 232B may be provided as a channel region of the second pull-down transistor PD2.

[0071] Each of the gate electrodes 131A, 131B, 132A, 132B, 231A, 231B, 232A, and 232B may include a conductive material, for example, at least one of TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, Al, or a combination thereof, but is not limited thereto. Each of the gate electrodes 131A, 131B, 132A, 132B, 231A, 231B, 232A, and 232B may be formed by a replacement process, but is not limited thereto.

[0072] Each of the gate electrodes 131A, 131B, 132A, 132B, 231A, 231B, 232A, and 232B is shown as only a single layer, but this is only an example. Each of the gate electrodes 131A, 131B, 132A, 132B, 231A, 231B, 232A, and 232B can be formed by stacking a plurality of conductive layers. For example, each of the gate electrodes 131A, 131B, 132A, 132B, 231A, 231B, 232A, and 232B may include a work function adjustment layer for adjusting the work function and a filling conductive layer for filling the space formed by the work function adjustment layer. The work function adjustment layer may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, or a combination thereof. The filling conductive layer may include, for example, W or Al.

[0073] In some embodiments, the lower gate electrodes 131A, 132A, 231A, and 232A and the upper gate electrodes 131B, 132B, 231B, and 232B may include different conductive materials. For example, the lower gate electrodes 131A, 132A, 231A, and 232A and the upper gate electrodes 131B, 132B, 231B, and 232B may include work function adjustment layers of different conductivity types. For example, the lower gate electrodes 131A, 132A, 231A, and 232A may include a p-type work function adjustment layer, and the upper gate electrodes 131B, 132B, 231B, and 232B may include an n-type work function adjustment layer. In some other embodiments, the lower gate electrodes 131A, 132A, 231A, and 232A and the upper gate electrodes 131B, 132B, 231B, and 232B may include the same conductive material.

[0074] The gate dielectric layer 120 may be interposed between the active patterns 110A, 110B, 210A, and 210B and the gate electrodes 131A, 131B, 132A, 132B, 231A, 231B, 232A, and 232B. The gate dielectric layer 120 may include a dielectric material, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide. The high dielectric constant material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof, but is not limited thereto.

[0075] The gate dielectric layer 120 is shown as being cut only by the cutting pattern CT, but this is only an example. As another example, the gate dielectric layer 120 may further extend along the side of the cutting pattern CT.

[0076] The gate spacer 140 may extend along a side of each of the gate electrodes 131A, 131B, 132A, 132B, 231A, 231B, 232A, and 232B. Each of the active patterns 110A, 110B, 210A, and 210B may extend in the first direction Y and pass through the gate spacer 140. The gate spacer 140 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon carbon nitride, silicon carbon nitride oxynitride, or a combination thereof, but is not limited thereto.

[0077] In some embodiments, the gate dielectric layer 120 may include an interface layer 122 and a high dielectric layer 124 sequentially stacked on the respective active patterns 110A, 110B, 210A, and 210B.

[0078] The interface layer 122 may at least partially surround the periphery of each of the bridge patterns 112, 113, 116, 117, 212, 213, 216, and 217. For example, the interface layer 122 may conformally extend along the periphery of each of the bridge patterns 112, 113, 116, 117, 212, 213, 216, and 217. In addition, the interface layer 122 may extend along the fin patterns 111 and 211 exposed from the field insulation layer 105.

[0079] In some embodiments, the interface layer 122 may be an oxide layer formed by oxidizing surfaces of the active patterns 110A, 110B, 210A, and 210B. For example, when the active patterns 110A, 110B, 210A, and 210B include silicon (Si), the interface layer 122 may include a silicon oxide layer.

[0080] The high dielectric layer 124 may at least partially surround the periphery of the interface layer 122. A portion of the high dielectric layer 124 may be interposed between the gate electrodes 131A, 131B, 132A, 132B, 231A, 231B, 232A, and 232B and the gate spacer 140. For example, the high dielectric layer 124 may conformally extend along the periphery of the interface layer 122 and the contour of the inner side of the gate spacer 140. The high dielectric layer 124 may further extend along the upper surface of the field insulation layer 105.

[0081] In some embodiments, the high dielectric constant layer 124 may include a high dielectric constant material having a dielectric constant greater than that of silicon oxide. The high dielectric constant material may include, for example, hafnium oxide (HfO 2 )、ZrO 2 ), lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Strontium Titanium Oxide (SrTiO 3 ), lanthanum aluminum oxide (LaAlO 3 ), yttrium oxide (Y 2 O 3 ), Hafnium Oxynitride (HfO x N y ), zirconium oxynitride (ZrO x N y ), lanthanum oxynitride (La 2 O x N y ), aluminum oxynitride (Al 2 O x N y ), titanium oxynitride (TiO x N y ), Strontium Titanium Oxynitride (SrTiO x N y ), lanthanum aluminum oxynitride (LaAlO x N y ), yttrium oxynitride (Y 2 O x N y ) or at least one of their combinations, but not limited thereto.

[0082] The lower source / drain region 160A may be formed on at least one side of each of the lower gate electrodes 131A, 132A, 231A, and 232A. The lower active patterns 110A and 210A may be connected to the lower source / drain region 160A by extending through the lower gate electrodes 131A, 132A, 231A, and 232A and the gate spacer 140. The lower source / drain region 160A may be electrically insulated from the lower gate electrodes 131A, 132A, 231A, and 232A by the gate spacer 140.

[0083] In some embodiments, the lower source / drain region 160A may include an epitaxial layer. For example, the lower source / drain region 160A may be an epitaxial layer grown from the lower active patterns 110A and 210A by an epitaxial growth method.

[0084] The upper source / drain region 160A may be formed on at least one side of each of the upper gate electrodes 131B, 132B, 231B, and 232B. The upper active patterns 110B and 210B may be connected to the upper source / drain region 160B by extending through the upper gate electrodes 131B, 132B, 231B, and 232B and the gate spacer 140. The upper source / drain region 160B may be electrically insulated from the upper gate electrodes 131B, 132B, 231B, and 232B by the gate spacer 140.

[0085] In some embodiments, the upper source / drain region 160B may include an epitaxial layer. For example, the upper source / drain region 160B may be an epitaxial layer grown from the upper active patterns 110B and 210B by an epitaxial growth method.

[0086] The lower source / drain region 160A may have a first conductivity type, and the upper source / drain region 160B may have a second conductivity type different from the first conductivity type. For example, the first conductivity type may be a p-type, and the second conductivity type may be an n-type. In this case, the lower active patterns 110A and 210A may be used as a channel region of a PFET, and the upper active patterns 110B and 210B may be used as a channel region of an NFET, but this is only an example. The first conductivity type may be a p-type, and the second conductivity type may be an n-type.

[0087] Lower source / drain contacts 171A to 174A may be disposed in the lower region I. The lower source / drain contacts 171A to 174A may be connected to the lower source / drain region 160A.

[0088] For example, a first lower source / drain contact 171A connected to the lower source / drain region 160A of the first lower active pattern 110A may be formed on a side of the first lower gate electrode 131A opposite to the third lower gate electrode 231A. For example, a second lower source / drain contact 172A connected to the lower source / drain region 160A of the first lower active pattern 110A may be formed between the first lower gate electrode 131A and the third lower gate electrode 231A. For example, a third lower source / drain contact 173A connected to the lower source / drain region 160A of the second lower active pattern 210A may be formed on a side of the fourth lower gate electrode 232A opposite to the second lower gate electrode 132A. For example, a fourth lower source / drain contact 174A connected to the lower source / drain region 160A of the second lower active pattern 210A may be formed between the second lower gate electrode 132A and the fourth lower gate electrode 232A. The shapes and arrangements of the lower source / drain contacts 171A to 174A are merely examples and are not limited to the illustrated examples.

[0089] In some embodiments, a length of the second lower source / drain contact 172A extending in the second direction X may be greater than a length of the fourth lower source / drain contact 174A extending in the second direction X. In some embodiments, a portion of the second lower source / drain contact 172A may overlap a portion of the fourth lower gate electrode 232A in the first direction Y.

[0090] Upper source / drain contacts 171B to 174B, 175, and 176 may be disposed in the upper region II. The upper source / drain contacts 171B to 174B, 175, and 176 may be connected to the upper source / drain region 160B.

[0091] For example, the first upper source / drain contact 171B connected to the upper source / drain region 160B of the first upper active pattern 110B may be formed on a side of the first upper gate electrode 131B opposite to the third upper gate electrode 231B. For example, the second upper source / drain contact 172B connected to the upper source / drain region 160B of the first upper active pattern 110B may be formed between the first upper gate electrode 131B and the third upper gate electrode 231B. For example, the third upper source / drain contact 173B connected to the upper source / drain region 160B of the second upper active pattern 210B may be formed on a side of the fourth upper gate electrode 232B opposite to the second upper gate electrode 132B. For example, the fourth upper source / drain contact 174B connected to the upper source / drain region 160B of the second upper active pattern 210B may be formed between the second upper gate electrode 132B and the fourth upper gate electrode 232B. For example, the fifth upper source / drain contact 175 connected to the upper source / drain region 160B of the first upper active pattern 110B may be formed on a side of the third upper gate electrode 231B opposite to the first upper gate electrode 131B. For example, the sixth upper source / drain contact 176 connected to the upper source / drain region 160B of the second upper active pattern 210B may be formed on a side of the second upper gate electrode 132B opposite to the fourth upper gate electrode 232B. The shapes and arrangements of the upper source / drain contacts 171B to 174B, 175, and 176 are merely examples and are not limited thereto.

[0092] In some embodiments, a length of the fourth upper source / drain contact 174B extending in the second direction X may be greater than a length of the second upper source / drain contact 172B extending in the second direction X. In some embodiments, a portion of the fourth upper source / drain contact 174B may overlap with a portion of the first upper gate electrode 131B in the first direction Y. In some embodiments, a portion of the fourth upper source / drain contact 174B may overlap with a portion of the second lower source / drain contact 172A in the third direction Z.

[0093] Wiring patterns MA1, MA2, MB, MC1, MC2, MD1, and MD2 may be disposed in the wiring region III. For example, an inter-wiring insulating layer 330 may be stacked on the interlayer insulating layer 320. Wiring patterns MA1, MA2, MB, MC1, MC2, MD1, and MD2 may be formed in the inter-wiring insulating layer 330 and insulated from each other.

[0094] A first signal having a first power / voltage may be provided to the first lower source / drain contact 171A. For example, a first lower contact via 181A connected to an upper surface of the first lower source / drain contact 171A may be formed. A first wiring pattern MA1 connected to the first lower contact via 181A may be formed in the wiring region III. The first wiring pattern MA1 may be provided as a power node V for providing a first signal to the first lower source / drain contact 171A. DD In some embodiments, the first lower contact via 181A may extend in the third direction Z over the lower region I and the upper region II.

[0095] The second lower source / drain contact 172A and the second upper source / drain contact 172B may be connected to each other. For example, a second lower contact via 182 may be formed to connect the upper surface of the second lower source / drain contact 172A with the lower surface of the second upper source / drain contact 172B. The second lower source / drain contact 172A and the second upper source / drain contact 172B may be set as output nodes of the first inverter INV1.

[0096] The first signal may be provided to the third lower source / drain contact 173A. For example, a third lower contact via 183A connected to the upper surface of the third lower source / drain contact 173A may be formed. A second wiring pattern MA2 connected to the third lower contact via 183A may be formed in the wiring region III. The second wiring pattern MA2 may be provided as a power node V for providing the first signal to the third lower source / drain contact 173A. DD In some embodiments, the third lower contact via 183A may extend in the third direction Z over the lower region I and the upper region II.

[0097] The fourth lower source / drain contact 174A and the fourth upper source / drain contact 174B may be connected to each other. For example, a fourth lower contact via 184 may be formed to connect the upper surface of the fourth lower source / drain contact 174A with the lower surface of the fourth upper source / drain contact 174B. The fourth lower source / drain contact 174A and the fourth upper source / drain contact 174B may be set as the output node of the second inverter INV2.

[0098] For example, the lower contact vias 181A, 182, 183A, and 184 may be connected to the lower source / drain contacts 171A to 174A by extending through the isolation insulating layer 310. The isolation insulating layer 310 may cover the lower source / drain region 160A or overlap the lower source / drain region 160A. The isolation insulating layer 310 may be inserted between the lower source / drain region 160A and the upper source / drain region 160B. The upper source / drain region 160B may be electrically insulated from the lower source / drain region 160A by the isolation insulating layer 310. The isolation insulating layer 310 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon carbon nitride, silicon oxynitride, or a combination thereof, but is not limited thereto.

[0099] A second signal having a power / voltage different from the first signal may be provided to the first upper source / drain contact 171B and the third upper source / drain contact 173B. For example, a first upper contact via 181B connected to the upper surface of the first upper source / drain contact 171B may be formed, and a second upper contact via 183B connected to the upper surface of the third upper source / drain contact 173B may be formed. In addition, a third wiring pattern MB connected to the first upper contact via 181B and the second upper contact via 183B may be formed in the wiring region III. The third wiring pattern MB may be set to a ground node V for providing a second signal to the first upper source / drain contact 171B and the third upper source / drain contact 173B. SS .

[0100] In some embodiments, the first upper contact vias 181B and the second upper contact vias 183B may be arranged along the first direction Y. The third wiring patterns MB may extend longer in the first direction Y to connect the first upper contact vias 181B and the second upper contact vias 183B.

[0101] The third gate electrodes 231A and 231B may be connected to the word line WL. For example, a first gate contact 191 connected to the upper surface of the third upper gate electrode 231B may be formed. A fourth wiring pattern MC1 connected to the first gate contact 191 may be formed in the wiring region III. The fourth wiring pattern MC1 may be set as a node of the word line WL, and thus may be connected to the gate of the first transfer transistor PS1 (i.e., the third gate electrodes 231A and 231B).

[0102] The second gate electrodes 132A to 132B may be connected to the word line WL. For example, a second gate contact 292 connected to the upper surface of the second upper gate electrode 132B may be formed. A fifth wiring pattern MC2 connected to the second gate contact 292 may be formed in the wiring region III. The fifth wiring pattern MC2 may be set as a node of the word line WL, and thus may be connected to the gate of the second transfer transistor PS2 (i.e., the second gate electrodes 132A and 132B).

[0103] In some embodiments, at least a portion of the fourth wiring pattern MC1 and at least a portion of the fifth wiring pattern MC2 may overlap each other in the second direction X.

[0104] The fifth upper source / drain contact 175 may be connected to the bit line BL. For example, a third upper contact via 185 connected to the upper surface of the fifth upper source / drain contact 175 may be formed. A sixth wiring pattern MD1 connected to the third upper contact via 185 may be formed in the wiring region III. The sixth wiring pattern MD1 may be set as the bit line BL, and thus may be connected to the first transfer transistor PS1 through the fifth upper source / drain contact 175. In some embodiments, the sixth wiring pattern MD1 may extend longer in the first direction Y.

[0105] The sixth upper source / drain contact 176 may be connected to a complementary bit line / BL. For example, a fourth upper contact via 186 connected to the upper surface of the sixth upper source / drain contact 176 may be formed. A seventh wiring pattern MD2 connected to the fourth upper contact via 186 may be formed in the wiring region III. The seventh wiring pattern MD2 may be set as a complementary bit line / BL, and thus may be connected to the second transfer transistor PS2 through the sixth upper source / drain contact 176. In some embodiments, the seventh wiring pattern MD2 may extend longer in the first direction Y.

[0106] The upper contact vias 181B, 183B, 185 and 186 may be connected to the upper source / drain contacts 171B to 174B, 175 and 176 by extending through the interlayer insulating layer 320. The interlayer insulating layer 320 may cover the upper source / drain region 160B or overlap the upper source / drain region 160B. The interlayer insulating layer 320 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon carbonitride, silicon carbon nitride or a combination thereof, but is not limited thereto. In addition, the first gate contact 191 may be connected to the third gate electrodes 231A and 231B by extending through the interlayer insulating layer 320, and the second gate contact 292 may be connected to the second gate electrodes 132A and 132B by extending through the interlayer insulating layer 320.

[0107] The lower shared contact SC1 may be disposed in the lower region I. The lower shared contact SC1 may connect the second lower source / drain contact 172A with the fourth gate electrodes 232A and 232B. The output node of the first inverter INV1 (i.e., the second lower source / drain contact 172A) may be connected to the input node of the second inverter INV2 (i.e., the fourth gate electrodes 232A and 232B) through the lower shared contact SC1.

[0108] The lower shared contact SC1 may be spaced apart from the upper source / drain contacts 171B to 174B, 175, and 176 in the third direction Z. For example, an upper surface of the lower shared contact SC1 may be formed at a height lower than a lower surface of the fourth upper source / drain contact 174B based on an upper surface of the substrate 100. Thus, the lower shared contact SC1 may be electrically insulated from the fourth upper source / drain contact 174B.

[0109] In some embodiments, the lower shared contact SC1 may extend in the first direction Y to connect the second lower source / drain contact 172A with the fourth lower gate electrode 232A. For example, the lower shared contact SC1 may extend along the first direction Y from a region where the second lower source / drain contact 172A and the fourth lower gate electrode 232A overlap each other in the first direction Y.

[0110] In some embodiments, the lower shared contact SC1 may be formed on the side of the second lower source / drain contact 172A and the side of the fourth lower gate electrode 232A. For example, the lower shared contact SC1 may protrude from the side of the second lower source / drain contact 172A in the first direction Y and thus be connected to the side of the fourth lower gate electrode 232A. In some embodiments, the lower shared contact SC1 may be formed at the same height as the lower source / drain contacts 171A to 174A. In the present disclosure, the term "same height" means "formed by the same manufacturing process".

[0111] In some embodiments, at least a portion of the lower shared contact SC1 may overlap the cutting pattern CT in the third direction Z. The lower shared contact SC1 may be connected to the side of the fourth lower gate electrode 232A extending in the second direction X, but the technical spirit of the present disclosure is not limited thereto. The lower shared contact SC1 may be connected to the side of the fourth lower gate electrode 232A extending in the first direction Y.

[0112] The upper shared contact SC2 may be disposed in the upper region II. The upper shared contact SC2 may connect the fourth upper source / drain contact 174B to the first gate electrodes 131A and 131B. The output node of the second inverter INV2 (i.e., the fourth upper source / drain contact 174B) may be connected to the input node of the first inverter INV1 (i.e., the first gate electrodes 131A and 131B) through the upper shared contact SC2.

[0113] The upper shared contact SC2 may be spaced apart from the lower source / drain contacts 171A to 174A in the third direction Z. For example, a lower surface of the upper shared contact SC2 may be formed at a height higher than an upper surface of the second lower source / drain contact 172A based on the upper surface of the substrate 100. Therefore, the upper shared contact SC2 may be electrically insulated from the second lower source / drain contact 172A.

[0114] In addition, the upper shared contact portion SC2 may be spaced apart from the wiring patterns MA1, MA2, MB, MC1, MC2, MD1, and MD2 in the third direction Z. For example, the upper surface of the upper shared contact portion SC2 may be formed at a height lower than the lower surfaces of the wiring patterns MA1, MA2, MB, MC1, MC2, MD1, and MD2 based on the upper surface of the substrate 100. Therefore, the upper shared contact portion SC2 may be electrically insulated from the wiring patterns MA1, MA2, MB, MC1, MC2, MD1, and MD2.

[0115] In some embodiments, the upper shared contact SC2 may extend in the first direction Y to connect the fourth upper source / drain contact 174B with the first upper gate electrode 131B. For example, the upper shared contact SC2 may extend along the first direction Y from a region where the fourth upper source / drain contact 174B and the first upper gate electrode 131B overlap each other in the first direction Y.

[0116] In some embodiments, the upper shared contact SC2 may be formed on the upper surface of the fourth upper source / drain contact 174B and the upper surface of the first upper gate electrode 131B. For example, the upper shared contact SC2 may extend in the first direction Y and thus be connected to the upper surface of the fourth upper source / drain contact 174B and the upper surface of the first upper gate electrode 131B. In some embodiments, the upper shared contact SC2 may be formed at the same height as the upper contact vias 181B, 183B, 185, and 186 and / or the gate contacts 191 and 292.

[0117] In some embodiments, the upper shared contact portion SC2 may not overlap with the cutting pattern CT in the third direction Z, but the technical spirit of the present disclosure is not limited thereto. At least a portion of the upper shared contact portion SC2 may be formed on an upper surface of the cutting pattern CT.

[0118] As semiconductor devices become more and more integrated, individual circuit patterns become more miniaturized to implement more semiconductor devices within the same area. To this end, a semiconductor device based on stacked multi-gate transistors is being studied, in which a multi-gate transistor in an upper region II is stacked on a multi-gate transistor in a lower region I. However, this semiconductor device has a problem that it is difficult to improve integration due to the complexity of the circuit pattern.

[0119] For example, in order to configure the latch circuit of SRAM, a shared contact for forming a node of the latch circuit can be set in the upper region II. However, depending on the arrangement of the gate electrode and the arrangement of the source / drain contact, the shared contact can be in the form of a diagonal or curved shape to configure the latch circuit. This leads to the severity of the complexity of the circuit pattern. In order to solve this problem, the wiring pattern for forming the node of the latch circuit can be set in the wiring region III on the upper region II. However, this also leads to the severity of the complexity of the wiring pattern, whereby the voltage drop (IR drop) and parasitic capacitance may increase.

[0120] Unlike the above examples, the semiconductor device according to some embodiments can reduce the complexity of the circuit pattern and / or the complexity of the wiring pattern by using the lower shared contact SC1 of the lower region I and the upper shared contact SC2 of the upper region II. In detail, as described above, the lower shared contact SC1 can connect the output node of the first inverter INV1 (i.e., the second lower source / drain contact 172A) with the input node of the second inverter INV2 (i.e., the fourth gate electrode 232A and 232B) in the lower region I. In addition, the upper shared contact SC2 can connect the output node of the second inverter INV2 (i.e., the fourth upper source / drain contact 174B) with the input node of the first inverter INV1 (i.e., the first gate electrode 131A and 131B) in the upper region II. That is, since the shared contacts are arranged to be distributed in the lower region I and the upper region II, a semiconductor device having improved freedom in design and integration can be provided.

[0121] In the semiconductor device according to some embodiments, the first gate structures 131A, 131B, 132A and 132B and the second gate structures 231A, 231B, 232A and 232B may all be cut by the same cutting pattern CT extending in a straight direction. In detail, as described above, the cutting pattern CT may extend longer in the first direction Y to separate the first gate electrodes 131A and 131B from the second gate electrodes 132A and 132B, and to separate the third gate electrodes 231A and 231B from the fourth gate electrodes 232A and 232B. Therefore, the difficulty of the process for forming the gate electrodes 131A, 131B, 132A, 132B, 231A, 231B, 232A and 232B may be reduced, and a semiconductor device with a more improved integration may be provided.

[0122] Figure 7 is a diagram showing an example layout of a semiconductor device according to some embodiments of the present disclosure. Figure 8 It shows Figure 7 For ease of description, the above referenced Figures 1 to 6Redundant parts of those described.

[0123] Reference Figure 7 and Figure 8 , in the semiconductor device according to some embodiments, the lower shared contact SC1 may be formed on an upper surface of the second lower source / drain contact 172A and an upper surface of the fourth lower gate electrode 232A.

[0124] For example, the lower shared contact SC1 may extend in the first direction Y and thus be connected to an upper surface of the second lower source / drain contact 172A and an upper surface of the fourth lower gate electrode 232A.

[0125] The lower shared contact SC1 may be spaced apart from the upper source / drain contacts 171B to 174B, 175 , and 176 in the third direction Z. For example, an upper surface of the lower shared contact SC1 may be formed at a height lower than upper surfaces of the second lower contact via 182 and the fourth lower contact via 184 based on an upper surface of the substrate 100 .

[0126] Fig. 9 is a diagram showing an example layout of a semiconductor device according to some embodiments of the present disclosure. Fig.10 It shows Fig. 9 For ease of description, the above referenced Figures 1 to 6 Redundant parts of those described.

[0127] Reference Fig. 9 and Fig.10 , in the semiconductor device according to some embodiments, the upper shared contact SC2 may be formed on a side of the fourth upper source / drain contact 174B and a side of the first upper gate electrode 131B.

[0128] For example, the upper shared contact SC2 may protrude from the side of the fourth upper source / drain contact 174B in the first direction Y and thus be connected to the side of the first upper gate electrode 131B. In some embodiments, the upper shared contact SC2 may be formed at the same height as the upper source / drain contacts 171B to 174B, 175, and 176.

[0129] The upper shared contact SC2 may be spaced apart from the lower source / drain contacts 171A to 174A in the third direction Z. For example, a lower surface of the upper shared contact SC2 may be formed at a height higher than an upper surface of the second lower source / drain contact 172A based on an upper surface of the substrate 100 .

[0130] Fig.11 is a diagram showing an example layout of a semiconductor device according to some embodiments of the present disclosure. Fig.12 It shows Fig.11For ease of description, the above referenced Figures 1 to 6 Redundant parts of those described.

[0131] Reference Fig.11 and Fig.12 In the semiconductor device according to some embodiments, the lower shared contact SC1 may be formed on the upper surface of the second lower source / drain contact 172A and the upper surface of the fourth lower gate electrode 232A, and the upper shared contact SC2 may be formed on the side of the fourth upper source / drain contact 174B and the side of the first upper gate electrode 131B. Figure 7 and Figure 8 The same as described above, and the upper shared contact portion SC2 is the same as that described above. Fig. 9 and Fig.10 The descriptions are the same, so their detailed descriptions will be omitted.

[0132] Fig.13 is a diagram showing an example layout of a semiconductor device according to some embodiments of the present disclosure. Fig.14 It shows Fig.13 For ease of description, the above referenced Figures 1 to 12 Redundant parts of those described.

[0133] Reference Fig.13 and Fig.14 , the semiconductor device according to some embodiments may further include a seventh upper source / drain contact 177 and an eighth upper source / drain contact 178 .

[0134] The seventh upper source / drain contact 177 may be connected to the first lower source / drain contact 171A. For example, the first lower contact via 181A may connect the upper surface of the first lower source / drain contact 171A with the lower surface of the seventh upper source / drain contact 177. In some embodiments, the seventh upper source / drain contact 177 may be inserted between the first upper source / drain contact 171B and the sixth upper source / drain contact 176.

[0135] The eighth upper source / drain contact 178 may be connected to the third lower source / drain contact 173A. For example, the third lower contact via 183A may connect the upper surface of the third lower source / drain contact 173A with the lower surface of the eighth upper source / drain contact 178. In some embodiments, the eighth upper source / drain contact 178 may be inserted between the third upper source / drain contact 173B and the fifth upper source / drain contact 175.

[0136] A first signal may be provided to the first lower source / drain contact 171A and the third lower source / drain contact 173A. For example, a fifth upper contact via 187 connected to the upper surface of the seventh upper source / drain contact 177 may be formed, and a sixth upper contact via 188 connected to the upper surface of the eighth upper source / drain contact 178 may be formed. In addition, a third wiring pattern MB connected to the fifth upper contact via 187 and the sixth upper contact via 188 may be formed in the wiring region III. The third wiring pattern MB may be provided as a power node V for providing a first signal to the first lower source / drain contact 171A and the third lower source / drain contact 173A. DD .

[0137] In some embodiments, the fifth upper contact via 187 and the sixth upper contact via 188 may be arranged along the first direction Y. The third wiring pattern MB may extend longer in the first direction Y to connect the fifth upper contact via 187 with the sixth upper contact via 188 .

[0138] A second signal different from the first signal may be provided to the first upper source / drain contact 171B. For example, a first wiring pattern MA1 connected to the first upper contact via 181B may be formed in the wiring region III. The first wiring pattern MA1 may be provided as a ground node V for providing the second signal to the first upper source / drain contact 171B. SS .

[0139] The second signal may be provided to the third upper source / drain contact 173B. For example, the second wiring pattern MA2 connected to the second upper contact via 183B may be formed in the wiring region III. The second wiring pattern MA2 may be set to a ground node V for providing the second signal to the third upper source / drain contact 173B. SS .

[0140] Fig.15 is an example circuit diagram illustrating a semiconductor device according to some embodiments of the present disclosure. Fig.16 and Fig.17 1 is a diagram showing various exemplary layouts of semiconductor devices according to some embodiments of the present disclosure. Figures 1 to 14 Redundant parts of those described.

[0141] Reference Fig.15 , a semiconductor device according to some embodiments may include first to fourth unit elements D1 to D4 adjacent to each other.

[0142] Each of the first to fourth unit elements D1 to D4 may include a plurality of cells connected in parallel at a power node V DD and ground node V SSA pair of inverters INV1 and INV2 therebetween, and a first pass transistor PS1 and a second pass transistor PS2 connected to output nodes of the inverters INV1 and INV2, respectively.

[0143] In some embodiments, the first to fourth cell elements D1 to D4 may share a complementary bit line / BL. For example, two bit lines BL extending in parallel may be formed on both sides of a complementary bit line / BL. The first cell element D1 and the third cell element D3 may be defined between one of the two bit lines BL and the complementary bit line / BL, and the second cell element D2 and the fourth cell element D4 may be defined between the other of the two bit lines BL and the complementary bit line / BL.

[0144] In some embodiments, the first cell element D1 and the second cell element D2 may share one word line WL, and the third cell element D3 and the fourth cell element D4 may share another word line WL.

[0145] Reference Figures 15 to 17 In the semiconductor device according to some embodiments, each of the first to fourth unit elements D1 to D4 may include a lower region I, an upper region II, and a wiring region III. Fig.16 The first unit element D1 to the fourth unit element D4 are the same as those mentioned above. Figures 2 to 6 The same as described above, so their detailed description will be omitted. Fig.17 The first unit element D1 to the fourth unit element D4 are the same as those mentioned above. Fig.13 and Fig.14 The descriptions are the same, so their detailed descriptions will be omitted.

[0146] In some embodiments, the first to fourth unit elements D1 to D4 may share the first wiring pattern MA1. For example, the first to fourth unit elements D1 to D4 may share one first lower contact via 181A connected to one first wiring pattern MA1. In addition, the first to fourth unit elements D1 to D4 may be symmetrically arranged based on the first lower contact via 181A.

[0147] In some embodiments, the first unit element D1 and the second unit element D2 may share the fourth wiring pattern MC1. For example, the first gate contact 191 of the first unit element D1 and the first gate contact 191 of the second unit element D2 may be connected to one fourth wiring pattern MC1 in common. Similarly, the third unit element D3 and the fourth unit element D4 may share the fourth wiring pattern MC1.

[0148] In some embodiments, the first unit element D1 and the third unit element D3 may share a third wiring pattern MB, a sixth wiring pattern MD1, and a seventh wiring pattern MD2. For example, the first unit element D1 and the third unit element D3 may share a first upper contact via 181B connected to a third wiring pattern MB. The second upper contact via 183B of the first unit element D1 and the second upper contact via 183B of the third unit element D3 may be connected to a third wiring pattern MB in common. For example, the third upper contact via 185 of the first unit element D1 and the third upper contact via 185 of the third unit element D3 may be connected to a sixth wiring pattern MD1 in common. For example, the first unit element D1 and the third unit element D3 may share a fourth upper contact via 186 connected to a seventh wiring pattern MD2. Similarly, the second unit element D2 and the fourth unit element D4 may share a third wiring pattern MB, a sixth wiring pattern MD1, and a seventh wiring pattern MD2.

[0149] Although the present disclosure has been specifically shown and described with reference to the exemplary embodiments of the present disclosure, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as defined by the appended claims. It is therefore desired that the present embodiments be considered in all respects as illustrative and not restrictive, with reference to the appended claims rather than the foregoing description to indicate the scope of the present disclosure.

Claims

1. A semiconductor device comprising a lower region and an upper region on a substrate, wherein the semiconductor device further comprises include: a first lower active pattern and a second lower active pattern extending in a first direction, extending in the lower region, and spaced apart from each other in a second direction intersecting the first direction; a first upper active pattern and a second upper active pattern extending in the first direction, extending in the upper region, and spaced apart from each other in the second direction; a first gate electrode overlapping the first lower active pattern and the first upper active pattern; a second gate electrode spaced apart from the first gate electrode in the second direction, wherein the second gate electrode overlaps at least one of the second lower active pattern and the second upper active pattern; a third gate electrode spaced apart from the first gate electrode in the first direction, wherein the third gate electrode overlaps at least one of the first lower active pattern and the first upper active pattern; a fourth gate electrode spaced apart from the third gate electrode in the second direction, wherein the fourth gate electrode overlaps the second lower active pattern and the second upper active pattern; a first lower source / drain contact electrically connected to the first lower active pattern and between the first gate electrode and the third gate electrode; a first upper source / drain contact electrically connected to the second upper active pattern and between the second gate electrode and the fourth gate electrode; a lower shared contact in the lower region, wherein the lower shared contact is electrically connected to the first lower source / drain contact and the fourth gate electrode; and An upper shared contact in the upper region, wherein the upper shared contact is electrically connected to the first upper source / drain contact and the first gate electrode.

2. The semiconductor device according to claim 1, in, The lower shared contact extends from a side surface of the first lower source / drain contact and is electrically connected to a side surface of the fourth gate electrode.

3. The semiconductor device according to claim 2, in, The lower shared contact extends in the first direction.

4. The semiconductor device according to claim 1, in, The upper shared contact is on an upper surface of the first upper source / drain contact and an upper surface of the first gate electrode.

5. The semiconductor device according to claim 4, in, The lower shared contact extends in the first direction.

6. The semiconductor device according to claim 1, further comprising: include: The cutting pattern extends in the first direction, separates the first gate electrode from the second gate electrode, and separates the third gate electrode from the fourth gate electrode.

7. The semiconductor device according to claim 6, in, The length of the first gate electrode in the second direction is the same as the length of the third gate electrode in the second direction, and A length of the second gate electrode in the second direction is the same as a length of the fourth gate electrode in the second direction.

8. The semiconductor device according to claim 1, further comprising: include: a second upper source / drain contact electrically connected to the first upper active pattern and between the first gate electrode and the third gate electrode; as well as a second lower source / drain contact electrically connected to the second lower active pattern and between the second gate electrode and the fourth gate electrode, wherein the first lower source / drain contact is electrically connected to the second upper source / drain contact, and The first upper source / drain contact is electrically connected to the second lower source / drain contact.

9. A semiconductor device comprising a lower region and an upper region on a substrate, wherein the semiconductor device further comprises include: a first lower active pattern and a second lower active pattern extending in a first direction, extending in the lower region, and spaced apart from each other in a second direction intersecting the first direction; a first upper active pattern and a second upper active pattern extending in the first direction, extending in the upper region, and spaced apart from each other in the second direction; a first gate electrode overlapping the first lower active pattern and the first upper active pattern; a second gate electrode overlapping the second lower active pattern and the second upper active pattern, wherein the second gate electrode does not overlap the first gate electrode in the second direction; a first lower source / drain contact electrically connected to the first lower active pattern and between the first gate electrode and the second gate electrode; a first upper source / drain contact electrically connected to the first upper active pattern and on the first lower source / drain contact; a second lower source / drain contact spaced apart from the first lower source / drain contact in the second direction and electrically connected to the second lower active pattern; a second upper source / drain contact spaced apart from the first upper source / drain contact in the second direction and electrically connected to the second upper active pattern; a lower shared contact in the lower region, wherein the lower shared contact is electrically connected to the first lower source / drain contact and the second gate electrode; and An upper shared contact in the upper region, wherein the upper shared contact is electrically connected to the second upper source / drain contact and the first gate electrode.

10. The semiconductor device according to claim 9, in, The first lower source / drain contact is electrically connected to the first upper source / drain contact, and The second lower source / drain contact is electrically connected to the second upper source / drain contact.

11. The semiconductor device according to claim 9, in, A length of the first lower source / drain contact in the second direction is greater than a length of the second lower source / drain contact in the second direction.

12. The semiconductor device according to claim 9, in, A length of the second upper source / drain contact in the second direction is greater than a length of the first upper source / drain contact in the second direction.

13. The semiconductor device according to claim 9, further comprising: include: a third lower source / drain contact, wherein the first gate electrode is between the first lower source / drain contact and the third lower source / drain contact, and wherein the third lower source / drain contact is electrically connected to the first lower active pattern; and a third upper source / drain contact on the third lower source / drain contact and electrically connected to the first upper active pattern, wherein the third lower source / drain contact is configured to receive a first signal including a first voltage, and The third upper source / drain contact is configured to receive a second signal including a second voltage.

14. The semiconductor device according to claim 13, further comprising: include: a fourth lower source / drain contact, wherein the second gate electrode is between the second lower source / drain contact and the fourth lower source / drain contact, and wherein the fourth lower source / drain contact is electrically connected to the second lower active pattern; and a fourth upper source / drain contact on the fourth lower source / drain contact and electrically connected to the second upper active pattern, wherein the fourth lower source / drain contact is configured to receive the first signal, and The fourth upper source / drain contact is configured to receive the second signal.

15. A semiconductor device, include: substrate; a first active pattern, comprising a first lower active pattern and a first upper active pattern, the first lower active pattern and the first upper active pattern being on the substrate, spaced apart from each other, and extending in a first direction; a second active pattern, comprising a second lower active pattern and a second upper active pattern, the second lower active pattern and the second upper active pattern being on the substrate, spaced apart from each other, and extending in the first direction, wherein the second active pattern is spaced apart from the first active pattern in a second direction intersecting the first direction; a cutting pattern extending in the first direction and between the first active pattern and the second active pattern; a first gate structure extending in the second direction, the first gate structure comprising a first gate electrode overlapping the first active pattern and a second gate electrode overlapping the second active pattern, wherein the first gate electrode and the second gate electrode are separated by the cutting pattern; a second gate structure spaced apart from the first gate structure and extending in the second direction, the second gate structure comprising a third gate electrode overlapping the first active pattern and a fourth gate electrode overlapping the second active pattern, wherein the third gate electrode and the fourth gate electrode are separated by the cutting pattern; a first lower source / drain contact electrically connected to the first lower active pattern and between the first gate electrode and the third gate electrode; a first upper source / drain contact electrically connected to the first lower source / drain contact and the first upper active pattern and on the first lower source / drain contact; a second lower source / drain contact electrically connected to the second lower active pattern and between the second gate electrode and the fourth gate electrode; a second upper source / drain contact electrically connected to the second lower source / drain contact and the second upper active pattern and on the second lower source / drain contact; a lower shared contact extending in the first direction and electrically connected to the first lower source / drain contact and the fourth gate electrode; and An upper shared contact extends in the first direction and is electrically connected to the second upper source / drain contact and the first gate electrode.

16. The semiconductor device according to claim 15, in, A first distance between an upper surface of the lower shared contact and an upper surface of the substrate is smaller than a second distance between a lower surface of the second upper source / drain contact and the upper surface of the substrate.

17. The semiconductor device according to claim 15, in, A first distance between a lower surface of the upper shared contact and an upper surface of the substrate is greater than a second distance between an upper surface of the first lower source / drain contact and the upper surface of the substrate.

18. The semiconductor device according to claim 15, in, At least a portion of the lower shared contact overlaps the cutting pattern in a third direction intersecting the upper surface of the substrate.

19. The semiconductor device according to claim 15, in, The upper shared contact portion does not overlap the cutting pattern in a third direction intersecting the upper surface of the substrate.

20. The semiconductor device according to claim 15, further comprising: include: a third lower source / drain contact, wherein the first gate electrode is between the first lower source / drain contact and the third lower source / drain contact, and wherein the third lower source / drain contact is electrically connected to the first lower active pattern; a third upper source / drain contact electrically connected to the first upper active pattern and on the third lower source / drain contact; a fourth lower source / drain contact, wherein the fourth gate electrode is between the second lower source / drain contact and the fourth lower source / drain contact, and wherein the fourth lower source / drain contact is electrically connected to the second lower active pattern; and a fourth upper source / drain contact electrically connected to the second upper active pattern and on the fourth lower source / drain contact, wherein the third lower source / drain contact and the fourth lower source / drain contact are configured to receive a first signal including a first voltage, and The third upper source / drain contact and the fourth upper source / drain contact are configured to receive a second signal including a second voltage.

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