Preparation method of selective boron-doped P + emitter by low-temperature process and battery

Abstract

The invention discloses a preparation method of a selective boron-doped P + emitter based on a low-temperature process and a battery. The preparation method comprises the following steps: (1) texturing two surfaces of a silicon substrate; (2) introducing a boron source into the surface of the silicon substrate, and simultaneously introducing water vapor to perform low-temperature BSG deposition; (3) carrying out laser boron doping on the front surface of the silicon substrate to form a selective boron-doped P + emitter; (4) carrying out oxidation treatment on the surface of the silicon substrate to obtain a silicon oxide layer; and (5) removing the BSG on the back surface of the silicon substrate, polishing the back surface, removing the low-concentration boron-doped region on the back surface, and then removing the BSG and the silicon oxide layer on the front surface to obtain the front-surface selective boron-doped P + emitter. Boron diffusion is realized through a low-temperature process, then doping is performed in cooperation with laser to form the selective P + emitter, bending and damage of the silicon wafer are avoided through low-temperature boron diffusion, limitation on thickness selection of the silicon wafer is reduced, the prepared P + emitter is the front-side selective boron-doped P + emitter, the surface recombination rate is low, and the battery efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of crystalline silicon solar cells, and in particular to a method for preparing a selectively boron-doped P+ emitter using a low-temperature process and a battery. Background Art

[0002] Photovoltaic power generation, as an important component of new energy, will play a pivotal role. Crystalline silicon cells are the most stable and reliable solar cells that have been verified by time. From polycrystalline to monocrystalline, from traditional aluminum back field cells to P-type PERC cells, and the currently promoted N-type TOPCon cells (tunneling oxide passivation contact), all are driven by conversion efficiency and cost per kilowatt-hour.

[0003] N-type TOPCon cells (tunnel oxide passivation contact) are about to become the mainstream of the market because their efficiency and cost per kilowatt-hour are better than those of traditional P-type PERC cell technology. The future path for continuous cost reduction of N-type TOPCon is very clear, which is to further improve the conversion efficiency of cells and reduce the thickness of the N-type silicon wafers used, but these two major problems are restricted by the currently used high-temperature boron diffusion process.

[0004] On the one hand, the current high-temperature boron diffusion process has a diffusion temperature of more than 1000 degrees Celsius and a diffusion time of up to 180 minutes. Silicon wafers will bend and twist in such a long high-temperature environment, resulting in an increase in the breakage rate of silicon wafers and a decrease in yield. To avoid this problem, silicon wafers with a thickness of more than 140um need to be selected, and the reduction in silicon wafer thickness is further restricted. On the other hand, the current high-temperature boron diffusion process forms a full-surface P+ emitter. The recombination rate of the passivated P+ emitter surface is 15 to 40fA, which is difficult to reduce to 15fA / cm 2 Therefore, the entire P+ emitter will further restrict the improvement of N-type TOPCon cell efficiency.

[0005] In view of this, this application is hereby filed. Summary of the invention

[0006] The problem in the prior art is that the high-temperature boron diffusion process in the preparation of N-type TOPCon batteries restricts the further thinning of the silicon wafer thickness, and the surface recombination rate is high after the entire surface of the P+ emitter is passivated, which restricts the improvement of the battery efficiency. In order to solve the above problems, the present invention provides a method for preparing a selective boron-doped P+ emitter by a low-temperature process and a battery. Boron diffusion is achieved by a low-temperature process and then laser doping is performed to form a selective P+ emitter. The low-temperature boron diffusion avoids bending and breakage of the silicon wafer, thereby reducing the restrictions on the selection of silicon wafer thickness. At the same time, the P+ emitter is a front selectively boron-doped P+ emitter with a low surface recombination rate, which can improve the efficiency of the battery.

[0007] The present invention is achieved through the following technical solutions:

[0008] In a first aspect, the present invention provides a method for preparing a selective boron-doped P+ emitter using a low temperature process, comprising the following steps:

[0009] (1) Double-sided texturing of silicon substrate;

[0010] (2) introducing a boron source and water vapor into the surface of the silicon substrate to deposit BSG at low temperature;

[0011] (3) laser boron doping is used on the front side of the silicon substrate where BSG is deposited to form a selectively boron-doped P+ emitter;

[0012] (4) oxidizing the surface of the silicon substrate treated in step (3) to obtain a silicon oxide layer;

[0013] (5) A single-sided HF etching process is used to remove the BSG on the back side of the silicon substrate, and an alkaline solution is used to polish the back side of the silicon substrate to remove the low-concentration boron-doped area on the back side. HF is then used to remove the BSG and silicon oxide layer on the front side to obtain a front selectively boron-doped P+ emitter.

[0014] In a specific embodiment, in step (2), water vapor and boron source are both carried in by nitrogen, the temperature of depositing BSG is 800-950°C, the time is 50-200 min, and the thickness of deposited BSG is 50-100 nm.

[0015] In a specific embodiment, in step (2), the boron source is boron tribromide or boron trichloride.

[0016] In a specific embodiment, the laser boron doping in step (3) uses a nanosecond or picosecond laser with a wavelength of 532nm and a power of 50 to 125W.

[0017] In a specific embodiment, the thickness of the silicon oxide layer in step (4) is 5 to 10 nm.

[0018] In a specific embodiment, the alkaline solution in step (5) is NaOH and a polishing additive; the polishing additive includes 0.2-2.5% surfactant, 1.0%-5.0% oxidant, and the rest is deionized water, and the mass ratio of the polishing additive to the alkaline solution is 0.5-3.0:100.

[0019] In a second aspect, the present invention provides a method for preparing an N-type passivated contact solar cell with a selective boron-doped P+ emitter based on a low temperature process, comprising steps (1) to (5) of the selective boron-doped P+ emitter preparation method, and further comprising the following steps:

[0020] (6) preparing a tunneling oxide layer on the back of the silicon substrate, and preparing an intrinsic amorphous silicon layer or a phosphorus-doped amorphous silicon layer on the tunneling oxide layer, wherein the thickness of the amorphous silicon layer is 50 to 200 nm;

[0021] (7) performing phosphorus doping or annealing on the intrinsic amorphous silicon layer;

[0022] (8) Chemical cleaning to remove the amorphous silicon layer on the front side of the silicon substrate and the PSG generated by phosphorus diffusion;

[0023] (9) depositing an aluminum oxide layer on the front side of the silicon substrate, and then using a PECVD device to deposit a SiNx layer on the front side and the back side respectively;

[0024] (10) Printing and sintering: The silver fine grid lines and silver main grid lines on the back and the silver aluminum paste fine grid lines and silver main grid lines on the front are printed by screen printing, and then the sintering process is performed to complete the production of the battery cell.

[0025] In a specific embodiment, in step (10), the position of the silver-aluminum paste fine grid lines screen-printed on the front side of the silicon substrate overlaps with the selectively boron-doped P+ emitter region, ensuring that the silver fine grid lines and the P+ region form good ohmic contact after sintering.

[0026] In a third aspect, the present invention provides a selectively boron-doped P+ emitter N-type passivated contact solar cell based on a low temperature process, which is prepared by the selectively boron-doped P+ emitter N-type passivated contact solar cell preparation method.

[0027] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0028] 1. A method for preparing a selective boron-doped P+ emitter by a low-temperature process and a battery provided in an embodiment of the present invention, wherein a low-temperature process is used to realize boron diffusion and then a laser is used for doping to form a selective P+ emitter. The low-temperature boron diffusion avoids the bending and damage of the silicon wafer, thereby reducing the restriction on the selection of the thickness of the silicon wafer. At the same time, the P+ emitter is a front selective boron-doped P+ emitter, and the surface recombination rate is low, which can improve the efficiency of the battery;

[0029] 2. The embodiments of the present invention provide a method for preparing a selective boron-doped P+ emitter using a low-temperature process and a battery. The selective P+ emitter formed by high-power laser burning has a lower surface recombination rate, which significantly improves the open circuit voltage and short-circuit current of the battery cell. The formed front selective boron-doped P+ emitter has a lower surface recombination rate after passivation than the whole-surface P+ emitter, thereby improving the efficiency of the N-type TOPCon battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 A schematic diagram of step (1) in the battery preparation process provided by an embodiment of the present invention;

[0032] Figure 2 A schematic diagram of step (2) in the battery preparation process provided by an embodiment of the present invention;

[0033] Figure 3 A schematic diagram of step (3) in the battery preparation process provided by an embodiment of the present invention;

[0034] Figure 4 A schematic diagram of step (4) in the battery preparation process provided by an embodiment of the present invention;

[0035] Figure 5 A schematic diagram of step (5) in the battery preparation process provided by an embodiment of the present invention;

[0036] Figure 6 A schematic diagram of step (6) in the battery preparation process provided by an embodiment of the present invention;

[0037] Figure 7 A schematic diagram of step (9) in the battery preparation process provided by an embodiment of the present invention;

[0038] Figure 8 A schematic diagram of step (10) in the battery preparation process provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention.

[0040] In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present invention. However, it is apparent to one of ordinary skill in the art that these specific details need not be employed to practice the present invention. In other embodiments, in order to avoid obscuring the present invention, well-known materials or methods are not specifically described.

[0041] Throughout the specification, references to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment of the present invention. Therefore, the phrases "one embodiment," "an embodiment," "an example," or "an example" appearing in various places throughout the specification do not necessarily all refer to the same embodiment or example. In addition, particular features, structures, or characteristics may be combined in one or more embodiments or examples in any suitable combination and / or subcombination. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0042] At present, the diffusion temperature of the high-temperature boron diffusion process is above 1000 degrees Celsius, and the diffusion time is as long as 180 minutes. The silicon wafer will bend and twist in such a long time in a high-temperature environment, resulting in an increase in the breakage rate of the silicon wafer and a decrease in the yield. To avoid this problem, the thickness of the silicon wafer needs to be more than 140um, and the reduction of the silicon wafer thickness is further restricted. In addition, the high-temperature boron diffusion process forms a full-surface P+ emitter. The recombination rate of the passivated P+ emitter surface is 15 to 40fA, which is difficult to reduce to 15fA / cm 2 Therefore, the entire P+ emitter will further restrict the improvement of N-type TOPCon cell efficiency.

[0043] In order to solve the above problems, the present invention provides the following technical solutions:

[0044] In a first aspect, the present invention provides a method for preparing a selective boron-doped P+ emitter using a low temperature process, comprising the following steps:

[0045] Step S01, selecting an N-type silicon substrate as a substrate for double-sided texturing;

[0046] Step S02, using boron tribromide or boron trichloride as a boron source on the surface of the N-type silicon substrate after the texturing treatment in step S01, and introducing water vapor to perform low-temperature deposition of BSG (boron-doped silicon dioxide);

[0047] Step S03, after the texturing treatment in step S01 and the BSG deposition in step S02, the front surface of the N-type silicon substrate is laser doped using a high-power nanosecond or picosecond laser to form a selective P+ emitter;

[0048] Step S04, performing oxidation treatment on the N-type silicon substrate after step S03, to obtain a silicon oxide layer;

[0049] In step S05, the N-type silicon substrate after step S04 is subjected to a single-sided HF etching process to remove the BSG on the back side of the N-type silicon wafer, and an alkaline solution is used to perform back polishing treatment to remove the low-concentration boron-doped area on the back side, and then HF is used to remove the BSG and silicon oxide layer on the front side, thereby forming a front selectively boron-doped P+ emitter.

[0050] In a specific embodiment, in step S02, water vapor and boron source are both carried in by nitrogen, the temperature of depositing BSG is 800-950°C, the time is 50-200 min, and the thickness of deposited BSG is 50-100 nm.

[0051] In a specific embodiment, the laser boron doping in step (3) uses a nanosecond or picosecond laser with a wavelength of 532nm, a power of 50-125W, and a spot shape of a circle or rectangle.

[0052] In a specific embodiment, the oxidation treatment in step (4) is performed at a temperature of 600 to 750° C. in an oxidation furnace, or a chain oxidation device is used for oxidation treatment. The purpose is to form a layer of silicon oxide on the surface of the front laser doped area to protect it from being affected during the alkali polishing process. The thickness of the oxide layer is 5 to 10 nm.

[0053] In a specific embodiment, the alkaline solution in step (5) is NaOH and a polishing additive; the polishing additive includes 0.2-2.5% surfactant, 1.0%-5.0% oxidant, and the rest is deionized water, and the mass ratio of the polishing additive to the alkaline solution is 0.5-3.0:100.

[0054] In a second aspect, the present invention provides a method for preparing an N-type passivated contact solar cell with a selective boron-doped P+ emitter based on a low temperature process, comprising steps (1) to (5) of the selective boron-doped P+ emitter preparation method, and further comprising the following steps:

[0055] (6) preparing a tunneling oxide layer on the back of the silicon substrate, and preparing an intrinsic amorphous silicon layer or a phosphorus-doped amorphous silicon layer on the tunneling oxide layer, wherein the thickness of the amorphous silicon layer is 50 to 200 nm;

[0056] (7) performing phosphorus doping or annealing on the intrinsic amorphous silicon layer;

[0057] (8) Chemical cleaning to remove the amorphous silicon layer on the front side of the silicon substrate and the PSG generated by phosphorus diffusion;

[0058] (9) depositing an aluminum oxide layer on the front side of the silicon substrate, and then using a PECVD device to deposit a SiNx layer on the front side and the back side respectively;

[0059] (10) Printing and sintering: The silver fine grid lines and silver main grid lines on the back and the silver aluminum paste fine grid lines and silver main grid lines on the front are printed by screen printing, and then the sintering process is performed to complete the production of the battery cell.

[0060] In a specific embodiment, in step (10), the position of the silver-aluminum paste fine grid lines screen-printed on the front side of the silicon substrate overlaps with the selectively boron-doped P+ emitter region, ensuring that the silver fine grid lines and the P+ region form good ohmic contact after sintering.

[0061] In a third aspect, the present invention provides a selectively boron-doped P+ emitter N-type passivated contact solar cell based on a low temperature process, which is prepared by the selectively boron-doped P+ emitter N-type passivated contact solar cell preparation method.

[0062] Example 1

[0063] like Figure 1 to Figure 7 As shown, an embodiment of the present invention provides a method for preparing a selective boron-doped P+ emitter in a relatively low temperature process and an N-type passivated contact cell based on the method, comprising the following steps:

[0064] (1) Select an N-type silicon substrate as the substrate for double-sided texturing. The silicon wafer size is preferably an M10 size N-type silicon wafer with a thickness of 150 um. The front surface of the N-type crystalline silicon wafer is texturized. After texturing, Figure 1 As shown;

[0065] (2) Place the N-type silicon wafer after texturing in a diffusion furnace, use boron tribromide or boron trichloride as the boron source, and introduce water vapor to deposit BSG (boron-doped silicon dioxide) at a low temperature of 800-950°C for 50-200 minutes. The thickness of the deposited BSG is 50-100 nm. Figure 2 As shown;

[0066] (3) The front surface of the N-type silicon wafer is laser doped with a high-power nanosecond or picosecond laser to form a selective P+ emitter. The laser boron doping uses a nanosecond or picosecond laser with a wavelength of 532nm, a power of 50 to 125W, and a circular or rectangular spot shape, such as Figure 3 As shown;

[0067] (4) The N-type silicon wafer is oxidized in a chain device. The purpose of chain oxidation is to form a layer of silicon oxide on the surface of the front laser doped area to protect it from being affected during the alkaline polishing process. The thickness is about 5 to 10 nm. Figure 4 As shown;

[0068] (5) Use a single-sided HF etching process to remove the BSG on the back of the N-type silicon wafer, and use an alkaline solution to polish the back to remove the low-concentration boron-doped area on the back. Then use HF to remove the BSG and silicon oxide layer on the front to form a P+ emitter with selective boron doping on the front. Figure 5 As shown, the alkaline solution in S05 is NAOH and a polishing additive, the composition of the polishing additive is 0.2% to 2.5% of a surfactant, 1.0% to 5.0% of an oxidant, and the rest is deionized water, and the mass ratio of the polishing additive to the alkaline solution is 0.5 to 3.0:100;

[0069] (6) An ultra-thin tunnel oxide layer is prepared on the back of the N-type silicon wafer by high temperature oxidation, and an intrinsic amorphous silicon layer is prepared on the tunnel oxide layer by LPCVD process on the back surface of the N-type silicon substrate. The thickness of the intrinsic amorphous silicon layer is 50 to 200 nm. Figure 6 As shown;

[0070] (7) subjecting the intrinsic amorphous silicon layer of the N-type silicon wafer to a high-temperature phosphorus diffusion doping treatment, wherein the diffusion temperature is preferably 800-900° C. and the diffusion process time is about 90 minutes;

[0071] (8) Chemical cleaning is used to remove the amorphous silicon layer on the front side of the N-type silicon wafer and the PSG layer generated by phosphorus diffusion;

[0072] (9) ALD is used to deposit a 2-5 nm aluminum oxide layer on the front side of the N-type silicon wafer, and then PECVD is used to deposit SiNx layers on the front and back sides respectively. The thickness of the SiNx layer on the front side is 60-80 nm, and the thickness of the SiNx layer on the back side is 50-70 nm. Figure 7 As shown;

[0073] (10) Printing and sintering: The silver fine grid lines & silver main grid lines on the back and the silver aluminum paste fine grid lines & silver main grid lines on the front are printed by screen printing. The position of the silver aluminum paste fine grid lines printed on the front of the N-type silicon wafer must coincide with the laser-doped P+ emitter area to ensure that the silver fine grid lines and the P+ area form good ohmic contact after sintering. Then, the sintering process is performed to complete the production of the battery cell. Figure 8 shown.

[0074] The re-sintered cells were tested, and the test electrical performance results are shown in Table 1 below.

[0075] Example 2

[0076] like Figure 1 to Figure 7 As shown, the embodiment of the present invention provides a method for preparing a selective boron-doped P+ emitter in a relatively low temperature process and an N-type passivated contact cell based on the method, comprising the following steps:

[0077] (1) Select an N-type silicon substrate as the substrate for double-sided texturing. The silicon wafer size is preferably an M10 size N-type silicon wafer with a thickness of 150 um. The front surface of the N-type crystalline silicon wafer is texturized. After texturing, Figure 1 As shown;

[0078] (2) Place the N-type silicon wafer after texturing in a diffusion furnace, use boron tribromide or boron trichloride as the boron source, and introduce water vapor to deposit BSG (boron-doped silicon dioxide) at a low temperature. The deposition temperature is 800-950°C, the time is 50-200 minutes, and the thickness of the deposited BSG is 50-100nm. Figure 2 As shown;

[0079] (3) The front surface of the N-type silicon wafer is laser doped with a high-power nanosecond or picosecond laser to form a selective P+ emitter. The laser boron doping uses a nanosecond or picosecond laser with a wavelength of 532nm, a power of 50-125W, and a circular or rectangular spot shape, such as Figure 3 As shown;

[0080] (4) Oxidation treatment of N-type silicon wafers in a diffusion furnace at a temperature of 700-750°C for 30-90 minutes is performed to form a layer of silicon oxide on the surface of the front laser doped area to protect it from being affected during the alkaline polishing process. The thickness is about 5-10 nm. Figure 4 As shown;

[0081] (5) Use a single-sided HF etching process to remove the BSG on the back of the N-type silicon wafer, and use an alkaline solution to polish the back to remove the low-concentration boron-doped area on the back. Then use HF to remove the BSG and silicon oxide layer on the front to form a P+ emitter with selective boron doping on the front. Figure 5 As shown, the alkaline solution in S05 is NAOH and a polishing additive, the composition of the polishing additive is 0.2% to 2.5% of a surfactant, 1.0% to 5.0% of an oxidant, and the rest is deionized water, and the mass ratio of the polishing additive to the alkaline solution is 0.5 to 3.0:100;

[0082] (6) An ultra-thin tunnel oxide layer is prepared on the back of the N-type silicon wafer using a PECVD device. The thickness of the oxide layer is 1 to 2 nm. At the same time, a phosphorus-doped amorphous silicon layer is prepared on the back surface of the N-type silicon substrate using a PECVD process on the tunnel oxide layer. The thickness of the crystalline silicon layer is 50 to 200 nm. Figure 6 As shown;

[0083] (7) subjecting the intrinsic amorphous silicon layer of the N-type silicon wafer to a high temperature annealing treatment, wherein the annealing temperature is preferably 800-900° C., and the annealing process duration is about 90 minutes. The purpose of the annealing is to convert the doped amorphous silicon layer into a polycrystalline silicon layer;

[0084] (8) chemical cleaning is used to remove the amorphous silicon layer on the front side of the N-type silicon wafer and the PSG layer generated by annealing;

[0085] (9) ALD is used to deposit a 2-5 nm aluminum oxide layer on the front side of the N-type silicon wafer, and then PECVD is used to deposit SiNx layers on the front and back sides respectively. The thickness of the SiNx layer on the front side is 60-80 nm, and the thickness of the SiNx layer on the back side is 50-70 nm. Figure 7 As shown;

[0086] (10) Printing and sintering: The silver fine grid lines & silver main grid lines on the back and the silver aluminum paste fine grid lines & silver main grid lines on the front are printed by screen printing. The position of the silver aluminum paste fine grid lines printed on the front of the N-type silicon wafer must coincide with the laser-doped P+ emitter area to ensure that the silver fine grid lines and the P+ area form good ohmic contact after sintering. Then, the sintering process is performed to complete the production of the battery cell. Figure 8 shown.

[0087] Comparative Example 1

[0088] This comparative example provides a conventional boron-doped P+ emitter preparation method for an N-type passivated contact cell and the steps of preparing the cell based on the conventional method are as follows:

[0089] (1) Selecting an N-type silicon substrate as a substrate for double-sided texturing treatment, with a thickness of 130 to 150 μm, and using the front surface of the N-type crystalline silicon wafer for texturing treatment;

[0090] (2) Load the N-type silicon wafer after texturing into a low-pressure diffusion furnace, and use nitrogen to carry the boron tribromide source or boron trichloride gas directly into the high-temperature diffusion furnace tube, and introduce oxygen at the same time; the deposition pressure needs to be maintained at <300mtor, the deposition temperature is 840-950°C, the time is 30-120min, and the thickness of the deposited BSG is 30-50nm;

[0091] (3) The front surface of the N-type silicon wafer is laser doped with a long-wavelength nanosecond or picosecond laser to form a selective P+ emitter. The laser boron doping uses a nanosecond or picosecond laser with a wavelength of 1064nm, a power of 50-100W, and a circular or rectangular spot shape;

[0092] (4) The N-type silicon wafer obtained in (2) is oxidized in a diffusion furnace at a temperature of 950 to 1050° C. for 30 to 90 minutes to form a layer of silicon oxide on the surface of the front boron-doped region to protect it from being affected during the alkaline polishing process. The thickness of the layer is about 20 to 50 nm.

[0093] (5) Using a single-sided HF etching process to remove the BSG on the back of the N-type silicon wafer, and using an alkaline solution to polish the back to remove the low-concentration boron-doped area on the back, and then using HF to remove the BSG and silicon oxide layer on the front to form a boron-doped P+ emitter on the front, wherein the alkaline solution is NAOH and a polishing additive, the polishing additive comprises 0.2% to 2.5% of a surfactant, 1.0% to 5.0% of an oxidant, and the rest is deionized water, and the mass ratio of the polishing additive to the alkaline solution is 0.5 to 3.0:100;

[0094] (6) A layer of ultra-thin tunnel oxide layer is prepared on the back of the N-type silicon wafer by using PECVD equipment, and the thickness of the oxide layer is 1 to 2 nm. At the same time, a phosphorus-doped amorphous silicon layer is prepared on the back surface of the N-type silicon substrate by using PECVD process on the tunnel oxide layer, and the thickness of the crystalline silicon layer is 50 to 200 nm;

[0095] (7) subjecting the N-type silicon wafer intrinsic amorphous silicon layer obtained in (6) to a high temperature annealing treatment, wherein the annealing temperature is preferably 800-900° C., and the annealing process duration is about 90 minutes. The purpose of the annealing is to transform the doped amorphous silicon layer into a polycrystalline silicon layer and to activate the phosphorus doping source at the same time;

[0096] (8) chemical cleaning is used to remove the amorphous silicon layer on the front side of the N-type silicon wafer and the PSG layer generated by annealing;

[0097] (9) ALD is used to deposit a 2-5 nm aluminum oxide layer on the front side of the N-type silicon wafer, and then PECVD is used to deposit a SiNx layer on the front side and the back side, respectively. The thickness of the SiNx layer on the front side is 60-80 nm, and the thickness of the SiNx layer on the back side is 50-70 nm.

[0098] (10) Printing and sintering: The silver fine grid lines and silver main grid lines on the back and the silver aluminum paste fine grid lines and silver main grid lines on the front are printed by screen printing. The position of the silver aluminum paste fine grid lines screen-printed on the front of the N-type silicon wafer must coincide with the laser-doped P+ emitter area to ensure that the silver fine grid lines and the P+ area form good ohmic contact after sintering. Then the sintering process is performed to complete the production of the battery cell.

[0099] Comparative Example 2

[0100] This comparative example provides a conventional boron-doped P+ emitter preparation method for an N-type passivated contact cell and the steps of preparing the cell based on the conventional method are as follows:

[0101] (1) Selecting an N-type silicon substrate as a substrate for double-sided texturing treatment, with a thickness of 130 to 150 μm, and using the front surface of the N-type crystalline silicon wafer for texturing treatment;

[0102] (2) Load the N-type silicon wafer after texturing into a low-pressure diffusion furnace, and use nitrogen to carry the boron tribromide source or boron trichloride gas directly into the high-temperature diffusion furnace tube, and introduce oxygen at the same time; the deposition pressure needs to be maintained at <300mtor, the deposition temperature is 840-950°C, the time is 30-120min, and the thickness of the deposited BSG is 30-50nm;

[0103] (3) The N-type silicon wafer obtained in (2) is oxidized in a diffusion furnace at a temperature of 950 to 1050° C. for 30 to 90 minutes. The purpose is to form a layer of silicon oxide on the surface of the front boron-doped region to protect it from being affected during the alkaline polishing process. The thickness is about 20 to 50 nm.

[0104] (4) Using a single-sided HF etching process to remove the BSG on the back of the N-type silicon wafer, and using an alkaline solution to polish the back to remove the low-concentration boron-doped area on the back, and then using HF to remove the BSG and silicon oxide layer on the front to form a boron-doped P+ emitter on the front, wherein the alkaline solution is NAOH and a polishing additive, the polishing additive comprises 0.2% to 2.5% of a surfactant, 1.0% to 5.0% of an oxidant, and the rest is deionized water, and the mass ratio of the polishing additive to the alkaline solution is 0.5 to 3.0:100;

[0105] (5) A layer of ultra-thin tunnel oxide layer is prepared on the back of the N-type silicon wafer by using PECVD equipment, and the thickness of the oxide layer is 1 to 2 nm. At the same time, a phosphorus-doped amorphous silicon layer is prepared on the back surface of the N-type silicon substrate by using PECVD process on the tunnel oxide layer, and the thickness of the crystalline silicon layer is 50 to 200 nm;

[0106] (6) subjecting the N-type silicon wafer intrinsic amorphous silicon layer obtained in (5) to a high temperature annealing treatment, wherein the annealing temperature is preferably 800-900° C., and the annealing process duration is about 90 minutes. The purpose of the annealing is to transform the doped amorphous silicon layer into a polycrystalline silicon layer and to activate the phosphorus doping source at the same time;

[0107] (7) chemical cleaning is used to remove the amorphous silicon layer on the front side of the N-type silicon wafer and the PSG layer generated by annealing;

[0108] (8) ALD is used to deposit a 2-5 nm aluminum oxide layer on the front side of the N-type silicon wafer, and then PECVD is used to deposit a SiNx layer on the front side and the back side, respectively. The thickness of the SiNx layer on the front side is 60-80 nm, and the thickness of the SiNx layer on the back side is 50-70 nm.

[0109] (9) Printing and sintering: The silver fine grid lines and silver main grid lines on the back and the silver aluminum paste fine grid lines and silver main grid lines on the front are printed by screen printing, and then the sintering process is performed to complete the production of the battery cell.

[0110] The battery cells prepared in Examples 1-2 and Comparative Examples 1-2 were subjected to corresponding electrical performance tests, and the test results are shown in Table 1 below (the following data are based on the normalized data of Comparative Example 1 as the reference group, and the other groups are all relative values).

[0111] Table 1

[0112] Serial number Battery efficiency (%) Open circuit voltage(mV) <![CDATA[Current (mA / cm 2 )]]> Fill factor (%) Comparative Example 1 1 1 1 1 Comparative Example 2 -0.25 +4.7 +0.18 -0.04 Example 1 +0.03 +2.2 -0.13 +0.1 Example 2 -0.04 +1.6 -0.07 +0.06

[0113] It can be seen from the above data that the embodiment of the present invention can obtain the same battery conversion efficiency as that of comparative example 1, but the thermal budget required for the boron doping step in embodiments 1 and 2 is significantly smaller than that of the comparative example; at the same time, boron diffusion is achieved through a low-temperature process and then laser doping is performed to form a selective P+ emitter. Low-temperature boron diffusion avoids bending and breakage of the silicon wafer, reduces restrictions on the selection of silicon wafer thickness, and at the same time, the P+ emitter obtained is a front-side selectively boron-doped P+ emitter with a low surface recombination rate, which can improve the efficiency of the battery.

[0114] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a selective boron-doped P+ emitter using a low temperature process, characterized in that: The steps include: (1) Double-sided texturing of silicon substrate; (2) introducing a boron source and water vapor into the surface of the silicon substrate to deposit BSG at low temperature; (3) Laser boron doping is used on the front side of the silicon substrate where BSG is deposited to form a selectively boron-doped P+ emitter.

2. The method for preparing a P+ emitter by selective boron doping using a low temperature process according to claim 1, characterized in that: In step (2), water vapor and boron source are both carried in by nitrogen gas, the temperature of depositing BSG is 800-950°C, the time is 50-200 min, and the thickness of deposited BSG is 50-100 nm.

3. The method for preparing a P+ emitter by selective boron doping using a low temperature process according to claim 1, characterized in that: In step (2), the boron source is boron tribromide or boron trichloride.

4. The method for preparing a P+ emitter by selective boron doping using a low temperature process according to claim 1, characterized in that: In step (3), the laser boron doping adopts nanosecond or picosecond laser with a wavelength of 532nm and a power of 50 to 125W.

5. The method for preparing a P+ emitter by selective boron doping using a low temperature process according to claim 1, characterized in that: Also includes: Step (4), oxidizing the surface of the silicon substrate treated in step (3) to obtain a silicon oxide layer; Step (5), using a single-sided HF etching process to remove the BSG on the back of the silicon substrate, using an alkaline solution to polish the back of the silicon substrate to remove the low-concentration boron-doped area on the back, and then using HF to remove the BSG and silicon oxide layer on the front to obtain a front selectively boron-doped P+ emitter.

6. The method for preparing a P+ emitter by selective boron doping using a low temperature process according to claim 5, characterized in that: In step (4), the thickness of the silicon oxide layer is 5 to 10 nm.

7. The method for preparing a P+ emitter by selective boron doping using a low temperature process according to claim 5, characterized in that: In step (5), the alkaline solution is NaOH and a polishing additive; the polishing additive includes 0.2-2.5% of a surfactant, 1.0%-5.0% of an oxidant, and the rest is deionized water, and the mass ratio of the polishing additive to the alkaline solution is 0.5-3.0:

100.

8. A method for preparing an N-type passivated contact solar cell with selective boron doping of a P+ emitter based on a low temperature process, characterized in that: The method for preparing a selective boron-doped P+ emitter according to any one of claims 1 to 7 further comprises the following steps: (6) preparing a tunneling oxide layer on the back of the silicon substrate, and preparing an intrinsic amorphous silicon layer or a phosphorus-doped amorphous silicon layer on the tunneling oxide layer, wherein the thickness of the amorphous silicon layer is 50 to 200 nm; (7) performing phosphorus doping or annealing on the intrinsic amorphous silicon layer; (8) Chemical cleaning to remove the amorphous silicon layer on the front side of the silicon substrate and the PSG generated by phosphorus diffusion; (9) depositing an aluminum oxide layer on the front side of the silicon substrate, and then using a PECVD device to deposit a SiNx layer on the front side and the back side respectively; (10) Printing and sintering: The silver fine grid lines and silver main grid lines on the back and the silver aluminum paste fine grid lines and silver main grid lines on the front are printed by screen printing, and then the sintering process is performed to complete the production of the battery cell.

9. The method for preparing a N-type passivated contact solar cell with selective boron doping of P+ emitter based on low temperature process according to claim 8, characterized in that: In step (10), the position of the silver-aluminum paste fine grid lines screen-printed on the front side of the silicon substrate overlaps with the selectively boron-doped P+ emitter region, ensuring that the silver fine grid lines and the P+ region form good ohmic contact after sintering.

10. A N-type passivated contact solar cell with selective boron doping of P+ emitter based on low temperature process, characterized in that: The method according to claim 8 or 9 is adopted to prepare the present invention.

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