Transmitting and receiving circuit and control method thereof

Abstract

A transceiver circuit and a control method thereof are disclosed. The transceiver circuit includes a receiving circuit and a digital circuit. The receiving circuit includes a first mixer, a second mixer, a bias circuit, a complex filter, and an analog-to-digital converter. In operation of the transceiver circuit, the digital circuit controls the bias circuit to sequentially switch a first bias to a plurality of first bias values, and the receiving circuit generates a plurality of first digital signals corresponding to the plurality of first bias values, respectively, and calculates a plurality of first quality parameters corresponding to the plurality of first bias values, respectively; and the digital circuit controls the bias circuit to make the first bias have a bias value corresponding to a best quality parameter, wherein the best quality parameter is determined by at least the plurality of first quality parameters.

Description

Technical Field

[0001] This invention relates to transceiver circuits and their control methods. Background Technology

[0002] Low-intermediate frequency (LIF) receivers are widely used in many electronic devices. To achieve a better image rejection ratio (IMRR), LIF receivers typically include both in-phase and quadrature channels, as well as a complex filter. Furthermore, multiple adjustable resistors are required in the complex filter for gain and phase correction and corresponding impedance matching, which increases the complexity of the resistor network and the chip area. Summary of the Invention

[0003] Therefore, one of the objectives of this invention is to provide a transceiver circuit that can maintain a good image rejection ratio even with a low-current design by adjusting the bias voltage of the mixer, so that complex resistor networks are not required in the composite filter, thereby solving the problems described in the prior art.

[0004] In one embodiment of the present invention, a transceiver circuit is disclosed, comprising a receiving circuit and a digital circuit. The receiving circuit includes a first mixer, a second mixer, a bias circuit, a composite filter, and an analog-to-digital converter. The first mixer is used to mix an input signal using a first oscillation signal to generate a first mixed signal. The second mixer is used to mix the input signal using a second oscillation signal to generate a second mixed signal. The bias circuit generates a first bias voltage to the first mixer and a second bias voltage to the second mixer. The composite filter generates a first intermediate frequency (IF) signal and a second IF signal based on the first and second mixed signals. The analog-to-digital converter performs an analog-to-digital conversion operation on an output IF signal to generate a digital signal, wherein the output IF signal is one of the first IF signal and the second IF signal. The digital circuit is coupled to the receiving circuit, wherein the digital circuit controls the bias circuit to sequentially switch the first bias to a plurality of first bias values, and the receiving circuit generates a plurality of first digital signals corresponding to the plurality of first bias values, and calculates a plurality of first quality parameters corresponding to the plurality of first bias values; and the digital circuit controls the bias circuit to make the first bias have a bias value corresponding to an optimal quality parameter, wherein the optimal quality parameter is determined at least by the plurality of first quality parameters.

[0005] In one embodiment of the present invention, a transceiver circuit control method is disclosed, wherein the transceiver circuit includes a receiving circuit and a digital circuit, and the receiving circuit includes a first mixer, a second mixer, a bias circuit, a composite filter, and an analog-to-digital converter. The first mixer is used to mix an input signal using a first oscillation signal to generate a first mixed signal. The second mixer is used to mix the input signal using a second oscillation signal to generate a second mixed signal. The bias circuit generates a first bias voltage to the first mixer and a second bias voltage to the second mixer. The composite filter generates a first intermediate frequency (IF) signal and a second IF signal based on the first and second mixed signals. The analog-to-digital converter performs an analog-to-digital conversion operation on an output IF signal to generate a digital signal, wherein the output IF signal is one of the first IF signal and the second IF signal. The control method includes the following steps: controlling the bias circuit to sequentially switch the first bias to a plurality of first bias values, so that the receiving circuit generates a plurality of first digital signals corresponding to the plurality of first bias values; calculating a plurality of first quality parameters corresponding to the plurality of first bias values ​​based on the plurality of first digital signals; and controlling the bias circuit so that the first bias has a bias value corresponding to an optimal quality parameter, wherein the optimal quality parameter is determined at least by the plurality of first quality parameters. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a transceiver circuit according to an embodiment of the present invention.

[0007] Figure 2 This is a flowchart of a control method for a transceiver circuit according to an embodiment of the present invention.

[0008] Figure 3 This is a schematic diagram of the desired signal after processing by a mixer and a composite filter.

[0009] Figure 4 This is a schematic diagram of the image signal after it has been processed by a mixer and a composite filter.

[0010] Figure 5 This is a schematic diagram of a mixer according to an embodiment of the present invention.

[0011] Figure 6 This is a schematic diagram of a bias circuit according to an embodiment of the present invention.

[0012] Figure 7 This is a schematic diagram of a transceiver circuit according to an embodiment of the present invention.

[0013] Symbol Explanation

[0014] 100: Transceiver circuit

[0015] 102: Antenna

[0016] 104: Matching Circuit

[0017] 110: Receiving circuit

[0018] 111: Low-noise amplifier

[0019] 112, 113: Mixers

[0020] 114: Composite Filter

[0021] 115: Switching Module

[0022] 116: Programmable gain amplifier

[0023] 117: Analog-to-digital converter

[0024] 118: Bias circuit

[0025] 120: Transmission circuit

[0026] 121: Power Amplifier

[0027] 122, 123: Mixers

[0028] 124, 125: Filters

[0029] 126, 127: Digital-to-Analog Converters

[0030] 130: Digital Circuits

[0031] 202~212: Steps

[0032] 500: Mixer

[0033] 600: Bias circuit

[0034] 610: Operational Amplifier

[0035] 700: Transceiver circuit

[0036] IF_I, IF_Q: Intermediate frequency signals

[0037] RXLO_I, RXLO_Q: Oscillation signals

[0038] TXLO_I, TXLO_Q: Oscillation signals

[0039] SW1, SW2: Switches

[0040] VB_I, VB_Q: Bias voltage

[0041] Vc: Control signal

[0042] Vin_I, Vin_Q: Signals after mixing

[0043] DC: Direct Current

[0044] IF: Frequency

[0045] RXLO: Frequency of RXLO_I / RXLO_Q

[0046] TXLO: Frequency of TXLO_I / TXLO_Q

[0047] C1, C2, C3: Capacitors

[0048] R1, R2, R3: Resistors

[0049] INL input signal

[0050] M1, M2: Transistors

[0051] Vin+, Vin-: Signal after mixing

[0052] N1: First endpoint

[0053] N2: Second endpoint

[0054] Vref: Reference voltage

[0055] VB1, VB2: Bias voltage

[0056] CT, control signals Detailed Implementation

[0057] Figure 1 This is a schematic diagram of a transceiver circuit 100 according to an embodiment of the present invention. Figure 1 As shown, the transceiver circuit 100 includes a receiving circuit 110, a transmitting circuit 120, and a digital circuit 130. The receiving circuit 110 includes a low-noise amplifier 111, two mixers 112 and 113, a composite filter 114, a switching module 115, a programmable gain amplifier (PGA) 116, an analog-to-digital converter 117, and a bias circuit 118. The switching module 115 includes two switches SW1 and SW2. The transmitting circuit 120 includes a power amplifier 121, two mixers 122 and 123, two filters 124 and 125, and two digital-to-analog converters 126 and 127. In this embodiment, the receiving circuit 110 and the transmitting circuit 120 are connected to an antenna 102 via a matching circuit 104 for signal reception and transmission. Furthermore, in this embodiment, the receiving circuit 110 is a low-intermediate frequency (IF) receiving circuit.

[0058] In the operation of the receiving circuit 110, the low-noise amplifier 111 receives a received signal from the antenna 102 through the matching circuit 104 and processes the received signal to generate an input signal. Next, mixer 112 uses an oscillation signal RXLO_I to mix the input signal to generate a mixed signal Vin_I, and mixer 114 uses an oscillation signal RXLO_Q to mix the input signal to generate a mixed signal Vin_Q. The oscillation signals RXLO_Q and RXLO_I have the same frequency and a 90-degree phase difference; that is, the mixed signal Vin_I corresponds to an in-phase channel, and the mixed signal Vin_Q corresponds to a quadrature channel. Then, the composite filter 114 receives the mixed signals Vin_I and Vin_Q to generate intermediate frequency (IF) signals IF_I and IF_Q, where the IF_I corresponds to the in-phase channel, and the IF_Q corresponds to the quadrature channel. Furthermore, since the operation of the composite filter 114 requires the simultaneous use of signals from both the in-phase and positive-path channels, the composite filter 114 generates an intermediate frequency (IF) signal IF_I based on the mixed signals Vin_I and Vin_Q, and generates an IF signal IF_Q based on the mixed signals Vin_I and Vin_Q. Since the composite filter 114 is well-known to those skilled in the art, its detailed circuit architecture will not be described in detail here. Next, the switching module 115 receives the IF signals IF_I and IF_Q, and selects one of them as an output IF signal based on a control signal Vc. Specifically, when the control signal Vc indicates that the IF signal IF_I should be output, the switching module 115 turns on switch SW1 and turns off switch SW2 to output the IF signal IF_I; and when the control signal Vc indicates that the IF signal IF_Q should be output, the switching module 115 turns on switch SW2 and turns off switch SW1 to output the IF signal IF_Q. Next, the programmable gain amplifier 116 amplifies the output intermediate frequency signal to generate an amplified intermediate frequency signal, and the analog-to-digital converter 117 performs an analog-to-digital conversion on the amplified intermediate frequency signal to generate a digital signal for subsequent processing by the digital circuit 130.

[0059] In the operation of the receiving circuit 110, since the switching module 115 selects only one of the intermediate frequency signals IF_I and IF_Q as the output intermediate frequency signal, the receiving circuit 110 only needs to set up a programmable gain amplifier 116 and an analog-to-digital converter 117 to process the intermediate frequency signal IF_I or the intermediate frequency signal IF_Q, instead of setting up two sets of circuits to process the intermediate frequency signals IF_I and IF_Q simultaneously as in the prior art. Therefore, the receiving circuit 110 of this embodiment can effectively reduce chip area and power consumption.

[0060] However, since the circuitry and signals in the in-phase and positive-path channels of the receiving circuit 110 are not perfectly matched—for example, the phase difference between the oscillation signals RXLO_I and RXLO_Q is not exactly 90 degrees, and the path gains are not exactly the same—the composite filter 114 will have inconsistent responses in the in-phase and positive-path channels, resulting in different signal qualities for the intermediate frequency (IF) signals IF_I and IF_Q. As described above, to enable the receiving circuit 110 to generate a better digital signal to the digital circuit 130 and to reduce the design complexity of the composite filter 114, this embodiment further proposes a method to adjust the bias voltages of mixers 112 and 113 and automatically determine which of the IF signals IF_I and IF_Q has better signal quality. The control switch module 115 selects the IF signal with better signal quality from the IF signals IF_I and IF_Q.

[0061] Figure 2 This is a flowchart of a control method for a transceiver circuit 100 according to an embodiment of the present invention. In step 200, the process begins, and the transceiver circuit 100 is powered on and starts operating. In step 202, the bias circuit 118 is controlled to sequentially generate multiple bias voltages VB_I with different values ​​to mixer 112, and to generate a bias voltage VB_Q with a preset value to mixer 113. For any of the multiple bias voltages VB_I, the digital circuit 130 determines the image rejection ratio (IMRR) (corresponding to a quality parameter) between the intermediate frequency signal IF_I of the in-phase channel and the intermediate frequency signal IF_Q of the positive-phase channel. Specifically, for any of the multiple bias voltages VB_I, refer to... Figure 1 and Figure 3 , Figure 4First, digital circuit 130 generates two digital test signals to digital-to-analog converters 126 and 127 to generate two analog signals. Next, the two analog signals are processed by filters 124 and 125 to generate a first filtered signal and a second filtered signal, respectively. Mixer 122 uses an oscillation signal TXLO_I to mix the first filtered signal to generate a first mixed signal, while mixer 123 uses an oscillation signal TXLO_Q to mix the second filtered signal to generate a second mixed signal. The oscillation signals TXLO_Q and TXLO_I have the same frequency and a 90-degree phase difference. Then, the first and second mixed signals are combined and processed by power amplifier 121 to generate a first test signal to matching circuit 104. In this embodiment, the first test signal represents a desired signal, and the frequency difference between the oscillation signals TXLO_I / TXLO_Q and TXLO_I / TXLO_Q is... Figure 3 The "IF" shown, where Figure 3 The frequencies of the oscillation signals TXLO_I / TXLO_Q are represented by "TXLO" and RXLO_I / RXLO_Q, respectively. Furthermore, the frequency of the desired signal is located within the in-band of the composite filter 114.

[0062] Next, the receiving circuit 110 receives the first test signal generated by the transmitting circuit 120 through the matching circuit 104, and processes the first test signal as a received signal. At this time, the digital circuit 130 can first generate a control signal Vc to control the switching module 115 to select the intermediate frequency signal IF_I. Figure 3 As shown, after processing by mixers 112 / 113 and composite filter 114, the intermediate frequency signals IF_I and IF_Q contain components corresponding to the frequency "IF", where the intermediate frequency signals IF_I and IF_Q are close to DC. It should be noted that... Figure 3 The response of the composite filter 114 shown is an ideal state. In reality, due to the mismatch between the in-phase and positive-phase channels, the response of the composite filter 114 is not perfectly symmetrical. Next, since the switching module 115 is controlled to output the intermediate frequency signal IF_I, the programmable gain amplifier 116 and the analog-to-digital converter 117 process the intermediate frequency signal IF_I to generate a digital signal for the digital circuit 130, which then determines the strength of the intermediate frequency signal IF_I with the desired signal.

[0063] Next, digital circuit 130 generates two digital test signals again and sends them to transmission circuit 120, which then performs a similar operation to generate a second test signal to matching circuit 104. (See reference) Figure 4 In this embodiment, the second test signal is used to represent the signal corresponding to... Figure 4 The required signal is a mirror image of the signal, and the frequency difference between the oscillation signals TXLO_I / TXLO_Q and RXLO_I / RXLO_Q is... Figure 4 The "IF" shown means, if Figure 3 The frequency TXLO of the first test signal shown is "RXLO+IF", then Figure 4 The frequency TXLO of the second test signal shown is "RXLO-IF".

[0064] Next, the receiving circuit 110 receives the second test signal generated by the transmitting circuit 120 through the matching circuit 104, and processes the second test signal as a received signal. At this time, the digital circuit 130 has generated a control signal Vc to control the switching module 115 to select the intermediate frequency signal IF_I. Figure 3 As shown, after processing by mixers 112 / 113 and composite filter 114, the intermediate frequency signals IF_I and IF_Q contain components corresponding to the frequency "-IF". Next, since the switching module 115 is controlled to output the intermediate frequency signal IF_I, the programmable gain amplifier 116 and analog-to-digital converter 117 process the intermediate frequency signal IF_I to generate a digital signal for the digital circuit 130, which then determines the strength of the intermediate frequency signal IF_I with a mirror signal.

[0065] As described above, since the digital circuit 130 determines the strength of the desired signal and the strength of the image signal, the image rejection ratio (IRR) of the intermediate frequency signal IF_I can be calculated. The calculation of the IRR can be found by referring to... Figure 4 As shown, this refers to the degree of attenuation of the mirror signal after passing through the response of the composite filter 114, for example... Figure 4 The image rejection ratio (IMRR) is indicated in the figure.

[0066] It should be noted that, in Figure 3 , Figure 4 In one embodiment, the frequency of the desired signal is "RXLO+IF", and the frequency of the mirror signal is "RXLO-IF", but the invention is not limited thereto. In other embodiments, the frequency of the desired signal can be "RXLO-IF", the frequency of the mirror signal is "RXLO+IF", and the center frequency of the composite filter 114 can be located near "RXLO-IF". These design variations should fall within the scope of the invention.

[0067] Next, similarly, digital circuit 130 again generates two digital test signals to transmission circuit 120, and transmission circuit 120 performs a similar operation to generate a third test signal to matching circuit 104. In this embodiment, this third test signal is used to indicate... Figure 3 The desired signal is shown, and the frequency difference between the oscillation signals TXLO_I / TXLO_Q and RXLO_I / RXLO_Q is... Figure 3 The "IF" shown.

[0068] Next, the receiving circuit 110 receives the third test signal generated by the transmitting circuit 120 through the matching circuit 104, and processes the third test signal as a received signal. At this time, the digital circuit 130 can first generate a control signal Vc to control the switching module 115 to select the intermediate frequency signal IF_Q. Figure 3 As shown, after processing by mixers 112 / 113 and composite filter 114, the intermediate frequency signals IF_I and IF_Q contain components corresponding to the frequency "IF". Since the switching module 115 has been controlled to output the intermediate frequency signal IF_Q, the programmable gain amplifier 116 and the analog-to-digital converter 117 process the intermediate frequency signal IF_Q to generate a digital signal for the digital circuit 130, so that the digital circuit 130 can determine the strength of the intermediate frequency signal IF_Q with the desired signal.

[0069] Next, digital circuit 130 generates two more digital test signals to transmission circuit 120, which then performs a similar operation to generate a fourth test signal to matching circuit 104. In this embodiment, this fourth test signal is used to indicate the corresponding... Figure 4 The required signal is a mirror image of the signal, and the frequency difference between the oscillation signals TXLO_I / TXLO_Q and RXLO_I / RXLO_Q is... Figure 4 The "IF" shown means, if Figure 3 The frequency TXLO of the third test signal shown is "RXLO+IF", then Figure 4 The frequency TXLO of the fourth test signal shown is "RXLO-IF".

[0070] Next, the receiving circuit 110 receives the fourth test signal generated by the transmitting circuit 120 through the matching circuit 104, and processes the fourth test signal as a received signal. At this time, the digital circuit 130 has generated a control signal Vc to control the switching module 115 to select the intermediate frequency signal IF_Q. Figure 4As shown, after processing by mixers 112 / 113 and composite filter 114, the intermediate frequency signals IF_I and IF_Q contain components corresponding to the frequency "-IF". Next, since the switching module 115 is controlled to output the intermediate frequency signal IF_Q, the programmable gain amplifier 116 and analog-to-digital converter 117 process the intermediate frequency signal IF_Q to generate a digital signal for the digital circuit 130, which then determines the strength of the intermediate frequency signal IF_Q with a mirror signal.

[0071] As described above, since the digital circuit 130 determines the strength of the desired signal and the strength of the image signal, the image rejection ratio of the intermediate frequency signal IF_Q can be calculated.

[0072] It should be noted that the generation and processing order of the first test signal, the second test signal, the third test signal and the fourth test signal is not a limitation of the present invention. That is, the order in which the digital circuit 130 determines the strength of the intermediate frequency signal IF_I with the desired signal, the strength of the intermediate frequency signal IF_I with the mirror signal, the strength of the intermediate frequency signal IF_Q with the desired signal and the strength of the intermediate frequency signal IF_Q with the mirror signal can be arbitrarily changed without affecting the concept of the present invention.

[0073] It should be noted that the above calculation of the image rejection ratio of the intermediate frequency signals IF_Q and IF_Q is merely an illustrative example and not a limitation of the present invention. In embodiments of the present invention, the image rejection ratio can be replaced by any quality parameter that can reflect the attenuation of the image signal of the intermediate frequency signals IF_Q and IF_Q.

[0074] As described above, in step 202, if the bias circuit 118 can switch the bias voltage VB_I to N bias values ​​(where N is a positive integer greater than or equal to 2), then in step 202, the image rejection ratios of the N intermediate frequency signals IF_I corresponding to the N bias voltages VB_I and the image rejection ratios of the N intermediate frequency signals IF_Q corresponding to the N bias voltages will be generated respectively.

[0075] In step 204, the digital circuit 130 selects an optimal value from the image rejection ratios of the multiple intermediate frequency signals IF_I and the multiple intermediate frequency signals IF_Q generated in step 202 as a first value, and the digital circuit 130 records the first value and the corresponding bias voltage VB_I and channel (i.e., in-phase channel or positive cross channel).

[0076] In step 206, the bias circuit 118 is controlled to sequentially generate multiple bias voltages VB_Q with different values ​​to mixer 113, and to generate a bias voltage VB_I with a preset value to mixer 112. For any of the multiple bias voltages VB_Q, the digital circuit 130 determines the image rejection ratio (IRR) of the intermediate frequency signal IF_I of the in-phase channel and the intermediate frequency signal IF_Q of the positive-phase channel. That is, if the bias circuit 118 can switch the bias voltage VB_Q to M bias values ​​(where M is a positive integer greater than or equal to 2), then in step 206, the image rejection ratios of the M intermediate frequency signals IF_I corresponding to the M bias values ​​and the image rejection ratios of the M intermediate frequency signals IF_Q corresponding to the M bias values ​​will be generated respectively. Since the detailed operation of step 206 can be referred to the embodiment of step 202 above, the detailed operation will not be repeated here.

[0077] In step 208, the digital circuit 130 selects an optimal value from the image rejection ratios of the plurality of intermediate frequency signals IF_I and the plurality of intermediate frequency signals IF_Q generated in step 206 as a second value, and the digital circuit 130 records the second value and the corresponding bias voltage VB_Q and channel (i.e., in-phase channel or positive cross channel).

[0078] In step 210, the digital circuit 130 selects the value with a better image rejection ratio from the first value and the second value.

[0079] It should be noted that steps 204, 208, and 210 above can be integrated to directly determine the optimal image rejection ratio and the corresponding bias voltages VB_I, VB_Q, and channels, without necessarily determining the aforementioned first and second values ​​first. In other words, the digital circuit 130 can directly determine an optimal image rejection ratio (i.e., optimal quality parameter) based on the image rejection ratios (i.e., multiple first quality parameters) of multiple intermediate frequency signals IF_I and multiple intermediate frequency signals IF_Q corresponding to different bias voltages VB_I generated in step 202, and the image rejection ratios (i.e., multiple second quality parameters) of multiple intermediate frequency signals IF_I and multiple intermediate frequency signals IF_Q corresponding to different bias voltages VB_Q generated in step 206.

[0080] In step 212, after determining the optimal image rejection ratio, in the subsequent operation of the transceiver circuit 100, the digital circuit 130 can control the bias circuit 118 to generate bias voltages VB_I and VB_Q corresponding to the optimal image rejection ratio to the mixers 112 and 113, and can also generate a control signal Vc to control the switching module 115 to select the intermediate frequency signal corresponding to the optimal image rejection ratio as the output intermediate frequency signal for subsequent processing by the programmable gain amplifier 116 and the analog-to-digital converter 117.

[0081] Figure 5 This is a schematic diagram of a mixer 500 according to an embodiment of the present invention, wherein the mixer 500 can be used to implement... Figure 1 Mixers 112 and 113 are shown. Figure 5 As shown, mixer 500 includes capacitors C1, C2, and C3, two resistors R1 and R2, and two transistors M1 and M2. In the operation of mixer 500, the bias voltage VB is input to the gates of transistors M1 and M2 through resistors R1 and R2. Transistors M1 and M2, controlled by oscillation signals LO+ and LO- respectively, perform a mixing operation (down-frequency operation) on an input signal IN to generate differentially mixed signals Vin+ and Vin-. Figure 5 In the embodiments, LO+ and LO- correspond to Figure 1 The RXLO_I or RXLO_Q, VB correspond to Figure 1 VB_I or VB_Q, and Vin+, Vin- correspond to Figure 1 Vin_I or Vin_Q.

[0082] It should be noted that, Figure 5 The mixer 500 shown is merely an example and not a limitation of the invention. In other embodiments, as long as the bias voltages VB_I and VB_Q generated by the bias circuit 118 are input into the mixer as bias voltages for the gates of transistors, Figure 1 Mixers 112 and 113 can be implemented using other single-balanced mixers or double-balanced mixers.

[0083] Figure 6 This is a schematic diagram of a bias circuit 600 according to an embodiment of the present invention, wherein the bias circuit 600 can be used to implement Figure 1 The bias circuit 118 is shown. (As shown) Figure 6 As shown, the bias circuit 600 includes an operational amplifier 610, a resistor R3, and four switching current sources. One input of the operational amplifier 610 is connected to a reference voltage Vref, and one output of the operational amplifier 610 is connected to a first terminal N1. Resistor R3 is coupled between the first terminal N1 and the second terminal N2. The first switching current source is coupled between the supply voltage VDD and the first terminal N1; the second switching current source is coupled between the supply voltage VDD and the second terminal N2; the third switching current source is coupled between the ground voltage and the first terminal N1; and the fourth switching current source is coupled between the ground voltage and the second terminal N2. The four switching current sources are respectively controlled by the control signal CT and... To control. In the operation of the bias circuit 600, the operational amplifier 610 receives the reference voltage Vref and controls it by changing the control signal CT. The voltage levels of bias voltages VB1 and VB2 are changed by adjusting the voltage levels of the bias voltages, where the bias voltage VB1 shown in the diagram can be... Figure 1 The bias voltage VB2 can be either VB_I or VB_Q, and the bias voltage VB2 can be either VB_I or VB_Q. Figure 1 The other of the bias voltages VB_I and VB_Q. For example, if the bias voltage VB1 is used as... Figure 1 The bias voltage VB_I, and the bias voltage VB2 as Figure 1 If the bias voltage VB_Q is such that, when the control signal CT enables the corresponding switch (e.g., CT=1), the bias voltage VB2 will be lower than the bias voltage VB1, causing the bias voltage VB_Q to be lower than the bias voltage VB_I, thus reducing the gain of the positive traffic channel. If the bias voltage VB1 is used as... Figure 1 The bias voltage VB_Q, and the bias voltage VB2 as Figure 1 If the bias voltage VB_I is lower than the bias voltage VB1, then when the control signal CT enables the corresponding switch, the bias voltage VB2 will be lower than the bias voltage VB1, causing the bias voltage VB_I to be lower than the bias voltage VB_Q, thus reducing the gain of the in-phase channel. If the bias voltage VB1 is used as... Figure 1 The bias voltage VB_I, and the bias voltage VB2 as Figure 1 The bias voltage VB_Q, then in the control signal When the enable switch is active (e.g., CT = 0), the bias voltage VB2 will be higher than the bias voltage VB1, thus increasing the gain of the positive traffic channel. If the bias voltage VB1 is used as... Figure 1 The bias voltage VB_Q, and the bias voltage VB2 as Figure 1 The bias voltage VB_I, then in the control signal When the enable switch is active, the bias voltage VB2 will be higher than the bias voltage VB1, thus increasing the gain of the non-inverting channel. It should be noted that... Figure 6 The bias circuit 600 shown is merely an example and not a limitation of the invention.

[0084] In another embodiment of the present invention, it can be Figure 1 Modifying the transceiver circuit 100 shown to disconnect the path from the non-inverting or positive-inverting channel to the programmable gain amplifier 116 can further reduce chip area and thus lower manufacturing costs. Specifically, refer to... Figure 7 This is a schematic diagram of a transceiver circuit 700 according to an embodiment of the present invention, wherein the transceiver circuit 700 and Figure 1 The difference between the transceiver circuits shown is that transceiver circuit 700 does not have a switching module 115, and the programmable gain amplifier 116 only receives the intermediate frequency signal IF_I generated by the in-phase channel. In the operation of transceiver circuit 700, it is similar to... Figure 2In this embodiment, since the programmable gain amplifier 116 only receives the intermediate frequency signal IF_I generated by the in-phase channel, only the image rejection ratio of multiple intermediate frequency signals IF_I corresponding to multiple bias voltages VB_I will be generated in step 202, and only the image rejection ratio of multiple intermediate frequency signals IF_I corresponding to multiple bias voltages VB_Q will be generated in step 206. As those skilled in the art will understand from reading this... Figures 1-4 The operation of the transceiver circuit 700 should be understood after reading the embodiments, so other details will not be repeated here.

[0085] In another embodiment of the present invention, the programmable gain amplifier 116 of the transceiver circuit 700 only receives the intermediate frequency signal IF_Q generated by the positive traffic channel. That is, in step 202, only the image rejection ratio of multiple intermediate frequency signals IF_Q corresponding to multiple bias voltages VB_I is generated, and in step 206, only the image rejection ratio of multiple intermediate frequency signals IF_Q corresponding to multiple bias voltages VB_Q is generated. These design variations should fall within the scope of the present invention.

[0086] In one embodiment of the present invention, the bias voltage VB_I or bias voltage VB_Q generated by the bias circuit 118 of the transceiver circuit 700 can be a fixed value, and it is not necessary to switch to multiple different bias values. For example, the bias voltage VB_Q generated by the bias circuit 118 can be a fixed value, and at this time... Figure 2 Steps 206, 208, and 210 can be removed, meaning that in step 204, the digital circuit 130 directly selects the optimal image rejection ratio (i.e., the optimal quality parameter) from the image rejection ratios (i.e., the multiple first quality parameters) of multiple intermediate frequency signals IF_I for use in step 212.

[0087] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A transceiver circuit, comprising: A receiving circuit, wherein the receiving circuit includes: A first mixer is used to perform a mixing operation on an input signal using a first oscillation signal to generate a first mixed signal. A second mixer is used to perform a mixing operation on the input signal using a second oscillation signal to generate a second mixed signal; A bias circuit is used to generate a first bias voltage to the first mixer and a second bias voltage to the second mixer. A composite filter is used to generate a first intermediate frequency (IF) signal and a second intermediate frequency (IF) signal based on the first mixed signal and the second mixed signal; and An analog-to-digital converter is used to perform an analog-to-digital conversion operation on an output intermediate frequency (IF) signal to generate a digital signal, wherein the output IF signal is one of the first IF signal and the second IF signal; and A digital circuit coupled to the receiving circuit, wherein the digital circuit controls the bias circuit to sequentially switch the first bias to a plurality of first bias values, and the receiving circuit generates a plurality of first digital signals corresponding to the plurality of first bias values, and calculates a plurality of first quality parameters corresponding to the plurality of first bias values; and the digital circuit controls the bias circuit to make the first bias have a bias value corresponding to an optimal quality parameter, wherein the optimal quality parameter is determined at least by the plurality of first quality parameters.

2. The transceiver circuit of claim 1, wherein the digital circuit further controls the bias circuit to sequentially switch the second bias to a plurality of second bias values, and the receiving circuit generates a plurality of second digital signals corresponding to the plurality of second bias values, and calculates a plurality of second quality parameters corresponding to the plurality of second bias values; and the digital circuit selects the optimal quality parameter from the first quality parameter and the plurality of second quality parameters.

3. The transceiver circuit as claimed in claim 1, wherein the receiving circuit further comprises: A switching module is used to receive the first intermediate frequency signal and the second intermediate frequency signal, and select one of the first intermediate frequency signal and the second intermediate frequency signal according to a control signal to generate the output intermediate frequency signal; The digital circuit generates the control signal to sequentially select one of the first intermediate frequency signal and the second intermediate frequency signal as the output intermediate frequency signal. When using the first intermediate frequency signal and the second intermediate frequency signal as the output intermediate frequency signal, the digital circuit controls the bias circuit to sequentially switch the first bias to the plurality of first bias values, so that the plurality of first quality parameters include quality parameters corresponding to the first intermediate frequency signal and quality parameters corresponding to the second intermediate frequency signal.

4. The transceiver circuit of claim 3, wherein the digital circuit further controls the bias circuit to sequentially switch the second bias to a plurality of second bias values, and the receiving circuit generates a plurality of second digital signals corresponding to the plurality of second bias values, and calculates a plurality of second quality parameters corresponding to the plurality of second bias values; and the digital circuit selects the optimal quality parameter from the first quality parameter and the plurality of second quality parameters.

5. The transceiver circuit of claim 4, wherein, for using the first intermediate frequency signal and the second intermediate frequency signal as the output intermediate frequency signal, the digital circuit controls the bias circuit to sequentially switch the second bias to the plurality of second bias values, such that the plurality of second quality parameters include quality parameters corresponding to the first intermediate frequency signal and quality parameters corresponding to the second intermediate frequency signal.

6. The transceiver circuit of claim 1, wherein each of the plurality of first quality parameters is an image rejection ratio.

7. The transceiver circuit of claim 1, wherein the first mixer includes at least one transistor, and the bias circuit generates the first bias voltage to the gate of the at least one transistor in the first mixer.

8. The transceiver circuit of claim 1, wherein the bias circuit comprises: An operational amplifier, wherein one input terminal of the operational amplifier is connected to a reference voltage, and one output terminal of the operational amplifier is connected to a first terminal. A resistor is coupled between the first terminal and a second terminal; A first switching current source is coupled between a supply voltage and the first terminal. A second switching current source is coupled between the supply voltage and the second terminal. The third switching current source is coupled between a ground voltage and the first terminal. as well as The fourth switching current source is coupled between the ground voltage and the second terminal. The first endpoint or the second endpoint is used to generate the first bias voltage.

9. A control method for a transceiver circuit, wherein the transceiver circuit comprises: A receiving circuit, wherein the receiving circuit includes: A first mixer is used to perform a mixing operation on an input signal using a first oscillation signal to generate a first mixed signal. A second mixer is used to perform a mixing operation on the input signal using a second oscillation signal to generate a second mixed signal; A bias circuit is used to generate a first bias voltage to the first mixer and a second bias voltage to the second mixer. A composite filter for generating a first intermediate frequency (IF) signal and a second intermediate frequency (IF) signal based on the first mixed signal and the second mixed signal; and An analog-to-digital converter is used to perform an analog-to-digital conversion operation on an output intermediate frequency (IF) signal to generate a digital signal, wherein the output IF signal is one of the first IF signal and the second IF signal; and This control method includes: The bias circuit is controlled to sequentially switch the first bias to multiple first bias values ​​so that the receiving circuit can generate multiple first digital signals corresponding to the multiple first bias values ​​respectively. Based on the multiple first digital signals, multiple first quality parameters corresponding to the multiple first bias values ​​are calculated respectively; as well as The bias circuit is controlled such that the first bias has a bias value corresponding to an optimal quality parameter, wherein the optimal quality parameter is determined by at least the plurality of first quality parameters.

10. The control method as described in claim 9, further comprising: The bias circuit is controlled to sequentially switch the second bias to multiple second bias values ​​so that the receiving circuit can generate multiple second digital signals corresponding to the multiple second bias values ​​respectively. Based on the multiple second digital signals, multiple second quality parameters corresponding to the multiple second bias values ​​are calculated respectively; as well as The optimal quality parameter is selected from the first quality parameter and the plurality of second quality parameters.

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