Random number generator of information encryption system, random number generation method, equipment and medium

Abstract

The invention discloses a random number generator of an information encryption system, a random number generation method, equipment and a medium, and relates to the technical field of information security, and the random number generator comprises a bus switching interface which is used for carrying out time sequence conversion on a configuration command and sending the converted command to a register unit; the register unit is used for configuring a register according to the converted command; the logic control unit is used for generating control logic according to the configuration condition, controlling the workflow according to the control logic and updating the state to the register unit; the entropy source determining unit is used for generating a true random number according to an entropy source circuit configured by the control logic and performing first operation on the true random number; the target processing unit is used for performing second operation on the true random number according to an algorithm selected by the control logic; the health detection unit is used for detecting the true random number; and the pseudo-random number generation unit is used for obtaining a pseudo-random number. The random number generation efficiency is improved, the cost is low, and large-scale popularization is facilitated.

Description

Technical Field

[0001] The present invention relates to the field of information security technology, and in particular to a random number generator, a random number generation method, a device and a medium for an information encryption system. Background Art

[0002] With the rapid development of the Internet of Things, big data, and cloud computing, data storage and information communication have become more and more frequent, and information security issues have received widespread attention. The encryption system is an important means to combat information theft in the field of information security. The true random number generator is an important component of the information encryption system equipment. The unpredictable and non-reproducible key digital string it generates is used for public keys, initialization vectors, etc., and is widely used in key generation and management, digital signatures, and identity authentication. To some extent, the performance and security of the true random number generator determines the performance and security of the entire encryption system.

[0003] Traditional methods of designing true random number generators mainly include the following: (1) obtaining a true random number generator through customized dedicated analog circuit design. This method consumes a lot of development time and R&D costs and is not convenient for integrated development; (2) developing and implementing it in programmable logic devices such as FPGA (Field-Programmable Gate Array) based on the principle of clock jitter. Since the jitter of FPGA devices is very small, the speed of generating random numbers is slow and the performance is low; (3) designing a true random number generator based on the photon effect. This method is costly and not conducive to large-scale popularization. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a random number generator, random number generation method, device and medium for an information encryption system, which improves the efficiency of random number generation, has low cost and is conducive to large-scale popularization. The specific scheme is as follows:

[0005] In a first aspect, the present application discloses a random number generator for an information encryption system, including a target bus transfer interface, a register unit, a logic control unit, an entropy source determination unit, a target processing unit, a health detection unit, a pseudo-random number generation unit and a cache unit, wherein:

[0006] The target bus transfer interface is used to perform timing conversion on the register configuration command sent by the central processing unit to obtain a converted command, and send the converted command to the register unit;

[0007] The register unit is used to configure each register according to the converted command;

[0008] The logic control unit is used to generate control logic according to the configuration of the register, and control the workflow of the entropy source determination unit, the target processing unit and the health detection unit according to the control logic, and update the execution status of the workflow to the register unit;

[0009] The entropy source determination unit is used to configure a target entropy source circuit according to the control logic, generate a true random number using the target entropy source circuit, and perform a first processing operation on the true random number;

[0010] The target processing unit is used to select a target algorithm according to the control logic, and perform a second processing operation on the true random number after the first processing operation according to the target algorithm;

[0011] The health detection unit is used to perform a health detection on the true random number that has undergone the second processing operation, and write the true random number that has passed the health detection into a target first-in-first-out queue in the cache unit;

[0012] The pseudo-random number generating unit is used to obtain a pseudo-random number based on a target initialization result and a target time parameter, and write the pseudo-random number into the target first-in-first-out queue.

[0013] Optionally, the random number generator further includes:

[0014] An output selection unit is used to select, according to the control logic, to write the true random number into the target first-in-first-out queue through the health detection unit, or to select to write the pseudo-random number into the target first-in-first-out queue through the pseudo-random number generation unit.

[0015] Optionally, the pseudo-random number generation unit is used to perform an XOR operation on the target initialization result and a target encryption result obtained by encrypting the target time parameter using a preset encryption algorithm to obtain a first XOR result, and encrypt the first XOR result using the preset encryption algorithm to obtain the pseudo-random number, and write the pseudo-random number into the target first-in-first-out queue.

[0016] Optionally, the target initialization result is a result obtained by initializing the internal state of the pseudo-random number generation unit according to the configuration of the register, or a result obtained by initializing the internal state of the pseudo-random number generation unit based on the true random number obtained after the second processing operation.

[0017] Optionally, the entropy source determination unit is used to configure the target entropy source circuit from multiple entropy source circuits according to the control logic, generate the true random number using the target entropy source circuit, perform an XOR operation on the true random number generated by the target entropy source circuit to obtain a second XOR result, perform sampling processing on the second XOR result to obtain a target sampling result, perform bit detection processing on the target sampling result to determine whether the target sampling result is all 0 bits or all 1 bits, and if not, perform serial-to-parallel conversion processing on the target sampling result to obtain the true random number after the first processing operation;

[0018] Correspondingly, the target processing unit is used to select the target algorithm from a plurality of preset algorithms according to the control logic, and to operate the true random number after the first processing operation according to the target algorithm to obtain a target processing result, and to perform bit detection processing on the target processing result to determine whether the target processing result is all 0 bits or all 1 bits, and if not, to determine the target processing result as the true random number after the second processing operation;

[0019] Correspondingly, the health detection unit is used to perform a health detection on the true random number that has undergone the second processing operation according to a preset health detection algorithm, and write the true random number that has passed the health detection into the target first-in-first-out queue; wherein the preset health detection algorithm includes a frequency test, a cumulative sum test, an autocorrelation test, a poker test, and a run test.

[0020] Optionally, the target bus adapter includes a peripheral bus adapter and a system bus adapter, and the peripheral bus adapter and the system bus adapter are isolated from each other through a macro definition mechanism.

[0021] Optionally, the peripheral bus conversion interface includes a peripheral bus to register read / write interface and a peripheral bus to first-in-first-out queue read interface, the system bus conversion interface includes a system bus to register read / write interface and a system bus to first-in-first-out queue read interface, and the peripheral bus to register read / write interface and the system bus to register read / write interface are connected to an advanced microcontroller bus structure for receiving register configuration commands sent by the central processing unit, and the peripheral bus to first-in-first-out queue read interface and the system bus to first-in-first-out queue read interface are connected to the target first-in-first-out queue for sending the true random number or the pseudo-random number to the central processing unit.

[0022] In a second aspect, the present application discloses a random number generation method for an information encryption system, comprising:

[0023] Performing timing conversion on the register configuration command sent by the central processing unit through the target bus transfer interface in the random number generator to obtain a converted command, and sending the converted command to the register unit in the random number generator;

[0024] configuring each register through the register unit and according to the converted command;

[0025] Generate control logic through the logic control unit in the random number generator according to the configuration of the register, control the workflow of the entropy source determination unit, the target processing unit and the health detection unit in the random number generator according to the control logic, and update the execution status of the workflow to the register unit;

[0026] configuring a target entropy source circuit through the entropy source determination unit and according to the control logic, then generating a true random number using the target entropy source circuit, and performing a first processing operation on the true random number;

[0027] Selecting a target algorithm through the target processing unit and according to the control logic, and then performing a second processing operation on the true random number after the first processing operation according to the target algorithm;

[0028] Performing a health check on the true random number that has undergone the second processing operation through the health check unit, and then writing the true random number that has passed the health check into a target first-in-first-out queue in a cache unit of the random number generator;

[0029] A pseudo-random number is obtained through a pseudo-random number generation unit in the random number generator based on a target initialization result and a target time parameter, and then the pseudo-random number is written into the target first-in-first-out queue.

[0030] In a third aspect, the present application discloses an electronic device, comprising:

[0031] Memory, used to store computer programs;

[0032] A processor is used to execute the computer program to implement the random number generation method of the aforementioned disclosed information encryption system.

[0033] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the random number generation method of the aforementioned information encryption system is implemented.

[0034] It can be seen that the present application proposes a random number generator for an information encryption system, comprising: a target bus transfer interface, a register unit, a logic control unit, an entropy source determination unit, a target processing unit, a health detection unit, a pseudo-random number generation unit and a cache unit, wherein the target bus transfer interface is used to perform timing conversion on the register configuration command sent by the central processing unit to obtain the converted command, and send the converted command to the register unit; the register unit is used to configure each register according to the converted command; the logic control unit is used to generate a control logic according to the configuration of the register, and control the workflow of the entropy source determination unit, the target processing unit and the health detection unit according to the control logic, and the workflow The execution status is updated to the register unit; the entropy source determination unit is used to configure the target entropy source circuit according to the control logic, and use the target entropy source circuit to generate a true random number, and perform a first processing operation on the true random number; the target processing unit is used to select a target algorithm according to the control logic, and perform a second processing operation on the true random number after the first processing operation according to the target algorithm; the health detection unit is used to perform a health detection on the true random number after the second processing operation, and write the true random number that passes the health detection into a target first-in-first-out queue in the cache unit; the pseudo-random number generation unit is used to obtain a pseudo-random number based on a target initialization result and a target time parameter, and write the pseudo-random number into a target first-in-first-out queue.

[0035] Beneficial effects: The present application first converts the register configuration command sent by the central processing unit through the target bus interface, and configures each register according to the converted command through the register unit, so that the logic control unit generates control logic according to the configuration of the register. It should be pointed out that the design of the control logic enables the random number generator of the present application to have better timing and better performance, reduces bit flipping to a certain extent, and reduces power consumption. Furthermore, the present application generates true random numbers according to the control logic through an entropy source determination unit and performs a first processing on the true random numbers, performs a second processing on the true random numbers through a target processing unit, performs a health detection on the true random numbers through a health detection unit, and writes the true random numbers that pass the detection into a first-in-first-out queue. In summary, compared with the traditional true random number generation method, the present application does not require customized dedicated analog circuits, does not need to be based on FPGA devices, and does not need to be based on photon quantum effects. Instead, it generates true random numbers based on the control logic obtained by converting register configuration commands, thereby improving the efficiency of true random number generation, having low costs, and being conducive to large-scale popularization. Furthermore, the pseudo-random numbers generated by the pseudo-random number unit in the present application are random and unpredictable, and can be used in various cryptographic business scenarios, and the random number generator in the present application supports the generation of true random numbers and pseudo-random numbers to adapt to different business scenarios and needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0037] Figure 1 A schematic diagram of a random number generator for an information encryption system disclosed in the present application;

[0038] Figure 2 A schematic diagram of a target bus adapter disclosed in this application;

[0039] Figure 3 A schematic diagram of a random number generator for a specific information encryption system disclosed in this application;

[0040] Figure 4 A schematic diagram of a register unit disclosed in this application;

[0041] Figure 5 A schematic diagram of a logic control unit disclosed in this application;

[0042] Figure 6 This is a schematic diagram of an entropy source determination unit disclosed in this application;

[0043] Figure 7 A schematic diagram of a pseudo-random number generation unit disclosed in this application;

[0044] Figure 8 A flow chart of a random number generation method disclosed in this application;

[0045] Fig. 9 This is a flow chart of another random number generation method disclosed in this application;

[0046] Fig.10 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] (1) A true random number generator is obtained by customizing a dedicated analog circuit design. This method consumes a lot of development time and R&D costs and is not convenient for integrated development. (2) The clock jitter principle is used to develop and implement it in programmable logic devices such as FPGA (Field-Programmable Gate Array). Since the jitter of FPGA devices is very small, the speed of generating random numbers is slow and the performance is low. (3) A true random number generator is designed based on the photon effect. This method is costly and not conducive to large-scale popularization.

[0049] To this end, the embodiment of the present application proposes a random number generation scheme for an information encryption system, which improves the efficiency of random number generation, has low cost, and is conducive to large-scale popularization.

[0050] The embodiment of the present application discloses a random number generator for an information encryption system, including a target bus transfer interface 11, a register unit 12, a logic control unit 13, an entropy source determination unit 14, a target processing unit 15, a health detection unit 16, a pseudo-random number generation unit 17 and a cache unit 18, see Figure 1 As shown,

[0051] The target bus transfer interface 11 is used to perform timing conversion on the register configuration command sent by the central processing unit to obtain a converted command, and send the converted command to the register unit 12 .

[0052] In this embodiment, the target bus is also called Advanced Microcontroller Bus Architecture (AMBA), and the target bus includes a system bus (Advanced high performance bus, AHB) and a peripheral bus (Advanced Peripheral Bus, APB), see Figure 2 As shown, the target bus adapter includes a peripheral bus adapter and a system bus adapter, and the peripheral bus adapter and the system bus adapter are isolated from each other through a macro definition mechanism. In this way, it can meet the needs of different projects and facilitate interface switching and code transplantation.

[0053] In this embodiment, the peripheral bus transfer interface integrates the peripheral bus transfer register read and write logic (ie Figure 2 apb2_reg_inf in the register group), which is used to generate the read and write enable signals and address signals of the register group, and integrates the peripheral bus to the first-in first-out queue (First Input First Output, Fifo) read logic (that is, Figure 2 apb2_fifo_inf in the FIFO register is used to generate the read enable and read data of the FIFO queue. The system bus transfer interface integrates the system bus transfer register read and write logic (that is, Figure 2 ahb2_reg_inf in the register group), which is used to generate the read and write enable signals and address signals of the register group, and integrates the system bus to first-in first-out queue read logic (that is, Figure 2 ahb2_fifo_inf in ahb2_fifo_inf) is used to generate the read enable and read data of the first-in-first-out queue.

[0054] See also Figure 2 As shown, the peripheral bus transfer interface includes a peripheral bus to register read / write interface and a peripheral bus to first-in first-out queue read interface, the system bus transfer interface includes a system bus to register read / write interface and a system bus to first-in first-out queue read interface, and the peripheral bus to register read / write interface and the system bus to register read / write interface (collectively referred to as Figure 3 The bus to register read / write interface in the system bus is connected to the advanced microcontroller bus structure to convert the timing of the register configuration command sent by the central processor, and the peripheral bus to first-in-first-out queue read interface is connected to the system bus to first-in-first-out queue read interface (collectively referred to as Figure 3 The bus in the first-in-first-out queue read interface) is connected to the target first-in-first-out queue in the cache unit, and is used to send true random numbers or pseudo-random numbers to the central processing unit.

[0055] In this embodiment, the corresponding bus adapter can be selected according to project requirements and through conditional compilation commands in Verilog HDL (a hardware description language).

[0056] The register unit 12 is used to configure each register according to the converted command.

[0057] In this embodiment, the register unit is used to configure each register according to the converted command to control the start of true / pseudo random number operation, control the start of health detection, adjust the sampling frequency, etc. Figure 3 and Figure 4 As shown in the figure, the register unit specifically includes the following types of registers:

[0058] (1) Control registers: used to control the generation of true / pseudo-random numbers, control the enablement of four noise sources, set one of them to be on by default and cannot be turned off, control the start and stop of the random number generator, control the power-on self-test and other functions, control the selection of the target algorithm (also called the post-processing algorithm), clear the soft reset register and the internal cache, etc.

[0059] (2) Status registers: used to inform the central processing unit of the current internal state of the random number generator, the pass status of health check items, and the power-on self-test status.

[0060] (3) Health detection enable register: Health detection is enabled by default and can be turned off through configuration.

[0061] (4) Interrupt registers: including normal interrupt status register, error interrupt status register, interrupt mask register, and interrupt clear register. The normal interrupt status register is used to notify the system that a new random number is ready, and the error interrupt status register is used to notify the system that the health check has failed.

[0062] (5) Sampling frequency control register: If the health check fails, the sampling frequency of the entropy source is adjusted by configuring this register.

[0063] (6) Data output register: stores the generated true / pseudo random number. It can be read after the interrupt is pulled high or the CPU knows through the status register that a new random number is ready. The number of reads depends on the size of the cache unit.

[0064] (7) Time parameter register: stores time parameter information for pseudo-random number generation. If the random number output mode of the output unit is configured as pseudo-random output, this register must be configured. If it is configured as true random output, this register does not need to be configured.

[0065] The logic control unit 13 is used to generate control logic according to the configuration of the register, and control the workflow of the entropy source determination unit, the target processing unit and the health detection unit according to the control logic, and update the execution status of the workflow to the register unit.

[0066] In this embodiment, the logic control unit is used to complete control information analysis, data flow control, random number generator workflow control, update internal status to the register unit, generate self-test enable signal and self-test verification parameters, generate five randomness verification enable signals and verification parameters, monitor true / pseudo-random number detection status, output power-on self-test / health test pass or fail status signals, generate interrupt information and control to start or stop the random number generator.

[0067] See also Figure 3 and Figure 5 As shown, the logic control unit contains a main state machine and several sub-state machines, which are mainly used for entropy source detection control, sampling frequency control, power-on self-test, health detection, true / pseudo-random number switching control and data flow control when the random number generator is working. The data flow is described as follows:

[0068] (1) The control signal output by the register unit is transmitted to the logic control unit through the internal interface. The logic control unit starts the main state machine, analyzes, determines and starts the corresponding sub-state machine and processes it.

[0069] (2) The startup of each sub-state machine is triggered by the internal state of the main state machine, and the state jump of the main state machine is triggered by the end state of the sub-state machine.

[0070] (3) The main state machine processes the status feedback after each stage is completed, including but not limited to: power-on self-test pass / fail, health test pass / fail, random number data ready, etc., and then feeds back these statuses in their respective stages.

[0071] (4) When the power-on self-test fails or the health check fails, the main state machine will be triggered to jump to the error state, an error interrupt will be generated, and the cause of the error will be written to the status register for the central processor to query.

[0072] (5) Under normal circumstances, when no errors occur, the logic control unit will detect the full signal of the first-in-first-out queue in the cache unit in real time while monitoring the random number generation process. When the full signal of the first-in-first-out queue is pulled high, it indicates that the current random number is ready for output. At this time, the logic control unit triggers the normal interrupt to be effective and waits for the central processor to read.

[0073] From the above, it can be seen that the control logic unit uses a master-slave state machine to complete the scheduling, state monitoring and logic control of the data flow. From the timing aspect, this embodiment triggers several sub-state machines through a master state machine. Compared with merging the master-slave state machines into one state machine, this embodiment improves the timing; from the functional perspective, for some logic functions that only run once after power-on reset or soft reset, and do not participate in subsequent operations, this embodiment can skip similar functions and directly run other logic functions, with better overall performance. Finally, this embodiment is also helpful in reducing power consumption and reducing unnecessary bit flips.

[0074] The entropy source determination unit 14 is used to configure a target entropy source circuit according to the control logic, generate true random numbers using the target entropy source circuit, and perform a first processing operation on the true random numbers.

[0075] See also Figure 3 and Figure 6 As shown, in this embodiment, the entropy source determination unit includes an entropy source part and a sampling and preprocessing part. The entropy source part is used to configure the target entropy source circuit from multiple entropy source circuits according to the control logic, wherein the target entropy source circuit can be obtained by configuring and combining 1 / 2 / 3 / 4 entropy source circuits. Further, the target entropy source circuit is used to generate the true random number, and the true random number generated by the target entropy source circuit is XORed to obtain a second XOR result. The sampling and preprocessing part is used to sample the second XOR result to obtain a target sampling result, perform bit detection processing on the target sampling result to determine whether the target sampling result is all 0 bits or all 1 bits, and output it to the target processing unit, so that the processing unit performs serial-to-parallel conversion processing on the target sampling result when the target sampling result is not all 0 bits or all 1 bits, and obtains a true random number after the first processing operation. Further, if the target sampling result is all 0 bits or all 1 bits, it indicates that it has not passed the detection, and then the central processor is informed through an interrupt, and the central processor changes the sampling frequency or the number of entropy source circuits.

[0076] It should be noted that, in this embodiment, entropy source loop 0 is enabled by default and cannot be configured to be turned off, entropy source loops 1-3 can be configured to be enabled, and are turned off by default. After power-on reset, soft reset ends, or the random number generator stops, it can be configured to be turned on. For the entropy source circuit, this embodiment can select multiple free-running ring oscillators (RO) (composed of an inverter, a delay, and a feedback loop), and other oscillators can also be selected, which improves flexibility at the design level. Further, in order to ensure the randomness of the sampled data, in addition to changing the sampling frequency, in terms of the entropy source, this embodiment can also increase the randomness of the entropy source by XORing the outputs of multiple ring oscillators. It should be noted that the multiplexer is a many-to-many structure, and the entropy value of the enabled loop is output and XORed, and then transmitted to the sampling and preprocessing part for processing. It should be pointed out that the sampling part in this embodiment adopts a dual D-type flip-flop sampling module structure. During sampling, the slow-frequency oscillator is used as the sampling clock input fs, and the fast-frequency oscillator, i.e., the entropy source XOR output, is used as the sampling data input. There cannot be obvious correlation between the sampled bit codes. Therefore, when selecting the sampling frequency, the following conditions must be met: 2σ / T>1.5, where σ is the standard deviation of the period jitter of the low-frequency oscillator, and T is the period of the high-frequency oscillation signal.

[0077] The target processing unit 15 is used to select a target algorithm according to the control logic, and perform a second processing operation on the true random number that has undergone the first processing operation according to the target algorithm.

[0078] See also Figure 3 As shown, the target processing unit is used to perform serial-to-parallel conversion processing on the target sampling result, and select the target algorithm from the preset multiple algorithms according to the control logic, and then calculate the true random number after the first processing operation according to the target algorithm to obtain the target processing result, and perform bit detection processing on the target processing result to determine whether the target processing result is all 0 bits or all 1 bits. If not, the target processing result is determined to be the true random number after the second processing operation, wherein the preset multiple algorithms include SM4-CTR (symmetric block encryption algorithm-counter) and 128-level LFSR) (linear feedback shift register) post-processing algorithm.

[0079] The health detection unit 16 is used to perform a health detection on the true random number that has undergone the second processing operation, and write the true random number that has passed the health detection into a target first-in-first-out queue in the cache unit 18 .

[0080] See also Figure 3As shown, the health detection unit is used to perform health detection on the true random number after the second processing operation according to the preset health detection algorithm, and write the true random number that passes the health detection into the target first-in-first-out queue; wherein the preset health detection algorithm includes frequency test, cumulative sum test, autocorrelation test, poker test and run test. Further, the health detection unit is also used to determine whether the tested data passes the test according to the pass rate and output the corresponding status information, and to control the writing of random numbers into the first-in-first-out queue until it is full, wherein the bit width of the random number can be configured according to the demand.

[0081] The pseudo-random number generating unit 17 is used to obtain a pseudo-random number based on a target initialization result and a target time parameter, and write the pseudo-random number into the target first-in-first-out queue.

[0082] (1) First, the internal state of the pseudo-random number generation unit is initialized to obtain a target initialization result. This embodiment specifically includes two initialization methods, one of which is to initialize the internal state of the pseudo-random number generation unit according to the configuration of the register, and the other is to initialize the internal state of the pseudo-random number generation unit based on the true random number after the second processing operation.

[0083] (2) A target encryption result (i.e., a mask) is obtained by encrypting the target time parameter using a preset encryption algorithm, wherein the preset encryption algorithm includes a symmetric block encryption algorithm, and the target time parameter is the time information at this moment. The data format of the target time parameter can be defined by itself and can be converted into ASCII code (American Standard Code for Information Interchange) or other formats. The time parameter only needs to be configured once during the initialization phase and is subsequently maintained and processed by the hardware.

[0084] (3) performing an XOR operation on the target initialization result and the target encryption result to obtain a first XOR result, and encrypting the first XOR result using a symmetric block encryption algorithm to obtain the pseudo-random number, and then writing the pseudo-random number into the target first-in-first-out queue.

[0085] (4) XOR the target encryption result with the pseudo-random number.

[0086] (5) Encrypt the XOR result of step (4) using a symmetric block encryption algorithm to obtain the necessary parameters required for internal state update.

[0087] (6) Use the result of step (5) as a parameter to update the internal state.

[0088] (7) Loop through steps (2) to (6) to continuously obtain the required number of pseudo-random numbers.

[0089] In summary, step (1) provides two methods for initializing the internal state, which provides users with the greatest degree of flexibility and can be selected according to needs and application scenarios. The second initialization method is more confidential and unpredictable, which helps to improve the quality of pseudo-random number generation. In step (2), in the process of encrypting the target time parameter, since the encryption key is unknown, the value of the target encryption result is unpredictable. In steps (3) and (4), the bit sequence is randomly flipped by the target encryption result to enhance randomness. Since the attacker cannot crack the password, the pseudo-random number output by step (3) cannot be inferred from the pseudo-random number output next time. The main function of steps (5) and (6) is to update the internal state. The new internal state is obtained by XORing the currently generated pseudo-random number with the encryption result. Therefore, even if the attacker obtains the current random number, the new internal state cannot be inferred because the attacker cannot know the encryption result and the encryption key.

[0090] See also Figure 7 As shown, Figure 7 The schematic diagram is a diagram of the internal execution logic of the pseudo-random number generation unit and the internal execution logic of the symmetric block encryption algorithm, wherein the internal execution logic of the pseudo-random number generation unit is specifically described in the aforementioned disclosed embodiment, and will not be described in detail here, and the internal execution logic of the symmetric block encryption algorithm is the traditional encryption algorithm execution logic, and will not be described in detail here. In this embodiment, the generated pseudo-random number has randomness and unpredictability, which meets the requirements of the cryptographic algorithm business for random numbers, and the efficiency of pseudo-random number generation is high, which can meet the requirements of multiple business scenarios and massive encryption and decryption.

[0091] The selection output unit 19 is used to select, according to the control logic, to write the true random number into the target first-in-first-out queue through the health detection unit, or to select to write the pseudo-random number into the target first-in-first-out queue through the pseudo-random number generation unit.

[0092] In this embodiment, the output selection unit is used to configure the output mode according to the selected output signal. The output mode includes outputting a pseudo-random number or outputting a true random number. If the output mode is to output a pseudo-random number, the pseudo-random number is written into the target first-in-first-out queue by the pseudo-random number generation unit. If the output mode is to output a true random number, the true random number is written into the target first-in-first-out queue by the health detection unit. In addition, the present embodiment can also automatically switch the selected output signal according to the time change cycle. The time change cycle in the present embodiment can be configured according to business needs. For example, if the business needs require the output of true random numbers and pseudo-random numbers in different time periods, the present embodiment can configure the corresponding selected output signals in different time periods. After configuring the corresponding selected output signals in the time period, the present embodiment can trigger the corresponding selected output signals in the corresponding time period, and output the corresponding true / pseudo-random numbers under the triggering of the corresponding selected output signals.

[0093] The present application discloses a method for generating random numbers. Figure 8 and Fig. 9 As shown, specifically including:

[0094] Step S11: performing timing conversion on the register configuration command sent by the central processing unit through the target bus conversion interface in the random number generator to obtain a converted command, and sending the converted command to the register unit in the random number generator.

[0095] Step S12: configuring each register through the register unit and according to the converted command.

[0096] Step S13: Generate control logic through the logic control unit in the random number generator and according to the configuration of the register, and control the workflow of the entropy source determination unit, the target processing unit and the health detection unit in the random number generator according to the control logic, and update the execution status of the workflow to the register unit.

[0097] Step S14: configuring a target entropy source circuit through the entropy source determination unit and according to the control logic, then using the target entropy source circuit to generate a true random number, and performing a first processing operation on the true random number.

[0098] Step S15: selecting a target algorithm through the target processing unit and according to the control logic, and then performing a second processing operation on the true random number that has undergone the first processing operation according to the target algorithm.

[0099] Step S16: performing a health check on the true random number that has undergone the second processing operation through the health check unit, and then writing the true random number that has passed the health check into a target first-in-first-out queue in the cache unit of the random number generator.

[0100] Step S17: obtaining a pseudo-random number through a pseudo-random number generation unit in the random number generator based on a target initialization result and a target time parameter, and then writing the pseudo-random number into the target first-in-first-out queue.

[0101] In this embodiment, (1) after power-on reset or soft reset, configure the number and sampling frequency of the internal 4-way entropy source loop circuits turned on, configure the output mode to true random number output, configure the target processing algorithm, the random number generator performs power-on self-test by default, and configure the start bit of the control register to start the random number generator. (2) The channel normal interrupt is pulled high, and the central processing unit queries the interrupt status register to obtain the power-on self-test passed. At this time, the random number generator is in the pause stage, and the interrupt clear register needs to be configured to clear the normal interrupt so that the random number generator can continue to generate random numbers. (3) The channel error interrupt is pulled high, and the central processing unit queries the error interrupt status register to obtain the power-on self-test failed status. At this time, the end bit of the configuration control register stops generating random numbers, and adjusts the number and sampling frequency of the entropy source loops, and then starts the random number generator until the power-on test passes. (4) The internal processing mechanism of the random number generator is as follows: when the first-in-first-out queue is filled with data, an interrupt is initiated to inform the central processor that there is a true random number to be read; during the operation of the random number generator, if a normal channel interrupt is received, the interrupt status register is queried. If it shows that the random number is ready, it means that there is a true random number to be read. The central processor can continuously read the random number output register or the first-in-first-out queue. The number of reads is determined by the depth of the first-in-first-out queue. At this time, the random number generator is in a pause stage. After the data is read, the normal interrupt is cleared and the random number generator continues to run. (5) Wait for the next interrupt. After reading the required random number, the stop bit of the random number generator can be configured to stop running.

[0102] In this embodiment, the output mode can be switched, that is, in this embodiment, the true / pseudo-random number output can be selected. The true / pseudo-random number switching process includes: (1) in the process of generating true random numbers, the register cannot be directly configured to switch the pseudo-random number. It is necessary to first configure the control register to stop the operation of the random number generator, and then configure the output type register to the pseudo-random number type. (2) Configure the parameters and states required for pseudo-random number generation: time parameter register, initial state register. (3) After power-on reset or soft reset, the random number generator can be directly started after performing steps (1) and (2). If the true / pseudo-random number is switched during the operation of the random number generator, since the random number before the switch may have been cached at this time, it is necessary to configure the cache clearing signal fifo_clr of the control register to clear the internal cache in the first-in first-out queue. (4) In order to reduce power consumption, one entropy source loop circuit can be enabled, the sampling frequency is configured to the lowest, and finally the random number generator is started to generate pseudo-random numbers. (5) Wait for the channel interrupt to be pulled high, read the corresponding interrupt status register, and read the pseudo-random number from the first-in first-out queue. After the reading is completed, configure the interrupt clear register to clear the interrupt and continue to wait for the next pseudo-random number to be ready.

[0103] In summary, the present application proposes a design and implementation method of a random number generator that meets the requirements of low power consumption, portability, and high efficiency, which can be used in various cryptographic computing business scenarios. The interface design of the present application covers the mainstream AMBA interface, which can be selected according to project needs, and can be quickly ported and integrated into the chip system; the control logic design has better timing and better performance, and reduces bit flipping to a certain extent, reducing power consumption. The control logic unit provides two ways to obtain random numbers: reading from registers and direct storage access reading by the system, which can adapt to different business scenarios and needs; the pseudo-random numbers output by the pseudo-random number unit are random and unpredictable, which can be used in various cryptographic business scenarios, and the generated pseudo-random numbers are highly efficient; the use process of the present application is concise and efficient, and is relatively friendly to firmware development and software adaptation. The present application also provides the above-mentioned complete hardware architecture and implementation steps.

[0104] Furthermore, an embodiment of the present application also provides an electronic device. Fig.10 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be considered as any limitation on the scope of use of the present application.

[0105] Fig.10A schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a display screen 23, an input / output interface 24, a communication interface 25, a power supply 26, and a communication bus 27. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the random number generation method disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0106] In this embodiment, the power supply 26 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 25 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 24 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0107] In addition, the memory 22, as a carrier for storing resources, may be a read-only memory, a random access memory, a disk or an optical disk, etc., and the resources stored thereon may include a computer program 221, and the storage method may be temporary storage or permanent storage. In addition to including a computer program that can be used to complete the random number generation method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 221 may further include a computer program that can be used to complete other specific tasks.

[0108] Furthermore, an embodiment of the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the random number generation method disclosed above is implemented.

[0109] For the specific steps of the method, reference may be made to the corresponding contents disclosed in the aforementioned embodiments, which will not be described in detail here.

[0110] Furthermore, an embodiment of the present application also discloses a computer program product, including a computer program / instruction, which implements the steps of the random number generation method disclosed above when executed by a processor.

[0111] The various embodiments in this application are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0112] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0113] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0114] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0115] The above is a detailed introduction to the random number generator, random number generation method, device and medium of an information encryption system provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A random number generator for an information encryption system, characterized in that: It includes a target bus transfer interface, a register unit, a logic control unit, an entropy source determination unit, a target processing unit, a health detection unit, a pseudo-random number generation unit and a cache unit, wherein: The target bus transfer interface is used to perform timing conversion on the register configuration command sent by the central processing unit to obtain a converted command, and send the converted command to the register unit; The register unit is used to configure each register according to the converted command; The logic control unit is used to generate control logic according to the configuration of the register, and control the workflow of the entropy source determination unit, the target processing unit and the health detection unit according to the control logic, and update the execution status of the workflow to the register unit; The entropy source determination unit is used to configure a target entropy source circuit according to the control logic, generate a true random number using the target entropy source circuit, and perform a first processing operation on the true random number; The target processing unit is used to select a target algorithm according to the control logic, and perform a second processing operation on the true random number after the first processing operation according to the target algorithm; The health detection unit is used to perform a health detection on the true random number that has undergone the second processing operation, and write the true random number that has passed the health detection into a target first-in-first-out queue in the cache unit; The pseudo-random number generating unit is used to obtain a pseudo-random number based on a target initialization result and a target time parameter, and write the pseudo-random number into the target first-in-first-out queue.

2. The random number generator of the information encryption system according to claim 1, characterized in that: The random number generator further comprises: An output selection unit is used to select, according to the control logic, to write the true random number into the target first-in-first-out queue through the health detection unit, or to select to write the pseudo-random number into the target first-in-first-out queue through the pseudo-random number generation unit.

3. The random number generator of the information encryption system according to claim 1, characterized in that: The pseudo-random number generating unit is used to perform an XOR operation on the target initialization result and a target encryption result obtained by encrypting the target time parameter using a preset encryption algorithm to obtain a first XOR result, and to encrypt the first XOR result using the preset encryption algorithm to obtain the pseudo-random number, and to write the pseudo-random number into the target first-in-first-out queue.

4. The random number generator of the information encryption system according to claim 3, characterized in that: The target initialization result is a result obtained by initializing the internal state of the pseudo-random number generation unit according to the configuration of the register, or a result obtained by initializing the internal state of the pseudo-random number generation unit based on the true random number after the second processing operation.

5. The random number generator of the information encryption system according to claim 1, characterized in that: The entropy source determination unit is used to configure the target entropy source circuit from multiple entropy source circuits according to the control logic, generate the true random number using the target entropy source circuit, perform an XOR operation on the true random number generated by the target entropy source circuit to obtain a second XOR result, perform sampling processing on the second XOR result to obtain a target sampling result, perform bit detection processing on the target sampling result to determine whether the target sampling result is all 0 bits or all 1 bits, and if not, perform serial-to-parallel conversion processing on the target sampling result to obtain the true random number after the first processing operation; Correspondingly, the target processing unit is used to select the target algorithm from a plurality of preset algorithms according to the control logic, and to operate the true random number after the first processing operation according to the target algorithm to obtain a target processing result, and to perform bit detection processing on the target processing result to determine whether the target processing result is all 0 bits or all 1 bits, and if not, to determine the target processing result as the true random number after the second processing operation; Correspondingly, the health detection unit is used to perform a health detection on the true random number that has undergone the second processing operation according to a preset health detection algorithm, and write the true random number that has passed the health detection into the target first-in-first-out queue; wherein the preset health detection algorithm includes a frequency test, a cumulative sum test, an autocorrelation test, a poker test, and a run test.

6. The random number generator of the information encryption system according to claim 1, characterized in that: The target bus adapter includes a peripheral bus adapter and a system bus adapter, and the peripheral bus adapter and the system bus adapter are isolated from each other through a macro definition mechanism.

7. The random number generator of the information encryption system according to claim 6, characterized in that: The peripheral bus conversion interface includes a peripheral bus to register read / write interface and a peripheral bus to first-in-first-out queue read interface, the system bus conversion interface includes a system bus to register read / write interface and a system bus to first-in-first-out queue read interface, and the peripheral bus to register read / write interface and the system bus to register read / write interface are connected to the advanced microcontroller bus structure for receiving register configuration commands sent by the central processing unit, the peripheral bus to first-in-first-out queue read interface and the system bus to first-in-first-out queue read interface are connected to the target first-in-first-out queue for sending the true random number or the pseudo-random number to the central processing unit.

8. A random number generation method for an information encryption system, characterized in that: include: Performing timing conversion on the register configuration command sent by the central processing unit through the target bus transfer interface in the random number generator to obtain a converted command, and sending the converted command to the register unit in the random number generator; configuring each register through the register unit and according to the converted command; Generate control logic through the logic control unit in the random number generator according to the configuration of the register, control the workflow of the entropy source determination unit, the target processing unit and the health detection unit in the random number generator according to the control logic, and update the execution status of the workflow to the register unit; configuring a target entropy source circuit through the entropy source determination unit and according to the control logic, then generating a true random number using the target entropy source circuit, and performing a first processing operation on the true random number; Selecting a target algorithm through the target processing unit and according to the control logic, and then performing a second processing operation on the true random number after the first processing operation according to the target algorithm; Performing a health check on the true random number that has undergone the second processing operation through the health check unit, and then writing the true random number that has passed the health check into a target first-in-first-out queue in a cache unit of the random number generator; A pseudo-random number is obtained through a pseudo-random number generation unit in the random number generator based on a target initialization result and a target time parameter, and then the pseudo-random number is written into the target first-in-first-out queue.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor is used to execute the computer program to implement the random number generation method of the information encryption system as claimed in claim 8.

10. A computer-readable storage medium, characterized in that: Used to store a computer program; wherein, when the computer program is executed by a processor, the random number generation method of the information encryption system as claimed in claim 8 is implemented.

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