Bus address allocation system and method, electronic equipment and readable storage medium

Abstract

The invention discloses a bus address distribution system and method, electronic equipment and a readable storage medium, and the electronic equipment is connected with a plurality of slaves through at least one RS485 port to realize data exchange, and is equipped with at least one IO port to send a trigger signal. The device carries a memory and a processor, and executes a bus address allocation control program. And the device generates and broadcasts the current address to be allocated, and activates the address occupation process of the first slave through the IO port. And the equipment monitors the bus, receives and confirms the address declaration of the slave, and updates the current slave, so that the current slave sends a new trigger signal after completing address occupation to trigger the address occupation process of the next slave. And if the declaration is not received overtime, address allocation is automatically ended. According to the invention, the host and the slave are allowed to be connected through the double RS485 ports and the IO ports which do not need to distinguish input and output, the installation efficiency and the system stability are improved, and dynamic address allocation and various network topology structures are supported.

Description

Technical Field

[0001] The present invention relates to the field of RS485 network technology, and in particular to a bus address allocation system, method, electronic equipment and readable storage medium. Background Art

[0002] RS485 is a differential signal transmission technology that allows long-distance, multi-node data transmission on a pair of twisted pairs. This technology is widely used in industrial automation, building automation, and remote monitoring systems. The RS485 bus system usually consists of a master device and multiple slave devices. The master device is responsible for controlling the communication process, while the slave device responds to the master device's request. In such a system, each device requires a unique address to ensure that the data can be correctly sent to the target device. Address allocation technology is the key to achieving this goal. The existing RS485 bus address allocation technology is divided into random allocation and ordered allocation. However, the existing address allocation technology has the following technical defects:

[0003] (1) Random allocation technology: Random address allocation may lead to address duplication, especially in large networks, which will cause communication conflicts. Random address allocation makes it difficult to identify the device type or location from the address, increasing the complexity of fault diagnosis. As the network scale expands, random allocation may be difficult to sustain and require more complex management strategies.

[0004] (2) Ordered allocation technology: Ordered allocation requires a strict wiring sequence. Wiring errors may cause communication failures or equipment damage. Once the system design is completed, adding or moving equipment may require rewiring, which limits the flexibility of the system. Communication between devices may be overly dependent on address order, reducing the system's fault tolerance. Summary of the invention

[0005] The main technical problem solved by the embodiments of the present invention is to provide a bus address allocation system, method, electronic device and readable storage medium, which solves the problem that wiring needs to strictly distinguish between input interfaces and output interfaces when RS485 addresses are allocated in an orderly manner, thereby simplifying the wiring steps, eliminating the error rate caused by wiring, and achieving the effect of improving the work efficiency of installers and improving the overall stability of the system.

[0006] To solve the above technical problems, a technical solution adopted by the present invention is: to provide an electronic device, comprising: at least one RS485 communication port, connected to the RS485 ports of multiple slaves on an RS485 bus; at least one IO port, connected to the IO port of a first slave; a first memory, used to store a bus address allocation control program; a first processor, used to call the bus address allocation control program stored in the first memory, and perform the following operations: generate and send an address information message, the address information message is broadcast to all slaves through the RS485 bus; wherein the address information message contains the current address to be allocated, triggering the slave to set its configured two IO ports to input state, and monitor the two IO ports; sending a trigger signal to the first slave through the IO port; monitoring the RS485 bus to receive an address occupation declaration message sent by the slave within a preset time, and sending an address confirmation message to the RS485 bus to confirm to all slaves that the current address to be allocated is occupied and the next address to be allocated; wherein In the embodiment, when the slave is set as the first slave, the first slave responds to the trigger signal sent by the host, selects to occupy the current address to be allocated according to the address information message, and sends the address occupation declaration message to the RS485 bus to declare to the host and other slaves that the current address to be allocated is occupied, and sends a trigger signal to the next slave connected to the IO port set with it; when the slave is set as the remaining slaves except the first slave, the slave responds to the trigger signal sent by the previous slave connected to its IO port, selects to occupy the current address to be allocated according to the address information message, and sends the address occupation declaration message to the RS485 bus to declare to the host and other slaves that the current address to be allocated is occupied, and sends a trigger signal to the next slave connected to the IO port set with it; when the RS485 bus is monitored and no address occupation declaration message sent by the slave is received within a preset time, it is confirmed that the address allocation is successful and an end address allocation message is sent to all slaves through the RS485 bus.

[0007] Among them, the first processor is also used to call the bus address allocation control program stored in the first memory, and perform the following operations: in the step of generating and sending an address information message, before the address information message is broadcast to all slaves through the RS485 bus, respond to the user's operation to enter the total number N of slaves to be allocated addresses; wherein N is a natural number; after the step of confirming that the address allocation is successful and sending the end address allocation message to all slaves through the RS485 bus, count the number n of slaves to which the addresses are successfully allocated; compare the number of slaves n obtained by statistics with the number of slaves N input by the user to confirm that the address allocation is consistent, confirm that the address allocation is successful and the address allocation process ends; compare the number of slaves n obtained by statistics with the number of slaves N input by the user to confirm that the address allocation is inconsistent, confirm that the address allocation is wrong and report an error, and then the address allocation process ends.

[0008] To solve the above technical problems, another technical solution adopted by the present invention is: to provide an electronic device, comprising: two RS485 ports, wherein one RS485 port is connected to an RS485 bus with an RS485 port of a host and RS485 ports of multiple slaves, and the other RS485 port is connected to an RS485 port of a next slave adjacent thereto, and the two RS485 ports are internally connected; two IO ports, wherein one IO port is connected to an IO port of the adjacent host or a previous slave, and the other IO port is connected to an IO port of the next slave; a second memory for storing a total of The second processor is used to call the bus address allocation control program stored in the second memory, and perform the following operations: receiving an address information message sent by the host through the RS485 port; wherein the address information message is generated by the host and broadcast to all slaves through the RS485 bus; the address information message contains the current address to be allocated; setting the two IO ports to the input state; monitoring the two IO ports set to the input state, and when any one of the IO ports monitors a trigger signal, responding to the trigger signal, selecting to occupy the current address to be allocated according to the address information message, and sending the address information message to the RS485 port. 5 bus sends an address occupation declaration message to declare to the host and other slaves that the current address to be allocated is occupied; wherein, when the slave is set to be the first slave, the trigger signal is sent by the host; when the slave is set to be a slave other than the first slave, the trigger signal is sent by the last slave connected to the IO port set to the input state; when the RS485 port receives the address confirmation message sent by the host, the vacant IO port is set to the output state; wherein, the address confirmation message is generated by the host after receiving the address occupation declaration message through the RS485 bus, and the address confirmation message includes sending a message to all slaves. The host sends a confirmation that the current address to be allocated is occupied and the next address to be allocated; sends a trigger signal to the next slave connected to the IO port set to the output state through the IO port set to the output state; wherein, the trigger signal is used to trigger the next slave to call and execute the bus address allocation control program; when the RS485 port is monitored to receive the end address information allocation message sent by the host, it is confirmed that the slave address allocation is completed; wherein, the end address information allocation message is generated when the host does not receive the address occupation declaration message sent by the slave within the preset time by monitoring the RS485 bus, and confirms that all addresses are allocated successfully.

[0009] To solve the above technical problems, another technical solution adopted by the present invention is: to provide a bus address allocation method, the method is applied to the electronic device as described above, the method comprising: generating and sending an address information message, the address information message is broadcast to all slaves through the RS485 bus; wherein, the address information message contains the current address to be allocated, triggering the slave connected to the RS485 bus to set its configured two IO ports to input state, and monitor the two IO ports; sending a trigger signal to the first slave connected to it through the IO port configured by the host; monitoring the RS485 bus to receive the address occupation declaration message sent by the slave within a preset time, and sending an address confirmation message to the RS485 bus to confirm to all slaves that the current address to be allocated is occupied and the next address to be allocated; wherein, when the slave is set to the first slave, the first slave responds to the trigger signal sent by the host. No., selects to occupy the current address to be allocated according to the address information message, and sends the address occupation declaration message to the RS485 bus to declare to the host and other slaves that the current address to be allocated is occupied, and sends a trigger signal to the next slave connected to the IO port set with it; when the slave is set to the remaining slaves except the first slave, the slave responds to the trigger signal sent by the previous slave connected to its IO port, selects to occupy the current address to be allocated according to the address information message, and sends the address occupation declaration message to the RS485 bus to declare to the host and other slaves that the current address to be allocated is occupied, and sends a trigger signal to the next slave connected to the IO port set with it; monitors the RS485 bus to confirm that the address allocation is successful and sends an end address allocation message to all slaves through the RS485 bus when no address occupation declaration message sent by the slave is received within a preset time.

[0010] Among them, it also includes: in the step of generating and sending an address information message, before the address information message is broadcast to all slaves through the RS485 bus, the method also includes: responding to the user's operation to enter the total number N of slaves to be assigned addresses; wherein N is a natural number; after the step of confirming that the address allocation is successful and sending the end address allocation message to all slaves through the RS485 bus, the method also includes: counting the number n of slaves to which the addresses are successfully assigned; comparing the number n of slaves obtained by statistics with the number N of slaves input by the user to be consistent, confirming that the address allocation is successful and the address allocation process is terminated; comparing the number n of slaves obtained by statistics with the number N of slaves input by the user to be inconsistent, confirming that the address allocation is wrong and reporting an error, and then the address allocation process is terminated.

[0011] In order to solve the above technical problems, another technical solution adopted by the present invention is: to provide a bus address allocation method, the method is applied to the electronic device as described above, the method comprising: receiving an address information message sent by a host through an RS485 port; wherein the address information message is generated by the host and broadcast to all slaves through an RS485 bus; the address information message contains the current address to be allocated; setting two IO ports to input status; monitoring two IO ports set to input status, and when any one of the IO ports monitors a trigger signal, responding to the trigger signal, selecting to occupy the current address to be allocated according to the address information message, and sending an address occupation declaration message to the RS485 bus to declare to the host and the remaining slaves that the current address to be allocated is occupied; wherein, when the slave is set to the first slave, the trigger signal is sent by the host; when the slave is set to the second slave or the remaining slaves, the trigger signal is sent by the slaves set to the input status. The method comprises the following steps: sending a trigger signal to the next slave connected to the IO port set to the output state through the IO port set to the output state; sending a trigger signal to the next slave connected to the IO port set to the output state through the IO port set to the output state; and confirming that the slave address allocation is completed when the RS485 port receives the end address information allocation message sent by the host; wherein, the end address information allocation message is generated when the host does not receive the address occupation declaration message sent by the slave within the preset time by monitoring the RS485 bus, and confirming that all addresses are successfully allocated.

[0012] In order to solve the above technical problems, another technical solution adopted by the present invention is: to provide a bus address allocation system, the system includes a host and multiple slaves; the host includes: at least one RS485 communication port, connected to the RS485 bus with the RS485 ports of multiple slaves; at least one IO port, connected to the IO port of the first slave; a first memory, used to store a bus address allocation control program; a first processor, used to call the bus address allocation control program stored in the first memory, and perform the following operations: generate and send an address information message, the address information message is broadcast to all slaves through the RS485 bus; wherein the address information message contains the current address to be allocated; Send a trigger signal to the first slave through the IO port; when the RS485 bus is monitored to receive an address occupation declaration message sent by the slave within a preset time, an address confirmation message is sent to the RS485 bus to confirm to all slaves that the current address to be allocated is occupied and the next address to be allocated; when the RS485 bus is monitored to not receive an address occupation declaration message sent by the slave within a preset time, the address allocation is confirmed to be successful and an address allocation end message is sent to all slaves through the RS485 bus; the slave includes: two RS485 ports, one of which is connected to the RS485 bus with the RS485 port of the host and the RS485 ports of multiple slaves; the other RS485 port and The first embodiment comprises a first IO port connected to the RS485 port of the next slave adjacent to it, wherein the two RS485 ports are internally connected; two IO ports, wherein one IO port is connected to the IO port of the adjacent host or the previous slave; and the other IO port is connected to the IO port of the next slave; a second memory for storing a bus address allocation control program; a second processor for calling the bus address allocation control program stored in the second memory, and performing the following operations: receiving an address information message sent by the host through the RS485 port; setting the two IO ports to the input state; monitoring the two IO ports set to the input state, and when any IO port monitors a trigger signal, responding to the trigger signal, and The address information message selects to occupy the current address to be allocated, and sends an address occupation declaration message to the RS485 bus to declare to the host and other slaves that the current address to be allocated is occupied; wherein, when the slave is set to the first slave, the trigger signal is sent by the host; when the slave is set to the remaining slaves except the first slave, the trigger signal is sent by the previous slave connected to the IO port set to the input state; when the RS485 port is monitored to receive the address confirmation message sent by the host, the vacant IO port is set to the output state; a trigger signal is sent to the next slave through the IO port set to the output state to trigger the next slave to call and execute the bus address allocation control program;When the RS485 port receives the end address information allocation message sent by the host, it confirms that the slave address allocation is completed. ;

[0013] Among them, the first processor is also used to call the bus address allocation control program stored in the first memory, and perform the following operations: before generating and sending an address information message, and before the address information message is broadcast to all slaves through the RS485 bus, respond to the user's operation to enter the total number N of slaves to be allocated addresses; wherein N is a natural number; after confirming that the address allocation is successful and sending an end address allocation message to all slaves through the RS485 bus, count the number n of slaves to which the addresses are successfully allocated; compare the number of slaves n obtained by statistics with the number of slaves N input by the user to confirm that the address allocation is successful and the address allocation process ends; compare the number of slaves n obtained by statistics with the number of slaves N input by the user to confirm that the address allocation is inconsistent, confirm that the address allocation is wrong and report an error, and then the address allocation process ends.

[0014] To solve the above technical problems, another technical solution adopted by the present invention is: providing a computer-readable storage medium, wherein the computer-readable storage medium stores a bus address allocation control program of a host, and when the control program of the host is executed by a processor, the steps of the bus address allocation method as described above are implemented.

[0015] To solve the above technical problems, another technical solution adopted by the present invention is: a computer-readable storage medium, which stores a bus address allocation control program of a slave machine, and when the control program of the slave machine is executed by a processor, the steps of the bus address allocation method as described above are implemented.

[0016] The beneficial effects of the embodiments of the present invention are as follows: Different from the prior art, the host and the slave in the embodiments of the present invention are equipped with two RS485 ports and two IO ports. The two RS485 ports and the two IO ports of the slave do not need to distinguish between input and output. The two RS485 ports are directly connected inside the slave to ensure that all ports are connected to the RS485 bus; there is no need to distinguish between input and output ports, the wiring steps are greatly simplified, the possibility of wiring errors is reduced, and the simplified wiring and automated address allocation process improve the work efficiency of the installer. By ensuring that only one slave is in the trigger state at the same time, the system reduces address conflicts and communication errors and enhances stability. Even when a slave fails, the design of the system allows other slaves to continue to work normally, improving the overall fault tolerance. Since the address allocation is dynamic, the system can be easily expanded to add more slaves without rewiring. Automated address allocation and trigger signal transmission reduce manual intervention and reduce the error rate of operation. Due to the versatility of the port, the system can adapt to different network topologies, including linear, tree or star structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a structural schematic diagram of a bus address allocation system in an embodiment of the present invention;

[0018] Figure 2 is a schematic diagram of the terminal structure of the hardware operating environment involved in the implementation manner of the present invention;

[0019] Figure 3 is a schematic diagram of a terminal structure of a hardware operating environment involved in another embodiment of the present invention;

[0020] Figure 4 is a flow chart of a bus address allocation method in an embodiment of the present invention;

[0021] Figure 5 is a flow chart of a bus address allocation method in another embodiment of the present invention;

[0022] Figure 6 It is a flowchart of a bus address allocation method in another embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to more clearly understand the above-mentioned purposes, features and advantages of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0024] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, and the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0026] It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be an intermediate component at the same time.

[0027] See also Figure 1, is a structural diagram of a bus address allocation system in an implementation manner of the present invention.

[0028] The system 100 includes a host 11 and multiple slaves 12; the host 11 and the multiple slaves 12 form a hierarchical communication network, and communicate using the RS485 bus and the IO port of the single-chip microcomputer. Among them, the host 11 can be a central control unit, manager or coordinator, responsible for the management and address allocation tasks of the entire system. The slaves 12 can be various types of sensors, actuators or devices with specific functions, such as temperature sensors, motor drivers, etc.

[0029] The host 11 includes:

[0030] At least one RS485 port for exchanging data with the slave 12;

[0031] At least one IO port is used to send a trigger signal to the slave 12 .

[0032] The slave machine 12 comprises:

[0033] Two RS485 ports for receiving address information and communicating with other slaves or hosts; the two RS485 ports are internally connected to achieve two-way transmission of signals without distinguishing between input and output;

[0034] Two IO ports, one for receiving the trigger signal from the previous slave or master, and the other for passing the trigger signal to the next slave.

[0035] The RS485 ports of the host 11 and all the slaves 12 are connected to a shared RS485 bus to form a bus-type network structure.

[0036] The IO port of the host 11 is connected to the IO port of the first slave 12a, and then the spare IO port of each slave is connected to the IO port of the next slave in turn, forming a chain structure.

[0037] The trigger signal starts from the master 11 and is transmitted to each slave through the cascaded IO ports to ensure the synchronization of the address allocation process.

[0038] Furthermore, the RS485 port and the IO port can be physically connected through the same wiring harness, simplifying the wiring. The RS485 port of the last slave is vacant and a termination resistor can be installed to prevent signal reflection.

[0039] The specific connection method of the host 11 and the multiple slaves 12 is: one RS485 port of the host 11 is connected to any RS485 port of the first slave 12a; the spare RS485 port of the first slave 12a is connected to any RS485 port of the second slave 12b; the spare RS485 port of the second slave 12b is connected to any RS485 port of the third slave 12c;

[0040] …

[0041] The spare RS485 port of the (n-1)th slave 12(n-1) is connected to any RS485 port of the nth slave 12n; the spare RS485 port of the nth slave 12n is left vacant.

[0042] At the same time, the two RS485 ports are directly connected inside each slave.

[0043] In this way, all RS485 ports of the host 11 and the n slaves 12 are directly connected to the RS485 bus.

[0044] An IO port of the host 11 is connected to any IO port of the first slave 12a; the spare IO port of the first slave 12a is connected to any IO port of the second slave 12b; the spare IO port of the second slave 12b is connected to any IO port of the three slaves 12c;

[0045] …

[0046] The spare IO port of the (n-1)th slave 12(n-1) is connected to any IO port of the nth slave 12n; the spare IO port of the nth slave 12n is vacant.

[0047] In this way, except for the last slave 12n, the IO ports of all other slaves are connected to one and only one IO port of another slave.

[0048] During the communication process, the host 11 and the slave 12 transmit address information via the RS485 bus, and the system 100 transmits a trigger signal via the cascaded IO port to ensure that only one slave 12 is in a triggered state at the same time and is allowed to send address information to the RS485 bus.

[0049] The specific principle of the bus address allocation method implemented by the bus address allocation system 10 is as follows.

[0050] See also Figure 2 , is a schematic diagram of the terminal structure of the hardware operating environment involved in the implementation manner of the present invention.

[0051] The terminal in the embodiment of the present invention may be the host 11 in the bus allocation system 10 or a control terminal of the host 11 .

[0052] like Figure 2 As shown, the terminal may include: a first processor 110 , such as a CPU, a first memory 111 and a first communication bus 112 .

[0053] The first communication bus 112 is used to realize the connection and communication between these components. The first memory 111 can be a high-speed RAM memory or a stable memory (non-volatile memory), such as a disk memory. The first memory 111 can also be a storage device independent of the first processor 110.

[0054] Those skilled in the art will understand that Figure 2 The terminal structure shown in the figure does not constitute a limitation on the terminal, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0055] like Figure 2 As shown, the first memory 111 as a computer storage medium may include an operating system and a bus address allocation control program.

[0056] exist Figure 2 In the terminal shown, the processor 110 can be used to call the bus address allocation control program stored in the memory 111 and perform the following operations:

[0057] Responding to the user's operation to enter the total number N of slaves to be assigned addresses; wherein N is a natural number;

[0058] Generate and send an address information message, which is broadcast to all slaves via the RS485 bus; wherein the address information message includes address allocation start information and the current address to be allocated, triggering the slave to set its two configured IO ports to input state and monitor the two IO ports;

[0059] Send a trigger signal to the first slave through the IO port;

[0060] Monitor the RS485 bus to receive the address occupation declaration message sent by the slave within a preset time, and confirm to all slaves that the current address to be allocated is occupied and the next address to be allocated by sending an address confirmation message to the RS485 bus; wherein, when the slave is set to the first slave, the first slave responds to the trigger signal sent by the host to select to occupy the current address to be allocated according to the address information message, and sends the address occupation declaration message to the RS485 bus to declare to the host and the remaining slaves that the current address to be allocated is occupied, and sends a trigger signal to the next slave connected to the IO port set with it; when the slave is set to the remaining slaves except the first slave, the slave responds to the trigger signal sent by the previous slave connected to its IO port, selects to occupy the current address to be allocated according to the address information message, and sends the address occupation declaration message to the RS485 bus to declare to the host and the remaining slaves that the current address to be allocated is occupied, and sends a trigger signal to the next slave connected to the IO port set with it;

[0061] When the RS485 bus is monitored and no address occupation declaration message sent by the slave is received within a preset time, the address allocation is confirmed to be successful and an end address allocation message is sent to all slaves via the RS485 bus.

[0062] Further, the processor 110 may call the bus address allocation control program stored in the memory 111, and further perform the following operations:

[0063] Before generating and sending an address information message, which is broadcast to all slaves via the RS485 bus, responding to a user's operation to enter the total number N of slaves to be assigned addresses; wherein N is a natural number;

[0064] After confirming that the address allocation is successful and sending the end address allocation message to all slaves via the RS485 bus, the number of slaves to which the addresses are successfully allocated, n, is counted;

[0065] Compare and verify that the number of slaves n obtained by statistics is consistent with the number of slaves N input by the user, confirming that the address allocation is successful and the address allocation process is completed;

[0066] The number of slaves n obtained by comparison and statistics is inconsistent with the number of slaves N input by the user, and the address allocation error is confirmed and reported, and then the address allocation process ends.

[0067] See also Figure 3 , is a schematic diagram of the terminal structure of the hardware operating environment involved in another embodiment of the present invention.

[0068] The terminal in the embodiment of the present invention is the slave 12 in the bus distribution system 10 or the control terminal of the slave 12 .

[0069] like Figure 3 As shown, the terminal may include: a second processor 120 , such as a CPU, a second memory 121 , and a second communication bus 122 .

[0070] The second communication bus 122 is used to realize the connection and communication between these components. The second memory 121 can be a high-speed RAM memory or a stable memory (non-volatile memory), such as a disk memory. The second memory 121 can also be a storage device independent of the aforementioned second processor 120.

[0071] Those skilled in the art will understand that Figure 3 The terminal structure shown in the figure does not constitute a limitation on the terminal, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0072] like Figure 3 As shown, the second memory 121 as a computer storage medium may include an operating system and a bus address allocation control program.

[0073] exist Figure 3 In the terminal shown, the second processor 120 can be used to call the bus address allocation control program stored in the second memory 121 and perform the following operations:

[0074] Receiving an address information message sent by the host through the RS485 port; wherein the address information message is generated by the host and broadcast to all slaves through the RS485 bus; the address information message includes the current address to be assigned;

[0075] Set the two IO ports to input state;

[0076] Monitor two IO ports set to input state, and when any one of the IO ports monitors a trigger signal, respond to the trigger signal, select to occupy the current address to be allocated according to the address information message, and send an address occupation declaration message to the RS485 bus to declare to the host and other slaves that the current address to be allocated is occupied; wherein, when the slave is set to the first slave, the trigger signal is sent by the host; when the slave is set to the remaining slaves except the first slave, the trigger signal is sent by the previous slave connected to the IO port set to the input state;

[0077] When the monitoring RS485 port receives an address confirmation message sent by the host, the vacant IO port is set to an output state; wherein the address confirmation message is generated by the host after receiving the address occupation declaration message through the RS485 bus, and the address confirmation message includes a confirmation that the current address to be allocated is occupied and the next address to be allocated sent to all slaves;

[0078] Sending a trigger signal to the next slave connected to the IO port set to the output state through the IO port set to the output state; wherein the trigger signal is used to trigger the next slave to call and execute the bus address allocation control program;

[0079] When the RS485 port is monitored and receives the end address information allocation message sent by the host, it is confirmed that the slave address allocation is completed; wherein, the end address information allocation message is generated when the host does not receive the address occupancy declaration message sent by the slave within a preset time by monitoring the RS485 bus and confirms that all addresses are allocated successfully.

[0080] See also Figure 4 , is a flow chart of a bus address allocation method in an embodiment of the present invention. The method is applied to the bus address allocation system as described above, and includes:

[0081] Step S200, the host responds to the user's input operation to input the number N of slaves to be assigned addresses, and sends an address information message through the RS485 bus.

[0082] The address information message includes address allocation start information and a first address to be allocated.

[0083] The address allocation start information may include: an initialization signal, which is used to inform all devices that the address allocation process is about to begin; a control instruction, such as "start address allocation" or a similar command, which instructs the slave to perform a specific initialization operation; an address range, which contains information about the address range to be allocated, such as the start address and the end address; and an address allocation rule, such as a specific allocation rule or sequence. This information provides the necessary context and parameters for the address allocation process, ensuring that all participating slaves can correctly understand and execute each step in the address allocation process.

[0084] Step S201: the host sends a trigger signal to the first slave through the IO port.

[0085] The IO port of the host is connected to any IO port of the first slave.

[0086] Specifically, the host delays x seconds after sending the address information message, and sends a trigger signal to the first slave through the IO port.

[0087] The trigger signal may be a level conversion signal or a pulse signal.

[0088] In step S202, the first slave receives a trigger signal from the host through the IO port, occupies the first address accordingly according to the address information message, and sends a first address occupation declaration message to the RS485 bus to declare to the host and other slaves that the first slave occupies the first address.

[0089] Specifically, at the same time as receiving the trigger signal, the first slave has received the address information message sent by the host through the RS485 bus, and the address information message includes address allocation start information and the first address to be allocated, for example, the address allocation start information is an address range or address allocation rule. The first slave determines its own address based on this information. In the scenario of the present invention, it is assumed that the first slave occupies the first address. When the first slave determines its own address, it declares to the host and other slaves that it has occupied this address, and sends a first address occupation declaration message to the RS485 bus to declare to the host and other slaves that the first slave occupies the first address. The first address occupation declaration message includes the identification information of the first slave and the occupied first address information, for example: "Slave 1 occupies address 1".

[0090] In this way, the first slave can autonomously determine and declare its own address based on the received trigger signal and address information message without physically distinguishing the input and output ports. This process ensures the orderliness and uniqueness of address allocation, while avoiding address conflicts and improving the stability and reliability of the system. The first slave broadcasts a message containing its address occupation declaration through the RS485 bus, which will be received by the host and all other slaves. This mechanism allows all devices in the system to understand the current address allocation status in real time, ensuring the transparency and synchronization of the address allocation process.

[0091] Step S203, the host receives the first address occupation declaration message sent by the first slave through the RS485 bus, and sends a first address confirmation message to the RS485 bus to confirm the occupation of the first address and the second address to be allocated to all slaves.

[0092] Specifically, the host receives the first address occupation declaration message sent by the first slave through the RS485 bus, and parses the first address occupation declaration message to identify that the first slave has occupied the first address. When the address declaration of the first slave is confirmed to be valid, the host generates a first address confirmation message; wherein the first address confirmation message confirms the first address occupied by the first slave, and also contains information about the second address to be allocated. The host sends the first address confirmation message through the RS485 bus. The first address confirmation message is a response to the first address occupation declaration message of the first slave, and is also a broadcast to all other slaves in the system, informing other slaves that the first address has been occupied and the next address is about to be allocated.

[0093] Furthermore, while sending the first address confirmation message, the host updates its internal address allocation status, records that the first address has been occupied, and prepares to allocate the next address, ie, the second address.

[0094] In this way, the host not only confirms the address occupied by the first slave, but also effectively manages the address allocation process of the entire system, ensuring the orderliness of address allocation and the stability of the system. At the same time, this mechanism also improves the transparency of the address allocation process, because all slaves can understand the current address allocation status in real time.

[0095] Step S204, after receiving the first address confirmation message, the first slave sets its own free IO port to an output state, and sends a trigger signal to the second slave through the IO port.

[0096] Specifically, the first slave parses the first address confirmation message received from the master to confirm that its address claim has been accepted and to learn the next address information to be assigned. After confirming its own address, the first slave switches its free IO port that was previously set to input state to output state, for sending a trigger signal to the next slave. The first slave sends a trigger signal to the second slave through the IO port that is newly set to output state. The trigger signal is used to inform the second slave that it is now its turn to make an address claim.

[0097] In this embodiment, the trigger signal is transmitted from the first slave to the IO port of the second slave via a physical connection (eg, a cable or a wiring harness).

[0098] Step S205, the second slave receives a trigger signal from the first slave at its IO port set to input state, selects a second address according to the first address confirmation message received from the RS485 bus, and sends a second address occupation declaration message to the RS485 bus to declare to the host and other slaves that the second slave occupies the second address.

[0099] Step S206, the host receives the second address occupation declaration message sent by the second slave through the RS485 bus, and sends a second address confirmation message to the RS485 bus to confirm the occupation of the second address and the third address to be allocated to all slaves.

[0100] Step S207, after receiving the second address confirmation message, the second slave sets its own free IO port to output state, and sends a trigger signal to the third slave through the IO port.

[0101] …

[0102] As described in steps S202 to S207, and so on, the host continues to monitor the RS485 bus, receives the address occupation declaration message sent by each slave in sequence, and for each address occupation declaration message sent by the slave, the host generates and sends a corresponding address confirmation message to confirm that the address occupation is valid, and broadcasts the information of the next address to be allocated.

[0103] Step S208, the n-1th slave receives a trigger signal from the n-2th slave on its IO port set to input state, selects the n-1th address according to the n-2th address confirmation message received from the RS485 bus, and sends the n-1th address occupation declaration message to the RS485 bus to declare to the host and other slaves that the n-1th slave occupies the n-1th address.

[0104] Step S209, the host receives the n-1th address occupation declaration message sent by the n-1th slave through the RS485 bus, and sends the n-1th address confirmation message to the RS485 bus to confirm the occupation of the n-1th address and the nth address to be allocated to all slaves.

[0105] Step S210, after receiving the nth address confirmation message, the (n-1)th slave sets its own free IO port to an output state, and sends a trigger signal to the nth slave through the IO port.

[0106] Step S211, the nth slave receives a trigger signal from the n-1th slave on its IO port set to input state, selects the nth address according to the n-1th address confirmation message received from the RS485 bus, and sends the nth address occupation declaration message to the RS485 bus to declare to the host and other slaves that the nth slave occupies the nth address.

[0107] Step S212, the host receives the nth address occupation declaration message sent by the nth slave through the RS485 bus, and sends the nth address confirmation message to the RS485 bus to confirm the occupation of the nth address and the n+1th address to be allocated to all slaves.

[0108] Step S213, after receiving the nth address confirmation message, the nth slave sets its own free IO port to output state and sends a trigger signal through the IO port.

[0109] Step S214, the host starts the timer, and if it does not listen to the n+1th address occupation declaration message within the preset time, it executes statistics to see whether the number n of slaves is consistent with the input number N; if so, the address allocation is successful and the process ends; otherwise, the address allocation fails and an error is reported, and then the process ends.

[0110] Although the nth slave is the last slave, it still sets its free IO ports to output state. This is to maintain the consistency and expected behavior of the system, even if there are no more slaves to receive the trigger signal in this scenario. The nth slave attempts to send a trigger signal to the n+1th slave through the IO port set to output state. However, since this is the last slave, there is actually no n+1th slave to receive this signal. After sending the nth address occupation declaration message, the host starts a preset timeout timer. When the timeout period arrives, the host checks whether it has received the address occupation declaration messages of all expected slaves. Specifically, the host confirms the number of slaves n by counting the addresses that have been successfully allocated.

[0111] If the counted number of slaves n is consistent with the number of slaves N initially input by the user, the host considers that the address allocation is successful and may send a message or signal to end the address allocation to notify all slaves that the address allocation process is complete.

[0112] If the counted number of slaves n is inconsistent with the input number N, it means that some slaves have failed to successfully allocate addresses or report their address occupancy, and the host will report an error. This error may be notified to the user by sending an error message, activating an alarm system, or displaying an error message on the user interface. Furthermore, by counting the number of slaves n, the host can determine that the slave with an address allocation error is the n+1th slave, thereby locating the fault through the statistical number, ensuring that once a problem with address allocation occurs, it can be quickly discovered and measures can be taken to correct it, while protecting the stability and reliability of the entire system.

[0113] It should be noted that in the case of an error, the system may need to perform error recovery or manual intervention, which may include rechecking the physical connection, slave configuration or restarting the address allocation process, and executing steps S200 to S214 as described above, which will not be repeated here.

[0114] It should be noted that, in order to facilitate the explanation of the bus address allocation method, the number of slaves to be allocated addresses in the system is pre-set to n. Under this premise, if Figure 4In the bus address allocation method, after the address allocation of n slaves is completed in step S214, a timer is started to determine whether the address allocation is completed. However, in reality, after the host receives an address occupation declaration message sent by a slave, on the one hand, it sends the address confirmation message to the RS485 bus to confirm the occupation of the address and the next address to be allocated to all slaves, and on the other hand, it starts the timer to monitor the RS485 bus to determine whether the next address occupation declaration message is received within a preset time. The specific principle can be found in Figure 5 and corresponding text description.

[0115] Please also see Figure 5 , is a flow chart of a bus address allocation method in another embodiment of the present invention, the method is applied to the host as described above, and comprises:

[0116] Step S300: The host responds to the user's input operation to input the total number N of slaves to be assigned addresses.

[0117] Step S301: the host generates and sends an address information message, which is broadcast to all slaves via the RS485 bus.

[0118] The address information message includes the current address to be allocated; the address allocation start information triggers the slave connected to the RS485 bus to set its two configured IO ports to input state and monitor the two IO ports.

[0119] Step S302: the host sends a trigger signal to the first slave connected to it through the configured IO port.

[0120] In step S303, the host monitors the RS485 bus to determine whether the address occupation declaration message sent by the slave is received within a preset time; if so, proceed to step S304; otherwise, proceed to step S305.

[0121] Among them, when the slave is set to the first slave, the first slave responds to the trigger signal sent by the host to call and execute the bus address allocation program, selects to occupy the current address to be allocated (i.e., the first address) according to the address information message, and sends the address occupation declaration message to the RS485 bus to declare to the host and the remaining slaves that the current address to be allocated (i.e., the first address) is occupied; when the slave is set to the remaining slaves except the first slave, the slave responds to the trigger signal sent by the previous slave connected to its IO port to call and execute the bus address allocation program, selects to occupy the current address to be allocated according to the address information message, and sends the address occupation declaration message to the RS485 bus to declare to the host and the remaining slaves that the current address to be allocated is occupied.

[0122] In this embodiment, when the host receives the address occupation declaration message sent by the current slave within the preset time, the host increases the count of the slaves to which the address is successfully allocated by one, so as to record the number of slaves to which the address allocation has been successfully completed.

[0123] As described in the bus address allocation system in the embodiment of the present invention, since the IO port of the host is not actually connected to the second slave and its subsequent slaves on the communication chain, the host will not directly send a trigger signal to the second slave and its subsequent slaves through the IO port. The host sends a trigger signal through the IO port when the first slave is configured, and the second slave and its subsequent slaves are assigned addresses by receiving the trigger signal sent through the IO port by the previous slave that has completed the address occupation declaration. Therefore, after completing the sending of the trigger signal to the first slave, the host starts the timer and enters the listening state to monitor whether the RS485 bus receives the address occupation declaration message sent by the slave (including any slave including the first slave, that is, the slave currently triggered to declare address occupation) during address allocation; if so, it means that the slave has not yet completed the address allocation; otherwise, it means that the remaining slaves have completed the address allocation.

[0124] Step S304: the host sends an address confirmation message to the RS485 bus to confirm to all slaves that the current address to be allocated is occupied and the next address to be allocated. Then, the process returns to step S303.

[0125] Step S305: the host sends an end address allocation message to all slaves via the RS485 bus.

[0126] Step S306, counting the number n of slaves to which addresses are successfully allocated.

[0127] In step S307, the host compares the number of slaves n obtained by statistics with the number of slaves N input by the user to see if they are consistent; if so, the address allocation is successful and the process ends; otherwise, it goes to step S308.

[0128] Step S308: an address allocation error occurs and an error is reported, and then the process ends.

[0129] See also Figure 6 , is a flow chart of a bus address allocation method in another embodiment of the present invention. The method is applied to the slave as described above, and comprises:

[0130] Step S400: The slave receives the address information message sent by the host through the RS485 port.

[0131] The address information message is generated by the host and broadcast to all slaves through the RS485 bus; the address information message includes the current address to be allocated.

[0132] Step S401: The slave sets two IO ports to input state.

[0133] In step S402, the slave monitors two IO ports set to input state, and determines whether any IO port monitors a trigger signal; if so, proceed to step S403; otherwise, continue to execute step S402.

[0134] The trigger signal is sent by the host or the previous slave through the IO port; specifically, when the slave is set as the first slave, the trigger signal it receives is sent by the host; when the slave is set as the second slave or subsequent slave, the trigger signal it receives is sent by the previous slave.

[0135] Step S403, the slave responds to the received trigger signal, selects to occupy the current address to be allocated according to the address information message, and sends an address occupation declaration message to the RS485 bus to declare to the host and other slaves that the address to be allocated is occupied.

[0136] When the slave is set as the first slave, the trigger signal is sent by the host; when the slave is set as the second slave or any other slave, the trigger signal is sent by the previous slave adjacent to it.

[0137] Specifically, in response to the received trigger signal, the slave selects the address information to be allocated as the occupied address according to the address information message.

[0138] Step S404, the slave monitors the RS485 port to determine whether the address confirmation message sent by the master is received. If yes, proceed to step S405; otherwise, continue to execute step S404.

[0139] The address confirmation message is generated by the host after receiving the address occupation declaration message through the RS485 bus, and the address confirmation message includes a message sent to all slaves confirming that the current address to be allocated is occupied and the next address to be allocated.

[0140] Step S405: The slave sets the spare IO port to output state.

[0141] Step S406: The slave sends a trigger signal to the next slave connected to it through the IO port set to the output state.

[0142] When the new trigger signal is sent to the next slave, it is used to trigger the next slave to call and execute the bus address allocation method, execute steps S401 to S406, complete the occupation of the corresponding address to be allocated and trigger the address allocation of the next slave; this cycle is repeated to complete the allocation of all slave addresses.

[0143] Step S407, the slave monitors the RS485 port to determine whether it has received the end address information allocation message sent by the host; if so, the process ends (the current slave address allocation ends); otherwise, continue to execute step S407.

[0144] The end address information allocation message is generated when the host fails to receive the address occupation declaration message sent by the slave within a preset time by monitoring the RS485 bus and the timing exceeds the preset time, and confirms that all addresses are allocated successfully.

[0145] The embodiments of the present invention provide a bus address allocation system, method, electronic device and readable storage medium. Both a host and a slave are equipped with two RS485 ports and two IO ports. The two RS485 ports and two IO ports of the slave do not need to distinguish between input and output. The two RS485 ports are directly connected inside the slave to ensure that all ports are connected to the RS485 bus. The host sends an address information message through the RS485 bus, and the slave occupies and confirms the address according to the information. The host dynamically updates and allocates the address according to the address occupancy information fed back by the slave. The system transmits a trigger signal through the cascaded IO ports to ensure that only one slave is in a triggered state at the same time, thereby performing address allocation in an orderly manner. The slave monitors the address occupancy and confirmation information from the RS485 bus, as well as the signal for ending address allocation.

[0146] Since there is no need to distinguish between input and output ports, the wiring steps are greatly simplified, reducing the possibility of wiring errors. The simplified wiring and automated address assignment process improve the work efficiency of installers. By ensuring that only one slave is in the trigger state at the same time, the system reduces address conflicts and communication errors and enhances stability. Even when a slave fails, the system design allows other slaves to continue to work normally, improving overall fault tolerance. Since address allocation is dynamic, the system can be easily expanded to add more slaves without rewiring. Automated address allocation and trigger signal transmission reduce manual intervention and reduce the error rate of operation. Due to the versatility of the port, the system can adapt to different network topologies, including linear and tree structures.

[0147] An embodiment of the present invention further proposes an electronic device, comprising a memory, a processor, and a control program of the electronic device stored in the memory and executable on the processor, wherein the control program of the electronic device, when executed by the processor, implements the steps of the host bus address allocation method as described in the above embodiments.

[0148] An embodiment of the present invention further proposes an electronic device, comprising a memory, a processor, and a control program of the electronic device stored in the memory and executable on the processor, wherein the control program of the electronic device, when executed by the processor, implements the steps of the slave execution bus address allocation method as described in the above embodiments.

[0149] An embodiment of the present invention further proposes a computer-readable storage medium, on which is stored a control program for the host to perform bus address allocation. When the bus address allocation control program is executed by a processor, the steps of the bus address allocation method described in the above embodiments are implemented.

[0150] An embodiment of the present invention further proposes a computer-readable storage medium, on which is stored a control program for the slave to perform bus address allocation. When the bus address allocation control program is executed by a processor, the steps of the bus address allocation method described in the above embodiments are implemented.

[0151] It should be noted that, in the embodiments provided by the present invention, "previous" and "next" are descriptions of the relative position of the slave device in a specific sequence or arrangement. These terms are used to clearly identify the device before or after a specific device (called "current device") in a series of devices. The definitions of "previous" and "next" depend on an established sequence or arrangement, for example, according to the installation order of the device, the address allocation order, the physical connection order or any other logical or physical order. Specifically, the "previous" device refers to the device that is located before the current device in the established sequence. For example, in the address allocation process, when the "previous" slave is mentioned, it refers to the slave that is assigned to the previous slave in the address allocation sequence. The "next" device refers to the device that is located after the current device in the established sequence. Continuing with the example of address allocation, when the "next" slave is mentioned, it refers to the next slave that is assigned to the current slave in the address allocation sequence. To avoid ambiguity, the "previous" and "next" mentioned in the embodiments provided in this application are always relative to the device or situation currently being discussed, and it is assumed that the reader has understood this established sequence or arrangement. In a specific example, if the slave numbered 3 is currently being discussed, then the "previous" slave will refer to the slave numbered 2, and the "next" slave will refer to the slave numbered 4.

[0152] In the embodiments provided by the present invention, the disclosed system, terminal and method can be implemented in other ways. For example, the terminal embodiment described above is illustrative, and the division of the units is a logical function division, and there may be other division methods in actual implementation.

[0153] The units described as separate components may or may not be physically separated, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0154] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0155] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform some steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program codes.

[0156] It should be noted that the preferred embodiments of the present invention are given in the specification and drawings of the present invention. However, the present invention can be implemented in many different forms and is not limited to the embodiments described in this specification. These embodiments are not intended to be additional limitations on the content of the present invention. The purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive. In addition, the above-mentioned technical features continue to be combined with each other to form various embodiments not listed above, which are all considered to be within the scope of the present invention; further, for ordinary technicians in this field, they can be improved or transformed according to the above description, and all these improvements and transformations should belong to the scope of protection of the claims attached to the present invention.

Claims

1. An electronic device, characterized in that: include: At least one RS485 communication port connected to the RS485 bus with the RS485 ports of multiple slaves; At least one IO port connected to the IO port of the first slave; A first memory, used for storing a bus address allocation control program; The first processor is configured to call the bus address allocation control program stored in the first memory and perform the following operations: Generate and send an address information message, which is broadcast to all slaves via the RS485 bus; wherein the address information message includes the current address to be assigned, triggering the slave to set its two configured IO ports to input state and monitor the two IO ports; Sending a trigger signal to the first slave via an IO port; When the RS485 bus is monitored to receive an address occupation declaration message sent by the slave within a preset time, an address confirmation message is sent to the RS485 bus to confirm to all slaves that the current address to be allocated is occupied and the next address to be allocated; wherein, when the slave is set to be the first slave, the first slave responds to the trigger signal sent by the host, selects to occupy the current address to be allocated according to the address information message, and sends the address occupation declaration message to the RS485 bus to declare to the host and the remaining slaves that the current address to be allocated is occupied, and sends a trigger signal to the next slave connected to the IO port set with it; when the slave is set to the remaining slaves except the first slave, the slave responds to the trigger signal sent by the previous slave connected to its IO port, selects to occupy the current address to be allocated according to the address information message, and sends the address occupation declaration message to the RS485 bus to declare to the host and the remaining slaves that the current address to be allocated is occupied, and sends a trigger signal to the next slave connected to the IO port set with it; When the RS485 bus is monitored and no address occupation declaration message sent by the slave is received within a preset time, the address allocation is confirmed to be successful and an end address allocation message is sent to all slaves via the RS485 bus.

2. The electronic device according to claim 1, characterized in that: The first processor is further configured to call a bus address allocation control program stored in the first memory, and perform the following operations: In step 1, generating and sending an address information message, before the address information message is broadcast to all slaves via the RS485 bus, responding to the user's operation to enter the total number N of slaves to be assigned addresses; wherein N is a natural number; After confirming that the address allocation is successful in step 1 and sending the end address allocation message to all slaves via the RS485 bus, the number of slaves to which the addresses are successfully allocated, n, is counted; Compare and verify that the number of slaves n obtained by statistics is consistent with the number of slaves N input by the user, confirming that the address allocation is successful and the address allocation process is completed; The number of slaves n obtained by comparison and statistics is inconsistent with the number of slaves N input by the user, and the address allocation error is confirmed and reported, and then the address allocation process ends.

3. An electronic device, characterized in that: include: Two RS485 ports, wherein one RS485 port is connected to an RS485 bus with an RS485 port of a host and RS485 ports of a plurality of slaves, and the other RS485 port is connected to an RS485 port of a next slave adjacent thereto, and the two RS485 ports are internally connected; Two IO ports, one of which is connected to the IO port of the adjacent host or the previous slave, and the other is connected to the IO port of the next slave; A second memory, used for storing a bus address allocation control program; The second processor is used to call the bus address allocation control program stored in the second memory and perform the following operations: Receiving an address information message sent by the host through the RS485 port; wherein the address information message is generated by the host and broadcast to all slaves through the RS485 bus; the address information message contains the current address to be assigned; Set the two IO ports to input state; Monitor two IO ports set to input state, and when any one of the IO ports monitors a trigger signal, respond to the trigger signal, select to occupy the current address to be allocated according to the address information message, and send an address occupation declaration message to the RS485 bus to declare to the host and other slaves that the current address to be allocated is occupied; wherein, when the slave is set to the first slave, the trigger signal is sent by the host; when the slave is set to the remaining slaves except the first slave, the trigger signal is sent by the previous slave connected to the IO port set to the input state; When the monitoring RS485 port receives an address confirmation message sent by the host, the vacant IO port is set to an output state; wherein the address confirmation message is generated by the host after receiving the address occupation declaration message through the RS485 bus, and the address confirmation message includes a confirmation that the current address to be allocated is occupied and the next address to be allocated sent to all slaves; Sending a trigger signal to the next slave connected to the IO port set to the output state through the IO port set to the output state; wherein the trigger signal is used to trigger the next slave to call and execute the bus address allocation control program; When the RS485 port is monitored and receives the end address information allocation message sent by the host, it is confirmed that the slave address allocation is completed; wherein, the end address information allocation message is generated when the host does not receive the address occupancy declaration message sent by the slave within a preset time by monitoring the RS485 bus and confirms that all addresses are allocated successfully.

4. A bus address allocation method, characterized in that: The method is applied to the electronic device according to claim 1 or 2, and the method comprises: Generate and send an address information message, which is broadcast to all slaves via the RS485 bus; wherein the address information message includes the current address to be assigned, triggering the slave connected to the RS485 bus to set its configured two IO ports to input state, and monitor the two IO ports; Send a trigger signal to the first slave connected to it through the IO port configured by the host; When the RS485 bus is monitored to receive an address occupation declaration message sent by the slave within a preset time, an address confirmation message is sent to the RS485 bus to confirm to all slaves that the current address to be allocated is occupied and the next address to be allocated; wherein, when the slave is set to be the first slave, the first slave responds to the trigger signal sent by the host, selects to occupy the current address to be allocated according to the address information message, and sends the address occupation declaration message to the RS485 bus to declare to the host and the remaining slaves that the current address to be allocated is occupied, and sends a trigger signal to the next slave connected to the IO port set with it; when the slave is set to the remaining slaves except the first slave, the slave responds to the trigger signal sent by the previous slave connected to its IO port, selects to occupy the current address to be allocated according to the address information message, and sends the address occupation declaration message to the RS485 bus to declare to the host and the remaining slaves that the current address to be allocated is occupied, and sends a trigger signal to the next slave connected to the IO port set with it; When the RS485 bus is monitored and no address occupation declaration message sent by the slave is received within a preset time, the address allocation is confirmed to be successful and an end address allocation message is sent to all slaves via the RS485 bus.

5. The bus address allocation method according to claim 4, characterized in that: Before the step of generating and sending an address information message, wherein the address information message is broadcast to all slaves via the RS485 bus, the method further comprises: Responding to the user's operation to enter the total number N of slaves to be assigned addresses; wherein N is a natural number; After the step of confirming that the address allocation is successful and sending an end address allocation message to all slaves via the RS485 bus, the method further includes: Count the number of slaves that have successfully assigned addresses n; Compare and verify that the number of slaves n obtained by statistics is consistent with the number of slaves N input by the user, confirming that the address allocation is successful and the address allocation process is completed; The number of slaves n obtained by comparison and statistics is inconsistent with the number of slaves N input by the user, and the address allocation error is confirmed and reported, and then the address allocation process ends.

6. A bus address allocation method, characterized in that: The method is applied to the electronic device as claimed in claim 3, and the method comprises: Receiving an address information message sent by the host through the RS485 port; wherein the address information message is generated by the host and broadcast to all slaves through the RS485 bus; the address information message includes the current address to be assigned; Set the two IO ports to input state; Monitor two IO ports set to input state, and when any IO port monitors a trigger signal, respond to the trigger signal, select to occupy the current address to be allocated according to the address information message, and send an address occupation declaration message to the RS485 bus to declare to the host and other slaves that the current address to be allocated is occupied; wherein, when the slave is set to the first slave, the trigger signal is sent by the host; when the slave is set to the second slave or the other slaves, the trigger signal is sent by the previous slave connected to the IO port set to the input state; When the monitoring RS485 port receives an address confirmation message sent by the host, the vacant IO port is set to an output state; wherein the address confirmation message is generated by the host after receiving the address occupation declaration message through the RS485 bus, and the address confirmation message includes a confirmation that the current address to be allocated is occupied and the next address to be allocated sent to all slaves; Sending a trigger signal to the next slave connected to the IO port set to the output state through the IO port set to the output state; wherein the trigger signal is used to trigger the next slave to call and execute the bus address allocation method; When the monitoring RS485 port receives the end address information allocation message sent by the host, it is confirmed that the slave address allocation is completed; wherein, the end address information allocation message is generated when the host confirms that all addresses are successfully allocated when it fails to receive the address occupation declaration message sent by the slave within a preset time by monitoring the RS485 bus.

7. A bus address allocation system, characterized in that: The system includes a host and multiple slaves; The host comprises: At least one RS485 communication port connected to the RS485 bus with the RS485 ports of multiple slaves; At least one IO port connected to the IO port of the first slave; A first memory, used for storing a bus address allocation control program; The first processor is configured to call the bus address allocation control program stored in the first memory and perform the following operations: Generate and send an address information message, which is broadcast to all slaves via the RS485 bus; wherein the address information message includes the current address to be assigned; Send a trigger signal to the first slave through the IO port; When the RS485 bus is monitored to receive an address occupation declaration message sent by the slave within a preset time, an address confirmation message is sent to the RS485 bus to confirm to all slaves that the current address to be allocated is occupied and the next address to be allocated; When monitoring the RS485 bus and failing to receive the address occupation declaration message sent by the slave within a preset time, confirming that the address allocation is successful and sending the end address allocation message to all slaves via the RS485 bus; The slave device comprises: Two RS485 ports, one of which is connected to an RS485 bus with an RS485 port of a host and RS485 ports of multiple slaves; the other RS485 port is connected to an RS485 port of a next slave adjacent thereto, and the two RS485 ports are internally connected; Two IO ports, one of which is connected to the IO port of the adjacent host or the previous slave; the other IO port is connected to the IO port of the next slave; A second memory, used for storing a bus address allocation control program; The second processor is used to call the bus address allocation control program stored in the second memory and perform the following operations: Receive the address information message sent by the host through the RS485 port; Set the two IO ports to input state; Monitor two IO ports set to input state, and when any IO port monitors a trigger signal, respond to the trigger signal, select to occupy the current address to be allocated according to the address information message, and send an address occupation declaration message to the RS485 bus to declare to the host and other slaves that the current address to be allocated is occupied; wherein, when the slave is set to the first slave, the trigger signal is sent by the host; when the slave is set to the remaining slaves except the first slave, the trigger signal is sent by the previous slave connected to the IO port set to the input state; When the RS485 port receives the address confirmation message sent by the host, the free IO port is set to output state; Sending a trigger signal to the next slave through the IO port set to the output state, so as to trigger the next slave to call and execute the bus address allocation control program; When the RS485 port receives the end address information allocation message sent by the host, it is confirmed that the slave address allocation is completed.

8. The bus address allocation system according to claim 7, characterized in that: The first processor is further configured to call the bus address allocation control program stored in the first memory, and perform the following operations: Before generating and sending an address information message, which is broadcast to all slaves via the RS485 bus, responding to a user's operation to enter the total number N of slaves to be assigned addresses; wherein N is a natural number; After confirming that the address allocation is successful and sending the end address allocation message to all slaves via the RS485 bus, the number of slaves to which the addresses are successfully allocated, n, is counted; Compare and verify that the number of slaves n obtained by statistics is consistent with the number of slaves N input by the user, confirming that the address allocation is successful and the address allocation process is completed; The number of slaves n obtained by comparison and statistics is inconsistent with the number of slaves N input by the user, and the address allocation error is confirmed and reported, and then the address allocation process ends.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a host bus address allocation control program, and when the host control program is executed by a processor, the steps of the bus address allocation method according to claim 1 or 2 are implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a bus address allocation control program of the slave, and when the control program of the slave is executed by the processor, the steps of the bus address allocation method according to claim 3 are implemented.

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