Antifuse unit, antifuse array, operation method thereof, and memory

Abstract

Embodiments of the present disclosure provide an antifuse unit, an antifuse array, an operating method thereof, and a memory device. The antifuse unit includes an active region comprising a first doped region, a second doped region, and a third doped region sequentially arranged along a first direction, and a fourth doped region spaced apart from the third doped region. A first gate structure is located on the surface of the second doped region; a second gate structure is located on the surface of the active region between the third doped region and the fourth doped region. A first conductive line is electrically connected to the first doped region and the fourth doped region; the first doped region is an N-type doped region, and the second, third, and fourth doped regions are P-type doped regions.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and is related to but not limited to an anti-fuse unit, an anti-fuse array, an operation method thereof, and a memory. Background Art

[0002] Dynamic random access memory (DRAM) chips typically have redundant memory cells that can replace defective cells in the DRAM chip to repair it. Repairing a DRAM chip requires the use of one-time programming devices, such as antifuses.

[0003] An antifuse cell typically consists of an antifuse device, a select transistor, and a bitline electrically connected to the source or drain region of the select transistor. During programming, a high voltage is applied to the programming gate of the antifuse device, a low voltage is applied to the bitline, and the select transistor is turned on. The high voltage difference between the programming gate and the bitline causes the gate oxide of the programming gate to break down, completing the programming operation. With the rapid advancement of integrated circuit technology and the continuous reduction in chip size, the area of ​​the antifuse cell must also be reduced to save valuable space in the memory array. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide an anti-fuse unit, an anti-fuse array, an operation method thereof, and a memory.

[0005] In a first aspect, an embodiment of the present disclosure provides an anti-fuse unit, comprising:

[0006] an active region, the active region comprising a first doping region, a second doping region, and a third doping region sequentially arranged along a first direction, and a fourth doping region spaced apart from the third doping region;

[0007] a first gate structure, located on the surface of the second doped region;

[0008] a second gate structure located on the surface of the active area between the third doping region and the fourth doping region;

[0009] a first conductive line electrically connected to the first doping region and the fourth doping region;

[0010] Wherein, the first doping region is an N-type doping region, and the second doping region, the third doping region and the fourth doping region are P-type doping regions;

[0011] The first direction is any direction within the plane where the active region is located.

[0012] In some embodiments, the anti-fuse unit further includes:

[0013] a first connecting structure connected between the first doped region and the first conductive line;

[0014] The second connecting structure is connected between the fourth doping region and the first conductive line.

[0015] In some embodiments, the anti-fuse unit further includes:

[0016] a fifth doped region, located in the active region below the second gate structure and a portion of the third doped region and the fourth doped region;

[0017] The fifth doping region is an N-type doping region.

[0018] In some embodiments, a size of the first gate structure in the first direction is larger than a size of the second gate structure in the first direction.

[0019] In some embodiments, the first gate structure includes a first gate dielectric layer located on the active region and a first gate conductive layer located on the first gate dielectric layer;

[0020] The second gate structure includes a second gate dielectric layer located on the active area and a second gate conductive layer located on the second gate dielectric layer;

[0021] The thickness of the first gate dielectric layer in the third direction is smaller than the thickness of the second gate dielectric layer in the third direction; the third direction is the thickness direction of the active region.

[0022] In some embodiments, the anti-fuse unit further includes:

[0023] a second conductive line extending along a second direction and electrically connected to the first gate conductive layer;

[0024] a third conductive line extending along the second direction and electrically connected to the second gate conductive layer;

[0025] The second direction and the first direction are located in the same plane and intersect with each other.

[0026] In a second aspect, an embodiment of the present disclosure provides an antifuse array, comprising:

[0027] Arrange a plurality of antifuse structures in an array along a first direction and a second direction;

[0028] Each of the antifuse structures includes two antifuse units as described in the first aspect; the two antifuse units in each of the antifuse structures are arranged along the first direction and share the first doped region;

[0029] Two adjacent antifuse structures arranged along the first direction share the fourth doped region;

[0030] In two adjacent anti-fuse units arranged along the second direction, the first gate structures are connected to each other and extend along the second direction, and the second gate structures are connected to each other and extend along the second direction.

[0031] In some embodiments, in a column of the anti-fuse units arranged along the second direction, the interconnected first gate structures are connected to the same second conductive line, and the interconnected second gate structures are connected to the same third conductive line;

[0032] The first doping regions and the fourth doping regions of a row of the anti-fuse units arranged along the first direction are all connected to the same first conductive line.

[0033] In a third aspect, an embodiment of the present disclosure provides an operating method for an anti-fuse unit, which is applied to the anti-fuse unit according to the first aspect, wherein the first gate structure and the second doped region constitute a programming device, and the second gate structure, the third doped region, and the fourth doped region constitute a switching device; the method includes:

[0034] A programming operation is performed on the anti-fuse unit; or a reading operation is performed on the anti-fuse unit.

[0035] In some embodiments, performing the programming operation on the anti-fuse unit includes:

[0036] Applying a first voltage to the first conductive line and the third conductive line, and applying a second voltage to the second conductive line, so as to turn off the switching device and break down the programming device;

[0037] The second voltage is greater than or equal to the breakdown voltage of the programming device, and the first voltage is zero voltage or ground voltage.

[0038] In some embodiments, performing the read operation on the anti-fuse unit includes:

[0039] Applying a third voltage to the first conductive line and applying the first voltage to the third conductive line to turn on the switching device, and reading data in the programming device according to a current flowing through the switching device and into the second conductive line;

[0040] The third voltage is less than the second voltage, and the difference between the first voltage and the third voltage is less than or equal to the turn-on voltage of the switching device.

[0041] In some embodiments, the operating method further includes:

[0042] After the programming operation and when the reading operation is not performed, applying a fourth voltage to the third conductive line to turn off the switching device;

[0043] The fourth voltage is greater than the first voltage.

[0044] In a fourth aspect, embodiments of the present disclosure provide an operating method for an antifuse array, which is applied to the antifuse array according to the second aspect, wherein the antifuse array includes a plurality of antifuse units, wherein in each antifuse unit, the first gate structure and the second doped region constitute a programming device, and the second gate structure, the third doped region, and the fourth doped region constitute a switching device; the method includes:

[0045] During a programming operation, a first voltage is applied to the first conductive line and the third conductive line corresponding to a programming device to be programmed, and a sixth voltage is applied to the second conductive line corresponding to the programming device to be programmed, so as to close the switch device corresponding to the programming device to be programmed and breakdown the programming device to be programmed. Simultaneously, a fifth voltage is applied to the other first conductive lines in the antifuse array, and the first voltage is applied to the other second conductive lines and the other third conductive lines in the antifuse array, so as to prevent the other programming devices except the programming device to be programmed from being breakdown. The programming device to be programmed is any one of the plurality of programming devices.

[0046] During a read operation, a seventh voltage is applied to the first conductive line corresponding to a programming device to be read, and the first voltage is applied to the second conductive line and the third conductive line corresponding to the programming device to be read, so as to open the switch device corresponding to the programming device to be read, and read data in the programming device to be read according to a current flowing through the switch device corresponding to the programming device to be read and into the corresponding second conductive line. Simultaneously, the first voltage is applied to the other first conductive lines and the other second conductive lines in the antifuse array, and the seventh voltage is applied to the other third conductive lines in the antifuse array.

[0047] Among them, the sixth voltage is greater than or equal to the breakdown voltage of the programming device that needs to be programmed, the sixth voltage is greater than the fifth voltage and the seventh voltage, the fifth voltage and the seventh voltage are greater than the first voltage, and the difference between the first voltage and the seventh voltage is less than or equal to the turn-on voltage of the switching device corresponding to the programming device that needs to be read; the first voltage is zero voltage or ground voltage.

[0048] In some embodiments, the operating method further includes:

[0049] After the programming operation and when the reading operation is not performed, applying an eighth voltage to all the third conductive lines in the antifuse array to turn off all the switching devices;

[0050] The eighth voltage is greater than the first voltage.

[0051] In a fifth aspect, an embodiment of the present disclosure provides a memory comprising the antifuse array as described in the second aspect.

[0052] The anti-fuse unit, anti-fuse array, operation method thereof, and memory provided by the embodiments of the present disclosure, wherein the first gate structure and the second doped region in the anti-fuse unit constitute a programming device, and the second gate structure, the third doped region, and the fourth doped region constitute a switching device. The second doped region in the programming device is a P-type doped region, the first doped region adjacent to the second doped region is an N-type doped region, and the switching device is a P-type device. In this way, by electrically connecting the first doped region and the fourth doped region with the first conductive line, when a programming voltage is applied to the first gate structure of the programming device for programming operation, the first doped region and the second doped region are turned on, and the write current passes through the programming device, flows through the first doped region, and then flows to the first conductive line without passing through the switching device. In other words, the device width of the switching device will not affect the programming process of the programming device. Therefore, the device width of the switching device can be made smaller, thereby reducing the area of ​​the anti-fuse unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0054] Figure 1 Schematic diagram of the structure of an antifuse array;

[0055] Figure 2 A schematic diagram of the layout structure of an antifuse structure;

[0056] Figure 3 A schematic diagram of the local structure of an antifuse array;

[0057] Figure 4 A schematic diagram of the layout structure of an anti-fuse unit provided in an embodiment of the present disclosure;

[0058] Figure 5 An anti-fuse unit provided in an embodiment of the present disclosure is provided along Figure 4 A-A' cross-sectional view;

[0059] Figure 6A schematic structural diagram of an antifuse array provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0061] In the following description, numerous details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0062] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0063] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the present disclosure necessarily has the first element, component, region, layer, or part.

[0064] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0065] Figure 1 Schematic diagram of the structure of an antifuse array, such as Figure 1 As shown, the antifuse array 100 includes a plurality of antifuse structures 100a arranged in a spaced relationship. The plurality of antifuse structures 100a are spaced apart along a first direction (i.e., the X-axis direction shown in the figure). In the antifuse array 100, all antifuse devices in the same row share the same programming conductor FG and the same word line XG. Therefore, when writing to a particular antifuse device, both the programming conductor FG and the word line XG must be turned on simultaneously. For antifuse devices in the same row that do not require high-voltage writing, a certain positive voltage must be applied to the corresponding bit line (BL) 109 to prevent other antifuse devices from being accidentally broken down.

[0066] Figure 2 is a schematic diagram of a layout structure of an antifuse structure 100a, such as Figure 2As shown, the antifuse structure 100a includes a first antifuse unit 11 and a second antifuse unit 12. The first antifuse unit 11 includes a first gate 101, a first source / drain region 102, a second gate 103, and a second source / drain region 104. The first gate 101 and the active region 13 located below the first gate 101 constitute a first antifuse device, and the first source / drain region 102, the second gate 103, and the second source / drain region 104 constitute a first select transistor. The second antifuse unit 12 includes a third gate 105, a second source / drain region 104, a third source / drain region 106, and a fourth gate 107. The fourth gate 107 and the active region 13 located below the fourth gate 107 constitute a second antifuse device, and the second source / drain region 104, the third gate 105, and the third source / drain region 106 constitute a second select transistor. The first and second select transistors share the second source / drain region 104, and a bit line connection structure 108 electrically connects the second source / drain region 104 to a bit line 109. For the anti-fuse structure 100a, when writing, a high voltage (for example, about 5 to 5.5 volts) is applied to the first gate 101 of the first anti-fuse device, 0V is set at the corresponding BL terminal, and the first selection transistor is turned on, so that the thin gate oxide of the first anti-fuse device is broken down under the high voltage and the resistance is significantly reduced, thereby achieving the purpose of writing; or, when writing, a high voltage (for example, about 5 to 5.5 volts) is applied to the fourth gate 107 of the second anti-fuse device, 0V is set at the corresponding BL terminal, and the second selection transistor is turned on, so that the thin gate oxide of the second anti-fuse device is broken down under the high voltage and the resistance is significantly reduced, thereby achieving the purpose of writing.

[0067] Please continue to refer to Figure 1 and Figure 2 The first gate 101, the second gate 103, the third gate 105 and the fourth gate 107 in the anti-fuse structure 100a are arranged in sequence along the second direction (i.e., the Y-axis direction shown in the figure), so that the length of the anti-fuse structure 100a is longer, thereby making the area of ​​the anti-fuse array 100 including multiple anti-fuse structures 100a larger.

[0068] Also, please continue to refer to Figure 2 When the width of the first selection transistor or the second selection transistor (i.e., the dimension along the X-axis direction) is small, the voltage division of the channel of the first selection transistor or the second selection transistor increases, so that the voltage difference across the corresponding first anti-fuse device or the second anti-fuse device becomes smaller, weakening the energy used to break down the gate oxide in the first anti-fuse device or the second anti-fuse device, resulting in the first anti-fuse device or the second anti-fuse device being difficult to write. Therefore, the first selection transistor or the second selection transistor needs to have a larger width, which limits the reduction of the area of ​​the anti-fuse structure 100a.

[0069] Figure 3is a partial structural diagram of the antifuse array 100, refer to Figure 3 Typically, an anti-fuse doping region 301 is provided in the substrate below the first and second anti-fuse devices. Due to the extremely high doping concentration of the anti-fuse doping region 301, the doping ions in the anti-fuse doping region 301 may diffuse to the vicinity of the channel doping region 302 of the first and second selection transistors during the high-temperature process, thereby reducing the turn-on voltage of the first and second selection transistors and increasing the risk of leakage. Therefore, the distance A between the first gate 101 and the second gate 103 and the distance C between the third gate 105 and the fourth gate 107 must be maintained at a large distance, for example, significantly larger than the distance B between the second gate 103 and the third gate 105. This makes it difficult to further reduce the length of the anti-fuse structure 100a.

[0070] Based on this, the embodiments of the present disclosure provide an anti-fuse unit, an anti-fuse array, an operation method thereof, and a memory, wherein the first gate structure and the second doped region in the anti-fuse unit constitute a programming device, and the second gate structure, the third doped region, and the fourth doped region constitute a switching device. The second doped region in the programming device is a P-type doped region, the first doped region adjacent to the second doped region is an N-type doped region, and the switching device is a P-type device. In this way, by electrically connecting the first doped region and the fourth doped region with the first conductive line, when a programming voltage is applied to the first gate structure of the programming device for programming operation, the first doped region and the second doped region are turned on, and the write current passes through the programming device, flows through the first doped region, and then flows to the first conductive line without passing through the switching device. In other words, the device width of the switching device will not affect the programming process of the programming device. Therefore, the device width of the switching device can be made smaller, thereby reducing the area of ​​the anti-fuse unit.

[0071] The antifuse unit and the antifuse array in the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0072] Before introducing the embodiments of the present disclosure, the three directions that may be used to describe the antifuse unit in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions may include the X-axis, the Y-axis, and the Z-axis. The thickness direction of the active area is defined as the Z-axis direction. In the plane direction where the active area is located, two directions that intersect with each other (for example, perpendicular to each other) are defined as the first direction and the second direction. For example, any direction in the plane where the active area is located can be defined as the first direction. Here, the first direction can be, for example, the X-axis direction, and the second direction can be, for example, the Y-axis direction.

[0073] An embodiment of the present disclosure provides an anti-fuse unit, Figure 4 A schematic diagram of the layout structure of the anti-fuse unit provided in an embodiment of the present disclosure, Figure 5 For the Figure 4The cross-section diagram of A-A' in Figure 4 and Figure 5 As shown, the anti-fuse unit 200 includes:

[0074] The active region 20 includes a first doping region 201, a second doping region 202, and a third doping region 203 sequentially arranged along the X-axis direction, and a fourth doping region 204 spaced apart from the third doping region 203;

[0075] A first gate structure 21 is located on the surface of the second doped region 202;

[0076] A second gate structure 22 is located on the surface of the active region 20 between the third doping region 203 and the fourth doping region 204;

[0077] A first conductive line 23 electrically connected to the first doping region 201 and the fourth doping region 204;

[0078] The first doping region 201 is an N-type doping region, and the second doping region 202 , the third doping region 203 and the fourth doping region 204 are P-type doping regions.

[0079] It should be noted that the first conductive line 23 may be a bit line BL.

[0080] In the disclosed embodiment, the first gate structure 21 and the second doped region 202 constitute a programming device, and the second gate structure 22, the third doped region 203, and the fourth doped region 204 constitute a switching device. The third doped region 203 can serve as either the source or drain region of the switching device, and the fourth doped region 204 can serve as the other of the source or drain regions of the switching device. The third doped region 203 and the fourth doped region 204 are P-type doped regions, meaning that the switching device is a P-type device (PMOS transistor).

[0081] In some embodiments, the active region 20 may be located in a P-type substrate ( Figure 5 Alternatively, the active region 20 may be located in an N-type substrate.

[0082] In some embodiments, please refer to Figure 5 The anti-fuse unit 200 also includes: a fifth doped region 205, located in the active area 20 below the second gate structure 22 and part of the third doped region 203 and the fourth doped region 204; the fifth doped region 205 includes a channel region of the switching device (PMOS tube), and the fifth doped region 205 is an N-type doped region.

[0083] In the embodiment of the present disclosure, because the first doping region 201 is an N-type doping region and the second doping region 202 is a P-type doping region, a PN junction is formed at the interface between the first doping region 201 and the second doping region 202. The PN junction is non-conductive when no external voltage is applied. When a positive voltage is applied to the first gate structure 21 of the programming device and a zero voltage or a ground voltage is applied to the first conductive line 23, it is equivalent to applying a forward voltage to the PN junction, which can make the PN junction conductive. In this way, conduction between the first doping region 201 and the second doping region 202 can be achieved.

[0084] In the embodiment of the present disclosure, by electrically connecting the first conductive line 23 to the first doping region 201 and the fourth doping region 204, when a programming voltage is applied to the first gate structure 21 of the programming device for a programming operation, the first doping region 201 and the second doping region 202 are turned on, and the write current passes through the programming device, flows through the first doping region 201, and then flows to the first conductive line 23 without passing through the switching device. In other words, the width of the switching device will not affect the write success rate of the programming device.

[0085] In some embodiments, please refer to Figure 4 In the antifuse unit 200, the device width (i.e., the dimension along the Y-axis) w3 of the switching device is the same as the device width (i.e., the dimension along the Y-axis) w4 of the programming device. This effectively reduces the area of ​​the antifuse unit and simplifies the formation process of the active area 20 by making the entire active area 20 have the same dimension along the Y-axis.

[0086] In some embodiments, the material of the first conductive line 23 can be any material with good conductivity, such as any one or more of titanium, titanium nitride, tungsten nitride, tungsten, cobalt, platinum, palladium, ruthenium, and copper.

[0087] In some embodiments, please refer to Figure 5 The antifuse unit 200 further includes a sixth doped region 206 located on a side of the third doped region 203 close to the second gate structure 22 and on a side of the fourth doped region 204 close to the second gate structure 22. The sixth doped region 206 may be a lightly doped drain region that can reduce the drain electric field in the switching device, thereby improving a series of short channel effects such as the hot electron degradation effect.

[0088] In some embodiments, please refer to Figure 4 and Figure 5 The anti-fuse unit 200 further includes: a first connection structure 231 connected between the first doping region 201 and the first conductive line 23 ; and a second connection structure 232 connected between the fourth doping region 204 and the first conductive line 23 .

[0089] In the embodiment of the present disclosure, the first conductive line 23 is located above the active area 20 and is electrically connected to the first doped area 201 and the fourth doped area 204 through the first connecting structure 231 and the second connecting structure 232, respectively. The first connecting structure 231 and the second connecting structure 232 can be located in the insulating dielectric layer ( Figure 5 not shown).

[0090] In some embodiments, the material of the first connection structure 231 and the second connection structure 232 can be any material with good conductivity, such as any one or more combinations of titanium, titanium nitride, tungsten nitride, tungsten, cobalt, platinum, palladium, ruthenium, and copper.

[0091] It should be noted that the material of the first connection structure 231 and the second connection structure 232 may be the same as or different from the material of the first conductive line 23 .

[0092] In some embodiments, the materials of the first and second connection structures 231 and 232 are the same as the material of the first conductive line 23 , so that the contact resistance between the first and second connection structures 231 and 232 and the first conductive line 23 is low.

[0093] In some embodiments, please refer to Figure 4 , a dimension d1 of the first gate structure 21 in the X-axis direction is greater than a dimension d2 of the second gate structure 22 in the X-axis direction.

[0094] In the embodiment of the present disclosure, the first gate structure 21 is the gate of the programming device. Since a higher breakdown voltage needs to be applied to the first gate structure 21 during the programming operation to break down the gate dielectric layer of the first gate structure 21, the size d1 of the first gate structure 21 in the X-axis direction is larger than the size d2 of the second gate structure 22, which can ensure the reliability of the performance of the programming device.

[0095] In some embodiments, please refer to Figure 5 The first gate structure 21 includes a first gate dielectric layer 211 located on the active area 20 and a first gate conductive layer 212 located on the first gate dielectric layer 211; the second gate structure 22 includes a second gate dielectric layer 221 located on the active area 20 and a second gate conductive layer 222 located on the second gate dielectric layer 221; wherein the thickness d3 of the first gate dielectric layer 211 in the Z-axis direction is less than the thickness d4 of the second gate dielectric layer 221 in the Z-axis direction.

[0096] In the embodiment of the present disclosure, since a higher breakdown voltage needs to be applied to the first gate conductive layer 212 to break down the first gate dielectric layer 211 during the programming operation, the thickness d3 of the first gate dielectric layer 211 is smaller than the thickness d4 of the second gate dielectric layer 221 in the Z-axis direction, so that when the programming operation is performed on the programming device, the first gate dielectric layer 211 can be broken down at the expected breakdown voltage, and the reliability of the switching device can also be guaranteed.

[0097] In some embodiments, the material of the first gate dielectric layer 211 and the second gate dielectric layer 221 can be silicon oxide or other suitable materials; the material of the first gate conductive layer 212 and the second gate conductive layer 222 can be any material with good conductivity, such as any one or more combinations of titanium, titanium nitride, tungsten nitride, tungsten, cobalt, platinum, palladium, ruthenium, copper, and polysilicon.

[0098] In some embodiments, please refer to Figure 4 The anti-fuse unit 200 further includes: a second conductive line 24 extending along the Y-axis direction and electrically connected to the first gate conductive layer 212 ; a third conductive line 25 extending along the Y-axis direction and electrically connected to the second gate conductive layer 222 .

[0099] It should be noted that the second conductive line 24 may be a programming conductive line FG, and the third conductive line 25 may be a word line XG.

[0100] Here, the second conductive line 24 leads the first gate conductive layer 212 out, so that when programming or reading the device, a programming voltage or a reading current is applied to the second conductive line 24. The third conductive line 25 leads the second gate conductive layer 222 out, so that a voltage is applied to the third conductive line 25 to turn the switching device on or off.

[0101] In some embodiments, the material of the second conductive line 24 and the third conductive line 25 can be any material with good conductivity, such as any one or more combinations of titanium, titanium nitride, tungsten nitride, tungsten, cobalt, platinum, palladium, ruthenium, and copper.

[0102] In this disclosure, please continue to refer to Figure 4 and Figure 5 The second conductive line 24 can be electrically connected to the first gate conductive layer 212 via the third connection structure 241, and the third conductive line 25 can be electrically connected to the second gate conductive layer 222 via the fourth connection structure 251. In actual processing, the third connection structure 241 and the fourth connection structure 251 can be formed simultaneously with the first connection structure 231 and the second connection structure 232 in a single step. The first conductive line 23, the second conductive line 24, and the third conductive line 25 can also be formed by patterning the same conductive material layer, which simplifies the process and reduces the number of layers in the interconnect structure.

[0103] Another embodiment of the present disclosure further provides an antifuse array, please refer to Figure 6 , which shows a schematic structural diagram of the antifuse array provided by an embodiment of the present disclosure. Figure 6 As shown, the antifuse array 300 includes a plurality of antifuse structures 300a arranged in an array along the X-axis direction and the Y-axis direction;

[0104] Each anti-fuse structure 300 a includes two anti-fuse units 200 as described in the above embodiment; the two anti-fuse units 200 in each anti-fuse structure 300 a are arranged along the X-axis direction and share the first doped region 201 ;

[0105] Two adjacent anti-fuse structures 300 a arranged along the X-axis direction share the fourth doped region 204 ;

[0106] In two adjacent anti-fuse units 200 arranged along the Y-axis direction, the first gate structures 21 are connected to each other and extend along the Y-axis direction, and the second gate structures 22 are connected to each other and extend along the Y-axis direction.

[0107] In the embodiment of the present disclosure, the two antifuse units 200 in each antifuse structure 300a are arranged along the X-axis direction and share the first doped region 201 , so that the length of the antifuse structure 300a in the X-axis direction is reduced, thereby reducing the area of ​​the antifuse structure 300a.

[0108] In some embodiments, please refer to Figure 6 The active regions 20 of adjacent antifuse structures 300a in the same column can be separated by shallow trench isolation structures 26, and the spacing distance between multiple antifuse structures 300a in the same column along the Y-axis direction is the same. The active regions 20 of the antifuse structures 300a in the same row are interconnected, and two adjacent antifuse structures 300a in the same row share the fourth doped region 204. In this way, the layout of the antifuse array 300 can be uniform, the layout area can be reasonably utilized, and the complexity of the manufacturing process of the antifuse array 300 can be reduced. Since the area of ​​the antifuse unit 200 is reduced, the area of ​​the antifuse structure 300a is also reduced. Moreover, the shallow trench isolation structure 26 is omitted between the antifuse structures 300a in the same row, thereby significantly reducing the area of ​​the antifuse array 300.

[0109] In the disclosed embodiment, in two adjacent antifuse units 200 arranged along the Y-axis, the first gate structures 21 are interconnected and extend along the Y-axis, enabling application of programming voltage or reading current to programming devices in the same column. The second gate structures 22 are interconnected and extend along the Y-axis, enabling control of the on / off switching of multiple switching devices in the same column via a single control terminal.

[0110] In some embodiments, continue to refer to Figure 6 In the antifuse array 300, in a column of antifuse units 200 arranged along the Y-axis direction, the interconnected first gate structures 21 are connected to the same second conductive line 24, and the interconnected second gate structures 22 are connected to the same third conductive line 25; the first doped regions 201 and the fourth doped regions 204 of a row of antifuse units 200 arranged along the X-axis direction are both connected to the same first conductive line 23.

[0111] In the disclosed embodiment, a first conductive line 23 electrically connects the first doped regions 201 and the fourth doped regions 204 of multiple antifuse cells 200 in the same row, serving as a bit line for the antifuse array 300. A second conductive line 24 electrically connects the gate conductive layers of the interconnected first gate structures 21. This second conductive line 24 can be used to apply a programming voltage or read current to multiple programming devices in the same column, serving as a programming conductor for the antifuse array 300. A third conductive line 25 electrically connects the gate conductive layers of the interconnected second gate structures 22. This third conductive line 25 can be used to control the on / off switching of multiple switching devices in the same column, serving as a word line for the antifuse array 300. The first conductive line 23, the second conductive line 24, and the third conductive line 25 can be used to select any programming device in the antifuse array 300 to be programmed.

[0112] It should be noted that Figure 6 Only four antifuse structures 300 a are shown in the antifuse array 300 in FIG. 1 . In actual implementation, the antifuse array 300 may include multiple rows and multiple columns formed by multiple antifuse structures 300 a .

[0113] Another embodiment of the present disclosure further provides an operating method of an anti-fuse unit, which is applicable to the aforementioned embodiment. Figure 4 and Figure 5 The anti-fuse unit 200 is shown. Figure 4 and Figure 5 , wherein the first gate structure 21 and the second doped region 202 constitute a programming device, and the second gate structure 22 and the third doped region 203 and the fourth doped region 204 constitute a switching device; the operation method of the anti-fuse unit 200 includes: performing a programming operation on the anti-fuse unit 200; or, performing a reading operation on the anti-fuse unit 200.

[0114] In some embodiments, please refer to Figure 4 and Figure 5 , performing a programming operation on the anti-fuse unit 200, including: applying a first voltage to the first conductive line 23 and the third conductive line 25, and applying a second voltage to the second conductive line 24 to turn off the switching device and break down the programming device.

[0115] It should be noted that when programming the programming device, the first voltage is zero voltage or ground voltage, so that the switching device is in a closed state, and the second voltage is greater than or equal to the breakdown voltage of the programming device. Here, the second voltage can range from 5 to 5.5V, for example, it can be 5.1V, 5.3V or 5.4V, so that the programming device can be broken down at the second voltage, and the write current passes through the programming device, flows through the first doped region and flows to the first conductive line. Since the write current does not pass through the switching device, on the one hand, the write success rate of the programming device is not affected by the device width of the switching device, and on the other hand, it can avoid adverse effects on the switching device during the programming operation.

[0116] In the embodiment of the present disclosure, when performing a write operation, 0V is applied to the BL (corresponding to the first conductive line 23) and the XG (corresponding to the third conductive line 25) and a high voltage is applied to the FG (corresponding to the second conductive line 24). An electron inversion layer is induced below the FG and is connected to the NSD (corresponding to the first doped region 201). Therefore, the thin oxide is broken down under the high electric field, and the write current path is referenced. Figure 5 Indicated by the solid arrow.

[0117] In some embodiments, please refer to Figure 4 and Figure 5 , performing a read operation on the anti-fuse unit 200, including: applying a third voltage to the first conductive line 23, applying a first voltage to the third conductive line 25 to open the switching device, and reading data in the programming device according to the current flowing through the switching device and into the second conductive line 24.

[0118] It should be noted that when reading the programming device, the third voltage is a positive voltage less than the breakdown voltage of the programming device, and the difference between the first voltage and the third voltage is less than or equal to the turn-on voltage of the switching device, so as to turn on the switching device, so that the read current passes through the first conductive line 23, flows through the switching device and flows to the second conductive line 24. That is, in the embodiment of the present disclosure, the write current path and the read current path are separated, so that the programming device can be more flexibly programmed and read, reducing the mutual influence between the programming and read operations. It is understandable that when the anti-fuse unit 200 is read, the first voltage (zero voltage or ground voltage) can be applied to the second conductive line.

[0119] In the embodiment of the present disclosure, when performing a read operation, a positive voltage is applied to the BL terminal and 0V is applied to the XG terminal. The voltage difference between the XG and BL terminals must be sufficient to turn on the XADD PMOS (corresponding to the above-mentioned switching device). When a positive voltage is applied to the BL terminal for reading, 0V is applied to the FG terminal. Considering that the NSD / PAF (corresponding to the above-mentioned second doped region 202) junction is reverse biased, the read current path can only be as follows: Figure 5As shown by the dotted arrow in the middle, it passes through the path of BL-XADD-PAF-FG.

[0120] In some embodiments, please refer to Figure 4 and Figure 5 The operating method of the anti-fuse unit 200 further includes: after the programming operation and when the reading operation is not performed, applying a fourth voltage to the third conductive line 25 to turn off the switching device.

[0121] It should be noted that, since the switching device is a P-type switching device, the fourth voltage is a positive voltage greater than the first voltage to turn off the switching device, thereby reducing the standby current of the device and further reducing the static power consumption of the device.

[0122] In the embodiment of the present disclosure, when no reading is performed after writing, the standby current in the anti-fuse unit 200 can be controlled by simply applying a positive voltage to the XG terminal to turn off XADD.

[0123] Another embodiment of the present disclosure further provides an operating method of an antifuse array, which is applicable to the aforementioned embodiment. Figure 6 The antifuse array 300 is shown. Figure 6 The antifuse array 300 includes a plurality of antifuse units 200. In each antifuse unit 200, the first gate structure 21 and the second doped region 202 constitute a programming device, and the second gate structure 22, the third doped region 203, and the fourth doped region 204 constitute a switching device. The operating method of the antifuse array 300 includes:

[0124] During the programming operation, a first voltage is applied to the first conductive line 23 and the third conductive line 25 corresponding to the programming device to be programmed, and a sixth voltage is applied to the second conductive line 24 corresponding to the programming device to be programmed, so as to close the switching device corresponding to the programming device to be programmed and break down the programming device to be programmed. At the same time, a fifth voltage is applied to the other first conductive lines 23 in the antifuse array 300, and a first voltage is applied to the other second conductive lines 24 and the other third conductive lines 25 in the antifuse array 300, so that the other programming devices except the programming device to be programmed are not broken down.

[0125] It should be noted that the programming device to be programmed is any one of the multiple programming devices.

[0126] It should also be noted that when programming a programming device to be programmed, the first voltage is zero voltage or ground voltage, so that the switching device corresponding to the programming device to be programmed is in a closed state, and the sixth voltage is greater than or equal to the breakdown voltage of the programming device to be programmed, so that the programming device to be programmed can be broken down at the sixth voltage. Here, the sixth voltage can range from 5 to 5.5V, for example, it can be 5.1V, 5.3V or 5.4V. The fifth voltage is a positive voltage greater than the first voltage and less than the sixth voltage, so that when the sixth voltage is applied through the second conductive line 24 to break down the programming device to be programmed, other programming devices in the same column as the programming device to be programmed are protected from breakdown.

[0127] It should also be noted that in the above-mentioned programming operation, the write current passes through the programming device to be programmed, flows through the first doped region 201 and flows to the first conductive line 23, and no longer passes through the switching device. Therefore, the state of the switching device in the antifuse array 300 is open or closed and has no effect on the programming operation.

[0128] During the reading operation, the seventh voltage is applied to the first conductive line 23 corresponding to the programming device to be read, and the first voltage is applied to the second conductive line 24 and the third conductive line 25 corresponding to the programming device to be read, so as to open the switching device corresponding to the programming device to be read, and read the data in the programming device to be read according to the current flowing through the switching device corresponding to the programming device to be read and flowing into the corresponding second conductive line 24. At the same time, the first voltage is applied to the other first conductive lines 23 and the other second conductive lines 24 in the antifuse array 300, and the seventh voltage is applied to the other third conductive lines 25 in the antifuse array 300.

[0129] It should be noted that when reading the programming device to be read, the seventh voltage is a positive voltage that is less than the breakdown voltage of the programming device to be read, and the difference between the first voltage and the seventh voltage is less than or equal to the turn-on voltage of the switching device corresponding to the programming device to be read, so as to open the switching device corresponding to the programming device to be read, so that the reading current passes through the first conductive line 23, flows through the switching device corresponding to the programming device to be read and flows to the second conductive line 24.

[0130] In the disclosed embodiment, during a write operation, the corresponding BL (corresponding to the aforementioned first conductive line 23) is applied with 0V, the corresponding FG (corresponding to the aforementioned second conductive line 24) is applied with a high voltage, and the remaining FGs are applied with 0V, thereby breaking down the programming device to be programmed. Furthermore, the BLs corresponding to other cells that do not need to be programmed are applied with a positive voltage to protect the thin gate oxide from breakdown.

[0131] When performing a read operation, all FGs are set to 0V, a positive voltage is applied to the corresponding BL, the remaining BL terminals are set to 0V, the corresponding XGs (corresponding to the third conductive line 25 mentioned above) are applied 0V, and the remaining XG terminals are applied with the same positive voltage as BL. The state of the programming device to be read can be read by flowing through the switching device corresponding to the programming device to be read and flowing into the corresponding second conductive line 24.

[0132] In some embodiments, please refer to Figure 6 The operating method of the antifuse array 300 further includes: after the programming operation and when no reading operation is performed, applying an eighth voltage to all third conductive lines 25 in the antifuse array 300 to turn off all switching devices.

[0133] It should be noted that since the switch device is a P-type switch device, the eighth voltage is a positive voltage greater than the first voltage to turn off the switch device, thereby reducing the standby current of the antifuse array 300 and further reducing the static power consumption of the device.

[0134] Yet another embodiment of the present disclosure provides a memory, comprising the antifuse array 300 in any of the foregoing embodiments, wherein the antifuse array 300 comprises the antifuse unit 200 in any of the foregoing embodiments;

[0135] Among them, multiple anti-fuse structures 300a are arranged in an array along the X-axis direction and the Y-axis direction; each anti-fuse structure 300a includes two anti-fuse units 200; the two anti-fuse units 200 in each anti-fuse structure 300a are arranged along the X-axis direction and share a first doped region 201; two adjacent anti-fuse structures 300a arranged along the X-axis direction share a fourth doped region 204; in two adjacent anti-fuse units 200 arranged along the Y-axis direction, the first gate structures 21 are interconnected and extend along the Y-axis direction, and the second gate structures 22 are interconnected and extend along the Y-axis direction.

[0136] In which, the anti-fuse unit 200 includes an active area 20, the active area 20 includes a first doping region 201, a second doping region 202 and a third doping region 203 arranged in sequence along the X-axis direction, and a fourth doping region 204 arranged at intervals with the third doping region 203; a first gate structure 21, located on the surface of the second doping region 202; a second gate structure 22, located on the surface of the active area 20 between the third doping region 203 and the fourth doping region 204; a first conductive line 23, electrically connected to the first doping region 201 and the fourth doping region 204; wherein the first doping region 201 is an N-type doping region, and the second doping region 202, the third doping region 203 and the fourth doping region 204 are P-type doping regions.

[0137] In some embodiments, the memory may include but is not limited to random access memory (RAM), such as dynamic random access memory (DRAM).

[0138] In the disclosed embodiment, the memory includes the aforementioned antifuse array 300 . Since the aforementioned antifuse array 300 has a relatively small area, the integration of the memory can be improved, thereby effectively increasing the storage capacity of the memory and improving its performance.

[0139] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in non-targeted ways. The structural embodiments described above are merely illustrative. For example, the division of units is merely a logical functional division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0140] The features disclosed in several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0141] The above are only some embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An anti-fuse unit, characterized in that: include: an active region, the active region comprising a first doping region, a second doping region, and a third doping region sequentially arranged along a first direction, and a fourth doping region spaced apart from the third doping region; a first gate structure, located on the surface of the second doped region; a second gate structure located on the surface of the active area between the third doping region and the fourth doping region; a first conductive line electrically connected to the first doping region and the fourth doping region; Wherein, the first doping region is an N-type doping region, and the second doping region, the third doping region and the fourth doping region are P-type doping regions; The first direction is any direction within the plane where the active region is located.

2. The anti-fuse unit according to claim 1, wherein: Also includes: a first connecting structure connected between the first doped region and the first conductive line; The second connecting structure is connected between the fourth doping region and the first conductive line.

3. The anti-fuse unit according to claim 1, wherein: Also includes: a fifth doped region, located in the active region below the second gate structure and a portion of the third doped region and the fourth doped region; The fifth doping region is an N-type doping region.

4. The anti-fuse unit according to any one of claims 1 to 3, characterized in that: A size of the first gate structure in the first direction is greater than a size of the second gate structure in the first direction.

5. The anti-fuse unit according to claim 4, wherein: The first gate structure includes a first gate dielectric layer located on the active area and a first gate conductive layer located on the first gate dielectric layer; The second gate structure includes a second gate dielectric layer located on the active area and a second gate conductive layer located on the second gate dielectric layer; The thickness of the first gate dielectric layer in the third direction is smaller than the thickness of the second gate dielectric layer in the third direction; the third direction is the thickness direction of the active region.

6. The anti-fuse unit according to claim 5, wherein: Also includes: a second conductive line extending along a second direction and electrically connected to the first gate conductive layer; a third conductive line extending along the second direction and electrically connected to the second gate conductive layer; The second direction and the first direction are located in the same plane and intersect with each other.

7. An antifuse array, characterized in that: include: Arrange a plurality of antifuse structures in an array along a first direction and a second direction; Each of the antifuse structures comprises two antifuse units as claimed in claim 6; The two anti-fuse units in each anti-fuse structure are arranged along the first direction and share the first doped region; Two adjacent antifuse structures arranged along the first direction share the fourth doped region; In two adjacent anti-fuse units arranged along the second direction, the first gate structures are connected to each other and extend along the second direction, and the second gate structures are connected to each other and extend along the second direction.

8. The antifuse array according to claim 7, wherein: In a column of the anti-fuse units arranged along the second direction, the interconnected first gate structures are connected to the same second conductive line, and the interconnected second gate structures are connected to the same third conductive line; The first doping regions and the fourth doping regions of a row of the anti-fuse units arranged along the first direction are all connected to the same first conductive line.

9. A method for operating an anti-fuse unit, characterized in that: The antifuse unit according to claim 6, wherein the first gate structure and the second doped region constitute a programming device, and the second gate structure, the third doped region, and the fourth doped region constitute a switching device; and the method comprises: performing a programming operation on the anti-fuse unit; or, A read operation is performed on the anti-fuse unit.

10. The operating method according to claim 9, characterized in that: Performing the programming operation on the anti-fuse unit includes: Applying a first voltage to the first conductive line and the third conductive line, and applying a second voltage to the second conductive line, so as to turn off the switching device and break down the programming device; The second voltage is greater than or equal to the breakdown voltage of the programming device, and the first voltage is zero voltage or ground voltage.

11. The operating method according to claim 10, characterized in that: Performing the read operation on the anti-fuse unit includes: Applying a third voltage to the first conductive line and applying the first voltage to the third conductive line to turn on the switching device, and reading data in the programming device according to a current flowing through the switching device and into the second conductive line; The third voltage is less than the second voltage, and the difference between the first voltage and the third voltage is less than or equal to the turn-on voltage of the switching device.

12. The operating method according to claim 11, characterized in that: Also includes: After the programming operation and when the reading operation is not performed, applying a fourth voltage to the third conductive line to turn off the switching device; The fourth voltage is greater than the first voltage.

13. A method for operating an antifuse array, characterized in that: The antifuse array according to claim 8, wherein the antifuse array comprises a plurality of antifuse units, wherein in each of the antifuse units, the first gate structure and the second doped region constitute a programming device, and the second gate structure, the third doped region, and the fourth doped region constitute a switching device; and the method comprises: During a programming operation, a first voltage is applied to the first conductive line and the third conductive line corresponding to a programming device to be programmed, and a sixth voltage is applied to the second conductive line corresponding to the programming device to be programmed, so as to close the switch device corresponding to the programming device to be programmed and breakdown the programming device to be programmed. Simultaneously, a fifth voltage is applied to the other first conductive lines in the antifuse array, and the first voltage is applied to the other second conductive lines and the other third conductive lines in the antifuse array, so as to prevent the other programming devices except the programming device to be programmed from being breakdown. The programming device to be programmed is any one of the plurality of programming devices. During a read operation, a seventh voltage is applied to the first conductive line corresponding to a programming device to be read, and the first voltage is applied to the second conductive line and the third conductive line corresponding to the programming device to be read, so as to open the switch device corresponding to the programming device to be read, and read data in the programming device to be read according to a current flowing through the switch device corresponding to the programming device to be read and into the corresponding second conductive line. Simultaneously, the first voltage is applied to the other first conductive lines and the other second conductive lines in the antifuse array, and the seventh voltage is applied to the other third conductive lines in the antifuse array. Among them, the sixth voltage is greater than or equal to the breakdown voltage of the programming device that needs to be programmed, the sixth voltage is greater than the fifth voltage and the seventh voltage, the fifth voltage and the seventh voltage are greater than the first voltage, and the difference between the first voltage and the seventh voltage is less than or equal to the turn-on voltage of the switching device corresponding to the programming device that needs to be read; the first voltage is zero voltage or ground voltage.

14. The operating method according to claim 13, characterized in that: Also includes: After the programming operation and when the reading operation is not performed, applying an eighth voltage to all the third conductive lines in the antifuse array to turn off all the switching devices; The eighth voltage is greater than the first voltage.

15. A memory, characterized in that: Comprising the antifuse array as claimed in claim 7 or 8.

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