Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes a pixel circuit disposed on a base layer and including a transistor including a source electrode, a drain electrode, a gate electrode, and a semiconductor layer; and a light emitting element electrically connected to the pixel circuit. The semiconductor layer includes a low-concentration region, a high-concentration region, and an inclined-concentration region between the low-concentration region and the high-concentration region, the low-concentration region, the high-concentration region, and the inclined-concentration region are divided based on a concentration of carriers, and are distinguished from each other in a length direction of the base layer. A portion of the sloped concentration region and the low concentration region form a channel region, and at least another portion of the sloped concentration region and the high concentration region form a source region and a drain region. In the inclined concentration region, the semiconductor layer satisfies formula 1.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0073682 filed in the Korean Intellectual Property Office on June 8, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to a display device and a method of manufacturing the display device. Background Art

[0003] Recently, as interest in information display increases, research and development for display devices are ongoing. The display device may include a light emitting element capable of emitting light and a pixel circuit for driving the light emitting element.

[0004] To realize a layer including pixel circuits, two or more conductive structures may be formed. Experimentally, the two or more conductive structures may electrically interfere with each other. For example, unintended parasitic capacitance may be formed adjacent to some circuit elements.

[0005] When parasitic capacitance is formed, the operation characteristics of the circuit elements including the drive transistor may be changed. When the operation characteristics of the circuit elements are changed, there is a risk of abnormal operation of the pixel circuit (variation of the drive current, etc.).

[0006] Therefore, there is a need for a display device including a structure in which interference between conductive structures is reduced, operational reliability is improved, and display quality is improved by including parasitic capacitance.

[0007] It will be understood that this background section is intended, in part, to provide a useful background for understanding the technology. However, this background section may also include ideas, concepts or understandings that were not part of what was known or understood by a person skilled in the relevant art prior to the corresponding effective filing date of the subject matter disclosed herein. Summary of the invention

[0008] The disclosed object relates to a display device and a method for manufacturing the display device, in which the carrier concentration gradient in the semiconductor structure of the transistor included in the pixel circuit is strictly controlled, thereby improving the reliability of the electrical signal and reducing the risk of deterioration in the display quality.

[0009] According to an embodiment, a display device may include: a pixel circuit, which is arranged on a substrate layer and includes a transistor, the transistor including a source electrode, a drain electrode, a gate electrode and a semiconductor layer; and a light-emitting element, which is electrically connected to the pixel circuit. The semiconductor layer may include a low concentration region, a high concentration region and an inclined concentration region between the low concentration region and the high concentration region, and the low concentration region, the high concentration region and the inclined concentration region are divided based on the concentration of carriers and are distinguished from each other in the length direction of the substrate layer. A portion of the inclined concentration region and the low concentration region may form a channel region, and at least another portion of the inclined concentration region and the high concentration region may form a source region and a drain region. The semiconductor layer in the inclined concentration region may satisfy Formula 1:

[0010] [Formula 1]

[0011]

[0012] Wherein ΔX is the length variation in the length direction of the semiconductor layer in the gradient concentration region [μm], and ΔY is the concentration variation of carriers in the length variation in the gradient concentration region [1 / (cm 3 )].

[0013] According to an embodiment, the semiconductor layer may be electrically connected to the source electrode in the source region, may be electrically connected to the drain electrode in the drain region, and may overlap the gate electrode in the inclined concentration region in a plan view.

[0014] According to an embodiment, at least a portion of the semiconductor layer may not overlap the gate electrode in the source region and the drain region in a plan view. In a plan view, the semiconductor layer may entirely overlap the gate electrode in the sloped concentration region.

[0015] According to an embodiment, the transistor may include a switching transistor.

[0016] According to an embodiment, the semiconductor layer may constitute a thin film transistor including an oxide semiconductor.

[0017] According to an embodiment, the oxide semiconductor may include In—Ga—Zn-oxide (IGZO).

[0018] According to an embodiment, the semiconductor layer in the sloped concentration region may satisfy Formula 2:

[0019] [Formula 2]

[0020]

[0021] in, It is a differential value defined based on the amount of capacitance change according to the amount of voltage change measured in the gradient concentration region of the semiconductor layer using a scanning capacitance microscope.

[0022] According to an embodiment, a length of the inclined concentration region in a length direction of the semiconductor layer may be in a range of about 0.05 μm to about 0.5 μm.

[0023] According to an embodiment, a display device may include: a pixel circuit, which is arranged on a substrate layer and includes a transistor, the transistor including a source electrode, a drain electrode and a semiconductor layer; and a light-emitting element, which is electrically connected to the pixel circuit. The semiconductor layer may include a low concentration region, a high concentration region and an inclined concentration region between the low concentration region and the high concentration region, and the low concentration region, the high concentration region and the inclined concentration region are divided based on the concentration of carriers and are distinguished from each other in the length direction of the substrate layer. A portion of the inclined concentration region and the low concentration region may form a channel region, and at least another portion of the inclined concentration region and the high concentration region may form a source region and a drain region. The semiconductor layer in the inclined concentration region may satisfy Formula 2:

[0024] [Formula 2]

[0025]

[0026] in, It is a differential value defined based on the amount of capacitance change according to the amount of voltage change measured in the gradient concentration region of the semiconductor layer using a scanning capacitance microscope.

[0027] According to an embodiment, a method for manufacturing a display device may include the following steps: patterning a base semiconductor layer on a base layer; and forming a semiconductor region in the base semiconductor layer. The step of forming the semiconductor region may include: performing a process for defining the semiconductor region; analyzing the concentration of carriers formed in the base semiconductor layer using a scanning capacitance microscope; and determining whether the concentration of carriers satisfies a selectable reference based on information about the concentration of carriers. In the case where the concentration of carriers does not satisfy the selectable reference, the step of forming the semiconductor region may further include performing an additional process for defining the semiconductor region, and additionally performing a step of analyzing the concentration of carriers after performing the additional process.

[0028] According to an embodiment, the step of analyzing the concentration of carriers may include: for each region of the base semiconductor layer, measuring the concentration of carriers by scanning capacitance microscopy. and It may be obtained based on data measured for each region of the base semiconductor layer, and may be a differential value defined based on the amount of capacitance change according to the amount of voltage change.

[0029] According to an embodiment, performing a process for defining a semiconductor region and performing an additional process may include performing an annealing process. The annealing process may be performed at a process temperature in a range of about 300°C to about 650°C.

[0030] According to an embodiment, the base semiconductor layer may include an oxide semiconductor.

[0031] According to an embodiment, in the case where the concentration of carriers satisfies a selectable reference, patterning of the source and drain electrodes may be performed without performing an additional process.

[0032] According to an embodiment, the step of performing a process for defining a semiconductor region may include providing a dopant to a base semiconductor layer to set a pre-update semiconductor layer. The pre-update semiconductor layer may include a pre-update low concentration region, a pre-update high concentration region, and a pre-update inclined concentration region between the pre-update low concentration region and the pre-update high concentration region, the pre-update low concentration region, the pre-update high concentration region, and the pre-update inclined concentration region being divided based on the concentration of carriers and being distinguished from each other in the length direction of the base layer.

[0033] According to an embodiment, a selectable reference may be defined in a pre-update sloped concentration region and may include whether a slope indicating a change in concentration of carriers according to a change in length of the pre-update semiconductor layer is greater than or equal to a selectable reference slope.

[0034] According to an embodiment, the selectable reference slope may be about 6.6 or less.

[0035] According to an embodiment, the selectable reference may include whether the length of the inclined concentration region in the length direction before updating is less than or equal to a selectable reference length.

[0036] According to an embodiment, a selectable reference length may be approximately 0.5 μm or less.

[0037] According to an embodiment, the method may further include the following steps: setting a semiconductor layer that satisfies an optional reference. The semiconductor layer may include a low concentration region, a high concentration region, and an inclined concentration region between the low concentration region and the high concentration region, the low concentration region, the high concentration region, and the inclined concentration region being divided based on the concentration of carriers and being distinguished from each other in the length direction of the substrate layer. A portion of the inclined concentration region and the low concentration region may form a channel region, and at least another portion of the inclined concentration region and the high concentration region may form a source region and a drain region. The semiconductor layer in the inclined concentration region may satisfy Formula 1:

[0038] [Formula 1]

[0039]

[0040] Wherein ΔX is the length change amount [μm] in the length direction of the semiconductor layer in the gradient concentration region, and ΔY is the concentration change amount of carriers in the length change amount in the gradient concentration region [1 / (cm 3 )].

[0041] According to an embodiment, a display device and a method for manufacturing the display device can be provided, in which a carrier concentration gradient in a semiconductor structure of a transistor included in a pixel circuit is strictly controlled, thereby improving the reliability of electrical signals and reducing the risk of deterioration in display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and other features of the disclosure will become more apparent by describing the disclosed embodiments in more detail with reference to the accompanying drawings, in which:

[0043] Figure 1 is a block diagram showing a display device according to an embodiment;

[0044] Figure 2 is a schematic cross-sectional view showing a display device according to an embodiment;

[0045] Figure 3 is a schematic diagram showing a pixel circuit according to an embodiment;

[0046] Figure 4 is a timing diagram showing an operation in which a sub-pixel according to an embodiment is driven;

[0047] Figure 5 and Figure 6 is a schematic cross-sectional view showing a display device according to an embodiment;

[0048] Figure 7 and Figure 8 is a schematic flowchart illustrating a method of manufacturing a display device according to an embodiment; and

[0049] Figures 9 to 15 2 is a schematic cross-sectional view for each process step showing a method of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0050] The disclosure can be modified in various ways and have various forms. Therefore, example embodiments will be shown in the drawings and will be described in detail in the specification. However, it should be understood that the disclosure is not intended to be limited to the disclosed form, and the disclosure includes all modifications, equivalents and replacements within the spirit and technical scope of the disclosure.

[0051] In the drawings, the size, thickness, ratio, and dimensions of elements may be exaggerated for convenience of description and for clarity. Like reference numerals refer to like elements throughout.

[0052] The terms "first", "second", etc. can be used to describe various components, but the components should not be limited by the terms. The terms are only used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the disclosure, a first component can be referred to as a second component, and similarly, a second component can also be referred to as a first component.

[0053] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0054] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunction or disjunction sense and may be understood to be equivalent to "and / or".

[0055] In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0056] It should be understood that when the terms "include" and its variations, "comprises" and its variations, and / or "have" and its variations are used in this specification, they indicate the presence of stated features, integers, steps, operations, elements, components and / or groups thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0057] In the case where a part of a layer, film, region, plate, etc. is referred to as being "on" another part, this includes not only the case where the part of the layer, film, region, plate, etc. is "directly on" the other part, but also the case where there is another part between the part of the layer, film, region, plate, etc. and the other part. In the specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part of the layer, film, region, plate, etc. on the side surface or in the lower direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "under" another part, this includes not only the case where the part of the layer, film, region, plate, etc. is "directly" "under" the other part, but also the case where there is another part between the part of the layer, film, region, plate, etc. and the other part.

[0058] The term "overlying" or variations thereof means that a first object can be above or below or to one side of a second object, and vice versa. Additionally, the term "overlying" may include layering, stacking, facing or facing, extending over, covering or partially covering, or any other suitable term as will be appreciated and understood by those of ordinary skill in the art.

[0059] When an element is described as “not “overlying” another element or variations thereof, this may include the elements being spaced apart from each other, offset from each other, or set offset from each other, or any other suitable terminology as would be appreciated and understood by one of ordinary skill in the art.

[0060] The terms "facing" and "facing" mean that the first element can be directly or indirectly opposite to the second element. In the case where a third element is placed between the first element and the second element, the first element and the second element may be understood to be indirectly opposite to each other although still facing each other.

[0061] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation of the specific value as determined by one of ordinary skill in the art, taking into account the measurement being discussed and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0062] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense, unless explicitly so defined herein.

[0063] It will be understood that when an element (or region, layer, portion, etc.) is referred to in the specification as being "on", "connected to" or "coupled to" another element, the element (or region, layer, portion, etc.) can be directly disposed on, directly connected to or directly coupled to the other element, or an intervening element may be disposed therebetween.

[0064] It will be understood that the term "connected to" or "coupled to" may include a physical connection (or coupling) or an electrical connection (or coupling).

[0065] The present invention relates to a display device and a method for manufacturing the display device. Hereinafter, a display device and a method for manufacturing the display device according to an embodiment are described with reference to the accompanying drawings.

[0066] Reference Figure 1 A display device DD according to the embodiment is described. Figure 1 is a block diagram showing a display device according to an embodiment.

[0067] The display device DD is configured to emit light. The display device DD may be a device using a light emitting element LD (see Figure 2 ) is an electronic device as a light source. According to an embodiment, the display device DD may include a pixel unit 110, a scan driver 120, a data driver 130, and a controller 140.

[0068] The pixel unit 110 may include a sub-pixel SPX connected to a scan line SL and a data line DL. According to an embodiment, one or more of the sub-pixels SPX may form (e.g., constitute) a pixel unit. Each of the sub-pixels SPX may be one of a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. For example, the sub-pixel SPX may include a first sub-pixel SPX1 that emits light of a first color (e.g., red), a second sub-pixel SPX2 that emits light of a second color (e.g., green), and a third sub-pixel SPX3 that emits light of a third color (e.g., blue). However, the disclosure is not limited to the above examples.

[0069] The scan driver 120 may be disposed at one side of the pixel unit 110. The scan driver 120 may receive a first control signal SCS from the controller 140. The scan driver 120 may provide a scan signal GW (refer to Figure 3 ). The scan driver 120 may supply the scan signal GW to the scan line SL in response to the first control signal SCS.

[0070] The first control signal SCS may be a signal for controlling the driving timing of the scan driver 120. The first control signal SCS may include a scan start signal and a clock signal for the scan signal GW. The scan signal GW may be set to be connected to a transistor (e.g., the second transistor T2 (refer to Figure 3 )) type corresponding to the gate conduction level.

[0071] The data driver 130 may be disposed at one side of the pixel unit 110. The data driver 130 may receive a second control signal DCS from the controller 140. The data driver 130 may provide a data signal DATA (refer to Figure 3 ). The data driver 130 may supply the data signal DATA to the data line DL in response to the second control signal DCS. For example, the second control signal DCS may be provided to the sub-pixel SPX through the data line DL. The second control signal DCS may be a signal for controlling the driving timing of the data driver 130.

[0072] A portion of the scan line SL may extend in the first direction DR1 and may be electrically connected to the subpixel SPX of the corresponding pixel row through another portion of the scan line SL extending in the second direction DR2. Thus, the scan line SL may supply the scan signal GW to the corresponding subpixel SPX.

[0073] The data line DL may extend along a pixel column (eg, in the second direction DR2 ) and may be electrically connected to the sub-pixel SPX. The data line DL may supply a data signal DATA to the connected sub-pixel SPX.

[0074] Here, the pixel row direction may be a horizontal direction and may represent a first direction DR1. The pixel column direction may be a vertical direction and may represent a second direction DR2. However, the disclosure is not limited thereto.

[0075] exist Figure 1 , the scan driver 120, the data driver 130, and the controller 140 are separately illustrated, but at least a portion of the scan driver 120, the data driver 130, and the controller 140 may be integrated into one module or integrated circuit (IC) chip.

[0076] Reference Figure 2 A cross-sectional structure of a display device DD (eg, a sub-pixel SPX formed on a base layer BSL) according to an embodiment is described. Figure 2 is a schematic cross-sectional view showing a display device according to an embodiment.

[0077] Reference Figure 2 The display device DD may include a first direction perpendicular to the first direction DR1 (see Figure 1 ) and the second direction DR2 (see Figure 1 ) in the third direction DR3.

[0078] The pixel circuit layer PCL may be a layer including a pixel circuit PXC for driving the light emitting element LD. The pixel circuit layer PCL may include a base layer BSL, a conductive layer for forming the pixel circuit PXC, and an insulating layer disposed on the conductive layer.

[0079] The base layer BSL may form (or constitute) a base surface of the display device DD. The base layer BSL may include a rigid substrate (or film) or a flexible substrate (or film). For example, the base layer BSL may be a glass substrate, and may be a base film including an organic material. The material or constituent material of the base layer BSL is not limited to the specific examples, and the base layer BSL may include various materials.

[0080] The light emitting element layer LEL may be disposed on the pixel circuit layer PCL. According to an embodiment, the light emitting element layer LEL may include a light emitting element LD. The light emitting element LD may be an inorganic light emitting diode including an inorganic semiconductor, and the light emitting element LD may be an organic light emitting diode (OLED) including an organic material. However, the disclosure is not limited to a specific example.

[0081] The light emitting element LD may be electrically connected to the pixel circuit PXC. The light emitting element LD may emit light based on an electrical signal (eg, intensity of current) provided from the pixel circuit PXC.

[0082] Reference Figure 3 A pixel circuit PXC according to an embodiment is described. Figure 3 is a schematic diagram showing a pixel circuit according to an embodiment.

[0083] According to an embodiment, the sub-pixel SPX may include a pixel circuit PXC. The pixel circuit PXC may include a first transistor T1, a second transistor T2, a storage capacitor Cst, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a holding capacitor Chold.

[0084] According to an embodiment, the first transistor T1 to the fifth transistor T5 may be implemented as an N-type metal oxide semiconductor (NMOS) transistor. However, the disclosure is not necessarily limited thereto. In an embodiment, a portion or all of the first transistor T1 to the fifth transistor T5 may be implemented as a P-type metal oxide semiconductor (PMOS) transistor. Hereinafter, the disclosure is described based on an embodiment in which the first transistor T1 to the fifth transistor T5 are implemented as NMOS transistors.

[0085] The first transistor T1 may provide a driving current to the light emitting element LD based on a voltage between the first node N1 and the second node N2 (e.g., a voltage stored in the storage capacitor Cst) to emit light. According to an embodiment, the first node N1 may be a gate node electrically connected to a gate electrode of the first transistor T1. According to an embodiment, the second node N2 may be a node connected to a source electrode of the first transistor T1. The first transistor T1 may be a driving transistor for generating a driving current.

[0086] According to an embodiment, the first transistor T1 may include a first gate electrode electrically connected to the first node N1, a drain electrode electrically connected to the fifth transistor T5, a source electrode electrically connected to the second node N2, and a second gate electrode SYNC electrically connected to the holding capacitor Chold. The first transistor T1 may have a dual-gate structure including a first gate electrode and a second gate electrode SYNC. According to an embodiment, the second gate electrode SYNC of the first transistor T1 may be a synchronous conductive layer. According to an embodiment, the first transistor T1 may include a second gate electrode SYNC, and the second gate electrode SYNC may be maintained at a substantially uniform voltage by the holding capacitor Chold, so that the driving characteristics of the first transistor T1 may be improved. For example, the drain-source current of the first transistor T1 according to the drain-source voltage of the first transistor T1 may be provided more uniformly.

[0087] The second transistor T2 may provide (eg, apply) the data line DL (see FIG. 1 ) to the first node N1 in response to the scan signal GW. Figure 1 ). The second transistor T2 may be a switching transistor. The second transistor T2 may transmit a voltage of the data line DL (e.g., a data signal DATA). According to an embodiment, the second transistor T2 may include a gate electrode receiving the scan signal GW, a drain electrode electrically connected to the data line DL, and a source electrode electrically connected to the first node N1.

[0088] The third transistor T3 may provide (e.g., apply) a reference voltage VREF to the first node N1 in response to the reset signal GR. The third transistor T3 may be a reset transistor for providing (e.g., applying) the reference voltage VREF to the first node N1. According to an embodiment, the third transistor T3 may include a gate electrode receiving the reset signal GR, a drain electrode electrically connected to a line of the reference voltage VREF, and a source electrode electrically connected to the first node N1.

[0089] The storage capacitor Cst may store the data voltage VDAT transmitted from the data line DL through the second transistor T2. The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2. According to an embodiment, the storage capacitor Cst may include a first electrode electrically connected to the first node N1 and a second electrode electrically connected to the second node N2.

[0090] The fourth transistor T4 may provide (e.g., apply) an initialization voltage VINT to the second node N2 in response to the initialization signal GI. The fourth transistor T4 may be an initialization transistor for initializing the second node N2. According to an embodiment, the fourth transistor T4 may include a gate electrode receiving the initialization signal GI, a drain electrode connected to a line of the initialization voltage VINT, and a source electrode connected to the second node N2.

[0091] The fifth transistor T5 may electrically connect the line of the first power supply voltage ELVDD to the drain electrode of the first transistor T1 in response to the emission signal EM. The fifth transistor T5 may be a light emitting transistor for forming a path of a driving current from the line of the first power supply voltage ELVDD to the line of the second power supply voltage ELVSS. According to an embodiment, the fifth transistor T5 may include a gate electrode receiving the emission signal EM, a drain electrode electrically connected to the line of the first power supply voltage ELVDD, and a source electrode electrically connected to the drain electrode of the first transistor T1.

[0092] The holding capacitor Chold may be a capacitor for maintaining the voltage of the second node N2. The holding capacitor Chold may be electrically connected to the second node N2. For example, the holding capacitor Chold may be electrically connected between the line of the first power supply voltage ELVDD and the second node N2. According to an embodiment, the holding capacitor Chold may include a first electrode connected to the line of the first power supply voltage ELVDD and a second electrode electrically connected to the second gate electrode SYNC.

[0093] The light emitting element LD may emit light based on the driving current provided from the first transistor T1. According to an embodiment, the light emitting element LD may include an anode electrode electrically connected to the second node N2 and a cathode electrode electrically connected to a line of the second power voltage ELVSS.

[0094] Experimentally, there may be a problem that the parasitic capacitance Cpa may be formed in a region adjacent to the second transistor T2 (eg, the switching transistor). For example, the parasitic capacitance Cpa may be formed in the semiconductor layer ACT (see FIG. 1 ) included in each transistor. Figure 5 ) is excessively adjacent to the gate electrode, a parasitic capacitance Cpa is generated. When the parasitic capacitance Cpa is formed, the threshold voltage VTH (refer to Figure 4 )'s compensation force, so stains or the like may be recognized on the display device DD, and thus a problem that display quality may deteriorate may occur.

[0095] According to the embodiment, a structure capable of minimizing the occurrence of parasitic capacitance Cpa can be implemented, and thus a display device DD having improved display quality and preventing stains, etc. from being recognized can be manufactured. Details on this will be described later. Figure 4 An aspect in which the driving current of the first transistor T1 (eg, the driving transistor) changes differently from an expected range when the parasitic capacitance Cpa is generated is described, and reference is made later to Figure 5 The following drawings describe the reason why the parasitic capacitance Cpa is generated.

[0096] Reference Figure 4An operation in which the sub-pixel SPX is driven is described. Influence on the generated electric signal in the case where a parasitic capacitance Cpa that may be generated near a switching transistor (eg, the second transistor T2) is formed is described.

[0097] Figure 4 is a timing diagram showing an operation in which a sub-pixel according to an embodiment is driven. Figure 4 , each signal and voltage at the nodes N1 and N2 according to the embodiment is shown as a solid line, and the voltage at the nodes N1 and N2 in the case where the parasitic capacitance Cpa is experimentally generated is shown as a dotted line.

[0098] According to an embodiment, the frame period FP for the sub-pixel SPX may include an initialization period IP, a compensation period CP, a data writing period WP, ​​and an emission period EP.

[0099] According to an embodiment, in the initialization period IP, the first node N1 and the second node N2 may be initialized. In the initialization period IP, the emission signal EM and the scan signal GW may have a low level, and the initialization signal GI and the reset signal GR may have a high level. The third transistor T3 may be turned on in response to the reset signal GR having a high level to provide (e.g., apply) a reference voltage VREF to the first node N1. The fourth transistor T4 may be turned on in response to the initialization signal GI having a high level to provide (e.g., apply) an initialization voltage VINT to the second node N2. Therefore, the first node N1 may be initialized based on the reference voltage VREF, and the second node N2 may be initialized based on the initialization voltage VINT.

[0100] According to an embodiment, in the compensation period CP, the threshold voltage of the first transistor T1 may be compensated. In the compensation period CP, the initialization signal GI and the scan signal GW may have a low level, and the emission signal EM and the reset signal GR may have a high level. The third transistor T3 may be turned on in response to the reset signal GR having a high level to provide (e.g., apply) a reference voltage VREF to the first node N1. The fifth transistor T5 may be turned on in response to the emission signal EM having a high level. In the case where the third transistor T3 is turned on, the reference voltage VREF may be provided (e.g., applied) to the first node N1 (e.g., the gate electrode of the first transistor T1). In the case where the fifth transistor T5 is turned on, the first transistor T1 may be turned on in a conduction condition.

[0101] The first transistor T1 may be turned on until the voltage at the second node N2 becomes a voltage obtained by subtracting the threshold voltage VTH of the first transistor T1 from the reference voltage VREF. Therefore, in the compensation period CP, the voltage of the second node N2 may be changed from the initialization voltage VINT to the reference voltage minus the threshold voltage (VREF-VTH). For example, the voltage of the second node N2 may be saturated with a voltage obtained by subtracting the threshold voltage VTH of the first transistor T1 from the reference voltage VREF, and the threshold voltage VTH of the first transistor T1 may be stored between both ends of the storage capacitor Cst. The operation of storing the threshold voltage VTH of the first transistor T1 in the storage capacitor Cst may be a compensation operation for compensating the threshold voltage VTH of the first transistor T1.

[0102] In the case where the parasitic capacitance Cpa is formed adjacent to the first transistor T1, the second node N2 may have a voltage different from the expected voltage range. For example, in the case where the parasitic capacitance Cpa is formed, the second node N2 may have a reduced voltage. For example, in the compensation period CP, the second node N2 may have a voltage of "VREF-VTH", but in the case where the parasitic capacitance Cpa is formed, the second node N2 may have a voltage of "VREF-VTH×(the size of the capacitance stored in the storage capacitor Cst / the size of the capacitance stored in the parasitic capacitance Cpa)". Therefore, there may be a risk that the size of the compensation operation for compensating the threshold voltage VTH may be distorted and reduced.

[0103] According to an embodiment, in the data writing period WP, ​​the data voltage VDAT of the data line DL may be written to the sub-pixel SPX. According to an embodiment, in the data writing period WP, ​​the emission signal EM, the initialization signal GI, and the reset signal GR may have a low level, and the scan signal GW may have a high level. The second transistor T2 may be turned on in response to the scan signal GW having a high level to provide (e.g., apply) the data voltage VDAT of the data line DL to the first node N1. Therefore, the storage capacitor Cst may store the data voltage VDAT at the first node N1 (e.g., the first electrode of the storage capacitor Cst). In the case where the voltage of the first node N1 (e.g., the voltage of the first electrode of the storage capacitor Cst) changes from the reference voltage VREF to the data voltage VDAT (e.g., in the case of changing "VDAT-VREF"), the voltage of the second electrode of the storage capacitor Cst (e.g., the voltage of the second node N2) may change the voltage change amount determined by the voltage change of the capacitors Cst and Chold of the sub-pixel SPX and the first node N1. For example, the voltage change amount ΔVg of the second node N2 may be determined as "(VDAT-VREF)×(Chold) / (Cst+Chold)", where Cst represents the capacitance of the storage capacitor Cst and Chold represents the capacitance of the holding capacitor Chold. According to an embodiment, when the voltage of the first node N1 becomes the data voltage VDAT and the voltage of the second node N2 becomes "VREF-VTH+ΔVg", the gate-source voltage of the first transistor T1 may become "VDAT-VREF+VTH-ΔVg".

[0104] In the case where the parasitic capacitance Cpa is formed, the second node N2 may be saturated with a voltage less than “VREF-VTH+ΔVg”.

[0105] According to an embodiment, in the emission period EP, the light emitting element LD may emit light. According to an embodiment, in the emission period EP, the initialization signal GI, the reset signal GR and the scan signal GW may have a low level, and the emission signal EM may have a high level. The first transistor T1 may generate a driving current based on the voltage (VDAT-VREF+VTH-ΔVg) stored in the storage capacitor Cst, and the fifth transistor T5 may be turned on in response to the emission signal EM having a high level to form a path of the driving current from the line of the first power supply voltage ELVDD to the line of the second power supply voltage ELVSS.

[0106] In the case where the parasitic capacitance Cpa is formed adjacent to the first transistor T1, the second node N2 may have a voltage according to a voltage path different from the expected voltage path. For example, as described above, in the case where the parasitic capacitance Cpa is formed before the emission period EP, the second node N2 may be saturated with a relatively low voltage, so the path in which the voltage of the second node N2 changes with time may be distorted due to the parasitic capacitance Cpa. Since the parasitic capacitance Cpa may be defined as the first electrode connected in series to the storage capacitor Cst, the total capacitance size defined adjacent to the first node N1 may be reduced, and thus the voltage of the first node N1 may be increased due to the parasitic capacitance Cpa in the emission period EP.

[0107] Finally, when the parasitic capacitance Cpa is formed, the intensity of the driving current provided by the first transistor T1 as the driving transistor may be distorted, which may impair the visibility of the display device DD, so minimizing the formation of the parasitic capacitance Cpa may be preferred.

[0108] Reference Figure 5 and Figure 6 A transistor of a display device DD according to an embodiment is described. For the convenience of description, contents that may overlap with the above contents are briefly described or not repeated.

[0109] Figure 5 and Figure 6 is a schematic cross-sectional view showing a display device according to an embodiment. Figure 5 and Figure 6 At least a portion of a pixel circuit layer PCL in which a transistor according to an embodiment is formed is schematically illustrated.

[0110] Figure 5 and Figure 6 The same cross-sectional structure is shown. Figure 5 Further shown are graphs relating to the concentration of carriers in each of the regions of the semiconductor layer ACT, Figure 6 Further shown are the measured values ​​in each of the regions of the semiconductor layer ACT using a scanning capacitance microscope. Related curve graphs.

[0111] Figure 5 and Figure 6 The transistor shown in can be a switch transistor (eg, a second transistor T2). However, the disclosure is not necessarily limited thereto, and Figure 5 and Figure 6 The transistor shown in may be at least one of other transistors (eg, the first transistor T1 and the third to fifth transistors T3 to T5 ) other than the switch transistor.

[0112] Reference Figure 5 and Figure 6The pixel circuit layer PCL may include a lower conductive layer BML disposed on the base layer BSL, a transistor, and an insulating layer. The transistor may include a semiconductor layer ACT, a gate electrode GAT, a source electrode SE, and a drain electrode DE.

[0113] The lower conductive layer BML may be disposed on the base layer BSL. The lower conductive layer BML may be used as a path for forming the pixel circuit PXC or a line electrically connected to the pixel circuit PXC.

[0114] The buffer layer BFL may prevent impurities from diffusing or moisture from penetrating into the semiconductor layer ACT of the transistor. According to an embodiment, the buffer layer BFL may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (Al x O y ) in the group of one or more. However, the disclosure is not necessarily limited to the above examples.

[0115] The semiconductor layer ACT may be disposed on the buffer layer BFL. According to an embodiment, the semiconductor layer ACT may include an oxide semiconductor. For example, the semiconductor layer ACT may constitute an oxide thin film transistor. The semiconductor layer ACT may include In-Ga-Zn-O (IGZO). However, the disclosure is not limited thereto. For example, the semiconductor layer ACT may include Hf-In-Zn-O (HIZO), In-Sn-Zn-O (ITZO), and Zn-ON (ZnON).

[0116] The semiconductor layer ACT may include regions that may be divided based on the concentration of carriers. As described above, since the disclosure is described based on an embodiment in which the transistor is an NMOS transistor, the carriers may be electrons. However, according to an embodiment, in the case where the transistor is a PMOS transistor, the carriers may be holes.

[0117] For example, the semiconductor layer ACT may include a semiconductor layer ACT based on a scanning capacitance microscope (SCM) 1 (refer to Fig.11 ) measured carrier concentration or The semiconductor layer ACT may be divided into a low concentration region LDA, a high concentration region HDA, and an inclined concentration region SLOA between the low concentration region LDA and the high concentration region HDA. The high concentration region HDA may include a first high concentration region HDA1 and a second high concentration region HDA2. The low concentration region LDA, the high concentration region HDA, and the inclined concentration region SLOA may be distinguished from each other in the length direction of the semiconductor layer ACT (e.g., the plane direction or the length direction of the base layer BSL).

[0118] In the specification, a plane direction may refer to a direction of a plane on which the base layer BSL is disposed (eg, a direction in which a portion extends in the first direction DR1 and another portion extends in the second direction DR2 ).

[0119] SCM 1 is an analytical technique capable of measuring charge distribution at very small scales including micrometer to nanometer scales within the spirit and scope of the disclosure. SCM 1 can measure charge distribution at the channel region / source region / drain region as an active region including the semiconductor material to be analyzed. According to an embodiment, A differential value of a change in capacitance with respect to a change in voltage at one position in the semiconductor layer ACT may be indicated.

[0120] According to an embodiment, the carrier concentration data measured in each of the regions LDA, HDA, and SLOA may be used. To show Figure 5 and Figure 6 For example, a graph showing the carrier concentration or For example, the carrier concentration or the carrier density measured in the semiconductor layer ACT is indicated for each position in each of the high concentration area HDA, the low concentration area LDA, and the sloped concentration area SLOA. The indicated carrier concentration is fitted to correspond to the y=ax+b graph, a line of the graph indicating its tendency can be obtained, and the obtained line of the graph is shown.

[0121] In the low concentration region LDA, the semiconductor layer ACT may have a carrier concentration within a low concentration range. The low concentration range may include a carrier concentration value of a low concentration CC. In the low concentration region LDA, the carrier concentration measured in the semiconductor layer ACT It is possible to have a differential value range that includes a relatively low value BR.

[0122] In the high concentration area HDA, the semiconductor layer ACT may have a carrier concentration in a high concentration range. The high concentration range may include a carrier concentration value of the high concentration TC. In the high concentration area HDA, the carrier concentration measured in the semiconductor layer ACT It is possible to have a range of differential values ​​that includes a relatively high value TR.

[0123] The high concentration TC may indicate a carrier concentration value greater than that of the low concentration CC. For example, the low concentration CC may be about 10 14 (Value / CM 3 ). The high concentration TC can be about 10 18(Value / CM 3 ). However, the disclosure is not limited thereto. In the case where high concentration TC is defined as a carrier concentration sufficiently greater than low concentration CC, high concentration TC may be sufficient.

[0124] The inclined concentration area SLOA may be defined between the high concentration area HDA and the low concentration area LDA. For example, a graph indicating the carrier concentration according to the position of the semiconductor layer ACT may have an inflection point between the graph of the carrier concentration in the inclined concentration area SLOA and the graph of the carrier concentration in the high concentration area HDA. The graph indicating the carrier concentration may have an inflection point between the graph of the carrier concentration in the inclined concentration area SLOA and the graph of the carrier concentration in the low concentration area LDA.

[0125] The sloped concentration area SLOA may be defined between an area with a high value TR and an area with a low value BR. The curve can be seen in the slope concentration region SLOA The curve of HDA in the high concentration area There is an inflection point between the curves of The curve can be seen in the slope concentration region SLOA The curve of the low concentration area LDA There is an inflection point between the curve graphs.

[0126] According to an embodiment, in a plan view, at least a portion of the semiconductor layer ACT may overlap the gate electrode GAT. In a plan view, at least another portion of the semiconductor layer ACT may not overlap the gate electrode GAT.

[0127] For example, in a plan view, the low concentration area LDA may overlap the gate electrode GAT in its entirety. According to an embodiment, in a plan view, the inclined concentration area SLOA may overlap the gate electrode GAT in its entirety. According to an embodiment, in a plan view, the inclined concentration area SLOA may overlap the gate electrode GAT in its entirety. For example, the inclined concentration area SLOA may include a first inclined concentration area SLOA1 adjacent to the drain area DEA and a second inclined concentration area SLOA2 adjacent to the source area SEA. The first inclined concentration area SLOA1 may overlap the first end of the gate electrode GAT. The second inclined concentration area SLOA2 may overlap the second end of the gate electrode GAT.

[0128] According to an embodiment, in the inclined concentration area SLOA, the carrier concentration may be changed according to a slope SLO. For example, in the inclined concentration area SLOA, the carrier concentration may be changed according to a concentration range determined based on the slope SLO according to the position change amount of the semiconductor layer ACT.

[0129] According to an embodiment, the slope SLO may be expressed as

[0130] According to an embodiment, in the sloped concentration area SLOA, the semiconductor layer ACT may satisfy the following Formula 1.

[0131] [Formula 1]

[0132]

[0133] In Formula 1, ΔX may be a length variation [μm] in the sloped concentration region SLOA along the length direction of the semiconductor layer ACT, and ΔY may be a carrier concentration variation [1 / (cm 3 )].

[0134] According to the embodiment, in the sloped concentration region SLOA, the The value of can be changed according to a capacitance slope DSLO. For example, in the sloped concentration region SLOA, It may be a capacitance variation amount according to a voltage, and may be changed in a range based on a capacitance slope DSLO according to a position variation amount of the semiconductor layer ACT.

[0135] According to an embodiment, in the sloped concentration area SLOA, the semiconductor layer ACT may satisfy the following Formula 2.

[0136] [Formula 2]

[0137]

[0138] In formula 2, It may be related to data measured by the SCM 1 and may be a differential value defined based on a capacitance variation amount according to a voltage variation amount measured in the sloped concentration region SLOA of the semiconductor layer ACT.

[0139] According to an embodiment, the semiconductor layer ACT (e.g., the semiconductor region SA of the semiconductor layer ACT) may include a channel region CHA and a source region or drain region SDA. The source region or drain region SDA may include a source region SEA formed on one side of the channel region CHA and electrically connected to the source electrode SE and a drain region DEA formed on the other side of the channel region CHA and electrically connected to the drain electrode DE.

[0140] The channel area CHA may include a portion of the inclined concentration area SLOA and the low concentration area LDA. For example, the channel area CHA may include a region having a carrier concentration less than the reference concentration RC as a portion of the inclined concentration area SLOA.

[0141] According to an embodiment, the reference concentration RC may be appropriately determined according to the operating characteristics of the transistor to be manufactured. The reference concentration RC may be included in the carrier concentration range defined in the sloped concentration area SLOA. The reference concentration RC may be greater than the low concentration CC and may be less than the high concentration TC.

[0142] According to an embodiment, the inclined concentration region SLOA may include a region overlapping the gate electrode GAT in a plan view among regions other than the channel region CHA (e.g., the source region SEA and the drain region DEA). The inclined concentration region SLOA may include a region of the channel region CHA overlapping the gate electrode GAT in a plan view.

[0143] The source or drain area SDA may include a portion of the inclined concentration area SLOA and the high concentration area HDA. For example, the source or drain area SDA may include a region having a greater carrier concentration than the reference concentration RC as a portion of the inclined concentration area SLOA.

[0144] According to an embodiment, a dopant may be provided (eg, doped) to the source or drain region SDA. For example, a dopant may be provided to the source or drain region SDA to control conductivity of the source or drain region SDA.

[0145] Experimentally, in the case where the source or drain region SDA overlaps the gate electrode GAT, there may be a risk of forming a parasitic capacitance Cpa between the source or drain region SDA and the gate electrode GAT. According to an embodiment, as a region other than the channel region CHA, the region overlapping the gate electrode GAT can be minimized, and the formation of the parasitic capacitance Cpa can be minimized.

[0146] For example, in order to minimize the region overlapping the gate electrode GAT as a region other than the channel region CHA, the length ΔL of the sloped concentration region SLOA may need to be reduced, and the slope SLO associated with the concentration of carriers may need to be increased in the sloped concentration region SLOA.

[0147] According to an embodiment, the semiconductor layer ACT may be manufactured to minimize the inclined concentration area SLOA, and to form the slopes SLO and SLO of the carrier concentration in the inclined concentration area SLOA. The capacitance slope DSLO of the sloped concentration region SLO may be defined to be relatively steep. For example, the slope SLO of the carrier concentration formed in the sloped concentration region SLOA may satisfy the above equation 1, and The capacitance slope DSLO may satisfy the above formula 2. According to an embodiment, the length ΔL of the inclined concentration area SLOA may be in the range of about 0.05 μm to about 0.5 μm. According to an embodiment, the length ΔL of the inclined concentration area SLOA may be in the range of about 0.1 μm to about 0.4 μm. However, the disclosure is not necessarily limited thereto.

[0148] The risk of overlapping the gate electrode GAT with the region other than the channel region CHA can be minimized, and the formation of the parasitic capacitance Cpa can be prevented. Therefore, the risk of visually recognizing an abnormal image (such as stains) due to the formation of the parasitic capacitance Cpa can be prevented, and as a result, a display device DD with excellent display quality can be realized.

[0149] The semiconductor layer ACT according to the embodiment may include an oxide semiconductor, and in order to steeply define the slope SLO and the capacitance slope DSLO (for example, to satisfy equations 1 and 2), the range of the low concentration area LDA needs to be defined to be relatively narrow, and the low concentration CC may need to be defined to be low. It is necessary to strictly control the process factors for manufacturing the semiconductor layer ACT.

[0150] Experimentally, oxide semiconductors may also include oxide films in materials (e.g., silicon) used to form semiconductors. Oxide semiconductors may have relatively large insulation properties and resistance properties, and have substantially non-uniform surface properties. Therefore, aspects of analyzing element properties (such as carriers for active layers including oxide semiconductors) may be somewhat difficult. Therefore, it may be difficult to strictly control process factors during semiconductor manufacturing processes.

[0151] However, according to an embodiment, in order to analyze the semiconductor layer ACT (for example, the semiconductor layer ACT including an oxide semiconductor), the SCM 1 may be used, and process factors may be controlled for properly performing the SCM 1. Therefore, element characteristics such as carriers may be strictly controlled, and thus a stable semiconductor layer ACT may be manufactured.

[0152] For example, according to an embodiment, a process of analyzing the semiconductor layer ACT using the SCM 1 may be performed under a suitable process environment, the process environment for defining element characteristics of the semiconductor layer ACT may be updated at least once, and a semiconductor layer ACT having characteristics expected by a process user (e.g., satisfying equations 1 and 2) may be manufactured. The manufacturing process is described later.

[0153] According to an embodiment, the gate insulating layer GAL may be disposed on the semiconductor layer ACT. At least a portion of the gate insulating layer GAL may be disposed between the gate electrode GAT and the semiconductor layer ACT. The gate insulating layer GAL may include an inorganic material, and examples thereof are not particularly limited.

[0154] According to an embodiment, the gate electrode GAT may be disposed on the gate insulating layer GAL. In a plan view, the gate electrode GAT may overlap the channel region CHA and overlap the sloped concentration region SLOA. The gate electrode GAT may include a conductive material, and examples thereof are not particularly limited.

[0155] According to an embodiment, an interlayer insulating layer ILD may be disposed on the gate electrode GAT. The interlayer insulating layer ILD may cover the gate electrode GAT and may include a hole in which the contact members CNP1, CNP2_1, and CNP2_2 are formed. The interlayer insulating layer ILD may include an inorganic material or an organic material, and examples thereof are not particularly limited.

[0156] According to an embodiment, the source electrode SE and the drain electrode DE may be disposed on the interlayer insulating layer ILD. The source electrode SE may be electrically connected to the source region SEA of the semiconductor layer ACT through the 2_1st contact member CNP2_1 passing through the interlayer insulating layer ILD and the gate insulating layer GAL. According to an embodiment, the source electrode SE may be electrically connected to the lower conductive layer BML through the 2_2nd contact member CNP2_2 passing through the interlayer insulating layer ILD, the gate insulating layer GAL, and the buffer layer BFL. The drain electrode DE may be electrically connected to the drain region DEA of the semiconductor layer ACT through the first contact member CNP1 passing through the interlayer insulating layer ILD and the gate insulating layer GAL. The source electrode SE and the drain electrode DE may include a conductive material, and examples thereof are not specifically limited.

[0157] Reference Figures 7 to 15 A method of manufacturing a display device DD according to an embodiment is described. For the convenience of description, contents that may overlap with the above contents are briefly described or not repeated.

[0158] Figure 7 and Figure 8 is a schematic flowchart illustrating a method of manufacturing a display device according to an embodiment. Figures 9 to 15 2 is a schematic cross-sectional view for each process step showing a method of manufacturing a display device according to an embodiment. Figures 9 to 15 The above reference Figure 5 and Figure 6 A cross-sectional structure of the described embodiment.

[0159] Reference Figure 7 , the method of manufacturing the display device DD according to the embodiment may include patterning a base semiconductor layer ( S100 ) and forming a semiconductor region ( S200 ).

[0160] Reference Figure 8 According to an embodiment, the step of forming a semiconductor region (S200) may include: performing a process for defining a semiconductor region (S220); analyzing a semiconductor layer using an SCM (S240); determining whether a concentration of carriers satisfies a reference (S260); and performing an additional process for defining a semiconductor region based on a determination result (S280).

[0161] Reference Figure 7 and Fig. 9In the step of patterning the base semiconductor layer ( S100 ), a base semiconductor layer BACT may be disposed on a base layer BSL (eg, a substrate, etc.) (eg, the base semiconductor layer BACT may be patterned).

[0162] For example, the buffer layer BFL may be disposed (or deposited) on the base layer BSL, and the base semiconductor layer BACT may be disposed to contact the buffer layer BFL. According to an embodiment, the lower conductive layer BML may be patterned before forming the buffer layer BFL.

[0163] According to an embodiment, a conductive layer or an insulating layer may be formed on the base layer BSL based on an optional process for manufacturing a semiconductor device. For example, a conductive layer or an insulating layer may be formed on the base layer BSL by a photolithography process, and the conductive layer or the insulating layer may be deposited by various methods (sputtering, chemical vapor deposition, etc.). The disclosure is not necessarily limited to specific examples.

[0164] According to an embodiment, the base semiconductor layer BACT may be used to manufacture the semiconductor layer ACT, and may include an oxide semiconductor material.

[0165] Reference Figure 7 , Figure 8 and Fig.10 As a partial step of forming the semiconductor region ( S200 ), a step of a process for defining the semiconductor region ( S220 ) may be performed.

[0166] In the specification, a “semiconductor region” may refer to a “channel region” and a “source region or drain region.” For example, this step may be a step of making the semiconductor layer ACT have element characteristics for functioning as a transistor including a threshold voltage.

[0167] This step may include doping the base semiconductor layer BACT with a dopant (eg, ions). This step may include a thermal treatment process (eg, an annealing process).

[0168] According to an embodiment, the heat treatment process in this step may be performed at a process temperature in the range of about 300° C. to about 650° C. In the case where the heat treatment process is performed within the above numerical range, even in the case where the base semiconductor layer BACT may include an oxide semiconductor, a sufficient threshold voltage may be ensured, and the range of the semiconductor region SA may be strictly controlled in the base semiconductor layer BACT including the oxide semiconductor.

[0169] According to an embodiment, a dopant may be provided to the base semiconductor layer BACT, and a heat treatment process may be performed to manufacture a pre-update semiconductor layer ACT'. According to an embodiment, the pre-update semiconductor layer ACT' may include a pre-update semiconductor region SA', and may include a pre-update low concentration region LDA', a pre-update sloped concentration region SLOA', and a pre-update high concentration region HDA'.

[0170] The pre-update inclined concentration area SLOA' may include a first pre-update inclined concentration area SLOA1' and a second pre-update inclined concentration area SLOA2'. The pre-update high concentration area HDA' may include a first pre-update high concentration area HDA1' and a second pre-update high concentration area HDA2'.

[0171] This step may be performed before performing carrier concentration analysis for the target layer using the SCM 1. Therefore, in this step, it may be difficult to clearly determine the carrier concentration for the semiconductor layer ACT' before update, and it may be difficult to clearly distinguish the low concentration area LDA' before update, the sloped concentration area SLOA' before update, and the high concentration area HDA' before update from each other.

[0172] Reference Figure 7 , Figure 8 , Fig.11 and Fig.12 As part of the step of forming the semiconductor region (S200), a step of analyzing the semiconductor layer using the SCM 1 (S240) may be performed. Fig.11 and Fig.12 , the semiconductor layer ACT' before renewal is shown based on data that does not satisfy one reference.

[0173] In this step, the SCM 1 may analyze the element characteristics of the semiconductor layer ACT' before updating, and thus, may obtain information on the carrier concentration in the semiconductor layer ACT' before updating.

[0174] For example, the SCM 1 can measure the temperature of each region of the semiconductor layer ACT' before updating. Based on the measured To analyze the carrier concentration of each region of the semiconductor layer ACT' before updating. The numerical trend of can correspond to the trend of carrier concentration and can be obtained based on the data obtained by SCM 1. The information is used to analyze the carrier concentration gradient for each region.

[0175] According to an embodiment, the SCM 1 may include a probe capable of electrically contacting an upper portion of the pre-renewal semiconductor layer ACT' to be analyzed. The probe may measure capacitance between the probe and the analysis target while scanning the analysis target, and thus may obtain information on charge distribution of the analysis target.

[0176] This step can be performed, and thus in the semiconductor layer ACT' before update, the low concentration area LDA' before update, the sloped concentration area SLOA' before update, and the high concentration area HDA' before update can be distinguished from each other. Based on the reference concentration RC, the source or drain area SDA' before update and the channel area CHA' before update can be distinguished. The source or drain area SDA' before update can also include the source area SEA' before update and the drain area DEA' before update.

[0177] Reference Figure 7 and Figure 8 As a partial step of forming the semiconductor region (S200), a step of determining whether the concentration of carriers satisfies a reference (S260) may be performed.

[0178] For example, in the previous process step, information about the carrier concentration in the semiconductor layer ACT' before updating can be obtained. Therefore, in this step, it can be determined whether the semiconductor layer ACT' before updating meets the reference by comparing the obtained information about the carrier concentration with the selectable carrier concentration reference.

[0179] For example, a carrier concentration reference may be selected based on As an example, a carrier concentration reference that can be selected can be based on A reference defined based on measurement results (e.g., only on measurement results).

[0180] According to an embodiment, the selectable carrier concentration reference may include whether the length ΔL (e.g., the length ΔL' before updating) of the inclined concentration region SLOA (e.g., the inclined concentration region SLOA' before updating) is less than or equal to the selectable reference length. For example, the selectable reference length may be about 0.5 μm or less. In the case where the length ΔL is less than the selectable reference length, it may be determined that the reference is satisfied.

[0181] According to an embodiment, the selectable carrier concentration reference may include whether the slope SLO (e.g., the slope SLO' before updating) defined in the sloped concentration region SLOA (e.g., the sloped concentration region SLOA' before updating) is greater than or equal to the selectable reference slope. For example, the selectable reference slope may be 6.6 or less. In the case where the slope SLO is greater than the selectable reference slope, it may be determined that the reference is satisfied.

[0182] According to an embodiment, the selectable carrier concentration reference may include whether a capacitance slope DSLO (e.g., a pre-update slope DSLO') defined in the sloped concentration area SLOA (e.g., a pre-update sloped concentration area SLOA') is greater than or equal to a selectable reference capacitance slope. In the pre-update low concentration area LDA', the capacitance measured in the pre-update semiconductor layer ACT' The differential value range may include a relatively low value BR', and the value measured in the semiconductor layer ACT' before updating in the high concentration area HDA' before updating may be It may have a differential value range including a relatively high value TR'. For example, the selectable reference slope may be 8600 or less. In the case where the capacitance slope DSLO is greater than the selectable reference capacitance slope, it may be determined that the reference is satisfied.

[0183] According to an embodiment, the selectable carrier concentration reference may include whether the numerical range of the high concentration TC and the low concentration CC is within the selectable reference numerical range. In the case where the numerical range of the high concentration TC and the low concentration CC is within the selectable reference numerical range, it may be determined that the reference is satisfied.

[0184] According to an embodiment, the selectable carrier concentration reference may include whether the length of the expected source or drain area SDA (e.g., the source or drain area (SDA') before update) and the length of the channel area CHA (e.g., the channel area CHA' before update) are included in the selectable reference length range.

[0185] In this step, in the case where the concentration of carriers satisfies the reference, it can be determined that the pre-update semiconductor layer ACT′ is manufactured to have appropriate element characteristics, and thus the pre-update semiconductor layer ACT′ can be set as the above-mentioned semiconductor layer ACT.

[0186] In this step, when the concentration of carriers does not satisfy the reference, it can be determined that the pre-update semiconductor layer ACT' is manufactured to have no suitable element characteristics, and therefore a subsequent additional process for more strictly defining the semiconductor region SA (for example, performing an additional process (S280)) can be further performed.

[0187] Reference Figure 7 , Figure 8 and Fig.13 As a partial step of forming the semiconductor region ( S200 ), a step of an additional process ( S280 ) for defining the semiconductor region may be performed.

[0188] This step may be performed in the case where the concentration of carriers does not satisfy the reference in the previous determination step ( S260 ).

[0189] In this step, at least a portion of the same process as that performed in the process for defining the semiconductor region (S220) may be performed. For example, a process for providing a dopant to a partial region of the semiconductor layer ACT' before updating and a heat treatment process may be performed. As described above, since information about the carrier concentration for each region of the semiconductor layer ACT' before updating can be strictly ensured using SCM 1, the process for defining the semiconductor region SA may be performed efficiently. For example, dopants may be selectively doped in some or more regions where the carrier concentration needs to be increased. Therefore, the semiconductor region SA may be manufactured so that the length ΔL of the inclined concentration region SLOA may have a value lower than a range of values.

[0190] In this step, the heat treatment process performed may also be performed at a process temperature in the range of about 300° C. to about 650° C., and the above-mentioned technical effects may also be maintained.

[0191] By performing this step, in the semiconductor layer ACT' before update, the carrier concentration for each region can be updated. Therefore, the semiconductor layer ACT' before update can be set as an update semiconductor layer. Therefore, a low concentration area LDA, a high concentration area HDA, and an inclined concentration area SLOA can be formed. At least a portion of the range of the low concentration area LDA, the high concentration area HDA, and the inclined concentration area SLOA can be different from the range in which the low concentration area LDA' before update, the inclined concentration area SLOA' before update, and the high concentration area HDA' before update are formed.

[0192] Reference Figure 7 , Figure 8 , Fig.14 and Fig.15 As a partial step of forming the semiconductor region (S200), after performing an additional process for defining the semiconductor region (S280), a step of analyzing the semiconductor layer using SCM 1 (S240) and a step of determining whether the concentration of carriers meets a reference (S260) may be further performed.

[0193] The analyzing ( S240 ) step and the determining ( S260 ) step performed after performing the additional process ( S280 ) may be substantially the same as the above-described process.

[0194] Therefore, according to an embodiment, an additional process may be performed to determine whether the updated semiconductor layer has appropriate element characteristics, and in the case where it is determined that the updated semiconductor layer has the appropriate element characteristics, the updated semiconductor layer may not be processed again, and the updated semiconductor layer may be set as the semiconductor layer ACT. In step, an additional process may be performed to determine whether the updated semiconductor layer has appropriate element characteristics, and in the case where it is determined that the updated semiconductor layer does not have the appropriate element characteristics, the execution of the additional process (S280), the execution of the analysis (S240), and the execution of the determination (S260) may be further performed.

[0195] For convenience of description, the disclosure is described based on an embodiment in which the above process cycle is performed once, but the number of repetitions of the above process cycle is not specifically limited.

[0196] Therefore, according to the embodiment, the manufacturing process of the semiconductor layer ACT can be optimized using the SCM 1, and thus the semiconductor layer ACT having expected element characteristics can be provided. Since the pixel circuit PXC has the expected element characteristics, the risk of forming a parasitic capacitance Cpa in a transistor (e.g., a switching transistor) including the semiconductor layer ACT can be prevented, and a display device DD having significantly improved display performance / quality can be manufactured.

[0197] After that, you can use the above reference Figure 5 and Figure 6 The insulating layer and the conductive layer (eg, gate electrode GAT, source electrode SE, and drain electrode DE) described are patterned, and thus the pixel circuit layer PCL can be manufactured. The light emitting element layer LEL including the light emitting element LD on the pixel circuit layer PCL can be manufactured, and thus the display device DD according to the embodiment can be manufactured.

[0198] As described above, although the disclosure has been described with reference to the above embodiments, those skilled in the art or those having common knowledge in the art will understand that various modifications and changes may be made to the disclosure without departing from the spirit and technical field of the disclosure and as described in the claims.

[0199] Therefore, the disclosed technical scope should not be limited to the contents described in the specific embodiments of the specification, but should also be defined by the claims.

Claims

1. A display device, the display device include: A pixel circuit is disposed on the substrate layer and includes a transistor, wherein the transistor includes a source electrode, a drain electrode, a gate electrode and a semiconductor layer; as well as A light emitting element is electrically connected to the pixel circuit, wherein The semiconductor layer includes a low concentration region, a high concentration region, and an inclined concentration region between the low concentration region and the high concentration region, the low concentration region, the high concentration region, and the inclined concentration region being divided based on the concentration of carriers and being distinguished from each other in the length direction of the base layer, A portion of the inclined concentration region and the low concentration region form a channel region, and at least another portion of the inclined concentration region and the high concentration region form a source region and a drain region, and The semiconductor layer in the gradient concentration region satisfies Formula 1: [Formula 1] Wherein, ΔX is the length variation [μm] in the inclined concentration region in the length direction of the semiconductor layer, and ΔY is the concentration variation [1 / (cm 3 )].

2. The display device according to claim 1, in, The semiconductor layer is electrically connected to the source electrode in the source region, is electrically connected to the drain electrode in the drain region, and overlaps with the gate electrode in the inclined concentration region in a plan view, In a plan view, at least a portion of the semiconductor layer does not overlap the gate electrode in the source region and the drain region, In a plan view, the semiconductor layer entirely overlaps the gate electrode in the inclined concentration region, and The transistor comprises a switching transistor.

3. The display device according to claim 1, in, The semiconductor layer constitutes a thin film transistor including an oxide semiconductor, and The oxide semiconductor includes IGZO.

4. The display device according to claim 1, in, The semiconductor layer in the sloped concentration region satisfies Formula 2: [Formula 2] in, The method comprises: using a scanning capacitance microscope, measuring a differential value defined based on a capacitance change amount according to a voltage change amount in the gradient concentration region of the semiconductor layer.

5. The display device according to claim 1, in, The length of the gradient concentration region in the length direction of the semiconductor layer is in the range of 0.05 μm to 0.5 μm.

6. A display device, the display device include: A pixel circuit is disposed on the substrate layer and includes a transistor, wherein the transistor includes a source electrode, a drain electrode and a semiconductor layer; as well as A light emitting element is electrically connected to the pixel circuit, wherein The semiconductor layer includes a low concentration region, a high concentration region, and an inclined concentration region between the low concentration region and the high concentration region, the low concentration region, the high concentration region, and the inclined concentration region being divided based on the concentration of carriers and being distinguished from each other in the length direction of the base layer, A portion of the inclined concentration region and the low concentration region form a channel region, and at least another portion of the inclined concentration region and the high concentration region form a source region and a drain region, and The semiconductor layer in the sloped concentration region satisfies Formula 2: [Formula 2] in, The method comprises: using a scanning capacitance microscope, measuring a differential value defined based on a capacitance change amount according to a voltage change amount in the gradient concentration region of the semiconductor layer.

7. A method for manufacturing a display device, the method The following steps are involved: patterning a base semiconductor layer on the base layer; as well as A semiconductor region is formed in the base semiconductor layer, wherein: The step of forming the semiconductor region comprises: performing a process for defining the semiconductor region; analyzing the concentration of carriers formed in the base semiconductor layer using a scanning capacitance microscope; and Based on the information about the concentration of the carriers, determining whether the concentration of the carriers satisfies a selectable reference, and the step of forming the semiconductor region when the concentration of the carriers does not satisfy the selectable reference also includes: performing an additional process for defining the semiconductor region; and additionally performing the step of analyzing the concentration of the carriers after performing the additional process.

8. The method according to claim 7, in, The step of analyzing the concentration of the carriers comprises: for each region of the base semiconductor layer, measuring the concentration of the carriers by the scanning capacitance microscope. and It is obtained based on data measured for each region of the base semiconductor layer, and is a differential value defined based on the amount of capacitance change according to the amount of voltage change.

9. The method according to claim 7, in, The step of performing the process for defining the semiconductor region and the step of performing the additional process include performing an annealing process, and The annealing process is performed at a process temperature ranging from 300° C. to 650° C.

10. The method according to claim 7, in, The base semiconductor layer includes an oxide semiconductor.

11. The method according to claim 7, in, In a case where the concentration of the carriers satisfies the selectable reference, patterning of source and drain electrodes is performed without performing the additional process.

12. The method according to claim 7, in, The step of performing the process for defining the semiconductor region includes providing a dopant to the base semiconductor layer to provide a pre-renewal semiconductor layer, and The semiconductor layer before update includes a low concentration region before update, a high concentration region before update, and a pre-update inclined concentration region between the low concentration region before update and the high concentration region before update, and the low concentration region before update, the high concentration region before update, and the pre-update inclined concentration region before update are divided based on the concentration of the carriers and are distinguished from each other in the length direction of the base layer.

13. The method according to claim 12, in, The selectable reference is defined in the pre-update sloped concentration region and includes whether a slope is greater than or equal to a selectable reference slope, the slope indicating a change in the concentration of the carriers according to a change in the length of the pre-update semiconductor layer, and The selectable reference slope is 6.6 or less.

14. The method according to claim 12, in, The selectable reference includes whether the length of the inclined concentration region before updating in the length direction is less than or equal to a selectable reference length, and The selectable reference length is 0.5 μm or less.

15. The method according to claim 7, further comprising: The following steps are involved: A semiconductor layer satisfying said selectable reference is provided, wherein: The semiconductor layer includes a low concentration region, a high concentration region, and an inclined concentration region between the low concentration region and the high concentration region, the low concentration region, the high concentration region, and the inclined concentration region being divided based on the concentration of the carriers and being distinguished from each other in a length direction of the base layer, A portion of the inclined concentration region and the low concentration region form a channel region, and at least another portion of the inclined concentration region and the high concentration region form a source region and a drain region, and The semiconductor layer in the gradient concentration region satisfies Formula 1: [Formula 1] Wherein, ΔX is the length variation [μm] in the inclined concentration region in the length direction of the semiconductor layer, and ΔY is the concentration variation [1 / (cm 3 )].

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