Display device

Abstract

Disclosed is a display device including: a substrate including a display area including an emission area and a non-display area; a circuit layer on the substrate; and an element layer on the circuit layer and including a light emitting element corresponding to the emission region. The circuit layer includes: a light emitting pixel driver electrically connected to the light emitting element; the data line is used for transmitting data signals; a first dummy line extending in a first direction crossing the data line; and second dummy lines extending parallel to the data lines and respectively paired with the data lines. Each of the data lines and the second dummy lines includes an extension portion extending in a second direction crossing the first direction, and one data line further includes first protrusions crossing some of the first dummy lines, and one second dummy line paired with one data line further includes a second protrusion crossing other first dummy lines among the first dummy lines.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0074029 filed in the Korean Intellectual Property Office on June 9, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] Aspects of embodiments of the present disclosure relate to a display device. Background Art

[0003] With the development of information society, more and more demands are put forward for display devices for displaying images in various ways. For example, display devices are used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices and smart TVs.

[0004] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light-emitting display device. Examples of the light-emitting display device may include an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting element such as an inorganic semiconductor, and a micro light-emitting display device including a micro light-emitting element.

[0005] Organic light-emitting display devices use light-emitting elements to display images. Each of the light-emitting elements may include a light-emitting layer made of an organic light-emitting material. Organic light-emitting display devices use self-luminous elements to realize image display, and therefore, compared with other display devices, power consumption, response speed, luminous efficiency, brightness, and wide viewing angle, they may have relatively excellent performance in terms of power consumption, response speed, luminous efficiency, brightness, and wide viewing angle.

[0006] One surface of the display device may include a display area in which an image is displayed and a non-display area as a periphery of the display area. An emission area for emitting light having corresponding brightness and color may be arranged in the display area.

[0007] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0008] The display device may include a data supply line disposed in the non-display area and electrically connecting the data line to the display driving circuit.

[0009] In order to reduce the width of the non-display area due to the arrangement of the data supply lines, the display device may further include a transmission bypass line disposed in the display area. The transmission bypass line may electrically connect some of the data supply lines to some of the data lines.

[0010] In addition, when a transmission bypass line is set in a portion of the display area (for example, only in a portion of the display area), in order to prevent or substantially prevent the presence or absence of the transmission bypass line from being visually recognized, the transmission bypass line can be set as a portion of a virtual line set in the entire display area.

[0011] In addition, because the connection holes used for electrical connection between some of the data lines and the transmission bypass lines can be formed to have a relatively large width since they penetrate the via layer, the data lines and each of the dummy lines extending parallel to or substantially parallel to the data lines may include a protrusion protruding from the extending portion and overlapping the connection hole.

[0012] When the protrusion is provided at a point where a connection hole is provided (for example, provided only at a point where a connection hole is provided), the presence or absence of the protrusion can be visually identified, and thus the protrusion can be arranged symmetrically or substantially symmetrically regardless of the point where the connection hole is provided.

[0013] However, because the protrusions may each have a relatively large width, there may be a limit to increasing the number of light-emitting pixel drivers that may be disposed on a substrate due to the arrangement of the protrusions, which may make it more difficult to achieve high resolution.

[0014] One or more embodiments of the present disclosure are directed to a display device that can achieve high resolution by reducing the number of protrusions without significantly increasing visibility of the protrusions.

[0015] According to one or more embodiments of the present disclosure, a display device includes: a substrate including a display area including an emission area and a non-display area around the display area; a circuit layer on the substrate; and an element layer on the circuit layer, and including light-emitting elements corresponding to the emission areas, respectively. The circuit layer includes: light-emitting pixel drivers, respectively electrically connected to the light-emitting elements and positioned side by side with each other; a data line, configured to transmit a data signal to the light-emitting pixel driver; a first dummy line extending in a first direction intersecting the data line; and a second dummy line extending parallel to the data line and paired with the data line, respectively. Each of the data line and the second dummy line includes: an extension portion extending in a second direction intersecting the first direction, one of the data lines also includes: a first protrusion intersecting with some of the first dummy lines, and one of the second dummy lines paired with one of the data lines also includes: a second protrusion intersecting with other first dummy lines in the first dummy lines.

[0016] In an embodiment, the light-emitting pixel driver may include: a first light-emitting pixel driver and a second light-emitting pixel driver, which are adjacent to each other in the second direction and overlap with one data line; and a third light-emitting pixel driver, which is adjacent to the first light-emitting pixel driver in the first direction. The first light-emitting pixel driver may overlap with a first protrusion among the first protrusions, and the second light-emitting pixel driver may overlap with a second protrusion among the second protrusions. Another data line among the data lines overlapped with the third light-emitting pixel driver may further include: a third protrusion, which is respectively positioned side by side with the second protrusion, and another second dummy line among the second dummy lines paired with another data line may further include: a fourth protrusion, which is respectively positioned side by side with the first protrusion.

[0017] In an embodiment, the display device may further include: a display driving circuit configured to output a data signal to a data line, and the circuit layer may further include: a data supply line in the non-display area and electrically connected to the display driving circuit. The bypass area on one side of the display area may include: a bypass middle area; a first bypass side area parallel to the bypass middle area in a first direction and in contact with the non-display area; and a second bypass side area between the bypass middle area and the first bypass side area. The data line may include: a first data line in the first bypass side area; and a second data line in the second bypass side area. The first dummy line may include: a first transmission bypass line electrically connected to the first data line, and the second dummy line may include: a second transmission bypass line paired with the second data line and electrically connected to the first transmission bypass line. Among the data supply lines, the first data supply line configured to transmit the data signal among the data signals to the first data line may be electrically connected to the first data line through the first transmission bypass line and the second transmission bypass line, and among the data supply lines, the second data supply line configured to transmit the data signal among the data signals to the second data line may be directly electrically connected to the second data line.

[0018] In an embodiment, the data line and the second dummy line may be located on a via layer covering the first dummy line, the first transmission bypass line may be electrically connected to the second transmission bypass line through a first bypass connection hole, and electrically connected to the first data line through a second bypass connection hole, and the first bypass connection hole and the second bypass connection hole may penetrate the via layer.

[0019] In an embodiment, one second dummy line may be located between one data line and another data line and may be closer to the other data line than the one data line, and an extension portion of the one second dummy line may be adjacent to an extension portion of the other data line.

[0020] In an embodiment, the first protrusion may face an extending portion of one second dummy line, and the second protrusion may face an extending portion of one data line.

[0021] In an embodiment, one second dummy line and another second dummy line may be located between one data line and another data line, an extended portion of one second dummy line may be adjacent to an extended portion of one data line, an extended portion of another second dummy line may be adjacent to an extended portion of another data line, a second protrusion of one second dummy line may face an extended portion of another second dummy line, and a fourth protrusion of another second dummy line may face an extended portion of one second dummy line.

[0022] In an embodiment, the first protrusion may protrude in a direction opposite to a direction from an extending portion of one data line toward one second dummy line, and the third protrusion may protrude in a direction opposite to a direction from an extending portion of another data line toward another second dummy line.

[0023] In an embodiment, one data line and another data line may be located between one second dummy line and another second dummy line, and an extended portion of one data line may be adjacent to an extended portion of another data line.

[0024] In an embodiment, the first protrusion and the second protrusion may be located between an extending portion of one data line and an extending portion of one second dummy line.

[0025] In an embodiment, the light emitting pixel driver may be electrically connected to the data line through the data connection hole, and the data line may further include a connection protrusion overlapping the data connection hole.

[0026] In an embodiment, the second dummy line may further include a dummy protrusion symmetrical to the connecting protrusion.

[0027] In an embodiment, the connection protrusion may face an extended portion of the second dummy line.

[0028] In an embodiment, the display area may further include: a non-emitting area as a separation area between the emitting areas; and a light sensing area located in a portion of the non-emitting area. The element layer may further include light sensing elements respectively in the light sensing areas, and the circuit layer may further include: light sensing pixel drivers respectively electrically connected to the light sensing elements; and a readout line electrically connected to the light sensing pixel drivers.

[0029] In an embodiment, one of the readout lines may be located between an extension portion of one data line and an extension portion of another data line.

[0030] According to one or more embodiments of the present disclosure, a display device includes: a substrate including a display area including an emission area and a non-display area around the display area; a circuit layer on the substrate; and an element layer on the circuit layer, and including light-emitting elements corresponding to the emission areas, respectively. The circuit layer includes: light-emitting pixel drivers, which are electrically connected to the light-emitting elements, respectively, and are positioned side by side with each other; a data line, configured to transmit a data signal to the light-emitting pixel driver; a first dummy line, extending in a first direction intersecting the data line; and a second dummy line, extending parallel to the data line, and paired with the data line, respectively. Each of the data line and the second dummy line includes: an extension portion, extending in a second direction intersecting the first direction, and the light-emitting pixel driver includes: a first light-emitting pixel driver and a second light-emitting pixel driver, which are adjacent to each other in the second direction and overlap with one of the data lines. A data line overlapped with the first light-emitting pixel driver and the second light-emitting pixel driver further includes: a first protrusion crossing some of the first dummy lines, and a second dummy line among the second dummy lines paired with a data line further includes: a second protrusion crossing other first dummy lines among the first dummy lines. The first light-emitting pixel driver overlaps with a first protrusion among the first protrusions, the second light-emitting pixel driver overlaps with a second protrusion among the second protrusions, and the first protrusion and the second protrusion are located between an extended portion of a data line and an extended portion of a second dummy line.

[0031] In an embodiment, the light-emitting pixel driver may further include: a third light-emitting pixel driver, adjacent to the first light-emitting pixel driver in the first direction, another data line among the data lines overlapping with the third light-emitting pixel driver may further include: a third protrusion, positioned side by side with the second protrusions, and another second virtual line among the second virtual lines paired with another data line may further include: a fourth protrusion, positioned side by side with the first protrusions, respectively.

[0032] In an embodiment, the display device may further include: a display driving circuit configured to output a data signal to a data line, and the circuit layer may further include: a data supply line in the non-display area and electrically connected to the display driving circuit. The bypass area on one side of the display area may include: a bypass middle area; a first bypass side area parallel to the bypass middle area in a first direction and in contact with the non-display area; and a second bypass side area between the bypass middle area and the first bypass side area. The data line may include: a first data line in the first bypass side area; and a second data line in the second bypass side area. The first dummy line may include: a first transmission bypass line electrically connected to the first data line, and the second dummy line may include: a second transmission bypass line paired with the second data line and electrically connected to the first transmission bypass line. Among the data supply lines, the first data supply line configured to transmit the data signal among the data signals to the first data line may be electrically connected to the first data line through the first transmission bypass line and the second transmission bypass line, and among the data supply lines, the second data supply line configured to transmit the data signal among the data signals to the second data line may be directly electrically connected to the second data line.

[0033] In an embodiment, one data line and another data line may be located between one second dummy line and another second dummy line, and an extended portion of one data line may be adjacent to an extended portion of another data line.

[0034] In an embodiment, the display area may further include: a non-emitting area as a separation area between the emitting areas; and a light sensing area located in a portion of the non-emitting area. The element layer may further include: light sensing elements, respectively in the light sensing areas. The circuit layer may further include: light sensing pixel drivers, respectively electrically connected to the light sensing elements; and readout lines, electrically connected to the light sensing pixel drivers. One of the readout lines may be located between an extension portion of one data line and an extension portion of another data line.

[0035] According to one or more embodiments of the present disclosure, a display device may include: a substrate; a circuit layer disposed on the substrate; and an element layer disposed on the circuit layer. The substrate may include a display area in which an emission area is arranged. The element layer may include light-emitting elements corresponding to the emission areas, respectively. The circuit layer may include: light-emitting pixel drivers, respectively electrically connected to the light-emitting elements and arranged side by side with each other; a data line for transmitting a data signal to the light-emitting pixel driver; a first dummy line extending in a first direction and crossing the data line; and a second dummy line extending parallel to or substantially parallel to the data line and paired with the data line, respectively. Each of the data line and the second dummy line may include an extension extending in a second direction crossing the first direction. In addition, one of the data lines may include a first protrusion crossing some of the first dummy lines. Among the second dummy lines, one of the second dummy lines paired with one of the data lines may include a second protrusion crossing the remaining first dummy lines of the first dummy lines.

[0036] In other words, according to one or more embodiments of the present disclosure, each of a data line and a second virtual line may not include a protrusion that crosses all of the first virtual lines, a data line may include a first protrusion that crosses some of the first virtual lines (e.g., only the first protrusion), and a second virtual line may include a second protrusion that crosses the remaining first virtual lines (e.g., only the second protrusion).

[0037] According to one or more embodiments of the present disclosure, a data line may include a first protrusion that is less than the total number of first dummy lines, and a second dummy line may include a second protrusion that is less than the total number of first dummy lines. Therefore, the total number of protrusions provided on the substrate can be reduced, thereby improving the volume ratio of the circuit layer, and thus achieving high resolution.

[0038] According to one or more embodiments of the present disclosure, the light-emitting pixel driver may include: a first light-emitting pixel driver and a second light-emitting pixel driver, which are adjacent to each other in the second direction; and a third light-emitting pixel driver, which is adjacent to the first light-emitting pixel driver in the first direction. The first light-emitting pixel driver and the second light-emitting pixel driver may overlap with a data line. The first light-emitting pixel driver may overlap with one of the first protrusions of a data line, and the second light-emitting pixel driver may overlap with one of the second protrusions of a second dummy line.

[0039] According to one or more embodiments of the present disclosure, a first protrusion of one data line and a second protrusion of one second dummy line may alternately overlap with the light emitting pixel drivers arranged along the second direction.

[0040] According to one or more embodiments of the present disclosure, the first protrusions and the second protrusions may be repeatedly and alternately arranged in the second direction, so that visibility is not greatly increased even if they are not symmetrical to each other.

[0041] According to one or more embodiments of the present disclosure, connection holes for electrical connection between some of the first dummy lines and some of the data lines and connection holes for electrical connection between some of the first dummy lines and some of the second dummy lines may be arranged side by side with each other in a diagonal direction intersecting the first direction and the second direction. Therefore, even when the total number of the first protrusions and the second protrusions is reduced, the electrical connection paths between the first dummy lines, the second dummy lines, and the data lines may be maintained.

[0042] According to one or more embodiments of the present disclosure, the first protrusion and the second protrusion may be disposed between an extension portion of one data line and an extension portion of one second dummy line. Since the first protrusion and the second protrusion may not face each other and may be alternately arranged in a zigzag shape in the second direction, the distance between the extension portion of one data line and the extension portion of one second dummy line may be reduced. As a result, the volume ratio of the circuit layer may be further improved, so that high resolution may be achieved.

[0043] However, aspects and features of the disclosure are not limited to those described above, and various other aspects and features may be included in the disclosure or may be learned by practicing one or more of the presented embodiments of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings, in which:

[0045] Figure 1 is a perspective view showing a display device according to an embodiment;

[0046] Figure 2 It is shown Figure 1 A plan view of a display device;

[0047] Figure 3 It is along Figure 2 A cross-sectional view taken along line AA';

[0048] Figure 4 It is shown Figure 2 A layout diagram of an enlarged view of portion B;

[0049] Figure 5 It is shown Figure 1 A plan view of a main area and a sub-area of ​​a display device;

[0050] Figure 6 It is shown Figure 5 A layout diagram of an enlarged view of a portion C;

[0051] Figure 7 is a diagram showing the first embodiment of the present invention. Figure 5 A plan view of a data line, a first dummy line, and a second dummy line in an enlarged view of portions D and E of FIG.

[0052] Figure 8 It is along Figure 7 A cross-sectional view taken along line G-G';

[0053] Fig. 9 is a plan view showing the data line and the first dummy line according to the first embodiment in more detail;

[0054] Fig.10 is a diagram showing the first embodiment of the present invention. Figure 5 A plan view of a data line, a first dummy line, and a second dummy line in an enlarged view of a portion F of FIG.

[0055] Fig.11 It is shown Figure 6 An equivalent circuit diagram of a light-emitting pixel driver;

[0056] Fig.12 It is shown Fig.11 A cross-sectional view of a portion of a light-emitting pixel driver and a light-emitting element;

[0057] Fig.13 is a diagram showing a method according to the second embodiment Figure 5 A plan view of a data line, a first dummy line, and a second dummy line in an enlarged view of portions D and E of FIG.

[0058] Fig.14 is a plan view showing the data line and the first dummy line according to the second embodiment in more detail;

[0059] Fig.15 is a diagram showing a method according to the third embodiment Figure 5 A plan view of a data line, a first dummy line, and a second dummy line in an enlarged view of portions D and E of FIG.

[0060] Fig.16 is a plan view showing a data line and a first dummy line according to a third embodiment in more detail;

[0061] Fig.17 is a diagram showing a fourth embodiment of the present invention. Figure 5 A plan view of a data line, a first dummy line, and a second dummy line in an enlarged view of portions D and E of FIG.

[0062] Fig.18is a plan view showing a data line and a first dummy line according to a fourth embodiment in more detail;

[0063] Fig.19 is a diagram showing a method according to the fifth embodiment Figure 2 A layout diagram of an enlarged view of portion B;

[0064] Fig. 20 is a block diagram showing a display device according to a fifth embodiment;

[0065] Fig.21 It is shown Fig. 20 An equivalent circuit diagram of a light sensing pixel driver;

[0066] Fig. 22 is a diagram showing a method according to the fifth embodiment Figure 5 A plan view of a data line, a first dummy line, and a second dummy line in an enlarged view of portions D and E of FIG.

[0067] Fig.23 is a plan view showing the data line and the first dummy line according to the fifth embodiment in more detail. DETAILED DESCRIPTION

[0068] Hereinafter, the embodiments will be described in more detail with reference to the accompanying drawings in which the same reference numerals always represent the same elements. However, the present disclosure can be implemented in various different forms and should not be interpreted as being limited to the embodiments shown here. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects and features of the present disclosure will be fully conveyed to those skilled in the art. Therefore, the processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise stated, in the entire drawings and written descriptions, the same reference numerals represent the same elements, and therefore, their redundant descriptions may not be repeated.

[0069] When a certain embodiment can be implemented differently, the specific process order may be different from the described order. For example, two processes described successively may be performed simultaneously or substantially simultaneously, or may be performed in the reverse order of the described order.

[0070] In the accompanying drawings, for clarity, the relative sizes, thicknesses and ratios of elements, layers and regions may be exaggerated and / or simplified. For ease of explanation, spatially relative terms such as "under ... ", "under ... ", "under ... ", "above ... " and "upper" may be used here to describe the relationship between an element or feature and another element or feature as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, the element described as "under" or "under" or "below" other elements or features will then be oriented to "above" other elements or features. Therefore, the exemplary terms "under ... " and "under ... " can include two orientations of above and below. The device can be oriented in addition (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used here should be interpreted accordingly.

[0071] In the drawings, directions DR1, DR2, and DR3 are not limited to directions corresponding to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, directions DR1, DR2, and DR3 may be perpendicular to each other or substantially perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0072] As used herein, the phrase "in a plan view" means when viewing an object portion from above, and the phrases "in a cross-sectional view" and "in a schematic cross-sectional view" mean when viewing a schematic cross-section taken by vertically cutting an object portion from the side. The term "overlapping with..." or "overlapping" means that the first object can be above or below the second object or on the side of the second object, and vice versa. In addition, the term "overlapping with..." may include stacking, stacking, facing or facing, extending on, covering or partially covering, or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The expression "non-overlapping" may include meanings such as "spaced apart", "biased" or "deviation" and any other suitable equivalents as will be appreciated and understood by a person of ordinary skill in the art. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, but still facing each other.

[0073] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first region, first layer or first section described below may be referred to as a second element, second component, second region, second layer or second section.

[0074] It will be understood that when an element or layer is referred to as being "on," "connected to," or "bonded to" another element or layer, the element or layer may be directly on, directly connected to, or directly bonded to the other element or layer, or there may be one or more intermediate elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, another region, or another element, the layer, region, or element may be directly electrically connected to the other layer, another region, or another element, and / or may be indirectly electrically connected with one or more intermediate layers, intermediate regions, or intermediate elements therebetween. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or the only layer between the two elements or layers, or there may also be one or more intermediate elements or intermediate layers.

[0075] The term used herein is for the purpose of describing specific embodiments, and is not intended to be a limitation of the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form "one (kind / person)" is also intended to include the plural form. It will also be understood that when the terms "include", "comprise", "have" and their variations are used in this specification, the descriptions indicate the existence of stated features, integral bodies, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or their groups. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. For example, the statement "A and / or B" represents A, B or A and B. When a statement such as "at least one (kind / person) in ... " is located after a column of elements, the entire column of elements is modified without modifying the individual elements in the column. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0076] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent variation in measured or calculated values ​​that one of ordinary skill in the art would recognize. For example, the term "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the term "using" and variations thereof may be considered synonymous with the term "utilizing" and variations thereof, respectively.

[0077] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0078] Figure 1 is a perspective view showing a display device according to an embodiment. Figure 2 It is shown Figure 1 A plan view of a display device. Figure 3 It is along Figure 2 A cross-sectional view taken along line AA'.

[0079] Reference Figure 1 and Figure 2 The display device 100 is a device for displaying moving images or still images. The display device 100 can be used as a display screen of various suitable devices such as televisions, laptop computers, monitors, billboards, and Internet of Things (IOT) devices, and for various suitable portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs).

[0080] The display device 100 may be a light-emitting display device, such as an organic light-emitting display including an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, and a micron light-emitting display including a micron or nanometer light-emitting diode (LED). Hereinafter, the display device 100 may be described in more detail in the context of an organic light-emitting display device as a representative example. However, the present disclosure is not limited thereto, and the display device 100 may be any suitable display device, for example, including an organic insulating material, an organic light-emitting material, and a metal material.

[0081] The display device 100 may be formed to be flat or substantially flat, but the present disclosure is not limited thereto. For example, the display device 100 may include curved portions formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display device 100 may be formed to be flexible so that it can be bent, folded, or curled.

[0082] like Figure 1 , Figure 2 and Figure 3 As shown in , the display device 100 includes a substrate 110 .

[0083] The substrate 110 may include a main area MA corresponding to a display surface of the display device 100 and a sub area SBA protruding from one side of the main area MA.

[0084] The main area MA may include a display area DA and a non-display area NDA disposed around (eg, adjacent to) the display area DA.

[0085] The display area DA may be formed in a rectangular shape having short sides extending in a first direction DR1 and long sides extending in a second direction DR2 intersecting the first direction DR1 in a plan view. Corners where the short sides extending in the first direction DR1 and the long sides extending in the second direction DR2 meet each other may be rounded to have a suitable curvature (e.g., a predetermined curvature), or may be right angles. The planar shape of the display area DA is not limited to a rectangular shape, and may be formed in other suitable polygonal shapes, circular shapes, or elliptical shapes.

[0086] The display area DA may occupy most of the main area MA. The display area DA may be disposed at the center of the main area MA.

[0087] The non-display area NDA may be disposed at an edge of the main area MA to surround the display area DA (eg, around a periphery of the display area DA).

[0088] The sub-region SBA may be a region protruding from the non-display region NDA of the main region MA to one side in the second direction DR2 .

[0089] Since a portion of the sub-area SBA may be deformed to be curved, another portion of the sub-area SBA may be disposed on the rear surface of the display device 100 .

[0090] Figure 2 and Figure 3 The display device 100 is shown in which a portion of the sub-area SBA is in a bent state.

[0091] like Figure 3As shown in , the display device 100 includes a substrate 110 , a circuit layer 120 disposed on the substrate 110 , and a light emitting element layer (or referred to as an element layer) 130 disposed on the circuit layer 120 .

[0092] In addition, the display device 100 may further include an encapsulation layer 140 covering the light emitting element layer 130 and a touch sensor layer 150 disposed on the encapsulation layer 140 .

[0093] The display device 100 may further include a display driving circuit 200 .

[0094] In addition, the display device 100 may further include a circuit board 300 and a touch driving circuit 400 .

[0095] The display driving circuit 200 may be provided as an integrated circuit (IC) and mounted on the sub-area SBA of the substrate 110 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. However, the present disclosure is not limited thereto, and the arrangement of the display driving circuit 200 is not limited to Figure 3 The arrangement shown in .

[0096] For example, the display driving circuit 200 may be attached to the circuit board 300 by a chip on film (COF) method.

[0097] The circuit board 300 may be coupled to a signal pad (also referred to as a “pad” or “solder pad”) SPD (see, for example, FIG. 1 ) disposed in the sub-area SBA of the substrate 110. Figure 5 ).

[0098] For example, the circuit board 300 may be attached and electrically connected to the signal pads SPD of the sub-area SBA using a low-resistance high-reliability material such as SAP or an anisotropic conductive film.

[0099] The circuit board 300 may include a plurality of circuits for supplying digital video data, timing signals, and driving voltages to the circuit layer 120 and the display driving circuit 200 .

[0100] The circuit board 300 may be a flexible printed circuit board such as a chip on film, a printed circuit board, or a flexible film.

[0101] The touch driving circuit 400 may be electrically connected to the touch sensor layer 150 .

[0102] The touch driving circuit 400 may apply a touch driving signal to the driving line of the touch sensor layer 150, and detect the amount of charge change of the capacitance based on the touch sensing signal received from the sensing line, thereby determining whether the user has touched or approached the relevant surface of the display device 100. The user's touch refers to the contact between the user's finger or an object such as a pen and the display device 100. The user's approach refers to the user's finger or an object such as a pen hovering at a suitable distance from the display device 100.

[0103] Figure 4 It is shown Figure 2 Layout diagram of an enlarged view of portion B.

[0104] Reference Figure 4 , the emission area EA may be disposed in the display area DA of the substrate 110 .

[0105] In other words, the display area DA may include the emission areas EA arranged side by side with each other and the non-emission areas NEA as separation areas between the emission areas EA.

[0106] The emission area EA may have a rhombus planar shape or a rectangular planar shape. However, the present disclosure is not limited thereto, and the planar shape of the emission area EA is not limited to Figure 4 In other words, the emission area EA may have a polygonal plan shape such as a quadrangle, a pentagon, or a hexagon, or may have a circular plan shape or an elliptical plan shape with curved edges.

[0107] The emission area EA may include a first emission area EA1 for emitting light of a first color in a suitable band (e.g., a predetermined band), a second emission area EA2 for emitting light of a second color in a band lower than the band of the first color, and a third emission area EA3 for emitting light of a third color in a band lower than the band of the second color.

[0108] For example, the first color may be red having a wavelength of about 600nm to 750nm, the second color may be green having a wavelength of about 480nm to 560nm, and the third color may be blue having a wavelength of about 370nm to 460nm.

[0109] The first emission regions EA1 and the third emission regions EA3 may be alternately arranged with each other along at least one of the first direction DR1 and the second direction DR2.

[0110] The second emission regions EA2 may be arranged side by side with each other in at least one of the first direction DR1 and the second direction DR2.

[0111] The pixels PX for displaying corresponding brightness and color may be provided with the first emission area EA1, the second emission area EA2, and the third emission area EA3 adjacent to each other among the emission areas EA.

[0112] In other words, each of the pixels PX may be a basic unit for displaying various colors including white at a desired brightness (eg, a predetermined brightness).

[0113] Each of the pixels PX may include at least one first emission area EA1, at least one second emission area EA2, and at least one third emission area EA3 adjacent to each other. Therefore, each of the pixels PX may display various colors by mixing light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3 adjacent to each other.

[0114] Figure 5 It is shown Figure 1 A plan view of the main area and sub-areas of a display device.

[0115] Reference Figure 5 , the substrate 110 of the display device 100 according to the embodiment includes a main area MA including a display area DA and a non-display area NDA, and a sub area SBA protruding from one side of the main area MA.

[0116] The display area DA may include a bypass area DEA disposed at one side of the display area DA adjacent to the sub area SBA, and a general area GA disposed in a remaining area of ​​the display area DA except the bypass area DEA.

[0117] The bypass area DEA includes a bypass middle area MDDA, a first bypass side area SDA1, and a second bypass side area SDA2. The bypass middle area MDDA may be disposed at the center of the bypass area DEA in the first direction DR1. The first bypass side area SDA1 may be parallel to or substantially parallel to the bypass middle area MDDA in the first direction DR1, and may contact the non-display area NDA. The second bypass side area SDA2 may be disposed between the bypass middle area MDDA and the first bypass side area SDA1.

[0118] The first bypass side area SDA1 may be disposed closer to a corner (eg, a curved or bent corner) of the substrate 110 than the bypass middle area MDDA and the second bypass side area SDA2.

[0119] The first and second bypass side areas SDA1 and SDA2 may be disposed between the bypass middle area MDDA and the non-display area NDA on both sides (eg, opposite sides) of the bypass middle area MDDA in the first direction DR1 .

[0120] The general area GA may include a general middle area GMA, a first general side area GSA1, and a second general side area GSA2. The general middle area GMA may be connected to the bypass middle area MDDA of the bypass area DEA in the second direction DR2. The first general side area GSA1 may be connected to the first bypass side area SDA1 of the bypass area DEA in the second direction DR2. The second general side area GSA2 may be connected to the second bypass side area SDA2 of the bypass area DEA in the second direction DR2.

[0121] The non-display area NDA may include a scan driving circuit area SCDA in which a scan driving circuit may be disposed.

[0122] The scan driving circuit area SCDA may be disposed in the non-display area NDA adjacent to at least one side of the display area DA in the first direction DR1.

[0123] The subregion SBA may include a bending region BA deformed into a curved shape, a first subregion SB1 disposed between one side of the bending region BA and the main region MA, and a second subregion SB2 connected to the other side (eg, opposite side) of the bending region BA.

[0124] When the bending area BA is deformed into a bent shape, the second sub-area SB2 is disposed under the substrate 110 and overlaps the main area MA.

[0125] The display driving circuit 200 may be disposed in the second sub-region SB2 .

[0126] A signal pad SPD coupled to the circuit board 300 may also be disposed in the second sub-region SB2 .

[0127] Figure 6 It is shown Figure 5 Layout diagram of an enlarged view of portion C.

[0128] Reference Figure 6 According to the embodiment, the circuit layer 120 of the display device 100 includes a plurality of light-emitting pixel drivers EPD, which are electrically connected to the light-emitting elements LE (see FIG. 1 ) of the element layer 130, which are respectively arranged in the emission area EA. Fig.11 ) and are arranged side by side with each other. The circuit layer 120 may also include a circuit for transmitting a data signal Vdata (eg, Fig.11 ) is transmitted to the data line DL of the light emitting pixel driver EPD, the first dummy lines DML1 extending in the first direction DR1 and crossing the data line DL, and the second dummy lines DML2 extending parallel or substantially parallel to the data line DL and respectively paired with the data lines DL.

[0129] The data line DL and the second dummy line DML2 may extend in the second direction DR2.

[0130] The circuit layer 120 may further include a data supply line DSPL disposed in the non-display area NDA and electrically connected to the display driving circuit 200 .

[0131] The data supply line DSPL electrically connects the display driving circuit 200 to the data line DL.

[0132] The data lines DL may include a first data line DL1 disposed in the first bypass side area SDA1 and a second data line DL2 disposed in the second bypass side area SDA2.

[0133] The first dummy line DML1 may include a first transmission bypass line TDEL1 electrically connected to the first data line DL1 of the first bypass side area SDA1.

[0134] The second dummy line DML2 may include a second transmission bypass line TDEL2 paired with the second data line DL2 of the second bypass side area SDA2 and electrically connected to the first transmission bypass line TDEL1 .

[0135] The data supply lines DSPL may include a first data supply line DSPL1 for transmitting a data signal of the first data line DL1 and a second data supply line DSPL2 for transmitting a data signal of the second data line DL2 .

[0136] The first data supply line DSPL1 may be electrically connected to the second transmission bypass line TDEL2 .

[0137] Therefore, the first data line DL1 may be electrically connected to the first data supply line DSPL1 through the first and second transmission bypass lines TDEL1 and TDEL2 provided in the bypass area DEA of the display area DA.

[0138] In other words, similar to the second data supply line DSPL2, even if the first data supply line DSPL1 extends to (for example, only extends to) the second bypass side area SDA2 relatively adjacent to the sub-area SBA, the electrical connection between the first data line DL1 and the first data supply line DSPL1 can be achieved through the first transmission bypass line TDEL1 and the second transmission bypass line TDEL2.

[0139] Therefore, because the first data supply line DSPL1 does not extend relatively long from the sub-area SBA to reach the first bypass side area SDA1 adjacent to the corner (e.g., a curved or bent corner) of the substrate 110, and is not disposed in a portion of the non-display area NDA between the corner of the substrate 110 and the first bypass side area SDA1, the width of the non-display area NDA can be reduced.

[0140] The second data supply line DSPL2 may extend to the second bypass side area SDA2 and may be directly electrically connected to the second data line DL2 .

[0141] The data lines DL may further include a third data line DL3 disposed in the bypass middle area MDDA. In addition, the data supply line DSPL may further include a third data supply line DSPL3 for transmitting a data signal of the third data line DL3.

[0142] The third data supply line DSPL3 may extend to the bypass middle area MDDA and may be directly electrically connected to the third data line DL3 .

[0143] The first dummy line DML1 may further include a first auxiliary line ASL1 in addition to the first transmission bypass line TDEL1 .

[0144] The second dummy line DML2 may further include a second auxiliary line ASL2 in addition to the second transmission bypass line TDEL2 .

[0145] The first and second auxiliary lines ASL1 and ASL2 may be included to reduce visibility of the first and second transmission bypass lines TDEL1 and TDEL2 limitedly disposed in the bypass area DEA (eg, disposed only in the bypass area DEA).

[0146] The second transmission bypass line TDEL2 may be disposed between the non-display area NDA and the first transmission bypass line TDEL1 .

[0147] Considering visibility of the second transmission bypass line TDEL2 , any one of the second auxiliary lines ASL2 may be disposed in series with the second transmission bypass line TDEL2 in the second direction DR2 and may extend from the second transmission bypass line TDEL2 to the display area DA.

[0148] Therefore, a portion of the second data line DL2 may be paired with the second transmission bypass line TDEL2, and another portion of the second data line DL2 may be paired with any one of the second auxiliary lines ASL2 in series with the second transmission bypass line TDEL2.

[0149] Since the second transmission bypass line TDEL2 is disposed in the second bypass side area SDA2 (eg, disposed only in the second bypass side area SDA2 ), the first data line DL1 of the first bypass side area SDA1 may be paired with the second auxiliary line ASL2 as a whole.

[0150] In addition, the third data line DL3 bypassing the middle area MDDA may be paired with the second auxiliary line ASL2 as a whole.

[0151] The circuit layer 120 may further include a first power line VDSPL and a second power line VSSPL, which respectively transmit a first power ELVDD (eg, see FIG. 1 ) for driving the light emitting element of the element layer 130. Fig.11 ) and a second power ELVSS (for example, see Fig.11 ).

[0152] The first power line VDSPL and the second power line VSSPL may be disposed in the non-display area NDA and may extend to the sub-area SBA.

[0153] Among the signal pads SPD disposed in the second sub-region SB2 , a first power pad for transmitting the first power ELVDD and a second power pad for transmitting the second power ELVSS may be electrically connected to the first power line VDSPL and the second power line VSSPL, respectively.

[0154] The first and second auxiliary lines ASL1 and ASL2 may be electrically connected to the second power line VSSPL.

[0155] Figure 7 is a diagram showing the first embodiment of the present invention. Figure 5 A plan view of a data line, a first dummy line, and a second dummy line in an enlarged view of portions D and E of FIG. Figure 8 It is along Figure 7 A cross-sectional view taken along line G-G'.

[0156] Figure 7 The portion D shows a portion of the first bypass side area SDA1 adjacent to the second bypass side area SDA2, Figure 7 The portion E of FIG. 1 shows a portion of the second bypass side area SDA2 adjacent to the first bypass side area SDA1 .

[0157] Reference Figure 7 , the light emitting pixel drivers EPD may be arranged side by side with each other in the first direction DR1 and the second direction DR2.

[0158] The light emitting pixel drivers EPD aligned with each other in the second direction DR2 may overlap any one of the data lines DL and may be electrically connected to one of the data lines DL through the data connection hole DTCH.

[0159] In other words, the light emitting pixel driver EPD may be electrically connected to the data line DL through the data connection hole DTCH.

[0160] The data line DL may include a connection protrusion DCPR overlapping the data connection hole DTCH of the light emitting pixel driver EPD.

[0161] In addition, considering the visibility of the connection bump DCPR, the second dummy line DML2 may include a dummy bump DMPR symmetrical or substantially symmetrical to the connection bump DCPR.

[0162] The circuit layer 120 may further include a first power auxiliary line VDAL electrically connected to the first power line VDSPL. The first power auxiliary line VDAL may extend in the first direction DR1 and may be alternately disposed with the first dummy lines DML1.

[0163] The first transmission bypass line TDEL1 may be disposed between the first data line DL1 and the second transmission bypass line TDEL2. Considering visibility of the first transmission bypass line TDEL1, any two first auxiliary lines ASL1 may extend from both ends (eg, opposite ends) of the first transmission bypass line TDEL1 to the non-display area NDA.

[0164] The first transmission bypass line TDEL1 may be electrically connected to the second transmission bypass line TDEL2 through the first bypass connection hole DECH1 , and may be electrically connected to the first data line DL1 through the second bypass connection hole DECH2 .

[0165] Reference Figure 8 , the first data line DL1 , the second data line DL2 , the second transmission bypass line TDEL2 , and the second auxiliary line ASL2 may be disposed on the via layer VIA1 covering the first transmission bypass line TDEL1 .

[0166] In other words, the data line DL and the second dummy line DML2 may be disposed on the via layer VIA1 covering the first dummy line DML1 .

[0167] In addition, the first bypass connection hole DECH1 for electrical connection between the first transmission bypass line TDEL1 and the second transmission bypass line TDEL2 and the second bypass connection hole DECH2 for electrical connection between the first transmission bypass line TDEL1 and the first data line DL1 may both penetrate the via layer VIA1 .

[0168] The data line DL, the second dummy line DML2 , and the first dummy line DML1 may be covered by the passivation layer VIA2 .

[0169] like Figure 7 As shown in FIG. 1 , according to the first embodiment, the data lines DL and the second dummy lines DML2 may be disposed alternately with each other along the first direction DR1. In other words, any one of the second dummy lines DML2 may be disposed between two data lines DL.

[0170] Fig. 9 is a plan view showing the data line and the first dummy line according to the first embodiment in more detail.

[0171] Reference Fig. 9 , each of the data line DL and the second dummy line DML2 includes an extending portion EXT extending in the second direction DR2.

[0172] One data line OR_DL of the data lines DL further includes a first protrusion PR1 crossing some of the first dummy lines DML1 .

[0173] In other words, one data line OR_DL may include the extension portion EXT, the first protrusion PR1, and the connection protrusion DCPR.

[0174] Among the second dummy lines DML2 , one second dummy line OR_DML2 paired with one data line OR_DL further includes a second protrusion PR2 crossing the remaining first dummy lines DML1 among the first dummy lines DML1 .

[0175] In other words, one second dummy line OR_DML2 may include the extension portion EXT, the second protrusion PR2 , and the dummy protrusion DMPR.

[0176] According to the first embodiment, the first protrusion PR1 of one data line OR_DL crosses some (eg, only some) of the first dummy lines DML1 instead of all of the first dummy lines DML1 .

[0177] On the other hand, the second protrusion PR2 of one second dummy line OR_DML2 paired with one data line OR_DL crosses the remaining (eg, only the remaining) first dummy lines DML1 except some of the first dummy lines DML1 crossing the first protrusion PR1 .

[0178] If each of one data line OR_DL and one second dummy line OR_DML2 includes protrusions crossing all the first dummy lines DML1, the total number of protrusions disposed at crossing regions (e.g., crossing points) between the first dummy line DML1 and each of one data line OR_DL and one second dummy line OR_DML2 becomes twice the number of first dummy lines DML1.

[0179] However, according to the first embodiment, the first protrusions PR1 cross some (e.g., only some) of the first dummy lines DML1, and the second protrusions PR2 cross the remaining (e.g., only the remaining) of the first dummy lines DML1. Therefore, the total number of the first protrusions PR1 and the second protrusions PR2 can be reduced to the total number of the first dummy lines DML1.

[0180] Therefore, the width of the area allocated for the arrangement of the first and second protrusions PR1 and PR2 in the display area DA can be reduced. Therefore, the number of light emitting pixel drivers EPD that can be disposed in the display area DA can be increased, so that high resolution can be achieved for the display device 100.

[0181] The light emitting pixel driver EPD may include a first light emitting pixel driver EPD1 , a second light emitting pixel driver EPD2 adjacent to the first light emitting pixel driver EPD1 in the second direction DR2 , and a third light emitting pixel driver EPD3 adjacent to the first light emitting pixel driver EPD1 in the first direction DR1 .

[0182] The first light emitting pixel driver EPD1 and the second light emitting pixel driver EPD2 may overlap one data line OR_DL.

[0183] The first light emitting pixel driver EPD1 may overlap one of the first protrusions PR1 included in one data line OR_DL.

[0184] The second light emitting pixel driver EPD2 may overlap one of the second protrusions PR2 of one second dummy line OR_DML2 .

[0185] Among the data lines DL, another data line OT_DL overlapped with the third light emitting pixel driver EPD3 may further include third protrusions PR3 disposed in parallel with the second protrusions PR2 , respectively.

[0186] Among the second dummy lines DML2 , another second dummy line OT_DML2 paired with another data line OT_DL may further include fourth protrusions PR4 disposed side by side with the first protrusions PR1 , respectively.

[0187] According to the first embodiment, one second dummy line OR_DML2 may be disposed between one data line OR_DL and the other data line OT_DL. In addition, one second dummy line OR_DML2 may be disposed closer to the other data line OT_DL than one data line OR_DL paired with one second dummy line OR_DML2.

[0188] In other words, the extending portion EXT of one second dummy line OR_DML2 may be adjacent to the extending portion EXT of another data line OT_DL.

[0189] According to the first embodiment, the first protrusion PR1 of one data line OR_DL may face the extending portion EXT of one second dummy line OR_DML2 , and the second protrusion PR2 of one second dummy line OR_DML2 may face the extending portion EXT of one data line OR_DL.

[0190] In other words, the first protrusion PR1 of one data line OR_DL and the second protrusion PR2 of one second dummy line OR_DML2 may be alternately arranged one by one with each other at the light emitting pixel driver EPD aligned with each other in the second direction DR2 .

[0191] According to the first embodiment, the first protrusions PR1 of the data line OR_DL and the fourth protrusions PR4 of the second dummy line OT_DML2 may be alternately arranged one by one with each other at the light emitting pixel driver EPD aligned with each other in the first direction DR1 .

[0192] In addition, the second protrusions PR2 of the second dummy line OR_DML2 and the third protrusions PR3 of the data line OT_DL may be alternately arranged one by one with each other at the light emitting pixel driver EPD aligned with each other in the first direction DR1 .

[0193] As described above, according to the first embodiment, the protrusions PR1 and PR3 of the data line DL crossing the first dummy line DML1 and the protrusions PR2 and PR4 of the second dummy line DML2 may be alternately arranged one after another in a zigzag shape in the first and second directions DR1 and DR2 .

[0194] As a result, even when the total number of the protrusions PR1 and PR3 of the data lines DL and the protrusions PR2 and PR4 of the second dummy lines DML2 that cross the first dummy lines DML1 decreases, a significant increase in the visibility of the protrusions PR1 and PR3 of the data lines DL and the protrusions PR2 and PR4 of the second dummy lines DML2 can be prevented or substantially prevented due to the relatively regular and symmetrical arrangement of the protrusions PR1 and PR3 of the data lines DL and the protrusions PR2 and PR4 of the second dummy lines DML2.

[0195] like Figure 7 As shown in FIG, a first bypass connection hole DECH1 for electrical connection between the first transmission bypass line TDEL1 and the second transmission bypass line TDEL2 may be provided in the second protrusion PR2. Also, a second bypass connection hole DECH2 for electrical connection between the first transmission bypass line TDEL1 and the first data line DL1 may be provided in the first protrusion PR1.

[0196] Therefore, even if the total number of protrusions PR1, PR2, PR3 and PR4 crossing the first virtual line DML1 decreases, the first bypass connection holes DECH1 can be arranged side by side with each other in a diagonal direction (e.g., a predetermined diagonal direction) crossing the first direction DR1 and the second direction DR2, and the second bypass connection holes DECH2 can also be arranged side by side with each other in a diagonal direction (e.g., a predetermined diagonal direction).

[0197] In other words, even if the total number of protrusions PR1 , PR2 , PR3 , and PR4 crossing the first dummy line DML1 decreases, the first transmission bypass lines TDEL1 may be sequentially arranged with the first power auxiliary line VDAL interposed between the first transmission bypass lines TDEL1 .

[0198] Therefore, no matter how the total number of protrusions PR1 , PR2 , PR3 , and PR4 crossing the first dummy line DML1 is reduced, the electrical connection path between the second transmission bypass line TDEL2 , the first transmission bypass line TDEL1 , and the first data line DL1 may be maintained.

[0199] Fig.10 is a diagram showing the first embodiment of the present invention. Figure 5 A plan view of a data line, a first dummy line, and a second dummy line in an enlarged view of portion F of FIG.

[0200] Fig.10 A portion of the bypass middle area MDDA is shown.

[0201] Reference Fig.10 , the data lines DL may include a third data line DL3 disposed in the bypass middle area MDDA. The third data line DL3 may be paired with the second auxiliary line ASL2 as a whole.

[0202] In the bypass middle area MDDA, each of the first auxiliary lines ASL1 may be electrically connected to at least one second auxiliary line ASL2 through the auxiliary connection hole ASCH.

[0203] The auxiliary connection holes ASCH may be arranged in a predetermined diagonal direction crossing the first direction DR1 and the second direction DR2.

[0204] Fig.11 It is shown Figure 6 Equivalent circuit diagram of the light-emitting pixel driver.

[0205] Reference Fig.11 The light emitting pixel drivers EPD of the circuit layer 120 are electrically connected to the light emitting elements LE of the element layer 130 respectively.

[0206] The circuit layer 120 may further include a first power line VDL for transmitting the first power ELVDD, a first initialization power line VIL for transmitting the first initialization power Vint, a second initialization power line VAIL for transmitting the second initialization power Vaint, and a bias power line VBL for transmitting the bias power VBS.

[0207] In addition, the circuit layer 120 may also include a scan write line GWL for transmitting a scan write signal GW, a scan initialization line GIL for transmitting a scan initialization signal GI, an emission control line ECL for transmitting an emission control signal EC, a gate control line GCL for transmitting a gate control signal GC, and a bias control line GBL for transmitting a bias control signal GB.

[0208] Each of the light emitting pixel drivers EPD may include a driving transistor DT generating a driving current for driving a light emitting element LE electrically connected to the one light emitting pixel driver EPD, two or more transistors ST1 to ST7 electrically connected to the driving transistor DT, and at least one first capacitor PC1.

[0209] The anode electrode 131 of the light emitting element LE (see, for example, Fig.12 ) can be electrically connected to the light emitting pixel driver EPD, and the cathode electrode 134 of the light emitting element LE (for example, see Fig.12 ) may be electrically connected to a second power line VSSPL for transmitting a second power ELVSS having a voltage level lower than that of the first power ELVDD.

[0210] The light emitting element LE may be an organic light emitting diode having a light emitting layer including an organic light emitting material (e.g., made of an organic light emitting material). In another embodiment, the light emitting element LE may be an inorganic light emitting element including a light emitting layer including an inorganic semiconductor (e.g., made of an inorganic semiconductor). In another embodiment, the light emitting element LE may be a quantum dot light emitting element including a quantum dot light emitting layer. In another embodiment, the light emitting element LE may be a micro light emitting diode.

[0211] exist Fig.11 The capacitor Cel shown in FIG. 1 as being connected in parallel or substantially in parallel with the light emitting element LE refers to a parasitic capacitance between the anode electrode 131 and the cathode electrode 134 .

[0212] The driving transistor DT is connected in series to the light emitting element LE between the first power line VDL and the second power line VSSPL. In other words, the first electrode (e.g., source electrode) of the driving transistor DT can be electrically connected to the first power line VDL through the fifth transistor ST5. In addition, the second electrode (e.g., drain electrode) of the driving transistor DT can be electrically connected to the anode electrode 131 of the light emitting element LE through the sixth transistor ST6.

[0213] The first electrode of the driving transistor DT may be electrically connected to the data line DL through the second transistor ST2 .

[0214] The gate electrode of the driving transistor DT may be electrically connected to the first power line VDL through the first capacitor PC1. In other words, the first capacitor PC1 may be electrically connected between the gate electrode of the driving transistor DT and the first power line VDL.

[0215] Therefore, the potential of the gate electrode of the driving transistor DT may be maintained or substantially maintained by the first power ELVDD of the first power line VDL.

[0216] Therefore, when the data signal Vdata of the data line DL is transmitted to the first electrode of the driving transistor DT through the turned-on second transistor ST2 , a voltage difference corresponding to the data signal Vdata and the first power ELVDD may be generated between the gate electrode of the driving transistor DT and the first electrode of the driving transistor DT.

[0217] In this case, when a voltage difference between a gate electrode of the driving transistor DT and a first electrode of the driving transistor DT (or in other words, a gate-source voltage difference) is greater than or equal to a threshold voltage, the driving transistor DT may be turned on.

[0218] Subsequently, when the fifth transistor ST5 and the sixth transistor ST6 are turned on, the driving transistor DT can be connected in series with the light emitting element LE between the first power line VDL and the second power line VSSPL. Therefore, a drain-source current corresponding to the data signal Vdata can be generated by the turned-on driving transistor DT and can be supplied as a driving current of the light emitting element LE.

[0219] Therefore, the light emitting element LE may emit light having brightness corresponding to the data signal Vdata.

[0220] The second transistor ST2 may be connected between the first electrode of the driving transistor DT and the data line DL. The second transistor ST2 may be turned on by a scan write signal GW of the scan write line GWL.

[0221] The first transistor ST1 may be connected between a gate electrode of the driving transistor DT and a second electrode of the driving transistor DT. The first transistor ST1 may be turned on by a gate control signal GC of a gate control line GCL.

[0222] The third transistor ST3 may be connected between the gate electrode of the driving transistor DT and the first initialization power line VIL. The third transistor ST3 may be turned on by a scan initialization signal GI of the scan initialization line GIL.

[0223] The first transistor ST1 and the third transistor ST3 may be provided with N-type MOSFETs.

[0224] The fourth transistor ST4 may be connected between the anode electrode of the light emitting element LE and the second initialization power line VAIL. The fourth transistor ST4 may be turned on by a bias control signal GB of a bias control line GBL.

[0225] The fifth transistor ST5 may be connected between the first electrode of the driving transistor DT and the first power line VDL.

[0226] The sixth transistor ST6 may be connected between the second electrode of the driving transistor DT and the anode electrode of the light emitting element LE.

[0227] The fifth transistor ST5 and the sixth transistor ST6 may be turned on by the emission control signal EC of the emission control line ECL.

[0228] The seventh transistor ST7 may be connected between the first electrode of the driving transistor DT and the bias power line VBL.

[0229] The seventh transistor ST7 may be turned on by the bias control signal GB of the bias control line GBL.

[0230] Fig.12 It is shown Fig.11 A cross-sectional view of a portion of a light-emitting element and a light-emitting pixel driver.

[0231] Fig.12 The cross-sectional view shows a light emitting pixel driver EPD including a portion of one emission area EA disposed in the first bypass side area SDA1 and a portion of a non-emission area NEA disposed around (eg, adjacent to) the one emission area EA.

[0232] Reference Fig.12 According to the first embodiment, the display device 100 may include a substrate 110, a circuit layer 120 disposed on the substrate 110, an element layer 130 disposed on the circuit layer 120, an encapsulation layer 140 disposed on the element layer 130, and a touch sensor layer 150 disposed on the encapsulation layer 140.

[0233] The circuit layer 120 includes light emitting pixel drivers EPD respectively corresponding to the emission areas EA.

[0234] The light emitting pixel driver EPD may include a driving transistor DT, first to seventh transistors ST1 to ST7 , and at least one first capacitor PC1 .

[0235] The circuit layer 120 may further include a scan write line GWL, a scan initialization line GIL, an emission control line ECL, a gate control line GCL, and a bias control line GBL electrically connected to the gate electrode of the driving transistor DT and the gate electrodes of the first to seventh transistors ST1 to ST7 .

[0236] In addition, the circuit layer 120 may include a data line DL electrically connected to the driving transistor DT and the first to seventh transistors ST1 to ST7 , a first power line VDL, a first initialization power line VIL, a second initialization power line VAIL, and a bias power line VBL.

[0237] Each of the driving transistor DT and the first to seventh transistors ST1 to ST7 may include a channel portion, a source portion, and a drain portion formed of a semiconductor layer, and a gate electrode formed of a conductive layer overlapping the channel portion. The channel portion may be disposed between the source portion and the drain portion.

[0238] Fig.12 The driving transistor DT and the second transistor ST2 and the sixth transistor ST6 among the first to seventh transistors ST1 to ST7 are shown.

[0239] The circuit layer 120 may include: a buffer layer 121 covering the substrate 110, a first semiconductor layer CHDT, SDT, DDT, CH2, S2, D2, CH6, S6 and D6 disposed on the buffer layer 121, a first gate insulating layer 122 covering the first semiconductor layer, a first gate conductive layer GDT, G2 and G6 disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer, a second gate conductive layer VDSBL1 disposed on the second gate insulating layer 123, a first interlayer insulating layer 124 covering the second gate conductive layer, a second semiconductor layer disposed on the first interlayer insulating layer 124, and a second semiconductor layer covering the second semiconductor layer. A third gate insulating layer 125, a third gate conductive layer arranged on the third gate insulating layer 125, a second interlayer insulating layer 126 covering the third gate conductive layer, a first source / drain conductive layer ANDE1, VDSBL2 and DCAE arranged on the second interlayer insulating layer 126, a first planarizing layer 127 covering the first source / drain conductive layer, a second source / drain conductive layer ANDE2, VDAL, DCE and TDEL1 arranged on the first planarizing layer 127, a second planarizing layer 128 covering the second source / drain conductive layer, and a third source / drain conductive layer ANDE3, DL1 and ASL2 arranged on the second planarizing layer 128.

[0240] The driving transistor DT may include a channel portion CHDT, a source portion SDT, and a drain portion DDT formed of a first semiconductor layer on the buffer layer 121 , and a gate electrode GDT disposed on the first gate insulating layer 122 and overlapping the channel portion CHDT.

[0241] The second transistor ST2 may include a channel portion CH2 formed of the first semiconductor layer on the buffer layer 121 , a source portion S2 , and a drain portion D2 , and a gate electrode G2 disposed on the first gate insulating layer 122 and overlapping the channel portion CH2 .

[0242] The sixth transistor ST6 may include a channel portion CH6 formed of the first semiconductor layer on the buffer layer 121 , a source portion S6 and a drain portion D6 , and a gate electrode G6 disposed on the first gate insulating layer 122 and overlapping the channel portion CH6 .

[0243] The anode electrode 131 of the light emitting element LE of the element layer 130 may be disposed on the third planarization layer 129 .

[0244] The anode electrode 131 may be electrically connected to the drain portion D6 of the sixth transistor ST6 through the first, second, and third anode connection electrodes ANDE1, ANDE2, and ANDE3.

[0245] The first anode connection electrode ANDE1 may be formed of a first source / drain conductive layer on the second interlayer insulating layer 126 .

[0246] The first anode connection electrode ANDE1 may be electrically connected to the drain portion D6 of the sixth transistor ST6 through a first anode connection hole ANCH1 penetrating the second interlayer insulating layer 126 , the third gate insulating layer 125 , the first interlayer insulating layer 124 , the second gate insulating layer 123 , and the first gate insulating layer 122 .

[0247] The second anode connection electrode ANDE2 may be formed of a second source / drain conductive layer on the first planarization layer 127 .

[0248] The second anode connection electrode ANDE2 may be electrically connected to the first anode connection electrode ANDE1 through a second anode connection hole ANCH2 penetrating the first planarization layer 127 .

[0249] The third anode connection electrode ANDE3 may be formed of a third source / drain conductive layer on the second planarization layer 128 .

[0250] The third anode connection electrode ANDE3 may be electrically connected to the second anode connection electrode ANDE2 through a third anode connection hole ANCH3 penetrating the second planarization layer 128 .

[0251] The anode electrode 131 may be electrically connected to the third anode connection electrode ANDE3 through a fourth anode connection hole ANCH4 penetrating the third planarization layer 129 .

[0252] Similar to the P-type MOSFETs of the driving transistor DT, the second transistor ST2, and the sixth transistor ST6, the fourth transistor ST4, the fifth transistor ST5, and the seventh transistor ST7 may be configured as P-type MOSFETs by the first semiconductor layer and the first gate conductive layer. The fourth transistor ST4, the fifth transistor ST5, and the seventh transistor ST7 may have the same or substantially the same structure as the driving transistor DT, the second transistor ST2, and the sixth transistor ST6, and therefore, a redundant description thereof may not be repeated.

[0253] The first transistor ST1 and the third transistor ST3 among the first to seventh transistors ST1 to ST7 may be configured as N-type MOSFETs by the second semiconductor layer on the first interlayer insulating layer 124 and the third gate conductive layer on the third gate insulating layer 125 .

[0254] The first power line VDL may include a first power sub-line VDSBL1 formed of a second gate conductive layer on the second gate insulating layer 123 and a second power sub-line VDSBL2 formed of a first source / drain conductive layer on the second interlayer insulating layer 126 .

[0255] The first capacitor PC1 may be provided by an overlapping region between the gate electrode GDT of the driving transistor DT and the first power sub-line VDSBL1 .

[0256] The first power sub-line VDSBL1 and the second power sub-line VDSBL2 may be electrically connected to each other.

[0257] In addition, the first power auxiliary line VDAL may be electrically connected to the second power sub-line VDSBL2 through the first power connection hole VDCH.

[0258] The first dummy line DML1 including the first transmission bypass line TDEL1 may be formed of a second source / drain conductive layer together with the first power auxiliary line VDAL on the first planarization layer 127 .

[0259] The data lines DL including the first data lines DL1 and the second dummy lines DML2 including the second auxiliary lines ASL2 may be formed of a third source / drain conductive layer on the second planarization layer 128 .

[0260] In this case, the via layer VIA1 (see, for example, Figure 8 ) may include a second planarization layer 128 , and the passivation layer VIA2 may include a third planarization layer 129 .

[0261] The first data line DL1 may be electrically connected to the source portion S2 of the second transistor ST2 through the data link electrode DCE and the data connection auxiliary electrode DCAE.

[0262] The data link electrode DCE may be formed of the second source / drain conductive layer on the first planarization layer 127 .

[0263] The first data line DL1 may be electrically connected to the data link electrode DCE through a data connection hole DTCH penetrating the second planarization layer 128 .

[0264] The data connection auxiliary electrode DCAE may be formed of the first source / drain conductive layer on the second interlayer insulating layer 126 .

[0265] The data link electrode DCE may be electrically connected to the data connection auxiliary electrode DCAE through the first data connection auxiliary hole DTAH1 penetrating the first planarization layer 127 .

[0266] The data connection auxiliary electrode DCAE may be electrically connected to the source portion S2 of the second transistor ST2 through a second data connection auxiliary hole DTAH2 penetrating the second interlayer insulating layer 126 , the third gate insulating layer 125 , the first interlayer insulating layer 124 , the second gate insulating layer 123 , and the first gate insulating layer 122 .

[0267] The element layer 130 may include light emitting elements LE disposed on the third planarization layer 129 and respectively corresponding to the emission areas EA.

[0268] Each of the light emitting elements LE may include a corresponding anode electrode 131 , a cathode electrode 134 facing or opposite to the corresponding anode electrode 131 , and a corresponding light emitting layer 133 disposed between the corresponding anode electrode 131 and the cathode electrode 134 .

[0269] In another embodiment, each of the light emitting elements LE may further include a first common layer disposed between the corresponding anode electrode 131 and the corresponding light emitting layer 133 and a second common layer disposed between the corresponding light emitting layer 133 and the cathode electrode 134 .

[0270] In other words, the element layer 130 may include anode electrodes 131 corresponding to the emission areas EA, respectively, a pixel defining layer 132 corresponding to the non-emission areas NEA and covering the edges of the anode electrodes 131, a light-emitting layer 133 respectively arranged on the anode electrodes 131, and a cathode electrode 134 arranged on the light-emitting layer 133 and the pixel defining layer 132.

[0271] The anode electrode 131 may be provided for each of the emission areas EA, and may be electrically connected to a corresponding one of the light emitting pixel drivers EPD of the circuit layer 120. The anode electrode 131 may be referred to as a pixel electrode.

[0272] The light emitting layer 133 may be formed of an organic light emitting material that converts electron-hole pairs into light.

[0273] The encapsulation layer 140 may be disposed on the circuit layer 120 and cover the element layer 130 .

[0274] The encapsulation layer 140 may include a first encapsulation layer 141, a second encapsulation layer 142 disposed on the first encapsulation layer 141, and a third encapsulation layer 143 disposed on the second encapsulation layer 142. The first encapsulation layer 141 disposed on the element layer 130 may include an inorganic insulating material (e.g., may be made of an inorganic insulating material). The second encapsulation layer 142 disposed on the first encapsulation layer 141 may overlap with the element layer 130 and may include an organic insulating material (e.g., may be made of an organic insulating material). The third encapsulation layer 143 disposed on the first encapsulation layer 141 to cover the second encapsulation layer 142 may include an inorganic insulating material (e.g., made of an inorganic insulating material).

[0275] Fig.13 is a diagram showing a method according to the second embodiment Figure 5 A plan view of a data line, a first dummy line, and a second dummy line in an enlarged view of portions D and E of FIG. Fig.14 is a plan view showing the data line and the first dummy line according to the second embodiment in more detail.

[0276] Reference Fig.13 and Fig.14 The display device 100 according to the second embodiment may be similar to the display device 100 described above with reference to FIG. 1 , except that in the second embodiment, one second dummy line OR_DML2 and another second dummy line OT_DML2 may be disposed between one data line OR_DL and another data line OT_DL. Figures 1 to 12 The described display apparatus 100 is the same or substantially the same, and thus, a redundant description may not be repeated hereinafter.

[0277] According to the second embodiment, the extending portion EXT of one second dummy line OR_DML2 may be adjacent to the extending portion EXT of one data line OR_DL.

[0278] The extending portion EXT of another second dummy line OT_DML2 may be adjacent to the extending portion EXT of another data line OT_DL.

[0279] According to the second embodiment, the second protrusion PR2 of one second dummy line OR_DML2 may face the extension portion EXT of the other second dummy line OT_DML2 .

[0280] The fourth protrusion PR4 of the other second dummy line OT_DML2 may face the extension portion EXT of the one second dummy line OR_DML2 .

[0281] According to the second embodiment, the first protrusion PR1 of one data line OR_DL may protrude from the extending portion EXT thereof in a direction opposite to a direction toward (eg, facing) one second dummy line OR_DML2 .

[0282] The third protrusion PR3 of the other data line OT_DL may protrude from the extending portion EXT thereof in a direction opposite to a direction toward (eg, facing) the other second dummy line OT_DML2 .

[0283] According to the second embodiment, the extension portion EXT of one second dummy line OR_DML2 is adjacent to the extension portion EXT of one data line OR_DL, and the extension portion EXT of another second dummy line OT_DML2 is adjacent to the extension portion EXT of another data line OT_DL. Therefore, the distance between the data line DL and the second dummy line DML2 paired with each other can be reduced, and thus the width of the area allocated for the arrangement of the data line DL and the second dummy line DML2 in the display area DA can be reduced.

[0284] Fig.15 is a diagram showing a method according to the third embodiment Figure 5 A plan view of a data line, a first dummy line, and a second dummy line in an enlarged view of portions D and E of FIG. Fig.16 is a plan view showing the data line and the first dummy line according to the third embodiment in more detail.

[0285] Reference Fig.15 and Fig.16 The display device 100 according to the third embodiment may be similar to the display device 100 described above with reference to FIG. 1 , except that in the third embodiment, one data line OR_DL and another data line OT_DL are disposed between one second dummy line OR_DML2 and another second dummy line OT_DML2. Figures 1 to 12 The described display apparatus 100 is the same or substantially the same, and thus, a redundant description may not be repeated hereinafter.

[0286] According to the third embodiment, the extending portion EXT of one data line OR_DL may be adjacent to the extending portion EXT of another data line OT_DL.

[0287] According to the third embodiment, the first protrusion PR1 of one data line OR_DL and the second protrusion PR2 of one second dummy line OR_DML2 may be disposed between the extending portion EXT of one data line OR_DL and the extending portion EXT of one second dummy line OR_DML2 .

[0288] In addition, the third protrusion PR3 of the other data line OT_DL and the fourth protrusion PR4 of the other second dummy line OT_DML2 may be disposed between the extending portion EXT of the other data line OT_DL and the extending portion EXT of the other second dummy line OT_DML2.

[0289] In other words, according to the third embodiment, the first protrusion PR1 of one data line OR_DL and the third protrusion PR3 of the other data line OT_DL may protrude in directions opposite to each other.

[0290] Therefore, the first protrusion PR1 of one data line OR_DL can be prevented or substantially prevented from contacting another data line OT_DL, so that the distance between one data line OR_DL and another data line OT_DL can be reduced, while preventing or substantially preventing a short circuit failure that may occur between one data line OR_DL and another data line OT_DL.

[0291] Fig.17 is a diagram showing a fourth embodiment of the present invention. Figure 5 A plan view of a data line, a first dummy line, and a second dummy line in an enlarged view of portions D and E of FIG. Fig.18 is a plan view showing the data line and the first dummy line according to the fourth embodiment in more detail.

[0292] Reference Fig.17 and Fig.18 , except that in the fourth embodiment, the second dummy line DML2 may not include a dummy protrusion DMPR facing the connection protrusion DCPR of the data line DL (eg, see Fig.15 and Fig.16 ) In addition, the display device 100 according to the fourth embodiment can be the same as the above reference Fig.15 and Fig.16 The described display apparatus 100 is the same or substantially the same, and thus, a redundant description may not be repeated hereinafter.

[0293] According to the fourth embodiment, since the dummy protrusion DMPR (for example, see Fig.15 and Fig.16 ), so the connection protrusion DCPR of the data line DL may face the extending portion EXT of the second dummy line DML2.

[0294] As a result, since the distance between the data line DL and the second dummy line DML2 paired with each other may be further reduced, the width of the area allocated for the arrangement of the data line DL and the second dummy line DML2 in the display area DA may be further reduced.

[0295] Fig.19 is a diagram showing a method according to the fifth embodiment Figure 2 Layout diagram of an enlarged view of portion B. Fig. 20 is a block diagram showing a display device according to a fifth embodiment. Fig.21 It is shown Fig. 20 Equivalent circuit diagram of the light sensing pixel driver. Fig. 22 is a diagram showing a method according to the fifth embodiment Figure 5 A plan view of a data line, a first dummy line, and a second dummy line in an enlarged view of portions D and E of FIG. Fig.23 is a plan view showing the data line and the first dummy line according to the fifth embodiment in more detail.

[0296] According to the fifth embodiment, the display device 100 may include a scanning function for detecting the curvature of an object in contact with the screen based on a difference in the amount of light reflected from the screen.

[0297] In more detail, the display device 100 may further include light sensing elements distributed in the display area DA and a scan driving circuit that periodically collects light sensing signals from the light sensing elements.

[0298] Reference Fig.19 , the display area DA of the substrate 110 of the display device 100 according to the fifth embodiment may further include a light sensing area ODA disposed in a portion of the non-emission area NEA.

[0299] Reference Fig. 20 The circuit layer 120 of the display device 100 according to the fifth embodiment may include light emitting pixel drivers EPD electrically connected to the light emitting elements LE of the emission area EA, light sensing elements PD electrically connected to the light sensing area ODA (for example, see Fig.21 )'s light sensing pixel driver DPD, a data line DL electrically connected to the light emitting pixel driver EPD, and a readout line ROL electrically connected to the light sensing pixel driver DPD.

[0300] The display device 100 according to the fifth embodiment may include a display driving circuit (e.g., a data driver) 200 electrically connected to a data line DL to supply a data signal Vdata, a scanning driving circuit (e.g., a scanning driver) 500 electrically connected to a light sensing pixel driver DPD and periodically collecting a light sensing signal of a light sensing element PD, a gate driving circuit (e.g., a gate driver) 101 electrically connected to gate electrodes of transistors included in a light emitting pixel driver EPD and a light sensing pixel driver DPD, an emission control circuit (e.g., an emission driver) 102 for supplying an emission control signal EC to the light emitting pixel driver EPD, a power supply unit (e.g., a power supply) 700 for supplying various power voltages to the light emitting pixel driver EPD and the light sensing pixel driver DPD, and a timing controller 800 for controlling a driving timing.

[0301] The gate driving circuit 101 and the emission control circuit 102 may be disposed in the scan driving circuit area SCDA of the non-display area NDA of the substrate 110 .

[0302] The timing controller 800 receives an image signal supplied from the outside of the display device 100. The timing controller 800 may output image data DATA and a data control signal DCS to the display driving circuit 200.

[0303] In addition, the timing controller 800 may generate a scan control signal SCS for controlling the operation timing of the gate driving circuit 101 and an emission control driving signal ECS for controlling the operation timing of the emission control circuit 102. For example, the timing controller 800 may generate a scan control signal SCS and an emission control driving signal ECS, output the scan control signal SCS to the gate driving circuit 101 through a scan control line, and output the emission control driving signal ECS to the emission control circuit 102 through an emission control driving line.

[0304] The display driving circuit 200 may convert the image data DATA into analog data voltages and output the analog data voltages to the data lines DL.

[0305] The gate driving circuit 101 may generate a gate signal in response to a scan control signal SCS, and sequentially output the gate signal to gate lines GL1 to GLn (n is a positive integer). Here, the gate lines GL1 to GLn may be collectively referred to as a scan write line GWL, a scan initialization line GIL, a gate control line GCL, a bias control line GBL, and a reset control line RSTL (for example, see Fig.21 ).

[0306] The power supply unit 700 may supply various powers for driving the light emitting pixel driver EPD and the light sensing pixel driver DPD.

[0307] For example, the power supply unit 700 may supply a first power ELVDD, a second power ELVSS, a first initialization power Vint, a second initialization power Vaint, a bias power VBS, and a reset power Vrst (eg, see Fig.21 ).

[0308] The emission control circuit 102 may sequentially output the emission control signal EC to the emission control line ECL in response to the emission control drive signal ECS. The emission control signal EC of the emission control circuit 102 may have a pulse of a first level voltage or a second level voltage. However, the present disclosure is not limited thereto, and the emission control circuit 102 may not be separately provided from the gate drive circuit 101, so that it may be included in the gate drive circuit 101. In this case, in addition to the above-mentioned other lines, the gate lines GL1 to GLn may also be collectively referred to as the emission control line ECL.

[0309] The scan driving circuit 500 may be electrically connected to the light sensing element PD through the readout line ROL and the light sensing pixel driver DPD.

[0310] Each of the light sensing elements PD may generate a photocurrent corresponding to the amount of light incident on the light sensing element PD, and the scan driving circuit 500 may detect the shape of the fingerprint of the user based on the photocurrent of each of the light sensing elements PD.

[0311] The scan driving circuit 500 may periodically collect the light sensing signal of the light sensing element PD.

[0312] Based on the collected light sensing signals, the scan driving circuit 500 can generate scan data about the shape of the object in contact with the screen by detecting the difference in the amount of light reflected by the object in contact with the screen. The scan data can be compared with reference data about the user's fingerprint to determine whether the user's fingerprint has been input.

[0313] Reference Fig.21 The circuit layer 120 of the display device 100 according to the fifth embodiment may further include a reset control line RSTL, a reset power line VRL, and a readout line ROL electrically connected to the light sensing pixel driver DPD.

[0314] Each of the light-sensing pixel drivers DPD may include two or more sensing transistors LT1 , LT2 , and LT3 , and may be electrically connected between corresponding light-sensing elements PD and connected to the scan driving circuit 500 .

[0315] Each of the light-sensing pixel drivers DPD may include first to third sensing transistors LT1 , LT2 , and LT3 .

[0316] The light sensing element PD may be a photoelectric conversion element that converts incident light into an electrical signal by generating a photocurrent corresponding to the amount of incident light and outputs a light sensing signal.

[0317] The light sensing element PD may be a photodiode including a sensing anode electrode, a sensing cathode electrode, and a photoelectric conversion layer disposed between the sensing anode electrode and the sensing cathode electrode.

[0318] The light sensing element PD may be a phototransistor or an inorganic photodiode formed of a PN type or PIN type inorganic material. As another example, the light sensing element PD may also be an organic photodiode including an electron supply material for generating donor ions and an electron accepting material for generating acceptor ions.

[0319] As photocharges generated in the photoelectric conversion layer move in response to incident light, a photocurrent may be generated between the sensing anode electrode and the sensing cathode electrode.

[0320] As an example, photocharges generated in the photoelectric conversion layer by light incident on the photo sensing element PD may be accumulated in the sensing anode electrode. In this case, the voltage of the first node N1 electrically connected to the sensing anode electrode may increase. When the photo sensing element PD and the readout line ROL are connected to the first node N1 by turning on the first sensing transistor LT1 and the third sensing transistor LT3, the sensing voltage may be accumulated at the third node N3 between the readout line ROL and the third sensing transistor LT3 in proportion to the voltage at the first node N1 where the charge is accumulated.

[0321] The first sensing transistor LT1 may be turned on by the voltage of the first node N1 to connect the second initialization power line VAIL to the second electrode of the third sensing transistor LT3 .

[0322] The first sensing transistor LT1 may be a source follower amplifier generating a source-drain current proportional to the amount of charge of the first node N1 input to the gate electrode of the first sensing transistor LT1 .

[0323] The first electrode of the first sensing transistor LT1 is shown to be connected to the second initialization power line VAIL, but the present disclosure is not limited thereto, and the first electrode of the first sensing transistor LT1 may be connected to the first power line VDL or the first initialization power line VIL.

[0324] The second sensing transistor LT2 may be turned on by the reset control signal RST of the reset control line RSTL to connect the first node N1 to the reset power line VRL. Therefore, the potential of the first node N1 may be reset.

[0325] The third sensing transistor LT3 may be turned on by the scanning write signal GW of the scanning write line GWL to connect the second electrode of the first sensing transistor LT1 and the readout line ROL to each other.

[0326] At least one of the first to third sensing transistors LT1, LT2 and LT3 can be set as an N-type MOSFET, which includes a channel portion, a source portion and a drain portion formed by a first semiconductor layer on the buffer layer 121, and a gate electrode formed by a first gate conductive layer on the first gate insulating layer 122.

[0327] At least one of the first to third sensing transistors LT1, LT2 and LT3 can be set as a P-type MOSFET, which includes a channel portion, a source portion and a drain portion formed by a second semiconductor layer on the first interlayer insulating layer 124, and a gate electrode formed by a third gate conductive layer on the third gate insulating layer 125.

[0328] Each active layer may include any one of polycrystalline silicon, amorphous silicon, and an oxide semiconductor.

[0329] For example, the first and third sensing transistors LT1 and LT3 may be formed of P-type MOSFETs, and the second sensing transistor LT2 may be formed of N-type MOSFETs.

[0330] Reference Fig. 22 and Fig.23 In addition to further including a readout line ROL electrically connected to the light sensing pixel driver DPD in the fifth embodiment, and one of the readout lines ROL is disposed between an extension portion EXT of one data line OR_DL and an extension portion EXT of another data line OT_DL, the display device 100 according to the fifth embodiment can be the same as that described above with reference to Fig.17 and Fig.18 The display device 100 described is the same or substantially the same, and therefore, a redundant description will not be repeated hereinafter.

[0331] As described above, according to various embodiments of the present disclosure, the protrusions PR1, PR2, PR3, and PR4 between the data line DL and the first dummy line DML1 and between the second dummy line DML2 and the first dummy line DML1 may not be disposed at all intersection regions (e.g., intersections) between the first dummy line DML1 and each of the data line DL and the second dummy line DML2. Because the number of protrusions is reduced, an additional width may be generated in the display area DA, which may facilitate the arrangement of the light sensing pixel driver DPD. Therefore, a display device 100 including a scanning function and having a high resolution may be implemented.

[0332] The foregoing is an explanation of some embodiments of the present disclosure and should not be interpreted as limiting it. Although some embodiments have been described, it will be readily appreciated by those skilled in the art that, without departing from the spirit and scope of the present disclosure, various modifications can be made in the embodiments. It will be understood that, unless otherwise described, the description of the features or aspects in each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Therefore, as will be apparent to those of ordinary skill in the art, unless otherwise specifically noted, the features, characteristics and / or elements described in conjunction with the specific embodiments can be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it will be understood that the foregoing is an explanation of various example embodiments and should not be interpreted as being limited to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other example embodiments are intended to be included in the spirit and scope of the present disclosure as defined in the attached claims and their equivalents.

Claims

1. A display device, the display device include: a substrate including a display area including an emission area and a non-display area around the display area; a circuit layer on the substrate; as well as an element layer, which is on the circuit layer and includes light emitting elements respectively corresponding to the emission areas, The circuit layer includes: light-emitting pixel drivers, which are electrically connected to the light-emitting elements, and are positioned side by side with each other; data lines, which are configured to transmit data signals to the light-emitting pixel drivers; first dummy lines, which extend in a first direction crossing the data lines; and second dummy lines, which extend parallel to the data lines and are paired with the data lines, respectively. Wherein, each of the data line and the second dummy line includes: an extension portion extending in a second direction intersecting the first direction, Wherein, one of the data lines further includes: a first protrusion intersecting with some of the first dummy lines, and Among the second dummy lines, one second dummy line paired with the one data line further includes: a second protrusion intersecting with other first dummy lines among the first dummy lines.

2. The display device according to claim 1, in, The light-emitting pixel driver comprises: A first light emitting pixel driver and a second light emitting pixel driver are adjacent to each other in the second direction and overlap the one data line; and a third light-emitting pixel driver, adjacent to the first light-emitting pixel driver in the first direction, wherein the first light-emitting pixel driver overlaps with one of the first protrusions; wherein the second light-emitting pixel driver overlaps with one of the second protrusions; Wherein, another data line among the data lines overlapped with the third light-emitting pixel driver further includes: a third protrusion, which is positioned side by side with the second protrusion, and Wherein, another second dummy line among the second dummy lines paired with the another data line further includes: fourth protrusions, which are respectively positioned side by side with the first protrusions.

3. The display device according to claim 2, further comprising: include: A display driving circuit is configured to output the data signal to the data line, Wherein, the circuit layer further includes: a data supply line, which is in the non-display area and electrically connected to the display driving circuit, Wherein, the bypass area on one side of the display area includes: Bypass middle area; a first bypass side region parallel to the bypass middle region in the first direction and in contact with the non-display region; and a second bypass side region, between the bypass middle region and the first bypass side region, The data lines include: a first data line in the first bypass side region; and a second data line in the second bypass side region. The first dummy line includes: a first transmission bypass line electrically connected to the first data line, The second dummy line includes: a second transmission bypass line, paired with the second data line and electrically connected to the first transmission bypass line, Among the data supply lines, a first data supply line configured to transmit a data signal among the data signals to the first data line is electrically connected to the first data line through the first transmission bypass line and the second transmission bypass line, and Among the data supply lines, a second data supply line configured to transmit a data signal among the data signals to the second data line is directly electrically connected to the second data line.

4. The display device according to claim 3, in, The data line and the second dummy line are located on a via layer covering the first dummy line, wherein the first transmission bypass line is electrically connected to the second transmission bypass line through a first bypass connection hole, and is electrically connected to the first data line through a second bypass connection hole, and Wherein, the first bypass connection hole and the second bypass connection hole penetrate the via layer.

5. The display device according to claim 3, in, The one second dummy line is located between the one data line and the another data line and is closer to the another data line than the one data line, and The extending portion of the one second dummy line is adjacent to the extending portion of the another data line.

6. The display device according to claim 5, in, The first protrusion faces the extended portion of the one second imaginary line, and Wherein, the second protrusion faces the extending portion of the one data line.

7. The display device according to claim 3, in, The one second dummy line and the other second dummy line are located between the one data line and the other data line, wherein the extending portion of the second dummy line is adjacent to the extending portion of the data line, wherein the extending portion of the another second dummy line is adjacent to the extending portion of the another data line, wherein the second protrusion of the one second imaginary line faces the extended portion of the other second imaginary line, and Wherein, the fourth protrusion of the other second imaginary line faces the extending portion of the one second imaginary line.

8. The display device according to claim 7, in, The first protrusion protrudes in a direction opposite to a direction from the extending portion of the one data line toward the one second dummy line, and The third protrusion protrudes in a direction opposite to a direction from the extending portion of the another data line toward the another second dummy line.

9. The display device according to claim 3, in, The one data line and the other data line are located between the one second dummy line and the other second dummy line, and Wherein, the extending portion of the one data line is adjacent to the extending portion of the other data line.

10. The display device according to claim 9, in, The first protrusion and the second protrusion are located between the extending portion of the one data line and the extending portion of the one second dummy line.

11. The display device according to claim 9, in, The light-emitting pixel driver is electrically connected to the data line through a data connection hole, and Wherein, the data line further includes a connection protrusion overlapping the data connection hole.

12. The display device according to claim 11, in, The second dummy line further includes a dummy protrusion symmetrical to the connecting protrusion.

13. The display device according to claim 11, in, The connecting protrusion faces the extending portion of the second dummy line.

14. The display device according to claim 9, in, The display area further includes: a non-emitting area as a separation area between the emitting areas; and a light sensing area located in a portion of the non-emitting area. Wherein, the element layer further includes light sensing elements respectively in the light sensing area, and Wherein, the circuit layer further includes: light sensing pixel drivers electrically connected to the light sensing elements, and readout lines electrically connected to the light sensing pixel drivers.

15. The display device according to claim 14, in, One of the readout lines is located between the extending portion of the one data line and the extending portion of the other data line.

16. A display device, the display device include: a substrate including a display area including an emission area and a non-display area around the display area; a circuit layer on the substrate; as well as an element layer, which is on the circuit layer and includes light emitting elements respectively corresponding to the emission areas, The circuit layer includes: light-emitting pixel drivers, which are electrically connected to the light-emitting elements, and are positioned side by side with each other; data lines, which are configured to transmit data signals to the light-emitting pixel drivers; first dummy lines, which extend in a first direction crossing the data lines; and second dummy lines, which extend parallel to the data lines and are paired with the data lines, respectively. Wherein, each of the data line and the second dummy line includes: an extension portion extending in a second direction intersecting the first direction, The light-emitting pixel driver includes: a first light-emitting pixel driver and a second light-emitting pixel driver, which are adjacent to each other in the second direction and overlap with one of the data lines. The data line overlapped with the first light-emitting pixel driver and the second light-emitting pixel driver further includes: a first protrusion intersecting with some of the first dummy lines; Among the second dummy lines, one second dummy line paired with the one data line further includes: a second protrusion intersecting with other first dummy lines among the first dummy lines, wherein the first light-emitting pixel driver overlaps with one of the first protrusions; wherein the second light-emitting pixel driver overlaps with one of the second protrusions, and Wherein, the first protrusion and the second protrusion are located between the extending portion of the one data line and the extending portion of the one second dummy line.

17. The display device according to claim 16, in, The light-emitting pixel driver further includes: a third light-emitting pixel driver, adjacent to the first light-emitting pixel driver in the first direction, Wherein, another data line among the data lines overlapped with the third light-emitting pixel driver further includes: a third protrusion, which is positioned side by side with the second protrusion, and Wherein, another second dummy line among the second dummy lines paired with the another data line further includes: fourth protrusions, which are respectively positioned side by side with the first protrusions.

18. The display device according to claim 17, wherein the display device further comprises: include: A display driving circuit is configured to output the data signal to the data line, Wherein, the circuit layer further includes: a data supply line, which is in the non-display area and electrically connected to the display driving circuit, Wherein, the bypass area on one side of the display area includes: Bypass middle area; a first bypass side region parallel to the bypass middle region in the first direction and in contact with the non-display region; and a second bypass side region, between the bypass middle region and the first bypass side region, The data lines include: a first data line in the first bypass side region; and a second data line in the second bypass side region. The first dummy line includes: a first transmission bypass line electrically connected to the first data line, The second dummy line includes: a second transmission bypass line, paired with the second data line and electrically connected to the first transmission bypass line, Among the data supply lines, a first data supply line configured to transmit a data signal among the data signals to the first data line is electrically connected to the first data line through the first transmission bypass line and the second transmission bypass line, and Among the data supply lines, a second data supply line configured to transmit a data signal among the data signals to the second data line is directly electrically connected to the second data line.

19. The display device according to claim 18, in, The one data line and the other data line are located between the one second dummy line and the other second dummy line, and Wherein, the extending portion of the one data line is adjacent to the extending portion of the other data line.

20. The display device according to claim 18, in, The display area further includes: a non-emitting area as a separation area between the emitting areas; and a light sensing area located in a portion of the non-emitting area. Wherein, the element layer further includes: light sensing elements, respectively in the light sensing area, The circuit layer further comprises: light sensing pixel drivers electrically connected to the light sensing elements; and readout lines electrically connected to the light sensing pixel drivers, and One of the readout lines is located between the extending portion of the one data line and the extending portion of the other data line.

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