Process for production of polycrystalline silicon carbide useful for production of integrated circuit substrates and silicon carbide obtained thereby

Abstract

The invention relates to a method for producing a polycrystalline SiC plate doped on the surface of graphite by chemical vapor deposition, in which a mixed gas is introduced into a heating chamber to form a gas phase comprising:-at least one gaseous precursor of silicon and / or carbon; -at least one dopant gas comprising at least one nitrogen atom; and-a carrier gas, the mixed gas decomposing on the graphite surface to form a polycrystalline SiC layer, characterized in that the temperature in the reactor is between 1450 K and 1650 K and the total partial pressure of the gaseous precursor is less than 350 mbar. The sheet is characterized by (i) having a texture coefficient C422 of less than 30%, and (iii. A) having a texture coefficient C220 of greater than 60%, or (iii. B) the sum of texture coefficients C111 + C222 + C511 of greater than 70%.

Description

Technical Field

[0001] The present invention relates to the field of materials science and in particular to the field of materials that can be used to manufacture substrates for integrated circuits, as well as to processes for producing these materials. More specifically, the present invention relates to polycrystalline silicon carbide. Like all materials used for microelectronic substrates, this material is realized in the form of thin sheets (in French, the professional technician usually uses the English term "wafer"), which are generally circular in shape. Silicon carbide SiC is particularly suitable for manufacturing substrates for power electronic components. SiC wafers must meet very strict specifications, including flatness, uniformity of characteristics and absence of defects.

[0002] The present invention proposes a new type of polycrystalline SiC wafers that can be used to manufacture integrated circuit substrates; these wafers have special crystallographic characteristics.

[0003] Since integrated circuits are usually deposited on the surface of single-crystal semiconductors, in the case of polycrystalline silicon carbide wafers, the electronically active surface (i.e. the surface on which the integrated circuits are deposited) must be specially prepared by transferring a layer of single-crystal SiC. Such a method for preparing a transferred single-crystal SiC layer does not fall within the scope of the present invention.

[0004] The invention also relates to a novel method for manufacturing such a multicrystalline SiC wafer which is able to receive the transfer of a single-crystalline SiC layer in a subsequent manufacturing step. Background Art

[0005] Since the birth of microelectronics technology, most microelectronic circuits have been manufactured on single-crystal silicon substrates. In some specific applications, semiconductor silicon is not an ideal substrate, but due to the lack of a better substrate, people still use semiconductor silicon.

[0006] Silicon carbide (SiC for short) is an excellent semiconductor material. It has a wide bandgap, a high breakdown field, high charge carrier mobility at saturation, and high thermal conductivity. This combination of special physical properties gives it excellent voltage resistance and the ability to pass very high current densities even at high temperatures. D.Tournier's article "Power components in SiC-Technology" (Section D-3120) published in the "Techniques de l'ingénieur" in 2007 provides an introduction to this aspect.

[0007] SiC is therefore a very suitable material for the manufacture of power components, which are necessary for efficient power conversion in applications such as power distribution, renewable energy, and electric vehicles. The use of SiC makes it possible to advantageously replace silicon transistors (such as IGBTs) with power components (such as MOSFET transistors) that have a voltage resistance of kilovolts and much lower energy losses when switching. The voltage resistance and high temperature resistance of these power components can become limiting factors when designing electronic components and the circuit boards on which they are mounted. The use of such SiC power components can greatly benefit the latest developments in electric vehicles by improving energy efficiency when converting direct current from batteries to alternating current that can be used by the motor. However, the cost and availability of these components remain obstacles to the adoption of this technology, so silicon is still widely used as a substrate even in specific applications where SiC has technical advantages.

[0008] According to the current state of the art, silicon carbide substrates for depositing microelectronic circuits are generally round in shape. Silicon carbide substrates are industrially produced by the PVT (physical vapor transfer) process, which consists in sublimating SiC powder at high temperatures (greater than 2200°C) and then condensing the vapor on a seed crystal to obtain an ingot or "ball" of SiC single crystal. Single-crystalline SiC substrates (wafers) are then sliced ​​from this single-crystalline ingot. A layer of crystalline SiC is deposited on one face of the substrate by epitaxy to obtain a crystal with as few defects as possible. After epitaxy, these wafers can be used to produce electronic components.

[0009] Improvements in the PVT industrial process over the past 30 years have significantly reduced the density of major crystal defects (such as dislocations and micro-pipes) in these substrates, which has a great impact on the reliability of SiC components. In addition, it has made it possible to expand the size standard of substrates (wafers) to 150 mm in diameter and soon to 200 mm. Despite the great efforts made by the industry, the PVT process is still complex, inefficient in production, and energy-intensive, as it requires keeping the oven at very high temperatures for about a hundred hours.

[0010] In addition, for power components, the resistance R in the on state should be as low as possible. onA decisive criterion for improving the energy efficiency of systems by limiting the heat generated by the Joule effect when current flows. In these applications, single-crystalline SiC is doped both to create the P / N junction of the component and to reduce the resistivity at the drain contact. The addition of nitrogen makes it possible to dope the substrate during the crystal growth process. Standardly, the resistivity of "n"-doped wafers is around 20 milliohm.cm (mOhm.cm). It is very difficult to reduce the resistivity below this critical value without degrading the crystal quality, because too much doping will cause stress and lead to more dislocations in the crystal.

[0011] A new technology currently under development will combine the use of low-cost SiC substrates (wafers) with improved electrical properties with thin layers of high-quality single-crystal SiC in which microelectronic components are manufactured.

[0012] As described in WO 01 / 18873 (Commissariat à l'Energie Atomique), a single crystal SiC layer is attached to a substrate by a molecular bonding process, thereby also ensuring that the contact resistance between the substrate and the attached single crystal layer is minimized. EP3018696A1 describes an embodiment of this method, which can form a single crystal SiC layer on a polycrystalline SiC substrate (hereinafter referred to as "P-SiC" or "P-SiC wafer").

[0013] These P-SiC substrates must meet stringent requirements for electrical resistance, thermal conductivity and flatness. Today, prototype products called "Dummy wafers" are already on the market, sold by companies such as Ferrotec. These wafers have a standard diameter of 150 mm and a thickness of 750 microns and are used in some processes to balance a batch of single-crystal SiC wafers to improve their uniformity.

[0014] According to the prior art, P-SiC wafers are obtained by depositing polycrystalline SiC on a cylindrical graphite substrate by chemical vapor deposition CVD. After machining and removing the SiC layer deposited around the cylinder to contact the graphite, two SiC discs can be separated from the two faces of the cylinder by air oxidation of the graphite. This is described in patent applications JP1994340994 and JP1997296361.

[0015] However, it soon became apparent that the discs (wafers) thus obtained presented deformations (bow and warp) that were unacceptable for the intended application. The parameters bow and warp, which indicate the flatness of wafers used in the semiconductor industry, are well known to those skilled in the art of semiconductor substrates for microelectronics (only English words are used here to denote these parameters, written here in capital letters); they are described in more detail below and can be measured according to the SEM IMF1390 standard. The processes described in the two Japanese documents mentioned above offer a solution to this problem by repeating multiple steps of depositing low thicknesses of less than 100 microns. In fact, for sufficiently thick deposits, the increase in grain diameter generates internal compressive stresses. The conical grains repel each other during growth. This physical mechanism was demonstrated by P. Chaudhari in the article "Grain growth and stress relief in thin films", Journal of Vacuum Science and Technology, vol. 9, p. 520 (1972), which is a fundamental document for any specialist working with vapor-deposited layers. The processes described in JP1994340994 and JP1997296361 allow obtaining P-SiC layers several hundred micrometers thick while limiting the increase in internal compressive stresses and, therefore, the deformation of the P-SiC layer after detachment from the graphite.

[0016] Japanese patent JP3648112B2 describes a similar process, which alternates the deposition of layers with tensile and compressive stresses to counteract the stress moment of the deposited layers throughout their thickness. This mechanical moment is indeed the source of the deformation observed when the P-SiC disk is removed from the graphite substrate.

[0017] However, it should be noted that the above process is not conducive to achieving low resistivity and good thermal conductivity throughout the thickness of the wafer, because there are multiple interfaces between the layers in the thickness of the wafer. A single-layer solution would be more beneficial.

[0018] US Patent 10,934,634 B2 describes the deposition of a SiC monolayer on a graphite substrate by CVD, obtaining a P-SiC wafer with excellent flatness. In the upper part of a sufficiently thick deposit (typically 2 mm), the grain diameter variation tends to stabilize. Since the compressive stress in this part no longer varies (as shown in the cited publication by Chaudhari), a slice with a thickness of 350 microns can be extracted by mechanical processing, which, as the grain size tends to stabilize in thickness, presents an almost zero stress gradient and therefore integrates an almost zero mechanical torque over the entire thickness. The expected effect is that the deformation of the wafer is very small. However, the cost and energy consumed by this process are likely to be unfavorable, because about 1.65 mm of the 2 mm CVD deposit must be removed by grinding and polishing to obtain the required wafer with a thickness of 350 microns and the required flatness.

[0019] To reduce the manufacturing cost of doped P-SiC wafers, the best practice is to grow a P-SiC layer as close to the final thickness as possible by high-speed CVD, and after the start of growth, the grain size of the P-SiC layer quickly stabilizes to avoid unnecessary thickness increase to reduce or eliminate the grain size gradient.

[0020] At the 2007 Transducers & Eurosensors 2007 conference, XAFu et al. published a paper entitled "Nitrogen doped polycrystalline 3C-SiC films deposited by LPCVD for MEMS applications".

[0021] In the paper, the authors study the deposition of SiC at concentrations of doping gas (NH3) varying from 2% to 12% in mole fraction of the silicon precursor (dichlorosilane). To obtain resistivities below 20 ohm cm under these conditions, the doping rate must exceed 5%. The higher the doping rate, the greater the residual stress, but without increasing the stress gradient. In this study, the deposition was carried out at low temperature of 900°C and low pressure, which favored crystal growth entirely along the axis (111), but at an extremely slow rate of 0.6 microns / hour. Under these conditions, heavy doping does not seem to change the crystal orientation of the deposited thin layer, as analyzed by X-ray diffraction (XRD).

[0022] HKELatha et al. published an article in the journal Materials Research Express (Volume 1, No. 015902) in 2014, studying the effect of highly doped 3C-SiC obtained by CVD using methyltrichlorosilane (MTCS) as silicon and carbon precursors and NH3 as a dopant. The deposition conditions were 1040°C and low pressure. The growth rate of the deposit was about 5 microns / hour, which is much higher than in the previous case, but still not enough to produce deposits of high thickness (several hundred microns) in an economically viable way. Under these conditions, it can be observed that the degree of doping has an effect on the crystal orientation and grain size. According to X-ray diffraction (XRD) analysis, a high degree of doping leads to a coarsening of the grain size and a change in its crystal orientation axis. Under certain CVD conditions, especially at higher temperatures (here 1040°C, not 900°C as described in the publication of Fu et al. cited above), a high degree of doping seems to have a very important effect on the crystal orientation of SiC deposited by CVD. Therefore, the obtained texture and grain size can change the stress distribution in these deposits.

[0023] Patent application WO 2021 / 060515 (Tokai Carbon) proposes a process for obtaining a P-SiC substrate with a thickness between 500μm and 6mm at a high deposition temperature close to 1500°C. The deposition time is between 5 and 15 hours, i.e. a deposition rate of more than 100 microns per hour, which is particularly suitable for industrial production. The doping of P-SiC is achieved by adding dinitrogen to the mixture. In order to obtain a sufficiently flat substrate, the patent proposes a process for varying the concentration of the SiC precursor during the deposition process in order to reduce an overly pronounced grain size gradient in the deposit. The process is suitable for nitrogen mass concentrations between 200ppm (2.8x 10 19 atm / cm 3 ) and 1000ppm(1.38x 10 20 atm / cm 3 ). When it exceeds 1000ppm, the excessively high nitrogen concentration in P-SiC will produce severe defects in the crystal and unwanted substrate deformation. Therefore, this prior art document also shows that high concentrations of nitrogen dopants in P-SiC materials may be a limiting factor in obtaining good flatness, but are desirable for obtaining low resistivity.

[0024] These conflicting trends must be taken into account when seeking to manufacture by CVD a raw P-SiC substrate with low resistivity (e.g. less than 10 mOhm cm) and sufficient flatness, so that the P-SiC wafer can be ground with the least possible thickness of material removed. With regard to the flatness of the raw substrate obtained by CVD, it must be noted that grinding away material from a hard surface like SiC is a long and expensive process, and furthermore, grinding away any thickness of material is a loss of material. In fact, the manufacturing cost of P-SiC wafers must be low enough to be used as substrates in power electronics applications in combination with thin layers of polycrystalline SiC.

[0025] According to the current industrial technology level, the nominal thickness of the finished P-SiC wafer is 350 microns with a nominal diameter of 150 mm. A thicker raw product (raw blank) is manufactured using a CVD deposition process on a graphite substrate. For economic reasons, the thickness of the P-SiC blank, after being peeled off from the graphite, must not exceed 1 mm; the target thickness of the P-SiC blank is usually 750 microns, preferably 600 microns, and in order to obtain a reasonable CVD deposition time and reduce the thickness removed by grinding and polishing, the corresponding maximum thickness of the P-SiC blank is 650 microns, usually 400 microns, and preferably 250 microns.

[0026] After grinding and polishing, a wafer with a diameter of six inches and a thickness of 350 microns must have a warpage of less than 50 microns to meet microelectronic standards. To achieve this goal, an intermediate blank is first prepared by grinding the original blank separated from the graphite. From this intermediate blank, the P-SiC wafer is then prepared by fine grinding and subsequent polishing, onto which the single-crystalline SiC layer is transferred. The difference between the initial thickness of the original blank and the deformation measured on the original blank must not be less than the thickness of the intermediate blank. This means that the volume of the ground intermediate (cylindrical) blank must be included in the volume of the original blank (see Figure 1 ).

[0027] In the present invention, the inventors aim to optimize the N-doping ratio of the substrate with high N-doping ratio (usually greater than 5 x 10 19 atoms / cm3 3 ), preferably greater than 10 20 The invention relates to the manufacture of a raw SiC substrate having a resistivity of typically less than 15 milliohm cm, preferably less than 10 milliohm cm, by using a substrate having a surface area of ​​1000 N atoms / cm3. The thermal conductivity of the material should typically be greater than 200 W / mK, but preferably greater than 250 W / m / K, although high N doping levels may affect thermal conductivity by creating additional crystal defects that are detrimental to phonon propagation. The invention also seeks a substrate with a very uniform grain size on the surface, preferably fine grains. Summary of the invention

[0028] According to the work done by the inventors of the present application, a solid plate of polycrystalline SiC (herein referred to as "P-SiC") can be obtained on a substrate comprising a graphite surface by chemical vapor deposition (CVD), the temperature range of chemical vapor deposition being about 1300K to 1800K. The method is the first object of the present invention, in which a gas mixture is introduced into a heated housing to produce a gas phase, the gas phase comprising at least one gaseous precursor of silicon and / or carbon, at least one doping gas containing at least one nitrogen atom and a carrier gas, the gas mixture decomposes on the surface of the graphite substrate to form a polycrystalline SiC layer on the graphite surface of the substrate, the method being characterized in that the temperature in the reactor is between 1450K and 1650K, the total partial pressure of the gaseous precursor is less than 350 mbar, preferably less than 300 mbar. The deposition is carried out on the graphite surface of the substrate comprising a graphite surface; the substrate can be a graphite plate. The substrate, in particular the graphite plate, is preferably circular in order to directly produce a circular SiC disk.

[0029] According to an advantageous embodiment, the gas phase comprises trichloromethylsilane as a precursor of silicon and carbon, preferably excluding other precursors of silicon and / or carbon. The doping gas is preferably selected from the group consisting of the following gases: NH3, N2H4, N2, H2NCH3.

[0030] The method deposits a layer of polycrystalline silicon carbide (P-SiC) and then separates it from the graphite surface; this creates a P-SiC disk whose thickness can be reduced by grinding and polishing both sides.

[0031] In this way, a polycrystalline SiC plate can be produced, which is another object of the present invention. This plate can be a raw blank, which then undergoes a correction step to become an intermediate blank, which is used to make a polycrystalline SiC substrate, which substrate can receive the transfer of a single crystal SiC layer to form a wafer that can be used to make a substrate for the deposition of integrated circuits. The plate, the raw blank and the intermediate blank represent other objects of the present invention, which will be explained below. As described below, they have a special microstructure and crystal texture.

[0032] The polycrystalline SiC plate has a specific crystal texture, which can obtain specific doping and conductive properties. Therefore, the second object of the present invention is a polycrystalline SiC plate, characterized in that: (i) its texture coefficient C 422 Less than 30%, and (ii.a) its texture coefficient C 220 Greater than 60%, preferably greater than 80%, or (ii.b) the sum of the texture coefficients C 111 +C 222 +C 511Greater than 70%; preferably greater than 80%. Advantageously, its texture coefficient C 422 Less than 20%, preferably less than 15%, preferably less than 10%.

[0033] According to the invention, such polycrystalline SiC plates are preferably doped with nitrogen. Another example of a polycrystalline SiC plate doped according to the invention is a phosphorus-doped plate.

[0034] Advantageously, the resistivity of such a polycrystalline SiC plate is less than 20 milliohm·cm, preferably less than 15 milliohm·cm, more preferably less than 10 milliohm·cm, and / or its nitrogen content is greater than 5 x 10 19 atoms / cm3, preferably greater than 1x10 20 atoms / cm3, more preferably greater than 1.5 x 10 20 atoms / cubic centimeter.

[0035] Typically, in the field of microelectronic substrates, doping rates (such as nitrogen doping rates) can be determined by secondary ion mass spectrometry (SIMS).

[0036] A particularly preferred embodiment of the second object of the present invention is a polycrystalline SiC plate doped with nitrogen, the nitrogen content of which is greater than 5 x 10 19 atoms / cm3, the resistivity of the plate is less than 15 milliohm-cm and has a preferred crystal orientation, and the plate is characterized by: (i) its texture coefficient C 422 less than 20%, and (ii.a) its texture coefficient C 220 Greater than 80%, or (ii.b) the sum of the texture coefficients C 111 +C 222 +C 511 Greater than 80%.

[0037] The polycrystalline SiC plate is usually in the shape of a disk. It is characterized by good flatness and a diameter preferably between 140 mm and 165 mm, or between 185 mm and 210 mm; these two diameter ranges include the sizes commonly used in the semiconductor industry, namely 6 inches and 8 inches.

[0038] The polycrystalline SiC plate can be a raw blank produced by a vapor deposition process. It can also be an intermediate blank obtained by grinding such a raw blank for manufacturing wafers. In one embodiment, the thickness of the polycrystalline SiC plate according to the present invention is less than 550 microns, preferably less than 500 microns, more preferably less than 450 microns, and more preferably between 355 microns and 420 microns; this embodiment is particularly suitable for plates with a diameter between 140 mm and 165 mm. In another embodiment, the thickness of the polycrystalline SiC plate according to the present invention is less than 850 microns, preferably less than 800 microns, more preferably less than 750 microns, and more preferably between 510 microns and 650 microns; this embodiment is particularly suitable for plates with a diameter between 185 mm and 210 mm.

[0039] In another embodiment, the polycrystalline SiC plate according to the invention has a diameter between 140 mm and 165 mm, a thickness between 350 μm and 450 μm, and a deformation characterized by a warpage of less than 50 μm, preferably less than 40 μm, and even more preferably less than 30 μm. Its thickness is preferably between 350 μm and 400 μm. For example, the plate has a thickness between 350 μm and 400 μm, a warpage of less than 40 μm (preferably less than 30 μm), or a thickness between 400 μm and 450 μm, a warpage of less than 50 μm (preferably less than 40 μm).

[0040] In another embodiment, the polycrystalline SiC plate according to the invention has a diameter between 185 mm and 210 mm and a thickness between 500 μm and 650 μm, and the deformation is characterized by a warpage of less than 70 μm, preferably less than 50 μm, and even more preferably less than 40 μm. Its thickness is preferably between 500 μm and 600 μm. For example, the plate has a thickness between 500 μm and 600 μm and a warpage of less than 50 μm (preferably less than 40 μm), or a thickness between 600 μm and 650 μm and a warpage of less than 70 μm (preferably less than 50 μm).

[0041] Such a plate can be manufactured by a CVD process. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 to 1 3 shows different aspects of the invention.

[0043] [ Figure 1 ] schematically shows the measurement of a parameter known as "warpage", which characterizes a specific aspect of semiconductor wafer flatness defects.

[0044] [ Figure 2 ] shows a backscattered electron image obtained by scanning electron microscopy from a cross section of a P-SiC layer obtained according to the process of Example 1.

[0045] [ Figure 3 ] shows an image obtained from a cross section of a P-SiC layer similar to that of Example 1 by direct mode scanning electron microscopy.

[0046] [ Figure 4 ] shows a backscattered electron image obtained by scanning electron microscopy from a cross section of a P-SiC layer obtained according to the process of Example 2.

[0047] [ Figure 5 ] shows an image obtained by direct mode scanning electron microscopy from a cross section of a P-SiC layer similar to that of Example 2.

[0048] [ Figure 6 ] shows a backscattered electron image obtained by scanning electron microscopy from a cross section of a P-SiC layer obtained according to the process of Example 3.

[0049] [ Figure 7 ] shows an image obtained from a cross section of a P-SiC layer similar to that of Example 3 by direct mode scanning electron microscopy.

[0050] [ Figure 8 ] shows a backscattered electron image obtained by scanning electron microscopy from a cross section of a P-SiC layer obtained according to the process of Example 4.

[0051] [ Fig. 9 ] shows an image obtained from a cross section of a P-SiC layer similar to that of Example 4 by direct mode scanning electron microscopy.

[0052] [ FIG. 10 ] shows a backscattered electron image obtained by a scanning electron microscope from a cross section of a P-SiC layer obtained according to the process of Example 5. [ FIG. 10 ] FIG.

[0053] [ Fig. 11 ] shows an image obtained from a cross section of a P-SiC layer similar to that of Example 5 by a direct mode scanning electron microscope.

[0054] [ Fig. 12 ] A vertical cross section schematically and simply shows a reactor for manufacturing an ingot of a polycrystalline SiC substrate according to the present invention.

[0055] [ FIG. 13 ] shows a backscattered electron image obtained by a scanning electron microscope from a cross section of a P-SiC layer obtained according to the process of Example 6. [ FIG. 13 ] FIG.

[0056] The following reference numerals are used in FIG. 12 and in this specification:

[0057] 1: Reactor according to the present invention

[0058] 2: Shell

[0059] 3: Reaction Space

[0060] 4: Heating space

[0061] 5: Exhaust space

[0062] 6: Heating element

[0063] 7: Graphite base

[0064] 8: Precursor gas inlet

[0065] 9: Reaction gas outlet

[0066] 10: Exit tip

[0067] 11: Injector

[0068] 12: Graphite disc (base) DETAILED DESCRIPTION

[0069] Those skilled in the art of microelectronic semiconductor substrate technology are familiar with different methods for characterizing the overall flatness of a wafer: these different parameters include the following terms or abbreviations: Bow (the distance between the surface at the center point of a non-fixed wafer and the best fit plane, see ASTM F534 "Standard Test Method for Bow of Silicon Wafers" point 3.1.2), Warp (for non-fixed wafers, the sum of the maximum positive deviation and the maximum negative deviation of the wafer surface from the best fit plane, see ASTM F 1390 "Standard test Method for Measuring Warp on Silicon Wafers by Automated Non-Contact Scanning"), TTV (total thickness deviation, i.e., the difference between the maximum thickness value and the minimum thickness value of a fixed wafer, see ASTM F657 "Standard Test Method for Measuring Warp and Total Thickness Variation on Silicon Slices and Wafers by a Non-contact Scanning Method”), TIR (Total Indicator Reading, which is the sum of the maximum positive and negative deviations of the wafer surface from the best-fit plane for a fixed wafer), SRAD (Spherical Reference Measurement, which represents the radius of curvature corresponding to the best-fit sphere); and other abbreviations for parameters that characterize the local flatness of a wafer, in particular: LFPD (Local Focal Plane Deviation, which is the maximum distance between the wafer surface and the best-fit plane (above or below the surface of a non-fixed wafer) within a given area) and LTV (Local Thickness Deviation, which is the difference between the maximum and minimum thickness values ​​within a given area for a non-fixed wafer).

[0070] In the present invention, the flatness of a wafer is characterized by a parameter generally referred to as “warpage.” This parameter refers to the algebraic difference of the wafer from a reference plane. Figure 1 The determination of this parameter from the surface profile by the algebraic difference of the ordinates B and C of a disk placed on a reference surface is schematically illustrated.

[0071] It is also possible to determine the median plane from the surface profile (usually using an algorithm implemented as a least squares method) and then calculate the warpage based on the deviation from the median plane, which will give the same result as long as the median plane is parallel to the reference plane. If the median plane is not parallel to the reference plane, then the measurement method relative to the reference plane will result in an increased warpage calculated based on the deviation from the median plane.

[0072] The method of the present invention is now described, which solves the proposed problem.

[0073] The method of the present invention adopts a chemical vapor deposition (CVD) technique implemented in a heated housing. The method involves a gas mixture, which includes at least one silicon precursor gas (such as silane or chlorosilane) and / or at least one carbon precursor gas (such as alkane or alkene), and / or at least one silicon and carbon precursor gas (such as methyltrichlorosilane, referred to as MTCS), and at least one nitrogen-containing doping gas (such as NH3, N2H4, N2). The doping gas can also be a precursor of carbon and / or silicon (for example, an amine, such as H2NCH3). These gases can be diluted in a carrier gas, which can be a reducing gas such as hydrogen and / or an inert gas such as argon.

[0074] For example, the gas components used to implement the method of the present invention may include a carbon precursor, a silicon precursor, a doping gas, and a carrier gas.

[0075] Another example gas composition includes silicon and carbon precursors, a silicon precursor, a carbon precursor, a doping gas, and a carrier gas.

[0076] This gas mixture enters the reactor at high temperature, where the precursor gases decompose and react on the surface to form the 3C-SiC polytype. This material is particularly suitable for use in combination with single-crystal SiC layers due to its mechanical and thermal properties, thermal expansion compatibility and purity. It can also be doped with nitrogen to very high levels, typically 10 20 The material has a resistivity of less than 20 ohms / cm and does not degrade the quality of the substrate, which would be detrimental to the manufacture of power components. Finally, the material can withstand the high temperatures that wafers must undergo during the manufacture of electronic components.

[0077] During deposition of SiC by CVD, the temperature of the reactor should be between about 1300 K and about 1800 K, preferably between about 1350 K and about 1700 K, more preferably between about 1400 K and about 1650 K, more preferably between about 1450 K and about 1650 K. The total pressure in the reactor advantageously does not exceed 350 mbar, preferably does not exceed 300 mbar.

[0078] In an advantageous embodiment of the method for manufacturing a P-SiC wafer according to the invention, the deposition is carried out on the graphite surface of the substrate by a CVD process. It is very advantageous that the substrate is an isostatic graphite substrate with fine grains and purified, which is used to avoid contamination and degassing of any impurities during the deposition process. For example, to obtain a wafer with a diameter of 150 mm, deposition can be carried out on a disc-shaped graphite cylinder with a diameter close to the nominal value of 150 mm and a thickness greater than 2 mm to ensure that the substrate has sufficient flatness. The reactor may include a plurality of such discs, the diameters of which may be the same or different. The flatness of the two sides of the disc is preferably less than 15 microns, which is obtained by sufficiently precise machining. The thermal expansion coefficient of the isostatic graphite is carefully selected so as to be compatible with the SiC layer during the cooling process after deposition. The "grade2303" substrate sold by the company MERSEN can be used.

[0079] Typical embodiments of the method according to the invention will now be described, and first of all, a reactor in which the method according to the invention can be implemented will be described by way of example in FIG. 12. The process of the invention is carried out in a reactor 1 of a special type. The reactor 1 comprises a reaction chamber 2, which comprises a reaction space 3, a heating space 4 and a space 5 for evacuating the reaction gas. The housing 2 is designed to be able to reach a low pressure of at least several tens of millibars by pumping the gas to an exhaust gas treatment device (not shown in the figure). The precursor gas enters the reaction space 3 of the reactor 1 through a plurality of injectors 11, which are supplied by a gas pipe 8 called the precursor gas inlet. The reaction gas leaves the reaction space 3 and enters the exhaust space 5, from which it is sucked into the gas line 9 called the reaction gas outlet through the outlet nozzle 10. The heating space 4 comprises a plurality of heating elements 6, which are usually solenoids. A graphite cylinder or disc 12 (also referred to herein as a substrate) is loaded into the housing 2; for simplicity, FIG. 12 does not show a bracket for fixing the substrate 12 in the reactor 1.

[0080] The deposition chamber 2 is heated by magnetic field induction in the graphite susceptor 7, and the precursor gas (such as silane, alkane and / or methylchlorosilane), carrier gas (such as hydrogen and / or argon), and doping gas (such as NH3, amine and / or N2) will circulate in the susceptor 7. The graphite substrate 12 is in thermal equilibrium in the reaction space 3, and the reaction space 3 is heated by the susceptor 7, and the temperature is generally between 1300K and 1700K (measured by thermocouples), more preferably between 1350K and 1650K. The mixed gas is introduced by the nozzle or injector 11 to evenly distribute the gas flow in the housing 2. In this temperature range, the deposition rate varies quite widely, from a few microns / hour to more than 100 microns / hour. The total partial pressure of the gaseous precursor is advantageously less than 350 mbar, preferably less than 300 mbar.

[0081] To achieve a minimum P-SiC deposition thickness of about 600 microns, the gas injection time can vary from a few hours to tens of hours or even hundreds of hours, depending on the selected conditions. The above control parameters can be adjusted to obtain a product in accordance with the present invention, as will be explained in detail in the examples. In this way, it is possible to obtain high-quality P-SiC plates under economically satisfactory conditions, enabling P-SiC plates to replace single-crystalline SiC produced by conventional PVT processes in electronic applications.

[0082] When the deposition thickness on the surface of the graphite substrate 12 is reached, the injection of precursor gas into the furnace is stopped, the housing is cooled to room temperature, and then the precursor gas is exhausted. The graphite disk 12 coated with a thick layer of SiC deposit is then machined and then air oxidized, typically at a temperature of 900°C, to remove any graphite residues. A pristine SiC disk is obtained on each side.

[0083] The deformation of the SiC disk (raw blank) is measured by scanning the surface of the disk in contact with the graphite using a white light confocal sensor. For the measurement, the face of the disk on the CVD deposition side is placed on a support. The difference between the maximum and minimum heights of the surface scanned by the sensor relative to the support plane of the measuring tool is measured. The graphite side surface is a flat reference surface before it is separated from the graphite. After separation from the graphite, the surface warps due to stress relaxation of the deposited layer. This warped surface can be interpolated with the median plane using the least squares method. If the median plane is parallel to the support plane, the deformation measurement is equal to the warpage. In general, this method of measuring deformation is mainly used to measure the warpage.

[0084] If the deformation measurements of the raw blank meet the targets set below, it can be corrected to a nominal thickness of slightly more than 350 microns and a final warpage of less than 50 microns for a standard 6-inch wafer.

[0085] In practice, it is first necessary to prepare an intermediate blank by grinding a raw blank separated from the graphite, and then, starting from this intermediate blank, to prepare the P-SiC wafer by fine grinding and subsequent polishing, onto which the single-crystalline layer of silicon carbide is transferred. The difference between the initial thickness of the raw blank and the deformation measured on said raw blank must not be less than the thickness of the intermediate blank. This means that the volume of the ground intermediate (cylindrical) blank must be included in the volume of the raw blank (see Figure 1 ). The purpose of the correction step is also to remove sufficient thickness from the face in contact with the graphite. This eliminates the initial growth zone of the crystals and thus eliminates the strong stresses generated during the evolution of the deposit.

[0086] So and Chun published a study on the growth orientation of P-SiC crystals in the temperature range of 1373K to 1673K in the paper "Growth and structure of chemical vapor deposited silicon carbide from methyltrichlorosilane and hydrogen in the temperature range of 1100 to 1400℃" (Journal of Vacuum Science & Technology A 6,5 (1988)). Figure 4 The texture coefficient in this temperature region changes from the preferred orientation (111) at low temperature to the orientation (220) at high temperature. The texture coefficient was measured using the method described in "X. Quantitative measurement of preferred orientation in rolled uranium bars" by GB Harris, published in Philosophical Magazine, Vol. 43, No. 336, pp. 113-123, Vol. 7, 1952.

[0087] The product obtained by the method of the present invention not only has excellent flatness (characterized by a low warpage parameter value), low resistance and good thermal conductivity, but also has a small grain size on its upper surface (i.e., the surface away from the growth substrate obtained by polishing and removing material) and good grain size uniformity.

[0088] Example

[0089] Examples 1 to 6 illustrate certain aspects of the present invention but do not limit the scope of the present invention.

[0090] In these examples, the diffraction peaks were collected in the angular range of 10° to 135° (2θ scale) using a PANalytical X'Pert PRO MPD X-ray diffractometer using the θ-2θ method. Within this range, the ten SiC3C diffraction peaks shown in Table 1 were classified by increasing Miller index (hkl):

[0091] Table 1: Considered diffraction peaks

[0092]

[0093] Texture coefficient C hkl (N = 10 diffraction peaks) is based on the peak intensity I which is proportional to the area under the sample peak. hkl And the theoretical strength of the powder I0hkl Calculated, theoretical strength I 0hkl It can be obtained from the theoretical intensity (%) published by ICDD (International Center for Diffraction Data).

[0094] C hkl =(I hkl / I 0hkl ) / (1 / N xΣ(I hkl / I 0hkl )).

[0095] In this case, the texture coefficient is between 0 and 10. It can also be expressed as a percentage. It quantifies the average preferred orientation of the deposited layer crystals relative to the surface normal of the sample.

[0096] In these examples, the carbon source and silicon source are the same molecule, methyltrichlorosilane (MTCS for short). The nitrogen source doping gas is NH3. By modifying several key parameters of the CVD process (temperature, partial pressure of the precursors, percentage of doping gas), the orientation of the deposited layer and its texture can be changed. This will affect the internal stress gradient of the deposit, thereby obtaining a target warpage on the blank.

[0097] Example 1: Conical coarse grain texture with preferred orientation (422)

[0098] A layer of 650 μm was deposited on a graphite substrate, the operating temperature was 1550 K, the MTCS partial pressure was 23 mbar, and the NH3 mole fraction was 3%.

[0099] Figure 2 A scanning electron microscope image of backscattered electrons obtained from a cross section of the obtained P-SiC layer is shown; the substrate is at the bottom, the black scale corresponds to a length of 100 micrometers. At the bottom is a texture triangle on which certain crystal planes marked with four different white symbols are marked for reference purposes. Figure 3 Similar images obtained with direct-mode scanning electron microscopy at higher magnification are shown; the white scale bar corresponds to a length of 20 microns.

[0100] In both micrographs, the substrate is at the bottom.

[0101] The observed orientation is a preferred orientation texture (422), and its texture coefficient is shown in Table 2:

[0102] Table 2: P-SiC texture coefficients obtained according to Example 1

[0103] <![CDATA[C 111 +C 222 +C 511 ]]> <![CDATA[C 220 ]]> <![CDATA[C 422 ]]> 9％ 1％ 80％

[0104] Figure 2 and Figure 3It is shown that the grain diameter continues to increase during the first 200 microns. The increase in grain size at each ordinate in the reference frame can be evaluated by counting the number of intersections of a horizontal line of constant ordinate with the grain boundaries on the EBSD image.

[0105] The nitrogen concentration of the formed layer was measured by SIMS to be 8x10 19 nitrogen atoms, and its resistivity was measured by a four-point method to be 16 ohm-cm.

[0106] The thermal conductivity of this layer was calculated from the results of thermal diffusivity measurements using the laser flash method. The value obtained was 210 W / m / K.

[0107] Although the physical properties were within the expected targets, the deformation measured on the raw discs was much higher than expected. The average deformation was 850 microns with a standard deviation of 140 microns in a total of 16 produced discs. It is not possible to produce P-SiC wafers by correcting the raw discs with a thickness less than 1000 microns.

[0108] After multiple depositions under this condition, the observed texture has a clear preferred orientation (422), where the texture coefficient C 422 >75%.

[0109] Example 2: Fine grain texture orientation (111)

[0110] A layer of 650 μm was deposited on a graphite substrate, the operating temperature was 1550 K, the MTCS partial pressure was 8 mbar, and the NH3 mole fraction was 6%. Figure 4 and Figure 5 is the same as Example 1 Figure 2 and Figure 3 Similar micrographs ( Figure 5 The white scale bar in the figure corresponds to a length of 50 μm).

[0111] The observed orientation is a preferred orientation (111) texture, and its texture coefficient is shown in Table 3:

[0112] Table 3: P-SiC texture coefficients obtained according to Example 2

[0113] <![CDATA[C 111 +C 222 +C 511 ]]> <![CDATA[C 220 ]]> <![CDATA[C 422 ]]> 86％ 1％ 8％

[0114] Figure 5 The grains that do not increase in size as the P-SiC layer grows are shown; these grains are thin rod-shaped and aligned with the normal direction of the basal plane. The increase in grain size at each ordinate in the reference frame can be evaluated by counting the number of intersections of a horizontal line of constant ordinate with the grain boundaries on the EBSD image.

[0115] The nitrogen concentration of the obtained deposit was measured by SIMS to be 7 x 10 20 The thermal conductivity of the layer was inferred from the results of thermal diffusivity measurements using the laser flash method. The value obtained was 52 W / m / K, which is well below the target value. The fine grain structure seems to limit the thermal conductivity to a large extent.

[0116] On the other hand, the deformation measurements performed on the raw discs showed very good results. The average deformation was 190 microns with a standard deviation of 72 microns in a total of 16 produced discs. This makes it possible to produce P-SiC wafers at reasonable cost by correcting the raw discs with a thickness of less than 1000 microns.

[0117] After multiple depositions under this condition, the observed orientation has a texture with a clear preferred orientation (111) and a texture coefficient C 111 +C 222 +C 511 >80%.

[0118] Example 3: Fine grain texture orientation (220)

[0119] A layer of 650 μm was deposited on a graphite substrate, the operating temperature was 1550 K, the MTCS partial pressure was 16 mbar, and the NH3 mole fraction was 4%.

[0120] Figure 6 and Figure 7 is the same as Example 1 Figure 2 and Figure 3 Similar micrographs.

[0121] The observed orientation is a preferred orientation (220) texture, and its texture coefficient is shown in Table 4:

[0122] Table 4: P-SiC texture coefficients obtained according to Example 3

[0123] <![CDATA[C 111 +C 222 +C 511 ]]> <![CDATA[C 220 ]]> <![CDATA[C 422 ]]> 2％ 93％ 3％

[0124] The nitrogen concentration of the obtained deposit was measured by SIMS to be 1.8 x 10 20 The dendritic texture appears to promote good thermal conductivity at high doping despite the small grain size.

[0125] The deformation measurements performed on the raw discs showed very good results. The average deformation was 210 microns with a standard deviation of 82 microns in a total of 16 produced discs. This makes it possible to produce P-SiC wafers at reasonable cost by correcting raw discs with thicknesses of less than 1000 microns.

[0126] After multiple depositions under this condition, the observed texture has a clear preferred orientation (220), where the texture coefficient C 220 >90% and C 422 <10%.

[0127] Example 4: The fine grain texture is mainly a texture along the (220) orientation, mixed with a large grain texture mainly along the (422) orientation.

[0128] Figure 8 and Fig. 9 is the same as Example 1 Figure 2 and Figure 3 Similar micrographs.

[0129] 800 micron layers were deposited on graphite substrates, the operating temperature was 1600 K, the MTCS partial pressure was 16 mbar, and the NH3 mole fraction was 4%. The texture observed had a preferred orientation (220), and the texture coefficients collected in Table 5 show a preferred orientation (422) for the coarse grains:

[0130] Table 5: P-SiC texture coefficients obtained according to Example 4

[0131] <![CDATA[C 111 +C 222 +C 511 ]]> <![CDATA[C 220 ]]> <![CDATA[C 422 ]]> 8％ 65％ 18％

[0132] The figure shows two groups of grains of different sizes. The diameter of the grains along the (220) orientation is between 1 and 10 microns. The other grains, which are mainly oriented along the (422) orientation, are conical in shape and can increase to 50 microns in diameter. The increase in grain size at each ordinate in the reference frame can be evaluated by counting the number of intersections of a horizontal line of constant ordinate with the grain boundaries on the EBSD image. In this case, the growth in average grain size stabilizes quickly, since large grains are still a minority in the texture.

[0133] The nitrogen concentration of the obtained deposit was measured by SIMS to be 2.2 x 10 20 The layer has nitrogen atoms and its resistivity was measured by the four-point method to be 3.3 ohm cm. The thermal conductivity of the layer was inferred from the results of measuring thermal diffusivity using the laser flash method. The value obtained was 215 W / m / K, which is above the target value.

[0134] The deformation measurements performed on the raw discs showed very good results. The average deformation was 235 microns with a standard deviation of 90 microns over a total of 16 produced discs. This makes it possible to produce P-SiC wafers at reasonable cost by correcting raw discs with thicknesses of less than 1000 microns.

[0135] After multiple depositions under this condition, the observed texture maintains a preferred orientation (220), where the texture coefficient C 220 >60% and C 422 <20%.

[0136] Example 5: A texture of large grains substantially along the (422) orientation, mixed with a fine texture of small grains primarily along the (220) orientation.

[0137] Layers of 800 μm were deposited on graphite substrates, the operating temperature was 1600 K, the MTCS partial pressure was 16 mbar, and the NH3 mole fraction was 6%.

[0138] FIG. 10 and FIG. 11 are similar to those of Example 1. Figure 2 and Figure 3 Similar micrographs.

[0139] The observed texture exhibits a preferred orientation (422) and the texture coefficients collected in Table 6 show the orientation of very large grains:

[0140] Table 6: P-SiC texture coefficients obtained according to Example 5

[0141] <![CDATA[C 111 +C 222 +C 511 ]]> <![CDATA[C 220 ]]> <![CDATA[C 422 ]]> 20％ 7％ 54％

[0142] The figure shows that the grains are mainly oriented along (422) or a few along (111), which are conical and can reach a diameter of 100 microns. There are very few small grains (220) less than 10 microns. The figure shows that the grain diameter continues to grow in the first 500 microns. The increase in grain size at each ordinate in the reference system can be evaluated by counting the number of intersections between the horizontal line of the constant ordinate and the grain boundary on the EBSD image.

[0143] The nitrogen concentration of the obtained deposit was measured by SIMS to be 6.8×10 20 The layer has nitrogen atoms and its resistivity was measured by the four-point method to be 0.9 ohm cm, which is well below the target upper limit. The thermal conductivity of the layer was also calculated by measuring the thermal diffusivity using the laser flash method. The value obtained was 130 W / m / K, which is below the target value.

[0144] In a total of 16 discs produced, the average deformation was 650 microns with a standard deviation of 178 microns. It is not possible to produce P-SiC wafers by correcting the original discs with a thickness less than 1000 microns.

[0145] After multiple depositions under this condition, the observed texture maintains a preferred orientation (422), where the texture coefficient C 422 >50% and C 111 +C 222 +C 511 >15% and C 220 <10%.

[0146] Example 6: Texture obtained according to Example 3 (but without adding doping gas).

[0147] The deposition of a layer of 800 microns on a graphite substrate was carried out under almost the same conditions as in Example 3, with an operating temperature of 1550 K, an MTCS partial pressure of 16 mbar, but with an NH3 mole fraction of 0%.

[0148] FIG. 13 is a diagram showing the Figure 6 Similar micrographs.

[0149] The observed texture orientation is mainly (422), followed by (111), and there is almost no (220) texture. The texture coefficients are shown in Table 7:

[0150] Table 7: P-SiC texture coefficients obtained according to Example 6

[0151] <![CDATA[C 111 +C 222 +C 511 ]]> <![CDATA[C 220 ]]> <![CDATA[C 422 ]]> 30％ 3,5％ 40％

[0152] The nitrogen concentration in the obtained sediments is below the SIMS detection threshold, far below 10 per cubic centimeter. 19 The layer has nitrogen atoms and its resistivity was measured by the four-point method to be 5 ohm cm. The thermal conductivity of the layer was inferred from the results of measuring thermal diffusivity using the laser flash method. The value obtained was 130 W / m / K, which is below the target value.

[0153] The deformation measured on the original discs was not as expected. Across a total of 16 discs produced, the average deformation was 530 microns with a standard deviation of 110 microns.

[0154] This does not allow P-SiC wafers to be produced at reasonable cost by rectifying the original disc with a thickness of less than 1000 microns.

[0155] After multiple depositions under this condition, the observed texture is mainly in the (422) direction, followed by the (111) direction, and the texture coefficient is as follows: C 422 >35% and C 111+C 222 +C 511 >20% and C 220 <15%.

[0156] Comparison of Examples 1 to 6

[0157] Table 7 summarizes the main results related to the above examples:

[0158] Table 7: Main results of Examples 1 to 6 above:

[0159]

[0160] Examples 2, 3 and 4 show that the texture is strongly oriented along two possible axes (111) and (220) (C 220 >60% or C 111 +C 222 +C 511 >80%), while the contribution of C422 orientation is always less than 20%. The texture consists of a series of elongated grains. The maximum diameter of the grain is stable at 10 microns and the length can reach 100 microns.

[0161] Example 6 was produced under the conditions of Example 3, but without adding doping gas. 422 When the orientation strength is greater than 20%, the deformation is large and it is impossible to produce P-SiC wafers from the original billet with a thickness of less than 1000 μm by grinding.

Claims

1. A doped polycrystalline SiC plate having a preferred crystal orientation, the plate being characterized by: (i) Its texture coefficient C 422 Less than 30%, and (ii.a) Its texture coefficient C 220 More than 60%, preferably more than 80%, or (ii.b) The sum of the texture coefficients C 111 +C 222 +C 511 Greater than 70%, preferably greater than 80%.

2. The polycrystalline SiC plate according to claim 1, characterized in that: Its resistivity is less than 20 milliohm·cm, preferably less than 15 milliohm·cm, even more preferably less than 10 milliohm·cm.

3. The polycrystalline SiC plate according to any one of claims 1 to 2, characterized in that: The polycrystalline SiC plate is doped with nitrogen, and the nitrogen content measured by secondary ion mass spectrometry is greater than 5x10 19 atoms / cm3, preferably greater than 1x10 20 atoms / cm3, even more preferably greater than 1.5x10 20 atoms / cubic centimeter.

4. The polycrystalline SiC plate according to any one of claims 1 to 3, characterized in that: Its texture coefficient C 422 Less than 20%, preferably less than 15%, more preferably less than 10%.

5. The polycrystalline SiC plate according to any one of claims 1 to 4, wherein the polycrystalline SiC plate is doped with nitrogen, and the nitrogen content measured by secondary ion mass spectrometry is greater than 5×10 19 atoms / cm3, the resistivity of the plate is less than 15 milliohm-cm, and has a preferred crystal orientation, and the plate is characterized by: (i) Its texture coefficient C 422 Less than 20%, and (ii.a) Its texture coefficient C 220 More than 60%, preferably more than 80%, or (ii.b) The sum of the texture coefficients C 111 +C 222 +C 511 Greater than 80%.

6. The polycrystalline SiC plate according to any one of claims 1 to 5, characterized in that: The polycrystalline SiC plate is a raw blank produced by a vapor deposition process.

7. The polycrystalline SiC plate according to any one of claims 1 to 5, characterized in that: The polycrystalline SiC plate is an intermediate blank obtained by grinding the original blank according to claim 6, and the intermediate blank is used for manufacturing a wafer.

8. The polycrystalline SiC plate according to claim 7, characterized in that: The thickness of the polycrystalline SiC plate is less than 550 microns, preferably less than 500 microns, more preferably less than 450 microns, and even more preferably between 355 microns and 420 microns.

9. The polycrystalline SiC plate according to any one of claims 1 to 8, characterized in that: The polycrystalline SiC plate has a diameter between 140 mm and 165 mm, a thickness between 350 μm and 450 μm, and a deformation characterized by a warpage of less than 50 μm, preferably less than 40 μm, and even more preferably less than 30 μm.

10. The polycrystalline SiC plate according to claim 9, characterized in that: The thickness of polycrystalline SiC plates is between 350 microns and 400 microns.

11. The polycrystalline SiC plate according to any one of claims 1 to 7, characterized in that: The polycrystalline SiC plate has a diameter between 185 mm and 210 mm, a thickness between 500 μm and 650 μm, and a deformation characterized by a warpage of less than 70 μm, preferably less than 50 μm, and even more preferably less than 40 μm.

12. The polycrystalline SiC plate according to claim 11, characterized in that: The thickness of the polycrystalline SiC plate is between 500 microns and 600 microns.

13. The polycrystalline SiC plate according to any one of claims 1 to 12, characterized in that: Polycrystalline SiC plates are obtained by CVD process.

14. A method for manufacturing a polycrystalline SiC plate according to any one of claims 1 to 13, comprising a step of chemically vapor depositing a polycrystalline SiC layer on a graphite surface of a substrate (12) comprising a graphite surface, in which step a gas mixture is introduced into a heated housing (2) to form a gas phase, the gas phase comprising: - at least one gaseous precursor of silicon and / or carbon, - at least one doping gas comprising at least one nitrogen atom, -Carrier gas, The gas mixture decomposes on the surface of the graphite substrate (12) to form a polycrystalline SiC layer on the graphite surface of the substrate. The method is characterized in that the temperature in the heating shell (2) is between 1450K and 1650K and the total partial pressure of the gaseous precursor is less than 350 mbar, preferably less than 300 mbar.

15. The method according to claim 14, characterized in that The gas phase comprises trichloromethylsilane and preferably comprises no other precursors of silicon and / or carbon.

16. The method according to any one of claims 14 and 15, characterized in that The doping gas is selected from the group consisting of the following gases: NH3, N2H4, N2, H2NCH3.

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