Semiconductor module

Abstract

The semiconductor module includes at least one substrate and a plurality of semiconductor switching elements. The substrate has a first electrode pattern, a second electrode pattern, and a third electrode pattern, and the first electrode pattern is located between the second electrode pattern and the third electrode pattern in plan view. The semiconductor switching element has a first surface joined to the first electrode pattern, and a second surface facing in a direction opposite to the first surface. The second surface is provided with a control electrode, a control wiring connected to the control electrode, and a main electrode having a plurality of regions divided by the control wiring. Each of the plurality of regions is electrically connected to the second electrode pattern via a first lead wire, and is electrically connected to the third electrode pattern via a second lead wire. The second electrode pattern is a pattern for a main current. The third electrode pattern serves as an auxiliary pattern for control.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor module. Background Art

[0002] In semiconductor modules represented by power semiconductor modules, a structure in which a plurality of semiconductor switching elements are connected in parallel may be adopted.

[0003] For example, in the semiconductor module described in Patent Document 1, on an insulating substrate on which a plurality of semiconductor switch elements are mounted, a drain pattern, a source pattern, a source control pattern, and a gate control pattern are provided in common for the plurality of semiconductor switch elements. Here, the drain pad of the semiconductor switch element is bonded to the drain pattern. The source pad of the semiconductor switch element is electrically connected to the source pattern by a wire. The source pad of the semiconductor switch element is electrically connected to the source control pattern by a wire. The gate pad of the semiconductor switch element is electrically connected to the gate control pattern by a wire.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: International Publication No. 2019 / 044748 Summary of the invention

[0007] Problem that the invention aims to solve

[0008] In the structure described in Patent Document 1, a wire for electrically connecting a source pad and a source control pattern is bonded to a position offset within the surface of the source pad, thereby causing current imbalance within the source pad, resulting in a problem of reduced switching characteristics.

[0009] In view of the above circumstances, an object of one aspect of the present disclosure is to improve the switching characteristics of a semiconductor module.

[0010] Solutions for solving problems

[0011] In order to solve the above problems, the semiconductor module of the preferred technical solution of the present invention comprises: at least one substrate, which has a first electrode pattern, a second electrode pattern and a third electrode pattern, and the first electrode pattern is located between the second electrode pattern and the third electrode pattern when viewed from above; and a plurality of semiconductor switching elements, which have a first surface joined to the first electrode pattern and a second surface facing in a direction opposite to the first surface, and a control electrode, a control wiring connected to the control electrode and a main electrode having a plurality of areas divided by the control wiring are provided on the second surface, and the plurality of areas are respectively electrically connected to the second electrode pattern via a first wire and electrically connected to the third electrode pattern via a second wire, the second electrode pattern is a pattern for main current, and the third electrode pattern is used as an auxiliary pattern for control. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a cross-sectional view of a semiconductor module according to an embodiment.

[0013] Figure 2 It is a partially omitted plan view of the semiconductor module according to the embodiment.

[0014] Figure 3 This is a circuit diagram of the upper arm of the semiconductor module.

[0015] Figure 4 This is a circuit diagram of an upper arm of a semiconductor module having a structure in which an auxiliary control terminal is connected to a main current path.

[0016] Figure 5 It is a side view for explaining the semiconductor switch element and the semiconductor element on the substrate for the upper arm.

[0017] Figure 6 It is a top view showing the structure on the substrate for the upper arm.

[0018] Figure 7 It is a top view showing the structure on the substrate for the lower arm.

[0019] Figure 8 It is a plan view showing a structural example of a control terminal.

[0020] Fig. 9 This is a plan view showing the structure on the substrate for the upper arm in Modification Example 1.

[0021] Fig.10 This is a plan view showing the structure on the substrate for the lower arm in Modification Example 1. DETAILED DESCRIPTION

[0022] Hereinafter, preferred embodiments of the present disclosure will be described with reference to the accompanying drawings. In addition, in the accompanying drawings, the size and scale of each part are appropriately different from the actual one, and there are also parts schematically shown for easy understanding. In addition, as long as there is no record of the meaning of the present disclosure being particularly limited in the following description, the scope of the present disclosure is not limited to these embodiments.

[0023] 1. Implementation Method

[0024] 1-1. Overall structure of semiconductor module

[0025] Figure 1 2 is a cross-sectional view of a semiconductor module 10 according to the embodiment. Figure 2 FIG. 1 is a top view of a semiconductor module 10 according to an embodiment, with part of the semiconductor module 10 omitted. Figure 1 In the figure, for the sake of convenience, the wires 91a, 91b, 92a, 92b, 93a, 93b, 94a, 94b, 95 described later are omitted, and the outer shapes of the housing 50 and the cover 60 described later are indicated by double-dashed lines. Figure 2 In the figure, for convenience of explanation, illustration of the housing 50 , the cover 60 , the main terminals 71 , 72 , 73 , and the control terminals 81 , 82 , 83 , 84 to be described later are omitted.

[0026] The semiconductor module 10 is a power module such as an IGBT (Insulated Gate Bipolar Transistor) module, etc. The semiconductor module 10 is used for power control in devices such as inverters and rectifiers mounted in industrial equipment, railway vehicles, automobiles, or household electrical equipment.

[0027] like Figure 1 and Figure 2 As shown, the semiconductor module 10 has two substrates 20a, two substrates 20b, eight semiconductor switch elements 31a, eight semiconductor switch elements 31b, eight semiconductor elements 32a, eight semiconductor elements 32b, a base 40, a shell 50, a cover 60, main terminals 71, 72, 73, control terminals 81, 82, 83, 84 and wires 91a, 91b, 92a, 92b, 93a, 93b, 94a, 94b, 95.

[0028] Here, the control terminals 82 and 84 are each an example of a "first control terminal". The control terminals 81 and 83 are each an example of a "second control terminal". The wires 91a and 91b are each an example of a "first wire". The wires 92a and 92b are each an example of a "second wire". The wires 93a and 93b are each an example of a "third wire". The wires 94a and 94b are each an example of a "fourth wire".

[0029] Eight semiconductor switch elements 31a and eight semiconductor elements 32a are separately mounted on two substrates 20a and electrically connected in parallel by wires 91a, 92a, 93a, and 94a, thereby forming an upper arm of the inverter circuit. On the other hand, eight semiconductor switch elements 31b and eight semiconductor elements 32b are separately mounted on two substrates 20b and electrically connected in parallel by wires 91b, 92b, 93b, and 94b, thereby forming a lower arm of the inverter circuit. The upper arm and the lower arm are electrically connected by a wire 95.

[0030] Below, first, based on Figure 1 and Figure 2 , the outline of each part of the semiconductor module 10 is described in sequence. In the following, for the convenience of description, the X-axis, Y-axis and Z-axis that are orthogonal to each other are appropriately used. The Z-axis is an axis parallel to the thickness direction or height direction of the semiconductor module 10. In the following, one direction along the X-axis is the X1 direction, and the direction opposite to the X1 direction is the X2 direction. One direction along the Y-axis is the Y1 direction, and the direction opposite to the Y1 direction is the Y2 direction. One direction along the Z-axis is the Z1 direction, and the direction opposite to the Z1 direction is the Z2 direction. The relationship between these directions and the vertical direction is not particularly limited and is arbitrary. In addition, in the following, the situation of observing in the direction along the Z-axis is sometimes referred to as "looking down".

[0031] Each of the two substrates 20a is housed in the case 50 and carries four semiconductor switch elements 31a and four semiconductor elements 32a. Similarly, each of the two substrates 20b is housed in the case 50 and carries four semiconductor switch elements 31b and four semiconductor elements 32b.

[0032] exist Figure 1 and Figure 2 In the example shown, two substrates 20a are arranged in the direction along the Y axis, and two substrates 20b are arranged in the direction along the Y axis at a position close to the X2 direction relative to the two substrates 20a. Here, one of the two substrates 20a is arranged at a position close to the X1 direction relative to one of the two substrates 20b, and the other substrate 20b is arranged at a position close to the X1 direction relative to the other substrate 20b.

[0033] The substrate 20a and the substrate 20b are each a laminated substrate such as a DCB (Direct Copper Bonding) substrate or a DBA (Direct Bonded Aluminum) substrate. Figure 2 As shown, the substrate 20a has an insulating plate 21a, a wiring layer 22a, and a heat dissipation layer 23a. Similarly, the substrate 20b has an insulating plate 21b, a wiring layer 22b, and a heat dissipation layer 23b.

[0034] The insulating plate 21a and the insulating plate 21b are each an insulating plate-shaped member, for example, made of ceramics such as aluminum nitride, aluminum oxide or silicon nitride. A wiring layer 22a is provided on one side of the insulating plate 21a, and a heat dissipation layer 23a is provided on the other side. Similarly, a wiring layer 22b is provided on one side of the insulating plate 21b, and a heat dissipation layer 23b is provided on the other side. The wiring layers 22a, 22b and the heat dissipation layers 23a, 23b are each made of metal such as copper or aluminum.

[0035] The wiring layer 22a is a conductive layer for mounting the semiconductor switch element 31a and the semiconductor element 32a. The main terminal 71 and the control terminals 81 and 82 are bonded to the wiring layer 22a using a conductive bonding material such as solder. The heat dissipation layer 23a is a thermally conductive layer for dissipating heat from the semiconductor switch element 31a and the semiconductor element 32a to the base 40, and is bonded to the base 40 using a conductive bonding material such as solder.

[0036] Similarly, the wiring layer 22b is a conductive layer for mounting the semiconductor switch element 31b and the semiconductor element 32b. The main terminals 72, 73 and the control terminals 83, 84 are bonded to the wiring layer 22b using a conductive bonding material such as solder. The heat dissipation layer 23b is a thermally conductive layer for dissipating heat from the semiconductor switch element 31b and the semiconductor element 32b to the base 40, and is bonded to the base 40 using a conductive bonding material such as solder.

[0037] In detail, Figure 2 As shown, the wiring layer 22a has electrode patterns 22a1, 22a2, 22a3, and 22a4 arranged at intervals from each other. Similarly, the wiring layer 22b has electrode patterns 22b1, 22b2, 22b3, and 22b4 arranged at intervals from each other.

[0038] Here, electrode pattern 22a1 and electrode pattern 22b1 are each an example of a "first electrode pattern". Electrode pattern 22a2 and electrode pattern 22b2 are each an example of a "second electrode pattern". Electrode patterns 22a1, 22b1, 22a2, 22b2 are each a pattern for main current. The main current refers to the largest current flowing in the semiconductor switch element 31a or the semiconductor switch element 31b, for example, the current flowing between the emitter electrode and the collector electrode, or the current flowing between the source electrode and the drain electrode. Electrode pattern 22a3 and electrode pattern 22b3 are each an example of a "third electrode pattern", used as an auxiliary pattern for control. Electrode pattern 22a4 and electrode pattern 22b4 are each an example of a "fourth electrode pattern", used as a main pattern for control. In addition, details of these electrode patterns will be described later based on Figures 5 to 7 Provide explanation.

[0039] The back surfaces of semiconductor switch element 31a and semiconductor element 32a are bonded to electrode pattern 22a1 of wiring layer 22a by conductive bonding material such as solder. Similarly, the back surfaces of semiconductor switch element 31b and semiconductor element 32b are bonded to electrode pattern 22b1 of wiring layer 22b by conductive bonding material such as solder.

[0040] exist Figure 2 In the figure, the main terminals 71, 72, 73 and the control terminals 81, 82, 83, 84 are omitted, but areas CTa, CTb, CTc, CTd, CTe, CTf, CTg for connecting these terminals to the wiring layers 22a, 22b using conductive bonding materials such as solder are shown.

[0041] Region CTa is a region for bonding the main terminal 71, and is provided in the electrode pattern 22a1 of the wiring layer 22a. Region CTb is a region for bonding the control terminal 82, and is provided in the electrode pattern 22a3 of the wiring layer 22a. Region CTc is a region for bonding the control terminal 81, and is provided in the electrode pattern 22a4 of the wiring layer 22a. Region CTd is a region for bonding the main terminal 73, and is provided in the electrode pattern 22b1 of the wiring layer 22b. Region CTe is a region for bonding the main terminal 72, and is provided in the electrode pattern 22b2 of the wiring layer 22b. Region CTf is a region for bonding the control terminal 84, and is provided in the electrode pattern 22b3 of the wiring layer 22b. Region CTg is a region for bonding the control terminal 83, and is provided in the electrode pattern 22b4 of the wiring layer 22b.

[0042] The semiconductor switch element 31a and the semiconductor switch element 31b are each a switch element such as an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (metal-oxide-semiconductor field-effect transistor). An input electrode is provided on the back side (first side) of each of the semiconductor switch element 31a and the semiconductor switch element 31b. The input electrode is a drain electrode or a collector electrode. On the other hand, an output electrode (main electrode) and a control electrode are provided on the front side (second side) of each of the semiconductor switch element 31a and the semiconductor switch element 31b. The output electrode is a source electrode or an emitter electrode. In addition, the control electrode is a gate electrode. In addition, details about the front side are based on Figure 6 and Figure 7 Provide explanation.

[0043] The semiconductor element 32a and the semiconductor element 32b are each a FWD (Free Wheeling Diode). An output electrode is provided on the back surface (third surface) of each of the semiconductor element 32a and the semiconductor element 32b. The output electrode is a cathode electrode. On the other hand, an input electrode is provided on the front surface (fourth surface) of each of the semiconductor elements 32a and 32b. The input electrode is an anode electrode.

[0044] The base 40 is a plate-shaped member for heat dissipation, and constitutes the bottom plate of the semiconductor module 10. The two substrates 20a and the two substrates 20b are bonded to the upper surface of the base 40. On the other hand, a heat dissipation member such as a heat sink (not shown) may be arranged on the lower surface of the base 40. The base 40 is, for example, a metal plate made of copper, a copper alloy, aluminum or an aluminum alloy. The base 40 has thermal conductivity and dissipates heat from the semiconductor switch elements 31a, 31b and the semiconductor elements 32a, 32b. In addition, the base 40 may also have electrical conductivity, for example, electrically connected to a reference potential such as a ground potential.

[0045] exist Figure 2 In the example shown, the thickness direction of the base 40 is along the Z axis. When viewed along the Z axis, the base 40 has a shape having a pair of long sides extending in the direction along the X axis and a pair of short sides extending in the direction along the Y axis. Mounting holes 41 are provided near each corner of the base 40. The mounting holes 41 are, for example, through holes for screwing a heat dissipation member such as a heat sink (not shown) to the base 40. In addition, the top view shape of the base 40 is not limited to Figure 2 The example shown is arbitrary. In addition, the mounting hole 41 is provided as needed and can also be omitted.

[0046] The housing 50 is a frame-shaped member for dividing the internal space for accommodating the semiconductor switch elements 31a, 31b and the semiconductor elements 32a, 32b. The housing 50 is a substantial insulator, and is made of a resin material such as PPS (Polyphenylene Sulfide) or PBT (Polybutylene terephthalate), and is obtained by injection molding or the like. Here, the housing 50 may also be integrally formed with the main terminals 71, 72, 73 and the control terminals 81, 82, 83, 84 by insert molding or the like. In addition, from the viewpoint of improving the mechanical strength or thermal conductivity of the housing 50, the resin material may also contain inorganic fibers such as glass fibers, and may also contain inorganic fillers such as alumina or silica.

[0047] The housing 50 may be filled with a sealing resin. The sealing resin is a potting material that covers the semiconductor switch elements 31a, 31b and the semiconductor elements 32a, 32b, and is composed of, for example, a thermosetting resin such as an epoxy resin or a silicone resin. Here, from the viewpoint of improving thermal conductivity, the sealing resin preferably contains an inorganic filler such as silicon dioxide or aluminum oxide. In addition, the sealing resin may also be in a gel state.

[0048] Although not shown, the internal space of the housing 50 is open in the Z1 direction and the Z2 direction. Here, the base 40 is bonded to the housing 50 by an adhesive or the like so as to block the opening of the housing 50 in the Z2 direction. In addition, the cover 60 is bonded to the housing 50 by an adhesive or the like so as to block the opening of the housing 50 in the Z1 direction.

[0049] The cover 60 is a member for closing the opening of the housing 50 in the Z1 direction. The cover 60 is made of a resin material such as PPS (Polyphenylene Sulfide) or PBT (Polybutylene terephthalate) as is the case 50. Figure 1 In the example shown, the cover 60 has a function of supporting parts of the main terminals 71, 72, and 73. Here, the cover 60 may be a nut housing for screwing the main terminals 71, 72, and 73 to a bus bar (not shown).

[0050] Each of the main terminals 71, 72, and 73 is a terminal for connecting a bus bar (not shown) to the semiconductor module 10, and has a portion exposed to the outside of the semiconductor module 10. Figure 1 In the illustrated example, the main terminals 71 , 72 , 73 penetrate the cover 60 , and parts of the main terminals 71 , 72 , 73 are exposed to the outside of the semiconductor module 10 .

[0051] The main terminal 71 is a terminal on the high potential side and is connected to the above-mentioned region CTa. The main terminal 72 is a terminal on the low potential side and is connected to the above-mentioned region CTe. The main terminal 73 is a terminal for output and is connected to the above-mentioned region CTd. The main terminals 71, 72, and 73 are each made of a metal such as copper, copper alloy, aluminum, aluminum alloy, or iron alloy, and are obtained by bending a metal plate, etc.

[0052] The control terminals 81 and 82 are terminals for connecting a control circuit (not shown) for controlling the operation of the semiconductor switch element 31a to the semiconductor module 10. The control circuit is provided outside the semiconductor module 10. Here, the control terminal 81 has a terminal portion 81a exposed to the outside of the semiconductor module 10. A signal for controlling the operation of the semiconductor switch element 31a is supplied from the control circuit to the control terminal 81. The control terminal 82 has a terminal portion 82a exposed to the outside of the semiconductor module 10. A constant potential serving as a reference for the signal is supplied from the control circuit to the control terminal 82.

[0053] Similarly, the control terminals 83 and 84 are terminals for connecting a control circuit (not shown) for controlling the operation of the semiconductor switch element 31b to the semiconductor module 10. The control circuit is provided outside the semiconductor module 10. Here, the control terminal 83 has a terminal portion 83a exposed to the outside of the semiconductor module 10. A signal for controlling the operation of the semiconductor switch element 31b is supplied from the control circuit to the control terminal 83. The control terminal 84 has a terminal portion 84a exposed to the outside of the semiconductor module 10. A constant potential serving as a reference for the signal is supplied from the control circuit to the control terminal 84.

[0054] Each of the control terminals 81 , 82 , 83 , 84 is made of metal such as copper, copper alloy, aluminum, aluminum alloy, or iron alloy, similarly to the main terminals 71 , 72 , 73 , and is obtained by bending a metal plate or the like.

[0055] Each of the wires 91a, 91b, 92a, 92b, 93a, 93b, 94a, 94b, and 95 is a conductive wire or a wire group composed of at least one bonding wire.

[0056] The wire 91a is bonded to the electrode pattern 22a2 of the wiring layer 22a and the output electrode of the semiconductor switch element 31a, respectively. Through this bonding, the electrode pattern 22a2 and the output electrode of the semiconductor switch element 31a are electrically connected via the wire 91a. Similarly, the wire 91b is bonded to the electrode pattern 22b2 of the wiring layer 22b and the output electrode of the semiconductor switch element 31b, respectively. Through this bonding, the electrode pattern 22b2 and the output electrode of the semiconductor switch element 31b are electrically connected via the wire 91b.

[0057] The wire 92a is bonded to the output electrode of the semiconductor switch element 31a, the output electrode of the semiconductor element 32a, and the electrode pattern 22a3 of the wiring layer 22a, respectively. Through this bonding, the output electrode of the semiconductor switch element 31a, the output electrode of the semiconductor element 32a, and the electrode pattern 22a3 are electrically connected via the wire 92a. Similarly, the wire 92b is bonded to the output electrode of the semiconductor switch element 31b, the output electrode of the semiconductor element 32b, and the electrode pattern 22b3 of the wiring layer 22b, respectively. Through this bonding, the output electrode of the semiconductor switch element 31b, the output electrode of the semiconductor element 32b, and the electrode pattern 22b3 are electrically connected via the wire 92b.

[0058] The wire 93a is bonded to the electrode pattern 22a4 of the wiring layer 22a and the control electrode of the semiconductor switch element 31a, respectively. Through this bonding, the electrode pattern 22a4 and the control electrode of the semiconductor switch element 31a are electrically connected via the wire 93a. Similarly, the wire 93b is bonded to the electrode pattern 22b4 of the wiring layer 22b and the control electrode of the semiconductor switch element 31b, respectively. Through this bonding, the electrode pattern 22b4 and the control electrode of the semiconductor switch element 31b are electrically connected via the wire 93b.

[0059] The wire 94a is bonded to the electrode pattern 22a4 of each of the two substrates 20a. Through this bonding, the electrode patterns 22a4 of the two substrates 20a are electrically connected to each other via the wire 94a. Similarly, the wire 94b is bonded to the electrode pattern 22b4 of each of the two substrates 20b. Through this bonding, the electrode patterns 22b4 of the two substrates 20b are electrically connected to each other via the wire 94b.

[0060] The wire 95 is bonded to the electrode pattern 22a2 and the electrode pattern 22b1 of the substrate 20a and the substrate 20b adjacent to each other in the direction along the X axis. By this bonding, the electrode pattern 22a2 and the electrode pattern 22b1 of the substrate 20a and the substrate 20b adjacent to each other in the direction along the X axis are electrically connected via the wire 95.

[0061] Here, as described above, the electrode pattern 22a2 is electrically connected to the output electrode of the semiconductor switch element 31a. On the other hand, the electrode pattern 22b1 is electrically connected to the input electrode of the semiconductor switch element 31b. Therefore, the semiconductor switch element 31a and the semiconductor switch element 31b of the substrate 20a and the substrate 20b adjacent to each other in the direction along the X-axis are electrically connected in series.

[0062] In the above semiconductor module 10, as described above, in the upper arm, the electrode pattern 22a3 used as an auxiliary pattern for control is independent of the electrode pattern 22a2, so the control terminal 82 is electrically connected to the output electrode of the semiconductor switch element 31a without passing through the main current path. Therefore, the current path for controlling the drive of the semiconductor switch element 31a is not easily affected by the current fluctuations in the main current path, so the switching characteristics of the semiconductor switch element 31a can be improved. Similarly, in the lower arm, the electrode pattern 22b3 used as an auxiliary pattern for control is independent of the electrode pattern 22b2, so the control terminal 84 is electrically connected to the output electrode of the semiconductor switch element 31b without passing through the main current path. Therefore, the current path for controlling the drive of the semiconductor switch element 31b is not easily affected by the current fluctuations in the main current path, so the switching characteristics of the semiconductor switch element 31b can be improved. The following, regarding this point, based on Figure 3 and Figure 4 An example of the upper arm will be described in detail as a representative example.

[0063] Figure 3 is a circuit diagram of the upper arm of the semiconductor module 10. Figure 3 , an electrical connection structure of four semiconductor switch elements 31 a and four semiconductor elements 32 a mounted on one substrate 20 a is shown.

[0064] exist Figure 3 In the example shown, the semiconductor switch element 31a is a MOSFET. Figure 3 As shown, in the upper arm, the control terminal 82 is electrically connected to the source of each of the four semiconductor switch elements 31a via the electrode pattern 22a3 without passing through the main current path. Therefore, the main current path does not exist in the current path for controlling the drive of the semiconductor switch element 31a. Therefore, the current path for controlling the drive of the semiconductor switch element 31a is not easily affected by the current fluctuation of the main current path.

[0065] Here, the path length of the main current path is different for each semiconductor switch element 31a. Therefore, the main current path has a different parasitic inductance L for each semiconductor switch element 31a. As a result, when the main current fluctuates, a back electromotive force of different magnitude is generated in the parasitic inductance L of each semiconductor switch element 31a.

[0066] However, in the semiconductor module 10, as described above, there is no main current path in the current path for controlling the drive of the semiconductor switch element 31a, so the current path for controlling the drive of the semiconductor switch element 31a is not affected by the back electromotive force. As a result, it is not easy to cause the exchange and imbalance of current between the gates of the four semiconductor switch elements 31a electrically connected in parallel, so it is possible to prevent oscillation caused by repeated charging and discharging. In addition, by bringing the current path for controlling the drive of the semiconductor switch element 31a close to each other between the four semiconductor switch elements 31a, the loop formed by the current path can be reduced. As a result, the electromagnetic radiation noise from the peripheral circuit is not easy to cross-link, so the risk of false triggering can be reduced. Moreover, through the above-mentioned effect, there is also the advantage of not needing to use a wire to bridge the source of the semiconductor switch element 31a.

[0067] Figure 4 1 is a circuit diagram of an upper arm of a semiconductor module 10X having a configuration in which an auxiliary control terminal 82X is connected to a main current path. The semiconductor module 10X is configured similarly to the semiconductor module 10 except that the control terminal 82 is replaced with a control terminal 82X.

[0068] In the semiconductor module 10X, as Figure 4 As shown, in the upper arm, the control terminal 82X is electrically connected to the source of each of the four semiconductor switch elements 31a via the main current path. Therefore, the parasitic inductance L of the main current path exists in the current path for controlling the driving of the semiconductor switch element 31a.

[0069] Therefore, in the semiconductor module 10X, when a counter electromotive force is generated in the parasitic inductance L due to a change in the main current, Figure 4 As shown by the dotted arrows in , current exchange and imbalance occur between the gates of the four semiconductor switch elements 31a electrically connected in parallel. Therefore, in the semiconductor module 10X, the risk of false triggering and element destruction increases due to oscillation caused by repeated charge and discharge.

[0070] 1-2. Details of electrode pattern and lead wire

[0071] Figure 5 It is a side view for explaining the semiconductor switch element 31a and the semiconductor element 32a on the substrate 20a for the upper arm. Figure 6 2 is a top view showing the structure on the upper arm substrate 20a. Figure 5 In the figure, for the sake of ease of observation, the wires 91a, 92a, 93a, 94a, and 95 are omitted.

[0072] like Figure 5 and Figure 6As shown, the electrode pattern 22a2, the electrode pattern 22a1, the electrode pattern 22a3, and the electrode pattern 22a4 are arranged in this order in the X1 direction.

[0073] exist Figure 6 In the example shown, the electrode pattern 22a3 and the electrode pattern 22a4 are each in the shape of a strip extending in the direction along the Y axis. In addition, the two ends of the electrode pattern 22a2, the electrode pattern 22a1, the electrode pattern 22a3, and the electrode pattern 22a4 in the direction along the Y axis are aligned. Therefore, the lengths of the electrode pattern 22a2, the electrode pattern 22a1, the electrode pattern 22a3, and the electrode pattern 22a4 in the direction along the Y axis are equal to each other. In addition, any one of the electrode pattern 22a, the electrode pattern 22a1, the electrode pattern 22a3, and the electrode pattern 22a4 is arranged over the entire area of ​​any other in the direction along the Y axis.

[0074] In addition, the shapes of the electrode pattern 22a1, the electrode pattern 22a2, the electrode pattern 22a3, and the electrode pattern 22a4 are not limited to Figure 6 For example, the lengths of the electrode pattern 22a2, the electrode pattern 22a1, the electrode pattern 22a3, and the electrode pattern 22a4 in the direction along the Y axis may be different from each other.

[0075] The plurality of semiconductor switch elements 31a and the plurality of semiconductor elements 32a are bonded to the electrode pattern 22a1 using a conductive bonding material such as solder. Figure 6 In the example shown, four semiconductor switch elements 31a are arranged in the direction along the Y axis, and four semiconductor elements 32a are arranged in the direction along the Y axis at positions closer to the four semiconductor switch elements 31a in the X1 direction.

[0076] The semiconductor switch element 31a has a first surface F1 and a second surface F2. The first surface F1 is a surface of the semiconductor switch element 31a that is bonded to the electrode pattern 22a1. Figure 5 In the example shown, the first surface F1 faces the Z2 direction. Although not shown, as described above, an input electrode serving as a drain electrode or a collector electrode is provided on the first surface F1. The second surface F2 is a surface of the semiconductor switch element 31a facing the direction opposite to the first surface F1. Figure 6 As shown, the control electrode 311 , the control wiring 312 , and the main electrode 313 are provided on the second surface F2 .

[0077] The control electrode 311 is a gate electrode. A control voltage from a control circuit (not shown) is input to the control electrode 311. The control electrode 311 is made of a metal such as aluminum. Figure 6In the example shown, the control electrode 311 is arranged at the end of the second surface F2 in the Y1 direction or the Y2 direction. Figure 6 For example, the control electrode 311 may be arranged at the end portion of the second plane F2 in the X1 direction or the X2 direction.

[0078] The control electrode 311 is electrically connected to the electrode pattern 22a4 via the wire 93a. Here, the wire 93a has one end connected to the electrode pattern 22a4 and the other end connected to the control electrode 311. Figure 6 In the example shown, the conductive wire 93a is composed of one conductive wire for each control electrode 311. Alternatively, the number of conductive wires constituting the conductive wire 93a for each control electrode 311 may be two or more.

[0079] The control wiring 312 is a wiring connected to the control electrode 311. The control wiring 312 is, for example, a stack of a gate channel made of a semiconductor such as polysilicon doped with impurities and a gate metal layer provided on the gate channel and made of a metal such as aluminum. Figure 6 In the example shown, the control wiring 312 extends from the control electrode 311 in the Y1 direction or the Y2 direction. In addition, the top view shape of the control wiring 312 is determined by the number and shape of the regions RE described later, and is not limited to Figure 6 For example, the control wiring 312 may have a portion along the outer edge of the main electrode 313 in a plan view.

[0080] The main electrode 313 is a source electrode or an emitter electrode, and outputs a main current when the semiconductor switch element 31a is in the on state. The main electrode 313 is made of a metal such as aluminum, an aluminum alloy, titanium, or a titanium alloy. The main electrode 313 is divided by the control wiring 312 in a plan view and has a plurality of regions RE_1 and RE_2. Hereinafter, the region RE_1 and the region RE_2 are sometimes referred to as regions RE, respectively.

[0081] In addition, Figure 6 In the example, the main electrode 313 is divided into two regions RE, but the present invention is not limited to this form. For example, the main electrode 313 may have three or more regions RE. That is, the number of divisions of the main electrode 313 is not limited to two, but may be three or more.

[0082] exist Figure 6In the example shown, the region RE_1 and the region RE_2 are arranged in this order in the X1 direction. In addition, the region RE_1 and the region RE_2 each extend in the direction along the Y axis. Moreover, the top view shapes of the regions RE_1 and RE_2 are the same. The regions RE_1 and RE_2 each have a rectangular shape when viewed from above. In addition, the top view shapes of the regions RE_1 and RE_2 are not limited to Figure 6 In the example shown, for example, the top-view shapes of the regions RE_1 and RE_2 may be different from each other. In addition, the regions RE_1 and RE_2 may each extend in the direction along the X-axis.

[0083] Here, although not shown, the semiconductor switch element 31a includes a plurality of transistor units constituting transistors such as IGBTs or power MOSFETs corresponding to the plurality of regions RE. Each region RE is electrically connected to a source region or an emitter region of a corresponding transistor unit. Here, the plurality of regions RE are electrically insulated from each other on the second surface F2, and output the main current independently of each other. In addition, the gates of the plurality of transistor units are electrically connected to the control wiring 312. Thus, the gate is electrically connected to the control electrode 311 via the control wiring 312. In addition, in the semiconductor switch element 31a, in addition to the transistor unit, a diode unit such as FWD may also be provided for each region RE.

[0084] Each of the region RE_1 and the region RE_2 is electrically connected to the electrode pattern 22a2 via the wire 91a, and is electrically connected to the electrode pattern 22a3 via the wire 92a.

[0085] Here, the wire 91a has one end joined to the electrode pattern 22a2 and the other end joined to the region RE. Figure 6 In the example shown, the conductive wire 91a is composed of two conductive wires for each region RE. In addition, the number of conductive wires constituting the conductive wire 91a for each region RE may be one or three or more.

[0086] The wire 92a has one end joined to the electrode pattern 22a3 and the other end joined to the region RE. Figure 6 In the example shown, the conductive wire 92a is composed of two conductive wires for each region RE. In addition, the number of conductive wires constituting the conductive wire 92a for each region RE may be one or three or more.

[0087] Here, the middle of the wire 92a is bonded to the semiconductor element 32a by stitch bonding. The middle of the wire 92a refers to any position between one end and the other end of the wire 92a. Figure 5 As shown in FIG. 1 , the semiconductor element 32a has a third surface F3 and a fourth surface F4. The third surface F3 is a surface of the semiconductor element 32a that is bonded to the electrode pattern 22a1. Figure 5In the example shown, the third surface F3 faces the Z2 direction. Although not shown, as described above, an output electrode as a cathode electrode is provided on the third surface F3. The fourth surface F4 is a surface of the semiconductor element 32a that faces the direction opposite to the third surface F3. Although not shown, as described above, an input electrode as an anode electrode is provided on the fourth surface F4, and the middle of the wire 92a is joined.

[0088] Although in Figure 6 Although not shown in the figure, the electrode patterns 22a1 of the two substrates 20a are electrically connected to each other via the main terminals 71. Figure 6 In FIG. 1 , the area CTa for joining the main terminal 71 is shown with grid lines. Figure 6 In the example shown, the region CTa is located at the center of the electrode pattern 22a1 in the direction along the Y axis. Figure 6 In the example shown, for example, the position of the electrode pattern 22a1 may be shifted from the center in the direction along the Y axis.

[0089] In addition, although Figure 6 Although not shown in the figure, the electrode patterns 22a3 of the two substrates 20a are electrically connected to each other via the control terminal 82. Figure 6 In FIG. 8 , the area CTb for joining the control terminal 82 is shown with grid lines. Figure 6 In the example shown, the region CTb is located at the center of the electrode pattern 22a3 in the direction along the Y axis. Figure 6 In the example shown, for example, the position of the electrode pattern 22a3 may be shifted from the center in the direction along the Y axis.

[0090] In this embodiment, the electrode patterns 22a3 of the two substrates 20a are electrically connected to each other not only via the control terminal 82, but also via a wire 94a which is an example of a "fourth wire". The wire 94a has one end connected to the electrode pattern 22a3 of one substrate 20a of the two substrates 20a and the other end connected to the electrode pattern 22a3 of the other substrate 20a. Figure 6 In the example shown, the conductive wire 94a is composed of one conductive wire. In addition, the number of conductive wires constituting the conductive wire 94a may be two or more.

[0091] Moreover, although Figure 6 Although not shown in the figure, the electrode patterns 22a4 of the two substrates 20a are electrically connected to each other via the control terminal 81. Figure 6 In FIG. 8 , the area CTc for joining the control terminal 81 is shown with grid lines. Figure 6 In the example shown, the region CTc is located at the center of the electrode pattern 22a4 in the direction along the Y axis. Figure 6 In the example shown, for example, the position of the electrode pattern 22a4 may be shifted from the center in the direction along the Y axis.

[0092] The electrode pattern 22a2 of the substrate 20a is electrically connected to the electrode pattern 22b1 of the substrate 20b described later via the wire 95. The wire 95 has one end connected to the electrode pattern 22a2 of the substrate 20a and the other end connected to the electrode pattern 22b1 of the substrate 20b. Figure 6 In the example shown, the conductor 95 is composed of a plurality of conductors. In addition, the number and arrangement of the conductors constituting the conductor 95 are not limited to Figure 6 The examples shown are rather arbitrary.

[0093] Figure 7 2 is a top view showing the structure on the substrate 20b of the lower arm. Figure 7 As shown, the electrode pattern 22b2, the electrode pattern 22b1, the electrode pattern 22b3, and the electrode pattern 22b4 are arranged in this order in the X2 direction.

[0094] exist Figure 7 In the example shown, the electrode pattern 22b3 and the electrode pattern 22b4 are each in the shape of a long strip extending in the direction along the Y axis. In addition, the two ends of the electrode pattern 22b1, the electrode pattern 22b3 and the electrode pattern 22b4 in the direction along the Y axis are aligned. Therefore, the lengths of the electrode pattern 22b1, the electrode pattern 22b3 and the electrode pattern 22b4 in the direction along the Y axis are equal to each other. In addition, any one of the electrode pattern 22b1, the electrode pattern 22b3 and the electrode pattern 22b4 is arranged over the entire area of ​​any other in the direction along the Y axis. Moreover, the lengths of the electrode pattern 22b1, the electrode pattern 22b3 and the electrode pattern 22b4 in the direction along the Y axis are longer than the length of the electrode pattern 22b2 in the direction along the Y axis. Moreover, the ends of the electrode pattern 22b1 and the electrode pattern 22b2 in the X1 direction are aligned.

[0095] In addition, the shapes of the electrode pattern 22b1, the electrode pattern 22b2, the electrode pattern 22b3, and the electrode pattern 22b4 are not limited to Figure 7 For example, the lengths of the electrode pattern 22b1, the electrode pattern 22b3, and the electrode pattern 22b4 in the direction along the Y axis may be different from each other.

[0096] The plurality of semiconductor switch elements 31b and the plurality of semiconductor elements 32b are bonded to the electrode pattern 22b1 via a conductive bonding material such as solder. Figure 7In the example shown, four semiconductor switch elements 31b are arranged in the direction along the Y axis, and four semiconductor elements 32b are arranged in the direction along the Y axis at positions closer to the four semiconductor switch elements 31b in the X2 direction.

[0097] Although not shown in the drawings, the semiconductor switch element 31 b has a first surface F1 and a second surface F2 similarly to the semiconductor switch element 31 a .

[0098] The region RE_1 and the region RE_2 of the semiconductor switch element 31 b are each electrically connected to the electrode pattern 22 b 2 via the wire 91 b , and is electrically connected to the electrode pattern 22 b 3 via the wire 92 b .

[0099] Here, the wire 91b has one end connected to the electrode pattern 22b2 and the other end connected to the region RE. Thus, the electrode pattern 22b2 and each region RE are electrically connected via the wire 91b. Figure 7 In the example shown, the conductive wire 91b is composed of two conductive wires for each region RE. In addition, the number of conductive wires constituting the conductive wire 91b for each region RE may be one or three or more.

[0100] The wire 92b has one end connected to the electrode pattern 22b3 and the other end connected to the region RE. Thus, the electrode pattern 22b3 and each region RE are electrically connected via the wire 92b. Figure 7 In the example shown, the conductive wire 92b is composed of two conductive wires for each region RE. In addition, the number of conductive wires constituting the conductive wire 92b for each region RE may be one or three or more.

[0101] Here, the middle of the wire 92b is bonded to the semiconductor element 32b by stitch bonding. The middle of the wire 92b refers to any position between one end and the other end of the wire 92b. Although not shown, the semiconductor element 32b has a third surface F3 and a fourth surface F4 in the same manner as the semiconductor element 32a. The middle of the wire 92b is bonded to the fourth surface F4 of the semiconductor element 32b.

[0102] Although in Figure 7 Although not shown in the figure, the electrode patterns 22b1 of the two substrates 20b are electrically connected to each other via the main terminal 73. Figure 7 In FIG. 1 , the area CTd for engaging the main terminal 73 is shown with grid lines. Figure 7 In the example shown, the region CTd is located at the center of the electrode pattern 22b1 in the direction along the Y axis. Figure 7 In the example shown, for example, the position of the electrode pattern 22 b 1 may be shifted from the center in the direction along the Y axis.

[0103] In addition, although Figure 7 Although not shown in the figure, the electrode patterns 22b2 of the two substrates 20b are electrically connected to each other via the main terminal 72. Figure 7 In FIG. 1 , the area CTe for engaging the main terminal 72 is shown by grid lines. Figure 7 In the example shown, the region CTe is located at the center of the electrode pattern 22b1 in the direction along the Y axis. Figure 7 In the example shown, for example, the position may be deviated from the center of the electrode pattern 22 b 1 in the direction along the Y axis.

[0104] Moreover, although Figure 7 Although not shown in the figure, the electrode patterns 22b3 of the two substrates 20b are electrically connected to each other via the control terminal 84. Figure 7 In FIG. 8 , the area CTf for joining the control terminal 84 is shown with grid lines. Figure 7 In the example shown, the region CTf is located at the center of the electrode pattern 22b3 in the direction along the Y axis. Figure 7 In the example shown, for example, the position of the electrode pattern 22b3 may be offset from the center in the direction along the Y axis.

[0105] In this embodiment, the electrode patterns 22b3 of the two substrates 20b are electrically connected to each other not only via the control terminal 84, but also via a wire 94b as an example of a "fourth wire". The wire 94b has one end connected to the electrode pattern 22b3 of one substrate 20b of the two substrates 20b and the other end connected to the electrode pattern 22b3 of the other substrate 20b. Figure 7 In the example shown, the conductive wire 94b is composed of one conductive wire. In addition, the number of conductive wires constituting the conductive wire 94b may be two or more.

[0106] Moreover, although Figure 7 Although not shown in the figure, the electrode patterns 22b4 of the two substrates 20b are electrically connected to each other via the control terminal 83. Figure 7 In FIG. 8 , the area CTg for joining the control terminal 83 is shown with grid lines. Figure 7 In the example shown, the region CTg is located at the center of the electrode pattern 22b4 in the direction along the Y axis. Figure 7 In the example shown, for example, the position of the electrode pattern 22b4 may be offset from the center in the direction along the Y axis.

[0107] Figure 8 81, 82, 83, 84 is a top view showing a configuration example of the control terminals 81, 82, 83, and 84. Figure 8In the figure, for easy observation, the control terminals 81, 83 and the control terminals 82, 84 are displayed with grayscales of different depths.

[0108] like Figure 8 As shown, the control terminal 81 is connected to the region CTc of the electrode pattern 22a4 of each of the two substrates 20a. Similarly, the control terminal 82 is connected to the region CTb of the electrode pattern 22a3 of each of the two substrates 20a. The control terminal 83 is connected to the region CTg of the electrode pattern 22b4 of each of the two substrates 20b. The control terminal 84 is connected to the region CTf of the electrode pattern 22b3 of each of the two substrates 20b.

[0109] As described above, the semiconductor module 10 includes at least one substrate 20a and a plurality of semiconductor switch elements 31a in the upper arm. Similarly, the semiconductor module 10 includes at least one substrate 20b and a plurality of semiconductor switch elements 31b in the lower arm.

[0110] In the upper arm, the at least one substrate 20a has an electrode pattern 22a1 as an example of a "first electrode pattern", an electrode pattern 22a2 as an example of a "second electrode pattern", and an electrode pattern 22a3 as an example of a "third electrode pattern". When viewed from above, the electrode pattern 22a1 is located between the electrode pattern 22a2 and the electrode pattern 22a3. Similarly, in the lower arm, the at least one substrate 20b has an electrode pattern 22b1 as an example of a "first electrode pattern", an electrode pattern 22b2 as an example of a "second electrode pattern", and an electrode pattern 22b3 as an example of a "third electrode pattern". When viewed from above, the electrode pattern 22b1 is located between the electrode pattern 22b2 and the electrode pattern 22b3.

[0111] In the upper arm, each of the plurality of semiconductor switch elements 31a has a first surface F1 joined to the electrode pattern 22a1 and a second surface F2 facing in a direction opposite to the first surface F1. Similarly, in the lower arm, each of the plurality of semiconductor switch elements 31b has a first surface F1 joined to the electrode pattern 22b1 and a second surface F2 facing in a direction opposite to the first surface F1. A control electrode 311, a control wiring 312 connected to the control electrode 311, and a main electrode 313 having a plurality of regions RE divided by the control wiring 312 are provided on the second surface F2.

[0112] On this basis, in the upper arm, each of the plurality of regions RE is electrically connected to the electrode pattern 22a2 via a conductor 91a as an example of the “first conductor”, and is electrically connected to the electrode pattern 22a3 via a conductor 92a as an example of the “second conductor”. Moreover, the electrode pattern 22a2 is a pattern for the main current. The electrode pattern 22a3 is used as an auxiliary pattern for control. Similarly, in the lower arm, each of the plurality of regions RE is electrically connected to the electrode pattern 22b2 via a conductor 91b as an example of the “first conductor”, and is electrically connected to the electrode pattern 22b3 via a conductor 92b as an example of the “second conductor”. Moreover, the electrode pattern 22b2 is a pattern for the main current. The electrode pattern 22b3 is used as an auxiliary pattern for control.

[0113] In the above semiconductor module 10, the electrode patterns 22a3 and 22b3 electrically connected to the main electrode 313 by a path independent of the main current path are used as auxiliary patterns for control, so that the degradation of the switching characteristics caused by the deviation of the parasitic inductance L of the main current path and the back electromotive force can be reduced. In addition, the plurality of regions RE of the main electrode 313 are electrically connected to the electrode patterns 22a3 and 22b3 via the wires 92a and 92b, respectively, so that the imbalance of the current in the main electrode 313 can be reduced. As a result, the switching characteristics can be improved.

[0114] As described above, the semiconductor module 10 of the present embodiment further includes control terminals 82 and 84 as an example of a "first control terminal". The control terminal 82 is joined to the electrode pattern 22a3. Therefore, compared with a structure in which the control terminal 82 is electrically connected via a pattern other than the electrode pattern 22a3 on the substrate 20a, it is easy to equalize the current of the main electrode 313 between the plurality of semiconductor switch elements 31a. This advantage contributes to improving the switching characteristics. In addition, in the structure in which the control terminal 82 is joined to the electrode pattern 22a3, it is also easy to simplify the wiring for the control terminal 82. In addition, the control terminal 84 is joined to the electrode pattern 22b3, so that the same advantage as the case in which the control terminal 82 is joined to the electrode pattern 22a3 can be obtained. Moreover, by using the control terminals 82 and 84, the area of ​​the wiring on the substrates 20a and 20b can be reduced, and as a result, the area required for mounting semiconductor chips on the substrates 20a and 20b can be easily ensured.

[0115] In addition, as described above, the electrode pattern 22a3 is in the shape of an elongated strip. Moreover, the control terminal 82 is joined to a portion of the electrode pattern 22a3 that is closer to the center than the end portion in the length direction. That is, the distance between the joining portion of the electrode pattern 22a3 and the control terminal 82 and the center in the length direction of the electrode pattern 22a3 is smaller than the distance between the joining portion of the electrode pattern 22a3 and the control terminal 82 and the end portion in the length direction of the electrode pattern 22a3. Therefore, it has the advantage of easily reducing the imbalance of the current in the electrode pattern 22a3. This advantage helps to improve the switching characteristics. Similarly, the electrode pattern 22b3 is in the shape of an elongated strip, and the control terminal 84 is joined to a portion of the electrode pattern 22b3 that is closer to the center than the end portion in the length direction, so the imbalance of the current in the electrode pattern 22b3 can also be reduced.

[0116] Moreover, as described above, the semiconductor module 10 further includes control terminals 81, 83 as an example of a "second control terminal". The at least one substrate 20a further includes an electrode pattern 22a4 as an example of a "fourth electrode pattern". The electrode pattern 22a4 is electrically connected to the control electrode 311 via a wire 93a as an example of a "third wire". Moreover, the control terminal 81 is joined to the electrode pattern 22a4. In addition, the electrode pattern 22a3 is located between the electrode pattern 22a1 and the electrode pattern 22a4 when viewed from above. Therefore, the electrode pattern 22a3 and the electrode pattern 22a4 can be respectively separated from the electrode pattern 22a2 for the main current. As a result, the electrode pattern 22a3 and the electrode pattern 22a4 can be less susceptible to the influence of the reactor caused by the change of the main current, so that the imbalance of the current can be reduced and false triggering can be prevented. In addition, by making the electrode pattern 22a3 closer to the electrode pattern 22a1 than the electrode pattern 22a4, even if the number of wires constituting the wire 92a is large, the wire 93a can be easily formed, so that it is easy to install. Moreover, compared with the structure in which the electrode pattern 22a4 is located between the electrode pattern 22a3 and the electrode pattern 22a1 in a plan view, the length of the wire 92a can be shortened. As a result, the imbalance of the current between the main electrodes 313 of the plurality of semiconductor switch elements 31a can be reduced.

[0117] Similarly, the at least one substrate 20b also has an electrode pattern 22b4 as an example of a "fourth electrode pattern". The electrode pattern 22b4 is electrically connected to the control electrode 311 via a wire 93b as an example of a "third wire". Moreover, the control terminal 83 is joined to the electrode pattern 22b4. In addition, the electrode pattern 22b3 is located between the electrode pattern 22b1 and the electrode pattern 22b4 when viewed from above. Therefore, the electrode pattern 22b3 and the electrode pattern 22b4 can be respectively separated from the electrode pattern 22b2 for the main current. As a result, the electrode pattern 22b3 and the electrode pattern 22b4 can be less susceptible to the influence of the reactor caused by the fluctuation of the main current, so the imbalance of the current can be reduced and false triggering can be prevented. In addition, by making the electrode pattern 22b3 closer to the electrode pattern 22b1 than the electrode pattern 22b4, the wire 93b can be easily formed even if the number of wires constituting the wire 92b is large, so it is easy to install. Furthermore, the length of the wire 92b can be shortened compared to a structure in which the electrode pattern 22b4 is located between the electrode pattern 22b3 and the electrode pattern 22b1 in a plan view. As a result, the imbalance of the current between the main electrodes 313 of the plurality of semiconductor switch elements 31b can be reduced.

[0118] In addition, as described above, the at least one substrate 20a includes a plurality of substrates 20a having an electrode pattern 22a1, an electrode pattern 22a2, and an electrode pattern 22a3. The control terminal 82 is connected to the electrode pattern 22a3 of each of the plurality of substrates 20a. Therefore, the current imbalance between the electrode patterns 22a3 of the plurality of substrates 20a can be reduced.

[0119] Similarly, the at least one substrate 20b includes a plurality of substrates 20b having an electrode pattern 22b1, an electrode pattern 22b2, and an electrode pattern 22b3. The control terminal 84 is connected to the electrode pattern 22b3 of each of the plurality of substrates 20b. Therefore, the current imbalance between the electrode patterns 22b3 of the plurality of substrates 20b can be reduced.

[0120] Furthermore, as described above, the semiconductor module 10 further includes the conductors 94a and 94b as an example of the "fourth conductor". The conductor 94a electrically connects the electrode patterns 22a3 of the plurality of substrates 20a. Therefore, the imbalance of the current between the electrode patterns 22a3 of the plurality of substrates 20a can be reduced. Similarly, the conductor 94b electrically connects the electrode patterns 22b3 of the plurality of substrates 20b. Therefore, the imbalance of the current between the electrode patterns 22b3 of the plurality of substrates 20b can be reduced.

[0121] In addition, as described above, the plurality of semiconductor switch elements 31a are electrically connected in parallel. Similarly, the plurality of semiconductor switch elements 31b are electrically connected in parallel. In this case, the above-mentioned effect of reducing the degradation of the switching characteristics caused by the deviation of the parasitic inductance L of the main current path and the back electromotive force, etc., is significantly obtained.

[0122] Furthermore, as described above, the wire 92a is composed of a plurality of wires for each of the plurality of regions RE. Therefore, the current imbalance can be reduced well in the main electrode 313 of the semiconductor switch element 31a. Similarly, the wire 92b is composed of a plurality of wires for each of the plurality of regions RE. Therefore, the current imbalance can be reduced well in the main electrode 313 of the semiconductor switch element 31b.

[0123] In addition, as described above, the semiconductor module 10 further includes a plurality of semiconductor elements 32a in the upper arm. Each of the plurality of semiconductor elements 32a has a third surface F3 joined to the electrode pattern 22a1 and a fourth surface F4 facing in the opposite direction to the third surface F3. Moreover, the middle of the wire 92a is joined to the fourth surface F4. Therefore, even in a structure having a semiconductor element 32a independent of the semiconductor switch element 31a, the imbalance of the current can be appropriately reduced in the main electrode 313 of the semiconductor switch element 31a.

[0124] Similarly, the semiconductor module 10 also includes a plurality of semiconductor elements 32b in the lower arm. Each of the plurality of semiconductor elements 32b has a third surface F3 joined to the electrode pattern 22b1 and a fourth surface F4 facing in the opposite direction to the third surface F3. Moreover, the middle of the wire 92b is joined to the fourth surface F4. Therefore, even in a structure having a semiconductor element 32b independent of the semiconductor switch element 31b, the imbalance of the current can be appropriately reduced in the main electrode 313 of the semiconductor switch element 31b.

[0125] 2. Modifications

[0126] The present disclosure is not limited to the above-described embodiment, and various modifications described below are possible. In addition, the embodiment and each modification example may be appropriately combined.

[0127] 2-1. Modification 1

[0128] Fig. 9 1 is a plan view showing the structure on the substrate 20 a for the upper arm in Modification Example 1. Fig.10 1 is a plan view showing the structure on the substrate 20 b for the lower arm in Modification 1.

[0129] Modification 1 is the same as the above-described embodiment, except that the arrangement of the electrode pattern 22a3 and the electrode pattern 22a4 are opposite, and the arrangement of the electrode pattern 22b3 and the electrode pattern 22b4 are opposite.

[0130] By using the above modification example 1, the switching characteristics can be improved in the same manner as in the above-mentioned embodiment. In modification example 1, as described above, the electrode pattern 22a4 as an example of the "fourth electrode pattern" is located between the electrode pattern 22a1 as an example of the "first electrode pattern" and the electrode pattern 22a3 as an example of the "third electrode pattern" when viewed from above. Therefore, the electrode pattern 22a3 and the electrode pattern 22a4 can be respectively separated from the electrode pattern 22a2 for the main current. As a result, the electrode pattern 22a3 and the electrode pattern 22a4 can be less susceptible to the influence of the reactor caused by the fluctuation of the main current, so the current imbalance can be reduced and false triggering can be prevented. In addition, by making the electrode pattern 22a3 farther away from the electrode pattern 22a1 than the electrode pattern 22a4, even if the diameter of the wire constituting the wire 92a exceeds 400μm, the wire 92a can be easily joined to the electrode pattern 22a3. Furthermore, since the region between the electrode pattern 22a1 and the electrode pattern 22a3 is effectively utilized by the electrode pattern 22a4, the substrate 20a can be miniaturized.

[0131] Similarly, as described above, the electrode pattern 22b4 as an example of the "fourth electrode pattern" is located between the electrode pattern 22b1 as an example of the "first electrode pattern" and the electrode pattern 22b3 as an example of the "third electrode pattern" when viewed from above. Therefore, the electrode pattern 22b3 and the electrode pattern 22b4 can be respectively separated from the electrode pattern 22b2 for the main current. As a result, the electrode pattern 22b3 and the electrode pattern 22b4 can be less susceptible to the influence of the reactor caused by the fluctuation of the main current, so that the current imbalance can be reduced and false triggering can be prevented. In addition, by making the electrode pattern 22b3 farther away from the electrode pattern 22b1 than the electrode pattern 22b4, the wire 92b can be easily joined to the electrode pattern 22b3 even if the diameter of the wire constituting the wire 92b exceeds 400μm. Moreover, the area between the electrode pattern 22b1 and the electrode pattern 22b3 is effectively used by the electrode pattern 22b4, so that the miniaturization of the substrate 20b can be achieved.

[0132] 2-2. Modification 2

[0133] In the above-mentioned embodiment, the number of semiconductor switch elements 31a or semiconductor elements 32a mounted on the substrate 20a is four, but the number may be more than one and less than three, or more than five. Similarly, the number of semiconductor switch elements 31b or semiconductor elements 32b mounted on the substrate 20b is four, but the number may be more than one and less than three, or more than five.

[0134] 2-3. Modification 3

[0135] In the above-mentioned embodiment, the number of substrates 20a or substrates 20b is two, but the number may be one or more than three. In addition, the substrate 20a and the substrate 20b may be integrally formed. In addition, in the above-mentioned embodiment, the structures of the substrate 20a and the substrate 20b are different from each other, but the present invention is not limited thereto, and the structures of the substrate 20a and the substrate 20b may be the same as each other.

[0136] 2-4. Modification 4

[0137] In the above-mentioned embodiments, the heat dissipation layers 23a and 23b of the substrates 20a and 20b are provided with the base 40 separately, but the present invention is not limited to this structure. For example, the base 40 may also be used as the heat dissipation layers 23a and 23b. In this case, it can also be said that the base 40 is a part of the substrates 20a and 20b.

[0138] Description of Reference Numerals

[0139] 10, semiconductor module; 10X, semiconductor module; 20a, substrate; 20b, substrate; 21a, insulating plate; 21b, insulating plate; 22a, wiring layer; 22a1, electrode pattern (first electrode pattern); 22a2, electrode pattern (second electrode pattern); 22a3, electrode pattern (third electrode pattern); 22a4, electrode pattern (fourth electrode pattern); 22b, wiring layer; 22b1, electrode pattern (first electrode pattern); 22 b2, electrode pattern (second electrode pattern); 22b3, electrode pattern (third electrode pattern); 22b4, electrode pattern (fourth electrode pattern); 23a, heat dissipation layer; 23b, heat dissipation layer; 31a, semiconductor switch element; 31b, semiconductor switch element; 32a, semiconductor element; 32b, semiconductor element; 40, base; 41, mounting hole; 50, housing; 60, cover; 71, main terminal; 72, main terminal; 73, main terminal; 81, control terminal; 81a, terminal portion; 82, control terminal; 82X, control terminal; 82a, terminal portion; 83, control terminal; 83a, terminal portion; 84, control terminal; 84a, terminal portion; 91a, wire (first wire); 91b, wire (first wire); 92a, wire (second wire); 92b, wire (second wire); 93a, wire (third wire); 93b, wire (third wire); 94a, wire (4th wire); 94b, wire (4th wire); 95, wire; 311, control electrode; 312, control wiring; 313, main electrode; CTa, region; CTb, region; CTc, region; CTd, region; CTe, region; CTf, region; CTg, region; F1, 1st surface; F2, 2nd surface; F3, 3rd surface; F4, 4th surface; L, parasitic inductance; RE, region; RE_1; region, RE_2, region.

Claims

1. A semiconductor module, wherein: The semiconductor module has: at least one substrate having a first electrode pattern, a second electrode pattern and a third electrode pattern, wherein the first electrode pattern is located between the second electrode pattern and the third electrode pattern in a plan view; as well as a plurality of semiconductor switch elements having a first surface bonded to the first electrode pattern and a second surface facing in a direction opposite to the first surface, The second surface is provided with a control electrode, a control wiring connected to the control electrode, and a main electrode having a plurality of regions divided by the control wiring. Each of the plurality of regions is electrically connected to the second electrode pattern via a first conductive wire, and is electrically connected to the third electrode pattern via a second conductive wire, The second electrode pattern is a pattern for main current, The third electrode pattern is used as an auxiliary pattern for control.

2. The semiconductor module according to claim 1, wherein: The semiconductor module further includes a first control terminal connected to the third electrode pattern.

3. The semiconductor module according to claim 2, wherein: The third electrode pattern is in the shape of a long strip. A distance between a junction between the third electrode pattern and the first control terminal and a center in a longitudinal direction of the third electrode pattern is smaller than a distance between a junction between the third electrode pattern and the first control terminal and an end in the longitudinal direction of the third electrode pattern.

4. The semiconductor module according to claim 2, wherein: The semiconductor module further comprises a second control terminal. The at least one substrate further comprises a fourth electrode pattern, and the fourth electrode pattern is electrically connected to the control electrode via a third wire. The second control terminal is connected to the fourth electrode pattern. The third electrode pattern is located between the first electrode pattern and the fourth electrode pattern in a plan view.

5. The semiconductor module according to claim 2, wherein: The semiconductor module further comprises a second control terminal. The at least one substrate further comprises a fourth electrode pattern, and the fourth electrode pattern is electrically connected to the control electrode via a third wire. The second control terminal is connected to the fourth electrode pattern. The fourth electrode pattern is located between the first electrode pattern and the third electrode pattern in a plan view.

6. The semiconductor module according to claim 2, wherein: The at least one substrate includes a plurality of substrates having the first electrode pattern, the second electrode pattern, and the third electrode pattern, The first control terminal is joined to the third electrode pattern of each of the plurality of substrates.

7. The semiconductor module according to claim 6, wherein: The semiconductor module further includes a fourth conductive wire that electrically connects the third electrode patterns of the plurality of substrates to each other.

8. The semiconductor module according to claim 1, wherein: The plurality of semiconductor switching elements are electrically connected in parallel.

9. The semiconductor module according to claim 1, wherein: The second conductive wire is composed of a plurality of conductive wires for each of the plurality of regions.

10. The semiconductor module according to claim 1, wherein The semiconductor module further includes a plurality of semiconductor elements, each of which has a third surface bonded to the first electrode pattern and a fourth surface facing in a direction opposite to the third surface. The middle of the second conductive wire is bonded to the fourth surface.

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