Back contact battery, manufacturing method thereof and photovoltaic module

Abstract

The invention relates to a back contact battery, a manufacturing method thereof and a photovoltaic module. The back contact cell includes: a substrate; the first passivation contact structure and the second passivation contact structure are arranged in the first region and the second region respectively, the first passivation contact structure comprises a P-type first polycrystalline silicon doped conductive layer, and the second passivation contact structure comprises an N-type second polycrystalline silicon doped conductive layer; the first electrode and the second electrode are electrically connected to the first polycrystalline silicon doped conductive layer and the second polycrystalline silicon doped conductive layer respectively; the first area is provided with a suede structure, and at least part of the orthographic projection of the first electrode on the first surface is located in the setting area of the suede structure; or the second area is provided with a suede structure, and at least part of the orthographic projection of the second electrode on the first surface is located in the setting area of the suede structure. According to the back contact battery and the manufacturing method thereof, the contact loss of the photovoltaic module is relatively small, and the efficiency is relatively high.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a back contact cell and a manufacturing method thereof, and a photovoltaic module. Background Art

[0002] With the development of the photovoltaic industry, TOPCon cells have gradually approached theoretical efficiency, and various manufacturers have begun to develop the next generation of cells that are more efficient than TOPCon cells. Among them, TBC cells stand out with many advantages such as high conversion efficiency and high compatibility with TOPCon cell production lines. The current TBC cells use a stacked structure of tunnel oxide layer and doped polysilicon in both the N and P regions on the back, which makes the back of the TBC cells have excellent passivation performance. However, the existing TBC cells still have problems with large contact loss and low efficiency. Summary of the invention

[0003] Based on this, it is necessary to provide a back-contact cell with less contact loss and higher efficiency, a method for manufacturing the same, and a photovoltaic module.

[0004] An embodiment of the present application provides a back contact battery, comprising:

[0005] A substrate, comprising a first surface, wherein the first surface comprises a first region, a second region, and an isolation region isolated between the first region and the second region;

[0006] A first passivation contact structure and a second passivation contact structure are respectively disposed in the first region and the second region, an isolation groove extending to the isolation region is disposed between adjacent first passivation contact structures and second passivation contact structures, the first passivation contact structure includes a P-type first polysilicon doped conductive layer, and the second passivation contact structure includes an N-type second polysilicon doped conductive layer; and

[0007] A first electrode and a second electrode are electrically connected to the first polysilicon doped conductive layer and the second polysilicon doped conductive layer, respectively;

[0008] The first region is configured with a textured structure, and at least a portion of an orthographic projection of the first electrode on the first surface is located in a setting area of ​​the textured structure; or

[0009] The second region is formed with a texture structure, and at least part of the orthographic projection of the second electrode on the first surface is located within the arrangement region of the texture structure.

[0010] In one embodiment, the velvet structure includes a plurality of pyramid-shaped protrusions, the height of the protrusions is 0.5 micrometers to 3 micrometers; and / or the side length of the bottom surface of the protrusions is 0.5 micrometers to 3 micrometers.

[0011] In one embodiment, when the first region is constructed with a velvet structure, all of the orthographic projections of the first electrode on the first surface are located in the setting area of ​​the velvet structure;

[0012] When the second region is configured with a textured structure, the orthographic projection of the second electrode on the first surface is entirely located within the arrangement region of the textured structure.

[0013] In one embodiment, when the first region is entirely constructed as a velvet structure, a ratio of a size of the first electrode along a width direction of the first electrode to a size of the first region along a width direction of the first electrode is 1 / 2-2 / 3;

[0014] When the second region is entirely constructed as a suede structure, the ratio of the size of the second electrode along the width direction of the second electrode to the size of the second region along the width direction of the second electrode is 1 / 2-2 / 3.

[0015] In one embodiment, when the first region is constructed with a suede structure, the area of ​​the first region accounts for 50%-80% of the area of ​​the first surface;

[0016] When the second region is constructed with a suede structure, the area of ​​the second region accounts for 50%-80% of the area of ​​the first surface.

[0017] The present application also provides a method for manufacturing a back contact battery, comprising:

[0018] A first tunnel oxide layer and a first P-type polysilicon doped conductive layer are formed in a first region of a first surface of the substrate, and are stacked on each other; the first surface is configured as a polished surface or a velvet surface, and the first surface further includes a second region and an isolation region isolated between the first region and the second region;

[0019] When the first surface is configured as a polished surface, the second area is formed into a velvet surface; when the first surface is configured as a velvet surface, the second area is polished;

[0020] Forming a second tunnel oxide layer and an N-type second polysilicon doped conductive layer stacked on each other in the second region, and forming an isolation groove extending to the isolation region between the first polysilicon doped conductive layer and the second polysilicon doped conductive layer;

[0021] A first electrode and a second electrode are prepared, and the first electrode and the second electrode are electrically connected to the first polysilicon doped conductive layer and the second polysilicon doped conductive layer respectively.

[0022] In one embodiment, the step of forming a first tunneling oxide layer and a first P-type polysilicon doped conductive layer stacked on each other in a first region of a first surface of a substrate specifically comprises:

[0023] A first tunneling material layer, a first doped polysilicon material layer and a first oxide material layer are sequentially stacked on each surface of the substrate;

[0024] The second region and the isolation region, the side surface of the substrate and the first oxide material layer corresponding to the second surface are removed, and the first oxide material layer corresponding to the first region is retained, the second surface is arranged opposite to the first surface, and the side surface is adjacent to the first surface and the second surface;

[0025] Using the first oxide material layer corresponding to the first region as a mask, the first tunneling material layer and the first doped polysilicon material layer covering the second region and the isolation region, the side and the second surface are removed to form a first tunneling oxide layer and a first polysilicon doped conductive layer in the first region.

[0026] In one embodiment, the step of forming the second region into a velvet surface specifically includes forming the second region into a velvet surface using a first alkaline solution;

[0027] The step of polishing the second area specifically includes polishing the second area using a second alkaline solution.

[0028] In one embodiment, in the step of forming the second area into a velvet surface using the first alkaline solution, the isolation area and the second surface are also velvet-formed;

[0029] In the step of polishing the second region, the isolation region and the second surface are also polished.

[0030] In one embodiment, the step of forming a second tunneling oxide layer and an N-type second polysilicon doped conductive layer stacked on each other in the second region specifically includes:

[0031] A second tunneling material layer, a second doped polysilicon material layer and a second oxide material layer are sequentially stacked on each surface of the substrate;

[0032] removing the second oxide material layer corresponding to the first region and the isolation region, the side surface and the second surface of the substrate, and retaining the second oxide material layer corresponding to the second region;

[0033] Using the second oxide material layer corresponding to the second region as a mask, the second tunneling material layer and the second doped polysilicon material layer covering the first region and the isolation region, the side and the second surface are removed to form a second tunneling oxide layer and a second polysilicon doped conductive layer in the second region.

[0034] In one embodiment, the step of removing the second oxide material layer corresponding to the first region and the isolation region, the side surface and the second surface of the substrate, and retaining the second oxide material layer corresponding to the second region specifically includes:

[0035] Laser film opening to remove the corresponding second oxide material layer on the first area and the isolation area;

[0036] The second oxide material layer corresponding to the side surface and the second surface of the substrate is removed by using HF.

[0037] In one embodiment, the step of removing the second tunneling material layer and the second doped polysilicon material layer covering the first region and the isolation region, the side surface and the second surface by using the second oxide material layer corresponding to the second region as a mask comprises:

[0038] The second doped polysilicon material layer and the second tunneling material layer covering the second surface and the side surface, the first region and the isolation region are removed by using a third alkaline solution, and the isolation region is textured.

[0039] In one embodiment, the steps of preparing the first electrode and the second electrode specifically include:

[0040] A first passivation layer and a first anti-reflection layer are sequentially stacked on the first polysilicon doped conductive layer and the second polysilicon doped conductive layer on a side facing away from the substrate;

[0041] A first electrode and a second electrode are respectively formed on the first anti-reflection layer, wherein the first electrode is electrically connected to the first polysilicon doped conductive layer, and the second electrode is electrically connected to the second polysilicon doped conductive layer.

[0042] The present application also provides a back-contact battery, which is manufactured using the above-mentioned back-contact battery manufacturing method.

[0043] An embodiment of the present application further provides a photovoltaic module, comprising at least one battery string, wherein the battery string comprises at least two of the above-mentioned back-contact batteries.

[0044] Beneficial effects of the above-mentioned back contact cell and its manufacturing method, and photovoltaic module:

[0045] By constructing a velvet structure in the first region, the surface of the first polysilicon doped conductive layer also has an uneven microstructure at the position corresponding to the velvet structure. Since at least part of the positive projection of the first electrode on the first surface is located in the setting area of ​​the velvet structure, the first electrode and the part of the microstructure of the first polysilicon doped conductive layer have a contact portion, so that the contact area between the first electrode and the first polysilicon doped conductive layer is increased, the contact is better, and the efficiency of the back contact battery is higher. In addition, since the velvet structure is constructed in the first region, compared with the polished surface, the proportion of light emitted from the back contact battery can also be reduced to further improve the battery efficiency.

[0046] The second region is provided with a velvet structure, so that the surface of the second polysilicon doped conductive layer also has an uneven microstructure at the position corresponding to the velvet structure. Since at least part of the orthographic projection of the second electrode on the first surface is located in the setting area of ​​the velvet structure, the second electrode has a contact portion with the microstructure of the second polysilicon doped conductive layer, so that the contact area between the second electrode and the second polysilicon doped conductive layer is increased, the contact is better, and the efficiency of the back contact battery is higher. In addition, since the velvet structure is constructed in the second region, compared with the polished surface, the proportion of light emitted from the back contact battery can also be reduced to further improve the battery efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] FIG1 is a schematic diagram of the structure of a back contact battery provided in an embodiment of the present application;

[0048] FIG2 is a schematic diagram of another structure of a back contact battery provided in an embodiment of the present application;

[0049] FIG3 is a schematic diagram of a process for manufacturing a back contact battery provided in an embodiment of the present application;

[0050] 4 is a schematic diagram of forming a first tunneling material layer, a first doped polysilicon material layer and a first oxide material layer on a substrate in a method for manufacturing a back contact cell provided in an embodiment of the present application;

[0051] FIG5 is a schematic diagram of partially removing the first oxide material layer in the method for manufacturing a back contact battery provided in an embodiment of the present application;

[0052] FIG6 is a schematic diagram of the first texturing step in the method for manufacturing a back contact battery provided in an embodiment of the present application;

[0053] 7 is a schematic diagram of forming a second tunneling material layer, a second doped polysilicon material layer, and a second oxide material layer in a method for manufacturing a back contact cell provided in an embodiment of the present application;

[0054] FIG8 is a schematic diagram of partially removing the second oxide material layer in the method for manufacturing a back contact battery provided in an embodiment of the present application;

[0055] FIG. 9 is a schematic diagram of the second texturing step in the method for manufacturing a back contact battery provided in an embodiment of the present application.

[0056] 10 is a schematic diagram of forming a first polysilicon doped conductive layer and a first tunnel oxide layer in a method for manufacturing a back contact cell provided by another embodiment of the present application;

[0057] 11 is a schematic diagram of forming a second tunneling oxide layer and a second polysilicon doped conductive layer in a method for manufacturing a back contact cell provided in another embodiment of the present application;

[0058] FIG. 12 is a schematic diagram of a back-contact battery formed by a method for manufacturing a back-contact battery provided in another embodiment of the present application.

[0059] Description of Figure Numbers:

[0060] 100. Back contact battery;

[0061] 10. substrate; 11. velvet structure; 20. first passivation contact structure; 30. second passivation contact structure;

[0062] 40. Isolation trough;

[0063] 50. a first tunneling oxide layer; 51. a first polysilicon doped conductive layer;

[0064] 60. a second tunneling oxide layer; 61. a second polysilicon doped conductive layer;

[0065] 71, first passivation layer; 710, first anti-reflection layer; 72, second passivation layer; 720, second anti-reflection layer;

[0066] 801, a first tunneling material layer; 802, a second tunneling material layer; 81, a first doped polysilicon material layer; 810, a first oxide material layer; 82, a second doped polysilicon material layer; 820, a second oxide material layer;

[0067] 91. a first electrode; 92. a second electrode;

[0068] F, first side; S, second side; C, side; Y, first zone; E, second zone; G, isolation zone. DETAILED DESCRIPTION

[0069] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0070] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0071] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0072] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0073] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0074] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and are not intended to be the only implementation method.

[0075] The back contact battery of the embodiment of the present application is described below in conjunction with the accompanying drawings. In the present application, the back contact battery is a TBC battery as an example for description, and the back contact battery can also be other types, and the back contact battery is other types. The case is similar and will not be repeated here.

[0076] FIG1 is a schematic diagram of the structure of a back-contact battery provided in an embodiment of the present application; FIG2 is a schematic diagram of another structure of a back-contact battery provided in an embodiment of the present application.

[0077] The back contact battery 100 provided in the embodiment of the present application can be manufactured using the back contact battery manufacturing method described below.

[0078] 1 and 2 , a back-contact battery 100 according to an embodiment of the present application includes a substrate 10 , a first passivation contact structure 20 and a second passivation contact structure 30 , and a first electrode 91 and a second electrode 92 .

[0079] The substrate 10 includes a first surface F, and the first surface F includes a first region Y, a second region E, and an isolation region G isolated between the first region Y and the second region E. Here, the first region Y and the second region E have opposite conductivity types. In the embodiment of the present application, the first region Y is a P region and the second region E is an N region for illustration.

[0080] The first passivation contact structure 20 and the second passivation contact structure 30 are respectively arranged in the first region Y and the second region E. An isolation groove 40 extending to the isolation region G and having an insulating isolation function is arranged between adjacent first passivation contact structures 20 and second passivation contact structures 30. The first passivation contact structure 20 includes a P-type first polysilicon doped conductive layer 51, and the second passivation contact structure 30 includes an N-type second polysilicon doped conductive layer 61. It should be noted that in the back contact battery 100, the first passivation contact structure 20 and the second passivation contact structure can be alternately arranged along a preset direction. In FIG1 , only two first passivation contact structures 20 and one second passivation contact structure 30 are illustrated. The structural arrangement of the remaining first passivation contact structures 20 and second passivation contact structures 30 is similar to this, and will not be repeated here.

[0081] The first electrode 91 and the second electrode 92 are electrically connected to the first polysilicon doped conductive layer 51 and the second polysilicon doped conductive layer 61 , respectively.

[0082] 1 , the second region E is provided with a velvet structure 11, and at least part of the orthographic projection of the second electrode 92 on the first surface F is located within the region where the velvet structure 11 is provided. At this time, the first region Y is not provided with a velvet structure 11, that is, the first region Y may be a polished surface.

[0083] In the example of FIG. 2 , as another possible implementation, the first region Y is configured with a velvet structure 11, and at least part of the orthographic projection of the first electrode 91 on the first surface F is located within the setting area of ​​the velvet structure 11. At this time, the velvet structure 11 is not provided in the second region E, that is, the second region E may be a polished surface.

[0084] The first region Y is constructed with a velvet structure, so that the surface of the first polysilicon doped conductive layer 51, corresponding to the position of the velvet structure 11, also has an uneven microstructure. Since at least part of the positive projection of the first electrode 91 on the first surface F is located in the setting area of ​​the velvet structure 11, the first electrode 91 has a contact portion with the microstructure of the first polysilicon doped conductive layer 51, so that the contact area between the first electrode 91 and the first polysilicon doped conductive layer is increased, the contact is better, and the efficiency of the back contact battery is higher. In addition, since the velvet structure is constructed in the first region Y, compared with the polished surface, the proportion of light emitted from the back contact battery can also be reduced to further improve the battery efficiency.

[0085] The second region E is constructed with a velvet structure, so that the surface of the second polysilicon doped conductive layer 61, corresponding to the position of the velvet structure 11, also has an uneven microstructure. Since at least part of the positive projection of the second electrode 92 on the first surface F is located in the setting area of ​​the velvet structure 11, the second electrode 92 has a contact portion with the microstructure of the second polysilicon doped conductive layer 61, so that the contact area between the second electrode 92 and the second polysilicon doped conductive layer 61 is increased, the contact is better, and the efficiency of the back contact battery is higher. In addition, since the velvet structure is constructed in the second region E, compared with the polished surface, the proportion of light emitted from the back contact battery can also be reduced to further improve the battery efficiency.

[0086] It can be understood that in the embodiment of the present application, when one of the first area Y and the second area E is constructed as a suede structure, the other can be a polished surface to avoid affecting the passivation performance of the first surface F.

[0087] In the embodiment of the present application, the velvet structure 11 includes a plurality of pyramid-shaped protrusions, the height of the protrusions is 0.5 micrometers to 3 micrometers. And / or the side length of the bottom surface of the protrusions is 0.5 micrometers to 3 micrometers. Such a configuration can ensure that an uneven microstructure is reliably formed on the surface of the first polysilicon doped conductive layer 51 or the second polysilicon doped conductive layer 61.

[0088] Further, when the first region Y is constructed with a velvet structure 11, all of the orthographic projections of the first electrode 91 on the first surface F are located within the setting area of ​​the velvet structure 11. When the second region E is constructed with a velvet structure 11, all of the orthographic projections of the second electrode 92 on the first surface F are located within the setting area of ​​the velvet structure 11. In this way, all parts of the first electrode 91 can be in good contact with the first polysilicon-doped conductive layer 51, and all parts of the second electrode 92 can be in good contact with the second polysilicon-doped conductive layer 61.

[0089] In a specific implementation, the entire first region Y may be formed into the suede structure 11 , or the entire second region E may be formed into the suede structure 11 .

[0090] 2 , when the first region Y is entirely constructed as the velvet structure 11, the ratio of the size of the first electrode 91 along the width direction of the first electrode 91 to the size of the first region Y along the width direction of the first electrode 91 is 1 / 2-1 / 3. In this way, the influence of the deviation caused by the manufacture of the first electrode 91 can be improved.

[0091] Furthermore, when the first zone Y is partially or completely constructed with a velvet structure 11, the area of ​​the first zone Y accounts for 50%-80% of the area of ​​the first surface F. In this way, the velvet structure 11 can have a sufficiently large area on the first surface F, so that the contact loss is low and the battery efficiency is high.

[0092] 1 , when the second region E is entirely constructed as the velvet structure 11, the ratio of the size of the second electrode 92 along the width direction of the second electrode 92 to the size of the second region E along the width direction of the second electrode 92 is 1 / 2-2 / 3. In this way, the influence of the deviation caused by the production of the second electrode 92 can be improved.

[0093] When the second area E is partially or completely constructed with a velvet structure 11, the area of ​​the second area E accounts for 50%-80% of the area of ​​the first surface F. Similar to the solution in which the first area Y is provided with a velvet structure 11, such a configuration enables the velvet structure 11 to have a sufficiently large area on the first surface F, so that the contact loss is low and the battery efficiency is high.

[0094] In the embodiment of the present application, the substrate 10 further includes a second surface S arranged opposite to the first surface F along the thickness direction. The first surface F is the backlight surface of the back contact battery 100 , and the second surface S is the light receiving surface of the back contact battery 100 .

[0095] In the embodiment of the present application, referring to FIG. 1 and FIG. 2 , the back contact cell 100 further includes a first passivation layer 71 and a second passivation layer 72. The first passivation layer 71 is disposed on the surface of the first polysilicon doped conductive layer 51 and the second polysilicon doped conductive layer 61 away from the substrate 10, and the second passivation layer 72 is disposed on the second surface S of the substrate 10. In addition, a portion of the first passivation layer 71 also covers the bottom wall of the isolation trench 40 and the side trench wall of the isolation trench 40 (not shown in the figure).

[0096] Furthermore, the back contact cell 100 further includes a first anti-reflection layer 710 and a second anti-reflection layer 720. The first anti-reflection layer 710 is disposed on the surface of the first passivation layer 71 away from the substrate 10, and the second anti-reflection layer 720 is disposed on the surface of the second passivation layer 72 away from the substrate 10.

[0097] In addition, the first electrode 91 is disposed at a position on the first anti-reflection layer 710 corresponding to the first polysilicon doped conductive layer 51, and is electrically connected to the first polysilicon doped conductive layer 51, and the second electrode 92 is disposed at a position on the first anti-reflection layer 710 corresponding to the second polysilicon doped conductive layer 61, and is electrically connected to the second polysilicon doped conductive layer 61.

[0098] Furthermore, the bottom of the isolation groove 40 may also be provided with a velvet structure.

[0099] Figure 3 is a schematic diagram of the process of the method for manufacturing a back-contact battery provided in an embodiment of the present application; Figure 4 is a schematic diagram of forming a first tunneling material layer, a first doped polysilicon material layer and a first oxide material layer on a substrate in the method for manufacturing a back-contact battery provided in an embodiment of the present application; Figure 5 is a schematic diagram of partially removing the first oxide material layer in the method for manufacturing a back-contact battery provided in an embodiment of the present application; Figure 6 is a schematic diagram of the first texturing in the method for manufacturing a back-contact battery provided in an embodiment of the present application; Figure 7 is a schematic diagram of forming a second tunneling material layer, a second doped polysilicon material layer and a second oxide material layer in the method for manufacturing a back-contact battery provided in an embodiment of the present application; Figure 8 is a schematic diagram of partially removing the second oxide material layer in the method for manufacturing a back-contact battery provided in an embodiment of the present application; Figure 9 is a schematic diagram of the second texturing in the method for manufacturing a back-contact battery provided in an embodiment of the present application. Figure 10 is a schematic diagram of forming a first polysilicon doped conductive layer and a first tunneling oxide layer in a method for manufacturing a back contact cell provided in another embodiment of the present application; Figure 11 is a schematic diagram of forming a second tunneling oxide layer and a second polysilicon doped conductive layer in a method for manufacturing a back contact cell provided in another embodiment of the present application; Figure 12 is a schematic diagram of a back contact cell formed by the method for manufacturing a back contact cell provided in another embodiment of the present application.

[0100] 3 , the present embodiment also provides a method for manufacturing a back-contact battery, which is used to manufacture the above-mentioned back-contact battery 100. The method comprises:

[0101] S10, forming a first tunneling oxide layer and a P-type first polysilicon doped conductive layer stacked on each other in a first region of a first surface of the substrate; the first surface is configured as a polished surface or a velvet surface, and the first surface further includes a second region and an isolation region isolated between the first region and the second region;

[0102] S20, when the first surface is a polished surface, the second area is formed into a suede surface; when the first surface is a suede surface, the second area is polished;

[0103] S30, forming a second tunneling oxide layer and an N-type second polysilicon doped conductive layer stacked on each other in the second region, and forming an isolation trench extending to the isolation region between the first polysilicon doped conductive layer and the second polysilicon doped conductive layer;

[0104] S40, preparing a first electrode and a second electrode, wherein the first electrode and the second electrode are electrically connected to the first polysilicon doped conductive layer and the second polysilicon doped conductive layer, respectively.

[0105] When the first surface F is constructed as a velvet surface, the first region Y is formed with a first tunneling oxide layer 50 and a first polysilicon doped conductive layer, which makes the first region Y have a velvet structure 11. When the first surface F is constructed as a velvet surface, the second region E is polished, that is, the second region E is formed as a polished surface, which makes the surface of the first polysilicon doped conductive layer 51 have an uneven microstructure. Since the first electrode 91 is electrically connected to the first polysilicon doped conductive layer 51, the contact area between the first electrode 91 and the first polysilicon doped conductive layer 51 is increased, the contact is better, and the efficiency of the back contact battery is higher. In addition, since the velvet structure 11 is constructed in the first region Y, compared with the polished surface, the light emission ratio in the back contact battery 100 can also be reduced to further improve the battery efficiency.

[0106] When the first surface F is configured as a polished surface, the second region E is formed as a velvet surface, so that the second region E is configured with a velvet structure 11. Since the second tunneling oxide layer 60 and the N-type second polysilicon doped conductive layer 61 are stacked on each other in the second region E. This makes the surface of the second polysilicon doped conductive layer 61 have an uneven microstructure. Since the second electrode 92 is electrically connected to the second polysilicon doped conductive layer 61, the contact area between the second electrode 92 and the second polysilicon doped conductive layer 61 is increased, the contact is better, and the efficiency of the back contact battery is higher. In addition, since the velvet structure 11 is configured in the second region E, compared with the polished surface, the proportion of light emitted from the back contact battery 100 can also be reduced to further improve the battery efficiency.

[0107] In the embodiment of the present application, referring to FIG. 4 , FIG. 5 , and FIG. 6 , in step S10, the step of forming a first tunneling oxide layer 50 and a first P-type polysilicon doped conductive layer 51 stacked on each other in the first region Y of the first surface F of the substrate 10 specifically includes:

[0108] 4 , a first tunneling material layer 801 , a first doped polysilicon material layer 81 and a first oxide material layer 810 are sequentially stacked and formed on respective surfaces of the substrate 10 .

[0109] 5 , the first oxide material layer 810 corresponding to the second region E and the isolation region G, the side surface C of the substrate 10 and the second surface S is removed, and the first oxide material layer 810 corresponding to the first region Y is retained. The second surface S is arranged opposite to the first surface F, and the side surface C is adjacent to the first surface F and the second surface S.

[0110] It can be understood that FIG. 4 and FIG. 5 correspond to the case where the first surface F is a polished surface. The case where the first surface F is a velvet surface is similar and is not illustrated here.

[0111] 6 and 10 , using the first oxide material layer 810 corresponding to the first region Y as a mask, the first tunneling material layer 801 and the first doped polysilicon material layer 81 covering the second region E and the isolation region G, the side surface C and the second surface S are removed to form a first tunneling oxide layer 50 and a first polysilicon doped conductive layer 51 in the first region Y.

[0112] In the embodiment of the present application, referring to FIG. 6 , the step of forming the second region E into a velvet surface specifically includes forming the second region E into a velvet surface using a first alkaline solution. That is, a velvet structure 11 is formed on the second region E. This step can be performed after removing the first tunneling material layer 801 and the first doped polysilicon material layer 81. The first alkaline solution can be the same as or different from the alkaline solution used to remove the first tunneling material layer 801 and the first doped polysilicon material layer 81.

[0113] Furthermore, in the step of forming the second region E into a velvet surface using the first alkaline solution, the isolation region G and the second surface S are also textured.

[0114] In a specific implementation, a first alkaline solution is used to remove the first doped polysilicon material layer 81 and the first tunneling material layer 801 on the second surface S and the side surface C, as well as the laser-opened area on the first surface F (the second region E and the isolation region G), and the exposed surface of the substrate 10 is textured (the texture of the side surface C is not shown), thereby forming the second region E into a textured structure 11 using the first alkaline solution, and the isolation region G and the second surface S are also textured.

[0115] 10 , the step of polishing the second region E specifically includes polishing the second region E using a second alkaline solution. That is, a polishing surface is formed on the second region E. This step can be performed after removing the first tunneling material layer 801 and the first doped polysilicon material layer 81. The second alkaline solution can be the same as or different from the alkaline solution used to remove the first tunneling material layer 801 and the first doped polysilicon material layer 81.

[0116] Furthermore, in the step of polishing the second region E, the isolation region G and the second surface S are also polished. In specific implementation, the first doped polysilicon material layer 81 and the first tunneling material layer 801 on the second surface S and the side surface C, and the laser-opened region (the second region E and the isolation region G) on the first surface F are removed with a second alkaline solution, and the exposed surface of the substrate 10 is polished, so that the second region E is formed into a polished surface by the second alkaline solution, and the isolation region G and the second surface S are also polished.

[0117] In the embodiment of the present application, in step S30, the step of forming the second tunneling oxide layer 60 and the N-type second polysilicon doped conductive layer 61 stacked on each other in the second region E specifically includes:

[0118] 7 , a second tunneling material layer 802 , a second doped polysilicon material layer 82 , and a second oxide material layer 820 are sequentially stacked and formed on each surface of the substrate 10 .

[0119] 8 , the second oxide material layer 820 corresponding to the first region Y and the isolation region G, the side surface C and the second surface S of the substrate 10 is removed, and the second oxide material layer 820 corresponding to the second region E is retained.

[0120] It can be understood that FIG. 7 and FIG. 8 correspond to the case where the first surface F of the substrate 10 is a polished surface. The case where the first surface F is a velvet surface is similar and is not illustrated here.

[0121] 9 and 11 , using the second oxide material layer 820 corresponding to the second region E as a mask, the second tunneling material layer 802 and the second doped polysilicon material layer 82 covering the first region Y and the isolation region G, the side surface C and the second surface S are removed to form a second tunneling oxide layer 60 and a second polysilicon doped conductive layer 61 in the second region E.

[0122] Further, referring to FIG. 8 , the steps of removing the second oxide material layer 820 corresponding to the first region Y and the isolation region G, the side C of the substrate 10 and the second surface S, and retaining the second oxide material layer 820 corresponding to the second region E specifically include:

[0123] Laser film opening is performed to remove the second oxide material layer 820 corresponding to the first region Y and the isolation region G. HF is used to remove the second oxide material layer 820 corresponding to the side surface C and the second surface S of the substrate 10 .

[0124] Furthermore, the step of removing the second tunneling material layer 802 and the second doped polysilicon material layer 82 covering the first region Y and the isolation region G, the side surface C and the second surface S by using the second oxide material layer 820 corresponding to the second region E as a mask specifically includes:

[0125] The second doped polysilicon material layer 82 and the second tunneling material layer 802 covering the second surface S and the side surface C, as well as the first region Y and the isolation region G are removed by using a third alkaline solution, and the isolation region G is textured.

[0126] It can be understood that in this step, in the embodiment of FIG. 9 , the side surface C and the second surface S can also be further textured, and in the previous step, the portion of the bottom of the isolation region G affected by the laser can be textured.

[0127] In this step, in the embodiment of FIG. 11 , the polished surface of the side surface C, the second surface S and the bottom of the isolation region G may be textured.

[0128] In the embodiment of the present application, in step S40, referring to FIG. 1 and FIG. 12 , the steps of preparing the first electrode 91 and the second electrode 92 specifically include:

[0129] A first passivation layer 71 and a first anti-reflection layer 710 are sequentially stacked on the sides of the first polysilicon-doped conductive layer 51 and the second polysilicon-doped conductive layer 61 facing away from the substrate 10 .

[0130] A first electrode 91 and a second electrode 92 are respectively formed on the first anti-reflection layer 710 , wherein the first electrode 91 is electrically connected to the first polysilicon doped conductive layer 51 , and the second electrode 92 is electrically connected to the second polysilicon doped conductive layer 61 .

[0131] Of course, the method may further include the step of forming a second passivation layer 72 and a second anti-reflection layer 720 on the second surface S of the substrate 10 .

[0132] A specific example is given below to illustrate the method for manufacturing a back contact battery according to an embodiment of the present application, the method comprising:

[0133] Step 1: polishing the N-type substrate 10 with an alkaline solution, the size of the plane tower base is 5-25 microns.

[0134] Step 2, referring to FIG. 4, a first tunneling material layer 801 and an intrinsic amorphous silicon material layer are prepared on the first surface F of the substrate 10 by LPCVD, and high-temperature thermal diffusion is performed to transform the intrinsic amorphous silicon material layer into a first doped polysilicon material layer 81 doped with boron, and a first oxide material layer 810 is formed on the surface of the first doped polysilicon material layer 81. The first oxide material layer 810 may be BSG.

[0135] Step 3, referring to Fig. 5, laser film opening is performed to remove (or destroy) the first oxide material layer 810 corresponding to the second region E (N-type region) of the first surface F and the isolation region G. HF is used to remove the first oxide material layer 810 corresponding to the second surface S and the side surface C.

[0136] Step 4, as shown in FIG6 , the first doped polysilicon material layer 81 and the first tunneling material layer 801 on the second surface S and the side surface C, and the laser-opened area (the second area E and the isolation area G) on the first surface F are removed with an alkaline solution, and the exposed substrate surface is textured (the textured surface on the side is not shown), thereby forming the first doped polysilicon material layer 81 and the first tunneling material layer 801 into a first polysilicon doped conductive layer 51 and a first tunneling oxide layer 50, respectively.

[0137] Step 5, as shown in FIG7 , a second tunneling material layer 802 and an intrinsic amorphous silicon material layer are prepared on the first surface F of the substrate 10 by LPCVD, and high-temperature thermal diffusion is performed to transform the intrinsic amorphous silicon material layer into a second doped polysilicon material layer 82 doped with phosphorus, and a second oxide material layer 820 is formed on the surface of the second doped polysilicon material layer 82. The second oxide material layer 820 may be, for example, PSG.

[0138] Step 6, referring to FIG8 , laser film opening is performed to remove (or destroy) the first region Y (P-type region) on the first surface F and the corresponding second oxide material layer 820 on the isolation region G. It is understandable that the laser treatment may affect the velvet surface of the isolation region G, and HF is used to remove the second oxide material layer 520 corresponding to the second surface S and the side surface C, and the second oxide material layer 520 corresponding to the second region E is retained.

[0139] Step 7, as shown in FIG9 , the second doped polysilicon material layer 82 and the second tunneling material layer 802 on the second surface E and the side surface C, and the laser-opened region (the first region Y and the isolation region G) on the first surface F are removed with an alkaline solution, and the exposed surface of the substrate 10 is textured for the second time (the texture of the side surface is not shown), so that the texture of the isolation region G is repaired. The second doped polysilicon material layer 82 and the second tunneling material layer 802 are formed into the second polysilicon doped conductive layer 61 and the second tunneling oxide layer 60, respectively, and an isolation trench 40 is formed between the first polysilicon doped conductive layer 51 and the second polysilicon doped conductive layer 61.

[0140] Step 8, referring to FIG. 1, after removing the first oxide material layer 810 corresponding to the first region Y and the second oxide material layer 820 corresponding to the second region E, a first passivation layer 71 and a first anti-reflection layer 710 are sequentially deposited on the first surface F side of the substrate 10, and a second passivation layer 72 and a second anti-reflection layer 720 are sequentially deposited on the second surface S side of the substrate 10. A first electrode 91 and a second electrode 92 are respectively formed on the first anti-reflection layer 710. The first electrode 91 is electrically connected to the first polysilicon doped conductive layer 51, and the second electrode 92 is electrically connected to the second polysilicon doped conductive layer 61.

[0141] It should be noted that, in the back contact cell 100 formed by the above method, the first region Y is a polished surface, and the second region E is a velvet surface.

[0142] In some other embodiments, referring to FIG. 10 to FIG. 12 , a method for manufacturing a back contact battery in which the first area Y is a velvet surface and the second area E is a polished surface includes:

[0143] Step 1: texturing the first surface F of the N-type substrate 10 with an alkaline solution.

[0144] Step 2: Prepare a first tunneling material layer 801 and an intrinsic amorphous silicon material layer on the entire first surface F of the substrate 10 by LPCVD, and perform high-temperature thermal diffusion to transform the intrinsic amorphous silicon material layer into a first doped polysilicon material layer 81 doped with boron, and form a first oxide material layer 810 on the surface of the first doped polysilicon material layer 81. The first oxide material layer 810 can be BSG.

[0145] Step 3: Laser film opening to remove (or destroy) the second region E (N-type region) on the first surface F and the first oxide material layer 810 corresponding to the isolation region G. HF is used to remove the first oxide material layer 810 corresponding to the second surface S and the side surface C.

[0146] Step 4: Use an alkaline solution to remove the first doped polysilicon material layer 81 and the first tunneling material layer 801 on the second surface S and the side surface C, as well as the laser-opened area (the second area E and the isolation area G) on the first surface F, and polish the exposed surface of the substrate 10, thereby forming the first doped polysilicon material layer 81 and the first tunneling material layer 801 into a first polysilicon doped conductive layer 51 and a first tunneling oxide layer 50, respectively, thereby forming a structure as shown in Figure 10.

[0147] Step 5: Prepare the second tunneling material layer 802 and the intrinsic amorphous silicon material layer on the first surface F of the substrate 10 by LPCVD, and perform high-temperature thermal diffusion to transform the intrinsic amorphous silicon material layer into a second doped polysilicon material layer 82 doped with phosphorus, and form a second oxide material layer 820 on the surface of the second doped polysilicon material layer 82. The second oxide material layer 820 can be, for example, PSG.

[0148] Step 6: Laser film opening to remove (or destroy) the first region Y (P-type region) on the first surface F and the corresponding second oxide material layer 820 on the isolation region G. HF is used to remove the second oxide material layer 820 corresponding to the second surface S and the side surface C, and the second oxide material layer 820 corresponding to the second region E is retained.

[0149] Step 7: Use an alkaline solution to remove the second doped polysilicon material layer 82 and the second tunneling material layer 802 on the second surface E and the side surface C, as well as the laser-opened area (first area Y and isolation area G) on the first surface F, and perform texturing on the exposed surface of the substrate 10 (the texturing of the side surface is not shown), so that the isolation area G and the second surface S (the isolation area G and the second surface S are originally polished surfaces) form a texturing structure. The second doped polysilicon material layer 82 and the second tunneling material layer 802 are respectively formed into the second polysilicon doped conductive layer 61 and the second tunneling oxide layer 60, and an isolation groove 40 is formed between the first polysilicon doped conductive layer 51 and the second polysilicon doped conductive layer 61. Thus, the structure shown in FIG. 11 is formed.

[0150] Step 8: After removing the first oxide material layer 810 corresponding to the first region Y and the second oxide material layer 820 corresponding to the second region E, a first passivation layer 71 and a first anti-reflection layer 710 are sequentially deposited on the first surface F of the substrate 10, and a second passivation layer 72 and a second anti-reflection layer 720 are sequentially deposited on the second surface S of the substrate 10. A first electrode 91 and a second electrode 92 are respectively formed on the first anti-reflection layer 710. The first electrode 91 is electrically connected to the first polysilicon doped conductive layer 51, and the second electrode 92 is electrically connected to the second polysilicon doped conductive layer 61, thereby forming another back contact cell 100 of structure as shown in FIG. 12.

[0151] The embodiment of the present application also provides a back-contact battery 100, which is manufactured using the above-mentioned method for manufacturing a back-contact battery.

[0152] The embodiments of the present application also provide a photovoltaic module and a photovoltaic system. The photovoltaic module includes at least one battery string, and the battery string includes at least two back-contact batteries 100 as described above, and the back-contact batteries 100 can be connected together by series welding.

[0153] The photovoltaic system includes the above-mentioned photovoltaic components. The photovoltaic system can be used in photovoltaic power stations, such as ground power stations, rooftop power stations, water power stations, etc. It can also be used in equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc. Of course, it can be understood that the application scenarios of the photovoltaic system are not limited to this, that is to say, the photovoltaic system can be used in all fields that require solar energy to generate electricity. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array can be an array combination of multiple photovoltaic components. For example, multiple photovoltaic components can form multiple photovoltaic arrays. The photovoltaic array is connected to the junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid. After that, it is connected to the mains network to realize solar power supply.

[0154] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0155] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A back contact battery, characterized in that: include: A substrate, comprising a first surface, wherein the first surface comprises a first region, a second region, and an isolation region isolated between the first region and the second region; A first passivation contact structure and a second passivation contact structure are respectively arranged in the first region and the second region, an isolation groove extending to the isolation region is arranged between the adjacent first passivation contact structures and the second passivation contact structures, the first passivation contact structure comprises a P-type first polysilicon doped conductive layer, and the second passivation contact structure comprises an N-type second polysilicon doped conductive layer; as well as A first electrode and a second electrode, electrically connected to the first polysilicon doped conductive layer and the second polysilicon doped conductive layer, respectively; The first region is constructed with a velvet structure, and at least part of the orthographic projection of the first electrode on the first surface is located in the setting area of ​​the velvet structure; or The second region is formed with a textured structure, and at least a portion of an orthographic projection of the second electrode on the first surface is located within a placement region of the textured structure.

2. The back contact cell according to claim 1, characterized in that: The velvet structure includes a plurality of pyramid-shaped protrusions, the height of the protrusions is 0.5 micrometers to 3 micrometers; and / or the side length of the bottom surface of the protrusions is 0.5 micrometers to 3 micrometers.

3. The back contact cell according to claim 1, characterized in that: When the first area is constructed with a velvet structure, all of the orthographic projections of the first electrode on the first surface are located in the setting area of ​​the velvet structure; When the second region is constructed with a velvet structure, the orthographic projections of the second electrode on the first surface are all located within the setting area of ​​the velvet structure.

4. The back contact cell according to claim 3, characterized in that: When the first region is entirely constructed as a suede structure, a ratio of a size of the first electrode along a width direction of the first electrode to a size of the first region along the width direction of the first electrode is 1 / 2-2 / 3; When the second region is entirely constructed as a suede structure, a ratio of a size of the second electrode along a width direction of the second electrode to a size of the second region along the width direction of the second electrode is 1 / 2-2 / 3.

5. The back contact cell according to claim 1, characterized in that: When the first region is constructed with a suede structure, the area of ​​the first region accounts for 50%-80% of the area of ​​the first surface; When the second region is configured with a suede structure, the area of ​​the second region accounts for 50%-80% of the area of ​​the first surface.

6. A method for manufacturing a back contact battery, characterized in that: include: A first tunneling oxide layer and a first P-type polysilicon doped conductive layer are formed in a first region of a first surface of a substrate, and are stacked on each other; the first surface is configured as a polished surface or a velvet surface, and the first surface further includes a second region and an isolation region isolated between the first region and the second region; When the first surface is configured as a polished surface, the second area is formed into a suede surface; when the first surface is configured as a suede surface, the second area is polished; forming a second tunneling oxide layer and an N-type second polysilicon doped conductive layer stacked on each other in the second region, and forming an isolation trench extending to the isolation region between the first polysilicon doped conductive layer and the second polysilicon doped conductive layer; A first electrode and a second electrode are prepared, wherein the first electrode and the second electrode are electrically connected to the first polysilicon doped conductive layer and the second polysilicon doped conductive layer, respectively.

7. The method for manufacturing a back contact battery according to claim 6, characterized in that: The step of forming a first tunneling oxide layer and a first P-type polysilicon doped conductive layer stacked on each other in the first region of the first surface of the substrate specifically comprises: Forming a first tunneling material layer, a first doped polysilicon material layer and a first oxide material layer in sequence on each surface of the substrate; Removing the first oxide material layer corresponding to the second region and the isolation region, the side surface and the second surface of the substrate, and retaining the first oxide material layer corresponding to the first region, wherein the second surface is arranged opposite to the first surface, and the side surface is adjacent to the first surface and the second surface; Using the first oxide material layer corresponding to the first region as a mask, the first tunneling material layer and the first doped polysilicon material layer covering the second region and the isolation region, the side surface and the second surface are removed to form a first tunneling oxide layer and a first polysilicon doped conductive layer in the first region.

8. The method for manufacturing a back contact battery according to claim 7, characterized in that: The step of forming the second region into a velvet surface specifically includes forming the second region into a velvet surface using a first alkaline solution; The step of polishing the second area specifically includes polishing the second area using a second alkaline solution.

9. The method for manufacturing a back contact battery according to claim 8, characterized in that: In the step of forming the second area into a velvet surface by using the first alkaline solution, the isolation area and the second surface are also velveted; In the step of polishing the second region, the isolation region and the second surface are also polished.

10. The method for manufacturing a back contact battery according to claim 9, characterized in that: The step of forming a second tunneling oxide layer and an N-type second polysilicon doped conductive layer stacked on each other in the second region specifically includes: Forming a second tunneling material layer, a second doped polysilicon material layer and a second oxide material layer in sequence on each surface of the substrate; removing the second oxide material layer corresponding to the first region and the isolation region, the side surface and the second surface of the substrate, and retaining the second oxide material layer corresponding to the second region; Using the second oxide material layer corresponding to the second region as a mask, the second tunneling material layer and the second doped polysilicon material layer covering the first region and the isolation region, the side surface and the second surface are removed to form a second tunneling oxide layer and a second polysilicon doped conductive layer in the second region.

11. The method for manufacturing a back contact battery according to claim 10, characterized in that: The step of removing the second oxide material layer corresponding to the first region and the isolation region, the side surface and the second surface of the substrate, and retaining the second oxide material layer corresponding to the second region specifically includes: Laser film opening to remove the second oxide material layer corresponding to the first area and the isolation area; The second oxide material layer corresponding to the side surface of the substrate and the second surface is removed by using HF.

12. The method for manufacturing a back contact battery according to claim 11, characterized in that: The step of using the second oxide material layer corresponding to the second region as a mask to remove the second tunneling material layer and the second doped polysilicon material layer covering the first region and the isolation region, the side surface and the second surface specifically comprises: The second surface and the side surface, as well as the second doped polysilicon material layer and the second tunneling material layer covering the first region and the isolation region are removed by using a third alkaline solution, and the isolation region is textured.

13. The method for manufacturing a back contact battery according to claim 11, characterized in that: The steps of preparing the first electrode and the second electrode specifically include: A first passivation layer and a first anti-reflection layer are sequentially stacked on the first polysilicon doped conductive layer and the second polysilicon doped conductive layer at a side away from the substrate; A first electrode and a second electrode are respectively formed on the first anti-reflection layer, wherein the first electrode is electrically connected to the first polysilicon doped conductive layer, and the second electrode is electrically connected to the second polysilicon doped conductive layer.

14. A back contact battery, characterized in that: The back contact battery is manufactured by the manufacturing method of any one of claims 6 to 13.

15. A photovoltaic module, characterized in that: The method comprises at least one battery string, wherein the battery string comprises at least two back-contact batteries according to any one of claims 1 to 6 and 14.

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