Circuit and method for reducing voltage overshoot during current test gear shifting

Abstract

The invention provides a circuit and method for reducing voltage overshoot during current test gear shifting, a plurality of detection branches are arranged in parallel, the first end parts of the plurality of detection branches are respectively connected with a voltage input end, and the second end parts of the plurality of detection branches are respectively connected with a voltage output end; detection resistors, branch on-off switches and impedance regulation and control circuits which are sequentially connected in series are arranged in the detection branches, the resistance values of the detection resistors in the detection branches in different groups are different, and the detection branches are configured to realize on-off adjustment of the corresponding two groups of detection branches through switching control of the branch on-off switches in the two groups of detection branches. And the impedance regulation and control circuit in the to-be-measured detection branch is utilized to regulate the overall impedance value of the to-be-measured detection branch to be linearly changed in unit time. According to the invention, when the source measurement unit switches the current test gear, the stable change of the measurement voltage can be maintained, and the instantaneous overshoot of the voltage can be avoided.

Description

Technical Field

[0001] The invention belongs to the technical field of current measurement, and in particular relates to a circuit and method for reducing voltage overshoot during gear shifting in current testing. Background Art

[0002] Source Measure Unit (SMU) is a professional instrument that can provide accurate current and voltage sources and measure current and voltage at the same time. SMU is often used in automated test and measurement environments, especially in the characteristic test and calibration process of semiconductor devices, sensors and other precision electronic components. In the current measurement process of the source measurement unit, since the amplitude of the test current is often very large, the span can reach up to 15 orders of magnitude, which makes it impossible to complete all current measurements with only one gear. Therefore, the source measurement unit is often provided with multiple gears, and the gears can be quickly switched to meet the test range requirements of different currents. Since the internal measurement circuits and electronic components of the source measurement unit are precisely designed, they are sensitive to the conversion of current and voltage. During the switching process of the current gear, if the current is interrupted or the impedance of the current detection loop changes too quickly, the voltage value directly measured by the source measurement unit will be instantly overshot, which will cause the line to be overvoltage, which is very easy to damage the source measurement unit and the device under test. Summary of the invention

[0003] The present invention aims to provide a circuit and method for reducing voltage overshoot during current test gear switching, so as to solve the technical problem that a conventional source measurement unit cannot maintain a stable transition of the measured voltage when implementing current test gear switching in the prior art.

[0004] To solve the above problems, the technical solution of the present invention is: a circuit for reducing voltage overshoot during current test shifting, comprising at least two groups of detection branches;

[0005] The plurality of detection branches are arranged in parallel, the first ends of the plurality of detection branches are electrically connected to the voltage input end, and the second ends of the plurality of detection branches are electrically connected to the voltage output end;

[0006] A plurality of the detection branches are respectively provided with detection resistors, branch on-off switches and impedance control circuits connected in series in sequence, the resistance values ​​of the detection resistors in the detection branches of different groups are different from each other, the branch on-off switches are used to limit the working state of the detection branch in which they are located, and the impedance control circuit is used to adjust the change of the overall impedance value of the detection branch in which they are located within a unit time;

[0007] The detection branch is configured to respectively realize on-off adjustment of the corresponding two groups of detection branches through switching control of the branch on-off switches in the two groups of detection branches, and utilize the impedance control circuit in the detection branch to be measured to adjust the overall branch impedance value of the detection branch to be measured to change linearly within unit time.

[0008] Preferably, the impedance control circuit is provided with a first impedance control sub-circuit, a second impedance control sub-circuit and a third impedance control sub-circuit;

[0009] The first impedance control subcircuit is provided with a first resistor and a first P-channel junction field effect transistor, the first end of the first resistor is connected to the second end of the branch on-off switch in the detection branch where the first resistor is located, the second end of the first resistor is connected to the source of the first P-channel junction field effect transistor, the gate of the first P-channel junction field effect transistor is connected to the first level control terminal, and the drain of the first P-channel junction field effect transistor is connected to the voltage output terminal;

[0010] The first impedance control sub-circuit is configured such that when the branch in the detection branch to be measured in which the first impedance control sub-circuit is located is opened or closed, the output of the first level control terminal is changed from a low level to a high level, the first P-channel junction field effect transistor is changed from a cut-off state to a conducting state, and the current in the detection branch to be measured flows through the first resistor.

[0011] Preferably, the second impedance control subcircuit is provided with a second resistor and a second P-channel junction field effect transistor, the first end of the second resistor is connected to the second end of the branch on-off switch in the detection branch where the second resistor is located, the second end of the second resistor is connected to the source of the second P-channel junction field effect transistor, the gate of the second P-channel junction field effect transistor is connected to the second level control terminal, and the drain of the second P-channel junction field effect transistor is connected to the voltage output terminal;

[0012] The second impedance control sub-circuit is configured such that, under the premise that the first P-channel junction field effect transistor is in the on state, the output of the second level control terminal is changed from a low level to a high level, the second P-channel junction field effect transistor is changed from a cut-off state to an on state, and the current in the detection branch to be measured flows through the first resistor and the second resistor connected in parallel respectively.

[0013] Preferably, the third impedance control subcircuit is provided with a third resistor and a third P-channel junction field effect transistor, the first end of the third resistor is connected to the second end of the branch on-off switch in the detection branch where the third resistor is located, the second end of the third resistor is connected to the source of the third P-channel junction field effect transistor, the gate of the third P-channel junction field effect transistor is connected to the third level control terminal, and the drain of the third P-channel junction field effect transistor is connected to the voltage output terminal;

[0014] The third impedance control subcircuit is configured such that, under the premise that the first P-channel junction field effect transistor and the second P-channel junction field effect transistor are both in the on state, the output of the third level control terminal is changed from a low level to a high level, the third P-channel junction field effect transistor is changed from a cut-off state to an on state, and the current in the detection branch to be measured flows through the first resistor, the second resistor and the third resistor connected in parallel respectively.

[0015] Preferably, the detection branch includes a first detection branch and a second detection branch, and the resistance values ​​of the first resistor, the second resistor and the third resistor in the first detection branch are limited to:

[0016] R 11 =10*R2,

[0017] R 12 =(R1+R2) / 2,

[0018] R 13 =1 / 10*R1,

[0019] Wherein, R1 is the detection resistor in the first detection branch, R2 is the detection resistor in the second detection branch, R 11 is the first resistor in the first impedance control sub-circuit, R 12 is the second resistor in the second impedance control sub-circuit, R 13 It is the third resistor in the third impedance control sub-circuit.

[0020] Preferably, the first impedance control subcircuit, the second impedance control subcircuit and the third impedance control subcircuit are further provided with a P-channel junction field effect transistor driving circuit respectively, and the P-channel junction field effect transistor driving circuit is used to drive the first P-channel junction field effect transistor, the second P-channel junction field effect transistor and the third P-channel junction field effect transistor to linearly convert from a cut-off state to a conduction state within a unit time, respectively, so that the impedance from the source to the drain of the first P-channel junction field effect transistor, the second P-channel junction field effect transistor and the third P-channel junction field effect transistor is linearly transformed respectively;

[0021] Furthermore, the conversion time from the cut-off state to the on state of the first P-channel junction field effect transistor, the second P-channel junction field effect transistor and the third P-channel junction field effect transistor is 5 ms respectively.

[0022] Preferably, the P-channel junction field effect transistor driving circuit is provided with a first charging and discharging resistor and a first timing capacitor, the first end of the first charging and discharging resistor is connected to the level control end, the second end of the first charging and discharging resistor is connected to the gate of the P-channel junction field effect transistor, the first end of the first timing capacitor is connected to the common node of the first charging and discharging resistor and the P-channel junction field effect transistor, and the second end of the first timing capacitor is grounded.

[0023] Preferably, the P-channel junction field effect transistor driving circuit is provided with a second charge and discharge resistor, a second timing capacitor and an operational amplifier, the non-inverting input terminal of the operational amplifier is connected in series with the second charge and discharge resistor and then connected to a +15V power supply, the inverting input terminal of the operational amplifier is respectively connected to the level control terminal and the first terminal of the second timing capacitor, and the gate of the P-channel junction field effect transistor is respectively connected to the second terminal of the second timing capacitor and the output terminal of the operational amplifier;

[0024] A first diode and a second diode are also provided, wherein the anode of the first diode is connected to the common node of the second charge and discharge resistor and the operational amplifier, the cathode of the first diode is grounded, the anode of the second diode is connected in parallel to the first end of the second timing capacitor, and the cathode of the second diode is connected in parallel to the second end of the second timing capacitor.

[0025] Preferably, a first voltage measurement loop and a second voltage measurement loop are respectively provided in the plurality of detection branches, the first end of the first voltage measurement loop is connected to the second end of the branch on-off switch of the detection branch in which it is located, the second end of the first voltage measurement loop is connected to the voltage measurement end, the first end of the second voltage measurement loop is connected to the voltage output end, and the second end of the second voltage measurement loop is connected to the voltage measurement end;

[0026] The first voltage measurement loop is provided with a first measurement switch and a first buffer operational amplifier connected in series, and the first measurement switch is used to limit the working state of the first voltage measurement loop; the second voltage measurement loop is provided with a second measurement switch and a second buffer operational amplifier connected in series, and the second measurement switch is used to limit the working state of the second voltage measurement loop.

[0027] Based on the same concept, the present invention also provides a method for reducing voltage overshoot during current test shifting, which is applied to a circuit for reducing voltage overshoot during current test shifting as described in any one of the above, and the detection branch is set to include at least a first detection branch and a second detection branch. When switching from the second detection branch to the first detection branch, the method includes the following steps:

[0028] S1: Keep the branch on-off switch of the second detection branch and the first measurement switch in a closed state, and the fourth level control terminal, the fifth level control terminal and the sixth level control terminal of the second detection branch are at a high level, and close the branch on-off switch of the first detection branch and the second measurement switch;

[0029] S2: Adjust the first level control terminal in the first impedance control subcircuit of the first detection branch from a low level output to a high level output, and wait for 10ms;

[0030] S3: Adjust the second level control terminal in the second impedance control subcircuit of the first detection branch from a low level output to a high level output, and wait for 10ms;

[0031] S4: adjusting the third level control terminal in the third impedance control subcircuit of the first detection branch from a low level output to a high level output, and waiting for 10 ms;

[0032] S5: opening the second measuring switch of the first detection branch and closing the first measuring switch of the first detection branch;

[0033] S6: disconnecting the branch on-off switch of the second detection branch from the first measurement switch, and outputting the fourth level control terminal, the fifth level control terminal and the sixth level control terminal of the second detection branch to a low level;

[0034] S7: Measure and calculate the current parameter flowing through the detection resistor in the first detection branch from the voltage input terminal and the voltage measurement terminal.

[0035] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art:

[0036] The present invention provides a circuit and method for reducing voltage overshoot during current test gear shifting. In multi-channel detection branches, impedance control circuits are respectively added. The impedance control circuits further include a first impedance control subcircuit, a second impedance control subcircuit and a third impedance control subcircuit. The first impedance control subcircuit, the second impedance control subcircuit and the third impedance control subcircuit are respectively provided with resistors and P-channel junction field effect transistors. The P-channel junction field effect transistors realize cut-off or on-state switching through high and low levels output by a level control terminal. In the process of working state switching, the impedance from the source to the drain of the P-channel junction field effect transistor is linearly transformed. The first impedance control subcircuit, the second impedance control subcircuit and the third impedance control subcircuit are used in combination. When the current test gear shifts when the resistance value difference of the detection resistor is too large, a linear and smooth transition of the impedance of the detection branch can be realized, and a smooth gear shifting operation is completed within a unit time, thereby effectively reducing the instantaneous change amplitude of the measured voltage during the current test gear shifting, preventing voltage overshoot, and effectively protecting the test safety of a source measurement unit and a device under test body. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of the structure of a circuit for reducing voltage overshoot during current test gear shifting provided by the present invention;

[0038] Figure 2 A schematic diagram of the structure of a current measurement unit circuit in a conventional source measurement unit;

[0039] Figure 3 A schematic structural diagram of a P-channel junction field effect transistor driving circuit provided by the present invention;

[0040] Figure 4 A graph a showing a change in gate-to-source voltage of a P-channel junction field effect transistor provided by the present invention;

[0041] Figure 5 A graph b showing a change in gate-to-source voltage of a P-channel junction field effect transistor provided by the present invention;

[0042] Figure 6 The present invention provides a flow chart of a method for reducing voltage overshoot during current test gear shifting. DETAILED DESCRIPTION

[0043] The following is a further detailed description of a circuit and method for reducing voltage overshoot during current test shifting proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims.

[0044] First embodiment

[0045] See also Figure 1-Figure 3This embodiment provides a circuit for reducing voltage overshoot during current test shifting, which is used to avoid measurement voltage overshoot when the source measurement unit performs current test shifting, thereby effectively ensuring the test safety of the source measurement unit and the device under test.

[0046] The circuit for reducing voltage overshoot during current test shifting provided in this embodiment includes at least two groups of switchable detection branches, and different detection branches correspond to test selection ranges of different current magnitudes, see Figure 1 In this embodiment, a detailed description will be given based on the situation where there are three groups of detection branches, where Figure 1 The circuit structures of the first detection branch and the second detection branch are specifically provided. The circuit structure of the third detection branch is similar to that of the first detection branch and the second detection branch, and will not be repeatedly marked.

[0047] Specifically, the first detection branch, the second detection branch and the third detection branch are arranged in parallel, the first ends of the first detection branch, the second detection branch and the third detection branch are electrically connected to the voltage input terminal VIN, and the second ends of the first detection branch, the second detection branch and the third detection branch are electrically connected to the voltage output terminal OUT, respectively.

[0048] The first detection branch, the second detection branch and the third detection branch are respectively provided with a detection resistor, a branch on-off switch and an impedance control circuit connected in series in sequence, and the resistance values ​​of the detection resistors in the first detection branch, the second detection branch and the third detection branch are different. In the present embodiment, the resistance value of the first detection resistor R1 in the first detection branch is selected to be 1Ω, the second detection resistor R2 in the second detection branch is selected to be 100Ω, and the third detection resistor R3 in the third detection branch is selected to be 10KΩ. In this embodiment, the branch on-off switch is used to limit the working state of the detection branch in which it is located. When the branch is on, off, closed, the detection branch in which it is located forms a path, and current flows through the detection resistor of the detection branch. Subsequently, by measuring the voltage value across the detection resistor, the actual current value flowing through the detection branch can be solved in the host computer through Ohm's law and based on the actual resistance value of the detection resistor. Conversely, when the branch on-off switch is disconnected, the detection branch in which it is located forms an open circuit. In theory, when the source measurement unit formally measures the current value of the device under test, it is necessary to ensure that only a single detection branch is a path. In this embodiment, the impedance control circuit is used to adjust the change in the overall impedance value of the detection branch in which it is located within a unit time. Taking the switch from the second detection branch to the first detection branch as an example, when the second detection resistor R2 with a larger measured resistance value is switched to the first detection resistor R1 with a smaller measured resistance value, the impedance control circuit can play a transition buffering function, so that the total impedance value at both ends of the voltage input terminal VIN and the voltage measurement terminal Vs decreases linearly and slowly within a unit time, gradually approaching 1Ω from 100Ω, thereby avoiding the situation where the resistance value jumps too fast and the measured voltage has an instantaneous overshoot.

[0049] In summary, this embodiment provides a circuit for reducing voltage overshoot during current test shifting. Figure 2 , the current measurement unit circuit in the traditional source measurement unit is often only provided with a detection resistor and a branch on-off switch in series in a single detection branch. When the branch on-off switches of different detection branches are directly controlled, there is a large difference in the resistance of the detected resistor used to measure the voltage, which can easily lead to current interruption or resistance mutation, and then cause the directly measured voltage value to overshoot, which is easy to damage the source measurement unit and the device under test. Compared with the current measurement unit circuit in the traditional source measurement unit, this embodiment is further provided with an impedance control circuit. When the current test gear is changed, the total impedance value at both ends of the voltage input terminal VIN and the voltage measurement terminal Vs decreases linearly and slowly within a unit time, and gradually changes from the resistance value of the detection resistor in one detection branch to the resistance value of the detection resistor in the detection branch to be measured, thereby effectively avoiding the current interruption or resistance mutation, and achieving the beneficial effect of keeping the measured voltage at both ends of the voltage input terminal VIN and the voltage measurement terminal Vs stable and with small fluctuations.

[0050] The specific structure of a circuit for reducing voltage overshoot during current test shifting provided by this embodiment will be described in further detail below:

[0051] In this embodiment, the impedance control circuits of the first detection branch, the second detection branch and the third detection branch are respectively provided with a first impedance control sub-circuit, a second impedance control sub-circuit and a third impedance control sub-circuit.

[0052] Taking the impedance control circuit of the first detection branch as an example, the first impedance control subcircuit is provided with a first resistor R 11 With the first P-channel junction field effect transistor M1, the first resistor R 11 The first end of the first resistor R is connected to the second end of the first branch on-off switch K1 in the first detection branch. 11 The second end is connected to the source of the first P-channel junction field effect transistor M1, the gate of the first P-channel junction field effect transistor M1 is connected to the first level control end, and the drain of the first P-channel junction field effect transistor M1 is connected to the voltage output end OUT.

[0053] The branch on-off switch K1 in the first detection circuit is closed, and the output of the first level control terminal Control1 is changed from a low level to a high level. After the first P-channel junction field effect transistor M1 is changed from a cut-off state to a conducting state, the current can flow through the first detection circuit, and at this time, the current in the first detection circuit only flows through the first detection resistor R1 and the first resistor R 11 .

[0054] Furthermore, a second resistor R is provided in the second impedance control subcircuit. 12 and the second P-channel junction field effect transistor M2, the second resistor R 12 The first end of the second resistor R 12 The second end is connected to the source of the second P-channel junction field effect transistor M2, the gate of the second P-channel junction field effect transistor M2 is connected to the second level control end, and the drain of the second P-channel junction field effect transistor M2 is connected to the voltage output end OUT.

[0055] Under the premise that the first P-channel junction field effect transistor M1 is in the on state, the output of the second level control terminal Control2 is changed from a low level to a high level. After the second P-channel junction field effect transistor M2 is changed from a cut-off state to a conducting state, the current in the first detection circuit flows through the first detection resistor R1 and the first parallel resistor R 11 With the second resistor R 12 .

[0056] Furthermore, a third resistor R is provided in the third impedance control subcircuit. 13and the third P-channel junction field effect transistor M3, the third resistor R 13 The first end of the third resistor R is connected to the second end of the first branch on-off switch K1 in the first detection branch. 13 The second end is connected to the source of the third P-channel junction field effect transistor M3, the gate of the third P-channel junction field effect transistor M3 is connected to the third level control end, and the drain of the third P-channel junction field effect transistor M3 is connected to the voltage output end OUT.

[0057] Under the premise that the first P-channel junction field effect transistor M1 and the second P-channel junction field effect transistor M2 are both in the on state, the output of the third level control terminal Control3 is changed from a low level to a high level. After the third P-channel junction field effect transistor M3 is changed from a cut-off state to a conducting state, the current in the first detection circuit flows through the first detection resistor R1 and the first parallel resistor R 11 , the second resistor R 12 With the third resistor R 13 .

[0058] It is worth noting that the impedance control circuit structure in the second detection branch and the third detection branch is exactly the same as the impedance control circuit structure in the first detection branch, with only the nominal values ​​of some electronic components being different. Therefore, the impedance control circuit structure in the second detection branch and the third detection branch will not be described again.

[0059] Preferably, taking the first detection branch as an example, the first resistor R in the first detection branch 11 , the second resistor R 12 With the third resistor R 13 The resistance value is limited to:

[0060] R 11 =10*R2,

[0061] R 12 =(R1+R2) / 2,

[0062] R 13 =1 / 10*R1,

[0063] That is, the first resistor R 11 The resistance value is greater than the second resistor R 12 , further the second resistor R 12 The resistance value is greater than the third resistor R 13 .

[0064] In summary, in this embodiment, a first impedance control sub-circuit, a second impedance control sub-circuit and a third impedance control sub-circuit are respectively provided in any detection branch. The operation principle of the impedance control circuit is further described in detail below by taking the switching from the second detection branch to the first detection branch as an example:

[0065] In the initial stage of switching from the second detection branch to the first detection branch, the second branch on-off switch K2 of the second detection branch is kept in a closed state, the first branch on-off switch K1 of the first detection branch is closed, and the second measurement switch K5 in the second voltage measurement loop is closed. At this time, the first level control end, the second level control end and the third level control end in the first detection branch all output a low level, that is, the first P-channel junction field effect transistor M1, the second P-channel junction field effect transistor M2 and the third P-channel junction field effect transistor M3 are all in a cut-off state, and the first detection branch is in a high-impedance state.

[0066] Then, the output of the first level control terminal Control1 is changed from low level to high level, and the first P-channel junction field effect transistor M1 is changed from cut-off state to on state. At this time, the first detection resistor R1 and the first resistor R 11 In series, and further connected in parallel with the second detection resistor R2 in the second detection branch, in the parallel circuit constructed by the first detection branch and the second detection branch, the voltages at both ends of each detection branch are equal. At the same time, in the first detection branch, the impedance measured at both ends of the voltage input terminal VIN and the voltage measurement terminal Vs is R1+R 11 .

[0067] Further, the output of the second level control terminal Control2 is changed from low level to high level, and the second P-channel junction field effect transistor M2 is changed from cut-off state to on state. At this time, the first detection resistor R1 in the first detection branch and the first resistor R 11 With the second resistor R 12 Further series connection makes the impedance measured between the voltage input terminal VIN and the voltage measurement terminal Vs equal to R1+[(R 11 *R 12 ) / (R 11 +R 12 )], that is, at this time, the impedance measured between the voltage input terminal VIN and the voltage measuring terminal Vs is further reduced.

[0068] Furthermore, the output of the third level control terminal Control3 is changed from a low level to a high level, and the third P-channel junction field effect transistor M3 is changed from a cut-off state to a conducting state. At this time, the first detection resistor R1 in the first detection branch and the first resistor R 11 , the second resistor R 12 and the second resistor R 13 Further series connection makes the impedance between the voltage input terminal VIN and the voltage measurement terminal Vs equal to R1+1 / [(1 / R 11 )+(1 / R 12 )+(1 / R 13)], that is, at this time, the impedance measured between the voltage input terminal VIN and the voltage measuring terminal Vs is further reduced.

[0069] It can be seen that in this embodiment, for the first detection branch to be measured, during the current measurement gear switching process, the impedance at both ends of the voltage input terminal VIN and the voltage measurement terminal Vs gradually decreases, thereby effectively avoiding the situation where the resistance value of the resistance to be measured jumps too quickly.

[0070] In this embodiment, the first impedance control sub-circuit, the second impedance control sub-circuit and the third impedance control sub-circuit are respectively provided with a P-channel junction field effect transistor driving circuit, and the P-channel junction field effect transistor driving circuit is used to drive the first P-channel junction field effect transistor M1, the second P-channel junction field effect transistor M2 and the third P-channel junction field effect transistor M3 to linearly convert from the cut-off state to the on state within a unit time, so that the impedance from the source to the drain of the first P-channel junction field effect transistor M1, the second P-channel junction field effect transistor M2 and the third P-channel junction field effect transistor M3 is linearly transformed.

[0071] Specifically, a P-channel junction field effect transistor drive circuit is implemented as follows: Figure 1 As shown in, taking the first impedance control sub-circuit in the first detection branch as an example, the P-channel junction field effect transistor drive circuit is provided with a first charge and discharge resistor R4 and a first timing capacitor C1, the first end of the first charge and discharge resistor R4 is connected to the first level control end Control1, the second end of the first charge and discharge resistor R4 is connected to the gate of the first P-channel junction field effect transistor M1, the first end of the first timing capacitor C1 is connected to the common node of the first charge and discharge resistor R4 and the first P-channel junction field effect transistor M1, and the second end of the first timing capacitor C1 is grounded.

[0072] In this embodiment, the first charge and discharge resistor R4 and the first timing capacitor C1 form an RC charge and discharge loop. When the output of the level control terminal changes from a low level to a high level, in the initial state, the voltage between the gate and the source of the P-channel junction field effect transistor is lower than the threshold voltage, the P-channel junction field effect transistor is in a cut-off state, and no current flows between the source and the drain of the P-channel junction field effect transistor. Subsequently, the level control terminal outputs a high level, and the first timing capacitor C1 is charged. As time goes by, the voltage between the gate and the source of the P-channel junction field effect transistor gradually rises. When the voltage between the gate and the source of the P-channel junction field effect transistor reaches the threshold voltage, the P-channel junction field effect transistor begins to conduct, and a current channel is formed between the source and the drain of the P-channel junction field effect transistor. As time goes on, the current channel between the source and the drain of the P-channel junction field effect transistor gradually increases, that is, the impedance between the source and the drain of the P-channel junction field effect transistor gradually decreases. Furthermore, the P-channel junction field effect transistor will enter the saturation region, and the current flowing between the source and the drain of the P-channel junction field effect transistor will no longer continue to increase, and it will enter the fully turned-on stage.

[0073] It can be seen that in this embodiment, the conversion of the P-channel junction field effect transistor from the cut-off state to the on state is a linear dynamic change process. Based on the P-channel junction field effect transistor driving circuit, the impedance between the source and the drain of the P-channel junction field effect transistor decreases slowly within a unit time. That is, taking the switching of the second detection branch to the first detection branch as an example, when the first impedance control sub-circuit, the second impedance control sub-circuit and the third impedance control sub-circuit of the first detection branch are turned on in sequence, the voltage input terminal VIN and the voltage measurement terminal V S The impedance at both ends decreases linearly, thereby achieving smooth shifting from the second detection branch to the first detection branch, and further avoiding large fluctuations in the resistance value, which may lead to current interruption or sudden change in resistance. Figure 4 When the above P-channel junction field effect transistor driving circuit is used, the voltage value from the gate to the source of the P-channel junction field effect transistor changes as follows: Figure 4 As shown, it increases in an exponential linear form, that is, the impedance between the source and the drain of the P-channel junction field effect transistor also changes in a linear form.

[0074] Specifically, in this embodiment, the switching time from the off state to the on state of the first P-channel junction field effect transistor M1 , the second P-channel junction field effect transistor M2 , and the third P-channel junction field effect transistor M3 is 5 ms respectively.

[0075] Another way to realize the P-channel junction field effect transistor drive circuit is as follows Figure 3 As shown, the P-channel junction field effect transistor driving circuit is provided with a second charging and discharging resistor R 41 , the second timing capacitor C11 The operational amplifier U1 has a second charging and discharging resistor R connected in series with the in-phase input terminal of the operational amplifier U1. 41 Then connected to the +15V power supply, the inverting input terminal of the operational amplifier U1 is connected to the level control terminal and the second timing capacitor R 41 The gate of the P-channel junction field effect transistor is connected to the first end of the second timing capacitor R 41 The second end of is connected to the output end of the operational amplifier U1.

[0076] In addition, the P-channel junction field effect transistor driving circuit is further provided with a first diode D1 and a second diode D2, wherein the anode of the first diode D1 is connected to the second charge and discharge resistor R 41 The cathode of the first diode D1 is grounded, and the anode of the second diode D2 is connected in parallel to the second timing capacitor C 11 The cathode of the second diode D2 is connected in parallel to the second timing capacitor C 11 The second end.

[0077] Similarly, in this embodiment, the second charge and discharge resistor R 41 With the second timing capacitor C 11 It forms an RC charge-discharge loop and uses the voltage following characteristic of the operational amplifier to realize the linear adjustment of the voltage value from the gate to the source of the P-channel junction field effect transistor. Figure 5 When the above P-channel junction field effect transistor driving circuit is used, the voltage value from the gate to the source of the P-channel junction field effect transistor changes as follows: Figure 5 As shown, it increases in a linear form with a fixed slope, thereby achieving precise control of the impedance between the source and the drain of the P-channel junction field effect transistor.

[0078] It is worth noting that the P-channel junction field effect transistor driving circuit structure in the remaining impedance control sub-circuit in the first detection branch, the second detection branch and the third detection branch is completely consistent with the P-channel junction field effect transistor driving circuit structure of the first impedance control sub-circuit in the first detection branch, only the nominal values ​​of some electronic components are different, so the remaining P-channel junction field effect transistor driving circuit structure in the first detection branch, the second detection branch and the third detection branch will not be repeated.

[0079] In this embodiment, a first voltage measurement circuit and a second voltage measurement circuit are respectively provided in the first detection branch, the second detection branch and the third detection branch. Taking the first detection branch as an example, the first end of the first voltage measurement circuit is connected to the second end of the first branch on-off switch K1, the second end of the first voltage measurement circuit is connected to the voltage measurement terminal Vs, the first end of the second voltage measurement circuit is connected to the voltage output terminal OUT, and the second end of the second voltage measurement circuit is connected to the voltage measurement terminal Vs.

[0080] Furthermore, a first voltage stabilizing resistor R is provided in series in the first voltage measurement circuit. 20 , a first measuring switch K4, and a first buffer operational amplifier U2. When the first measuring switch K4 is closed, the current value flowing only through the first detection resistor R1 can be obtained by measuring the voltage value at both ends of the voltage input terminal VIN and the voltage measuring terminal Vs. The second voltage measurement loop is provided with a second voltage stabilizing resistor R1 in series. 21 , a second measuring switch K5 and a second buffer operational amplifier U3. When the second measuring switch K5 is closed, the current value flowing through the overall impedance of the first detection branch can be obtained by measuring the voltage value across the voltage input terminal VIN and the voltage measuring terminal Vs.

[0081] It is worth noting that the structures of the first voltage measurement circuit and the second voltage measurement circuit in the second detection branch and the third detection branch are consistent with those of the first detection branch, and only the nominal values ​​of some electronic components are different. Therefore, the structures of the first voltage measurement circuit and the second voltage measurement circuit in the second detection branch and the third detection branch will not be described repeatedly. In one embodiment, the first detection branch, the second detection branch, and the second voltage measurement circuit in the third detection branch can share a line, see Figure 1 .

[0082] In the present embodiment, taking the switching from the second detection branch to the first detection branch as an example, at the initial stage of switching from the second detection branch to the first detection branch, the first branch on-off switch K1 of the first detection branch is closed, the second measurement switch K5 in the second voltage measurement loop is closed, and the first measurement switch K4 in the first voltage measurement loop is disconnected, and then the first level control terminal, the second level control terminal and the third level control terminal in the first detection branch are enabled to output high levels in sequence. In this process, the voltage value measured across the voltage input terminal VIN and the voltage measurement terminal Vs is actually the voltage value of the overall impedance of the first detection branch, and then when the overall impedance of the first detection branch changes slowly linearly, the voltage value measured across the voltage input terminal VIN and the voltage measurement terminal Vs can maintain a smooth transition. When the first impedance control subcircuit, the second impedance control subcircuit and the third impedance control subcircuit of the first detection branch have completed the impedance adjustment operation in sequence, the second measurement switch K5 in the second voltage measurement loop in the first detection branch is disconnected, and the first measurement switch K4 in the first voltage measurement loop is closed, so that the voltage value measured at both ends of the voltage input terminal VIN and the voltage measurement terminal Vs is actually the voltage value of the first detection resistor R1, thereby preventing the on-resistance of the P-channel junction field effect transistor in the impedance control circuit from being transmitted into the voltage measurement loop to cause voltage measurement error. At the same time, because the actual resistance value of the on-resistance of the P-channel junction field effect transistor is relatively small, when the second measurement switch K5 and the first measurement switch K4 are switched, neither measurement jitter nor measurement error will be caused, which fully meets the test accuracy requirements of the source measurement unit.

[0083] Second embodiment

[0084] This embodiment provides a method for reducing voltage overshoot during current test gear shifting, which is applied to a circuit for reducing voltage overshoot during current test gear shifting described in any one of the first embodiments. In this embodiment, it is assumed that there are three groups of detection branches, and the example of switching from the second detection branch to the first detection branch is used for explanation. Figure 6 , specifically including the following steps:

[0085] S1: In the early stage of switching from the second detection branch to the first detection branch, keep the second branch on-off switch K2 of the second detection branch and the first measurement switch K6 in the first voltage measurement loop still in the closed state, and the fourth level control terminal Control4, the fifth level control terminal Control5 and the sixth level control terminal Control6 of the second detection branch still output a high level. Then close the first branch on-off switch K1 of the first detection branch, open the first measurement switch K4 in the first voltage measurement loop, close the second measurement switch K5 in the second voltage measurement loop, and wait for 10ms.

[0086] S2: Adjust the first level control terminal Control1 in the first impedance control sub-circuit of the first detection branch from a low level output to a high level, and wait for 10ms. During this process, the voltage from the gate to the source of the first P-channel junction field effect transistor M1 in the first impedance control sub-circuit gradually increases, so that the impedance from the source to the drain of the first P-channel junction field effect transistor M1 gradually decreases until the first P-channel junction field effect transistor M1 is fully turned on.

[0087] S3: Then adjust the second level control terminal Control2 in the second impedance control sub-circuit of the first detection branch from a low level output to a high level, and wait for 10ms. During this process, the voltage from the gate to the source of the second P-channel junction field effect transistor M2 in the second impedance control sub-circuit gradually increases, so that the impedance from the source to the drain of the second P-channel junction field effect transistor M2 gradually decreases until the second P-channel junction field effect transistor M2 is fully turned on.

[0088] S4: Then adjust the third level control terminal Control3 in the third impedance control sub-circuit of the first detection branch from a low level output to a high level, and wait for 10ms. During this process, the voltage from the gate to the source of the third P-channel junction field effect transistor M3 in the third impedance control sub-circuit gradually increases, so that the impedance from the source to the drain of the third P-channel junction field effect transistor M3 gradually decreases until the third P-channel junction field effect transistor M3 is fully turned on.

[0089] In the process S2-S4, the voltage value measured between the voltage input terminal VIN and the voltage measurement terminal Vs is actually the voltage value of the overall impedance of the first detection branch, and the overall impedance of the first detection branch changes linearly and slowly, gradually approaching the resistance value of the first detection resistor R1.

[0090] S5: Close the first measuring switch K4 in the first voltage measuring loop in the first detection branch, and open the second measuring switch K5 in the second voltage measuring loop.

[0091] S6: disconnect the branch on-off switch K2 of the second detection branch from the first measurement switch K6 in its first voltage measurement loop, and change the outputs of the fourth level control terminal Control4, the fifth level control terminal Control5 and the sixth level control terminal Control6 of the second detection branch from high level to low level.

[0092] S7: By measuring the voltage values ​​across the voltage input terminal VIN and the voltage measuring terminal Vs, and calculating the current parameter flowing through the first detection resistor R1 in the first detection branch based on Ohm's law, the current gear shifting and current testing operations are completed.

[0093] In summary, this embodiment provides a method for reducing voltage overshoot during current test gear shifting. Through the impedance control effect of the first impedance control sub-circuit, the second impedance control sub-circuit and the third impedance control sub-circuit in the detection branch to be measured, a linear and slow adjustment of the impedance of the detection branch to be measured is achieved to avoid current interruption or excessively rapid changes in the impedance of the current detection loop, thereby keeping the measured voltage value stable, preventing overvoltage, and ensuring the test safety of the source measurement unit and the device under test.

[0094] The embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they still fall within the protection scope of the present invention.

[0095] In the description of the present application, it should be understood that the orientations or positional relationships indicated by the terms "first end", "second end", "first", "second", "third", etc. are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

Claims

1. A circuit for reducing voltage overshoot during current testing gear shifting, characterized in that: At least two groups of detection branches are included; The plurality of detection branches are arranged in parallel, the first ends of the plurality of detection branches are electrically connected to the voltage input end, and the second ends of the plurality of detection branches are electrically connected to the voltage output end; A plurality of the detection branches are respectively provided with detection resistors, branch on-off switches and impedance control circuits connected in series in sequence, the resistance values ​​of the detection resistors in the detection branches of different groups are different from each other, the branch on-off switches are used to limit the working state of the detection branch in which they are located, and the impedance control circuit is used to adjust the change of the overall impedance value of the detection branch in which they are located within a unit time; The detection branch is configured to respectively realize on-off adjustment of the corresponding two groups of detection branches through switching control of the branch on-off switches in the two groups of detection branches, and utilize the impedance control circuit in the detection branch to be measured to adjust the overall branch impedance value of the detection branch to be measured to change linearly within unit time.

2. The circuit for reducing voltage overshoot during current test shifting as claimed in claim 1, characterized in that: The impedance control circuit is provided with a first impedance control sub-circuit, a second impedance control sub-circuit and a third impedance control sub-circuit; The first impedance control subcircuit is provided with a first resistor and a first P-channel junction field effect transistor, the first end of the first resistor is connected to the second end of the branch on-off switch in the detection branch where the first resistor is located, the second end of the first resistor is connected to the source of the first P-channel junction field effect transistor, the gate of the first P-channel junction field effect transistor is connected to the first level control terminal, and the drain of the first P-channel junction field effect transistor is connected to the voltage output terminal; The first impedance control sub-circuit is configured such that when the branch in the detection branch to be measured in which the first impedance control sub-circuit is located is opened or closed, the output of the first level control terminal is changed from a low level to a high level, the first P-channel junction field effect transistor is changed from a cut-off state to a conducting state, and the current in the detection branch to be measured flows through the first resistor.

3. The circuit for reducing voltage overshoot during current test shifting as claimed in claim 2, characterized in that: The second impedance control subcircuit is provided with a second resistor and a second P-channel junction field effect transistor, the first end of the second resistor is connected to the second end of the branch on-off switch in the detection branch where the second resistor is located, the second end of the second resistor is connected to the source of the second P-channel junction field effect transistor, the gate of the second P-channel junction field effect transistor is connected to the second level control terminal, and the drain of the second P-channel junction field effect transistor is connected to the voltage output terminal; The second impedance control sub-circuit is configured such that, under the premise that the first P-channel junction field effect transistor is in the on state, the output of the second level control terminal is changed from a low level to a high level, the second P-channel junction field effect transistor is changed from a cut-off state to an on state, and the current in the detection branch to be measured flows through the first resistor and the second resistor connected in parallel respectively.

4. The circuit for reducing voltage overshoot during current test shifting as claimed in claim 3, characterized in that: The third impedance control subcircuit is provided with a third resistor and a third P-channel junction field effect transistor, the first end of the third resistor is connected to the second end of the branch on-off switch in the detection branch where the third resistor is located, the second end of the third resistor is connected to the source of the third P-channel junction field effect transistor, the gate of the third P-channel junction field effect transistor is connected to the third level control terminal, and the drain of the third P-channel junction field effect transistor is connected to the voltage output terminal; The third impedance control subcircuit is configured such that, under the premise that the first P-channel junction field effect transistor and the second P-channel junction field effect transistor are both in the on state, the output of the third level control terminal is changed from a low level to a high level, the third P-channel junction field effect transistor is changed from a cut-off state to an on state, and the current in the detection branch to be measured flows through the first resistor, the second resistor and the third resistor connected in parallel respectively.

5. The circuit for reducing voltage overshoot during current test shifting as claimed in claim 4, characterized in that: The detection branch includes a first detection branch and a second detection branch, and the resistance values ​​of the first resistor, the second resistor and the third resistor in the first detection branch are limited to: R 11 =10*R2, R 12 =(R1+R2) / 2, R 13 =1 / 10*R1, Wherein, R1 is the detection resistor in the first detection branch, R2 is the detection resistor in the second detection branch, R 11 is the first resistor in the first impedance control subcircuit, R 12 is the second resistor in the second impedance control sub-circuit, R 13 It is the third resistor in the third impedance control sub-circuit.

6. The circuit for reducing voltage overshoot during current test shifting as claimed in claim 4, characterized in that: The first impedance control subcircuit, the second impedance control subcircuit and the third impedance control subcircuit are further provided with a P-channel junction field effect transistor driving circuit respectively, and the P-channel junction field effect transistor driving circuit is used to drive the first P-channel junction field effect transistor, the second P-channel junction field effect transistor and the third P-channel junction field effect transistor to linearly convert from a cut-off state to a conducting state within a unit time, respectively, so that the impedance from the source to the drain of the first P-channel junction field effect transistor, the second P-channel junction field effect transistor and the third P-channel junction field effect transistor is linearly transformed respectively; Furthermore, the conversion time from the cut-off state to the on state of the first P-channel junction field effect transistor, the second P-channel junction field effect transistor and the third P-channel junction field effect transistor is 5 ms respectively.

7. The circuit for reducing voltage overshoot during current test shifting as claimed in claim 6, characterized in that: The P-channel junction field effect transistor drive circuit is provided with a first charge and discharge resistor and a first timing capacitor, wherein the first end of the first charge and discharge resistor is connected to the level control end, the second end of the first charge and discharge resistor is connected to the gate of the P-channel junction field effect transistor, the first end of the first timing capacitor is connected to the common node of the first charge and discharge resistor and the P-channel junction field effect transistor, and the second end of the first timing capacitor is grounded.

8. The circuit for reducing voltage overshoot during current test shifting as claimed in claim 6, characterized in that: The P-channel junction field effect transistor driving circuit is provided with a second charge and discharge resistor, a second timing capacitor and an operational amplifier, the in-phase input terminal of the operational amplifier is connected in series with the second charge and discharge resistor and then connected to a +15V power supply, the inverting input terminal of the operational amplifier is respectively connected to the level control terminal and the first terminal of the second timing capacitor, and the gate of the P-channel junction field effect transistor is respectively connected to the second terminal of the second timing capacitor and the output terminal of the operational amplifier; A first diode and a second diode are also provided, wherein the anode of the first diode is connected to the common node of the second charge and discharge resistor and the operational amplifier, the cathode of the first diode is grounded, the anode of the second diode is connected in parallel to the first end of the second timing capacitor, and the cathode of the second diode is connected in parallel to the second end of the second timing capacitor.

9. The circuit for reducing voltage overshoot during current test shifting as claimed in claim 1, characterized in that: A first voltage measurement loop and a second voltage measurement loop are respectively provided in the plurality of detection branches, wherein the first end of the first voltage measurement loop is connected to the second end of the branch on-off switch of the detection branch in which it is located, the second end of the first voltage measurement loop is connected to the voltage measurement end, the first end of the second voltage measurement loop is connected to the voltage output end, and the second end of the second voltage measurement loop is connected to the voltage measurement end; The first voltage measurement loop is provided with a first measurement switch and a first buffer operational amplifier connected in series, and the first measurement switch is used to limit the working state of the first voltage measurement loop; the second voltage measurement loop is provided with a second measurement switch and a second buffer operational amplifier connected in series, and the second measurement switch is used to limit the working state of the second voltage measurement loop.

10. A method for reducing voltage overshoot during current test shifting, characterized in that: A circuit for reducing voltage overshoot during current test shifting as claimed in any one of claims 1 to 9, wherein the detection branch is set to include at least a first detection branch and a second detection branch, and when switching from the second detection branch to the first detection branch, the circuit comprises the following steps: S1: Keep the branch on-off switch of the second detection branch and the first measurement switch in a closed state, and the fourth level control terminal, the fifth level control terminal and the sixth level control terminal of the second detection branch are at a high level, and close the branch on-off switch of the first detection branch and the second measurement switch; S2: Adjust the first level control terminal in the first impedance control subcircuit of the first detection branch from a low level output to a high level output, and wait for 10ms; S3: Adjust the second level control terminal in the second impedance control subcircuit of the first detection branch from a low level output to a high level output, and wait for 10ms; S4: adjusting the third level control terminal in the third impedance control subcircuit of the first detection branch from a low level output to a high level output, and waiting for 10 ms; S5: opening the second measuring switch of the first detection branch and closing the first measuring switch of the first detection branch; S6: disconnecting the branch on-off switch of the second detection branch from the first measurement switch, and outputting the fourth level control terminal, the fifth level control terminal and the sixth level control terminal of the second detection branch to a low level; S7: Measure and calculate the current parameter flowing through the detection resistor in the first detection branch from the voltage input terminal and the voltage measurement terminal.

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