Test circuit and test system of power device
By designing an auxiliary device in parallel with the device to be tested, it ensures that it remains in conduction state and reduces switching losses. It solves the problems of heat generation and humidity changes in the device to be tested in the active switching mode test, and achieves stability in the test environment Sex and accuracy.
Patent Information
- Application Number
- CN202410663469.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-27
- Publication Date
- 2024-12-13
AI Technical Summary
In the active switching method test of semiconductor power devices, the device to be tested generates switching losses during the switching process, resulting in heat generation and humidity changes, and deviating from the test environment target.
Design a test circuit in which the first auxiliary device and the second auxiliary device are connected in parallel with the device to be tested. The auxiliary device remains in a conductive state when the device to be tested is turned on, ensuring that the device to be tested is switched under zero voltage condition, reducing switching losses .
By controlling the loss of the device to be tested, maintaining the high temperature and high humidity conditions in the test environment, ensuring the accuracy and reliability of the test results.
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Figure CN119125817A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a test circuit for a power device. Background Art
[0002] The reliability test of semiconductor power devices includes not only static tests, such as high temperature reverse bias test (High Temperature Reverse Bias, HTRB), high temperature gate bias test (High Temperature Gate Bias, HTGB), etc., but also dynamic tests, which test some key parameters of semiconductor power devices during the opening or closing process. Especially for wide bandgap power devices made of silicon carbide (SiC) and gallium nitride (GaN), traditional tests cannot identify the impact of certain new faults, so new test methods need to be customized for specific applications. Since these faults have an impact on practical applications, according to the definition of the AQG324 standard, dynamic high humidity and high temperature reverse bias (H3TRB) or dynamic reverse bias (Dynamic Reverse Bias, DRB) is used to fill this gap to test whether the device meets certain dv / dt conditions. During the test process, in addition to electrical conditions, the more stringent requirement is the need to superimpose high temperature and high humidity environments.
[0003] According to the AQG324 standard, there are two ways to implement this dynamic test in a dual 85 environment, one is the passively switched method and the other is the active switched method.
[0004] In the passive switching mode, the gate of the device under test is applied with a turn-off level, such as Vgs = 0V or negative voltage, so that the device under test is in the off state. The device under test is directly connected in parallel to the two ends of the auxiliary device, and the switching of the auxiliary device brings a dynamically changing reverse bias voltage to the device under test. Because the device under test is in the off state throughout the process, it is called a passive switching mode.
[0005] In the active switching mode, two devices under test form a half-bridge topology. If a complementary opening drive signal is given to the gates of the two devices under test at a certain switching frequency, a dynamically changing reverse bias voltage can also be obtained at both ends of the devices under test. Because the gate of the device under test will switch back and forth between high and low levels, the device under test will also be in the on or off state accordingly, so it is called an active switching mode.
[0006] The active switching method requires applying high and low levels to the gate of the device under test, so that the device under test is in a high-frequency switching state. In addition to the dynamic reverse bias voltage, the assessment of the gate dynamic voltage (Dynamic Gate Stress, DGS) is also added, thereby allowing the device under test to be tested more comprehensively and fully.
[0007] However, in the active switching test of power devices, the device under test (DUT) will generate switching losses during the switching process. This switching loss causes the DUT to heat up, resulting in a decrease in the local humidity of the DUT, thereby deviating from the test environment target. Summary of the invention
[0008] In view of the above problems, the purpose of the present application is to provide a test circuit for a semiconductor power device, which controls the loss of the device under test during the switching test of the device under test to reduce the self-heating of the device under test, thereby making the test environment of the device under test meet the requirements.
[0009] According to one embodiment of the present invention, a test circuit is provided, comprising: a first auxiliary device, having a first end coupled to a power supply voltage end, and a second end coupled to a test connection end; and a second auxiliary device, having a first end coupled to the test connection end, and a second end coupled to ground; wherein the first auxiliary device can be connected in parallel to a first device under test, and the second auxiliary device can be connected in parallel to a second device under test; wherein: the first auxiliary device remains in a conducting state when the first device under test performs a conducting action; and the second auxiliary device remains in a conducting state when the second device under test performs a conducting action.
[0010] According to one embodiment of the present invention, a test system is provided, including the test circuit as described above, and also including: a first device under test, having a first end coupled to a power supply voltage end, and a second end coupled to a test connection end; and a second device under test, having a first end coupled to the test connection end, and a second end coupled to ground. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings:
[0012] Figure 1 is a schematic diagram of a circuit structure of a test system 10 according to an embodiment of the present invention;
[0013] Figure 2 Schematic diagram of waveforms of a first test auxiliary control signal GA1, a second test auxiliary control signal GA2, a first test control signal G1, and a second test control signal G2 according to an embodiment of the present invention;
[0014] Figure 3 Schematic diagram of waveforms of a first test auxiliary control signal GA1 , a second test auxiliary control signal GA2 , a first test control signal G1 , and a second test control signal G2 according to an embodiment of the present invention. DETAILED DESCRIPTION
[0015] The specific implementation of the present application is further described in detail below in conjunction with the drawings and examples.
[0016] Figure 1 1 is a schematic diagram of a circuit structure of a test system 10 according to an embodiment of the present invention. The test system 10 includes a test circuit 100 , a first device under test 111 , a second device under test 112 , and a power supply circuit 103 .
[0017] exist Figure 1 In the embodiment, the test circuit 100 includes a first auxiliary device 101 and a second auxiliary device 102 .
[0018] The first auxiliary device 101 is connected in parallel to the first device under test 111. The second auxiliary device 102 is connected in parallel to the second device under test 112. The first auxiliary device 101 and the second auxiliary device 102 are coupled in series between the power supply voltage terminal 104 and the ground 105 to form a half-bridge circuit. The first device under test 111 and the second device under test 112 are connected in series between the power supply voltage terminal 104 and the ground 105 to form a half-bridge circuit. The connection point between the first auxiliary device 101 and the second auxiliary device 102 is coupled to the connection point between the first device under test 111 and the second device under test 112 to form a test connection terminal 108.
[0019] The first auxiliary device 101 receives the first test auxiliary control signal GA1, and the second auxiliary device 102 receives the second test auxiliary control signal GA2. In one embodiment of the present invention, the auxiliary device 101 and the auxiliary device 102 are complementarily turned on and off under the control of the test auxiliary control signals GA1 and GA2, respectively.
[0020] The first DUT 111 receives the first test control signal G1, and the second DUT 112 receives the second test control signal G2. In one embodiment of the present invention, the first DUT 111 and the second DUT 112 are alternately turned on and off under the control of the first test control signal G1 and the second test control signal G2, respectively.
[0021] exist Figure 1 In the embodiment, the power circuit 103 includes a voltage source 106 and a filter circuit 107. The voltage source 106 is coupled between the power voltage terminal 104 and the ground 105 to provide a power voltage Vin. The filter circuit 107 includes a capacitor C1 and a resistor R1 to filter the power voltage Vin.
[0022] Figure 2 1 is a waveform diagram of a first test auxiliary control signal GA1, a second test auxiliary control signal GA2, a first test control signal G1, and a second test control signal G2 according to an embodiment of the present invention. Figure 2 In the embodiment, the high level of each signal corresponds to the on-state of the device controlled by the signal, and the low level of each signal corresponds to the off-state of the device controlled by the signal. It should be understood that in different embodiments, the level of the signal and the switch state of the device controlled by it may be different. For example, the high level of the signal may also correspond to the off-state of the device, and the low level of the signal may also correspond to the on-state of the device. Moreover, the high and low level states of the signal are also relative.
[0023] like Figure 2 As shown, at time t1, the first test auxiliary control signal GA1 jumps to a high level, controlling the first auxiliary device 101 to turn on, while the second auxiliary device 102, the first device under test 111 and the second device under test 112 are in the off state. When the first auxiliary device 101 is turned on, the voltage between the power supply voltage terminal 104 and the test connection terminal 108 is close to zero, that is, the voltage across the first device under test 111 is close to zero. At time t2, the first test control signal G1 controls the first device under test 111 to turn on, that is, the first device under test 111 is turned on under zero voltage conditions at both ends. It should be understood that the switching loss of the device is mainly determined by the product of the voltage across the device and the current flowing through the device at the switching moment. When the first device under test 111 is turned on at zero voltage, its conduction loss is close to zero. At time t3, the first test control signal G1 controls the first device under test 111 to turn off. At this time, the first auxiliary device 101 is still in the on state, and the voltage across the first device under test 111 is still zero. Therefore, the first device under test 111 is turned off under zero voltage condition, and its turn-off loss is close to zero. After the first device under test 111 is turned off, at time t4, the first auxiliary device 101 is turned off.
[0024] Similarly, the second device under test 112 is also turned on at zero voltage and turned off at zero voltage, and its switching loss is close to zero. Specifically, at time t5, the second test auxiliary control signal GA2 jumps to a high level, controls the second auxiliary device 102 to turn on, and the voltage between the test connection terminal 108 and the ground 105 is close to zero, that is, the voltage across the second device under test 112 is close to zero. At time t6, the second test control signal G2 controls the second device under test 112 to turn on, and the second device under test 112 is turned on under zero voltage conditions, and its conduction loss is close to zero. At time t7, the second test control signal G2 controls the second device under test 112 to turn off. At this time, the second auxiliary device 102 is still in the on state, and the voltage across the second device under test 112 is still zero. Therefore, the second device under test 112 is turned off under zero voltage conditions, and its turn-off loss is close to zero. After the second device under test 112 is turned off, at time t8, the second auxiliary device 102 is turned off.
[0025] exist Figure 2 In the embodiment, the first auxiliary device 101 and the second auxiliary device 102 are complementary to each other, that is, after the first auxiliary device 101 is turned off, the second auxiliary device 102 is turned on; after the second auxiliary device 102 is turned off, the first auxiliary device 101 is turned on. In order to prevent the first auxiliary device 101 and the second auxiliary device 102 from being turned on at the same time, that is, being directly turned on, there is a dead time between the two, such as Figure 2 Time t4-t5 is shown.
[0026] exist Figure 1 In the embodiment, the first auxiliary device 101, the second auxiliary device 102, the first device under test 111 and the second device under test 112 are all N-type switches, which are turned on when a high level is applied to the control terminal (i.e., the voltage at the control terminal is greater than the on-threshold of the switch), and are turned off when a low level is applied to the control terminal (i.e., the voltage at the control terminal is less than the on-threshold of the switch). It should be understood that when the first auxiliary device 101, the second auxiliary device 102, the first device under test 111 and the second device under test 112 are all P-type switches, the situation is just the opposite. In some embodiments, the first auxiliary device 101 can be a P-type switch, and the second auxiliary device 102 can be an N-type switch. Accordingly, the control signals of the first auxiliary device 101 and the second auxiliary device 102 should also be adaptively adjusted. Similarly, the first switch under test 111 can be a P-type switch, and the second switch under test 112 can be an N-type switch.
[0027] In an embodiment of the present invention, the first device under test 111 and the second device under test 112 may be power electronic switching devices composed of wide bandgap semiconductors such as SiC devices or GaN devices, such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or IGBT (Isolated Gate Bipolar Transistor). In some embodiments, the first device under test 111 and the second device under test 112 are SiC single tubes or GaN single tubes. In some embodiments, the first device under test 111 and the second device under test 112 are SiC power modules or GaN power modules. The first auxiliary device 101 and the second auxiliary device 102 may be single tubes or power modules of the same type as the device under test, or may be single tubes or power modules with a higher withstand voltage rating.
[0028] exist Figure 1 In an embodiment, the first auxiliary device 101, the second auxiliary device 102, the first device under test 111, and the second device under test 112 are power devices of the same type. In some embodiments, the first auxiliary device 101, the second auxiliary device 102, the first device under test 111, and the second device under test 112 may be power devices of different types. For example, the first auxiliary device 101 and the second auxiliary device 102 may be IGBTs, while the first device under test 111 and the second device under test 112 may be MOSFETs, or vice versa. In some embodiments, the first auxiliary device 101 and the second auxiliary device 102 may also be power devices of different types, for example, the first auxiliary device 101 may be a MOSFET, while the second auxiliary device 102 is an IGBT. Similarly, the first device under test 111 and the second device under test 112 may also be power devices of different types.
[0029] exist Figure 1 In the embodiment, in order to improve the test efficiency, two devices under test are formed into a half-bridge structure, and the performance of the devices under test is tested in a switching manner. It should be understood that the present invention is also applicable to testing a single device under test. That is, the principle of the present invention can be used to connect a single device under test in parallel to the first auxiliary device 101 or to the second auxiliary device 102, and the device under test can be switched to zero voltage by controlling the switching of the first auxiliary device 101 or the second auxiliary device 102.
[0030] Figure 3 1 is a waveform diagram of a first test auxiliary control signal GA1, a second test auxiliary control signal GA2, a first test control signal G1, and a second test control signal G2 according to an embodiment of the present invention. Figure 3In the embodiment, in order to increase the frequency of dynamic gate stress (DGS) assessment on the device under test, the first test control signal G1 and the second test control signal G2 respectively control the first device under test 111 and the second device under test 112 to switch multiple times. Figure 3 As shown, during the period when the first test control signal G1 jumps multiple times to control the first device under test 111 to switch multiple times, the first auxiliary device 101 always remains on to ensure the zero voltage switching of the first device under test 111, so as to reduce the switching loss of the first device under test 111. Similarly, during the period when the second test control signal G2 jumps multiple times to control the second device under test 112 to switch multiple times, the second auxiliary device 102 always remains on to ensure the zero voltage switching of the second device under test 112, so as to reduce the switching loss of the second device under test 112.
[0031] In one embodiment, the first auxiliary device 101 and the second auxiliary device 102 are each turned on and off with a duty cycle of 50%.
[0032] In the embodiment of the present invention, the test system 10 further includes a switch signal circuit 109. The first test auxiliary control signal GA1, the second test auxiliary control signal GA2, the first test control signal G1 and the second test control signal G2 are generated by the switch signal circuit 109. In one embodiment, the switch signal circuit 109 provides a square wave signal to control each power device, and the duty cycle and frequency of the square wave signal are controllable.
[0033] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.
Claims
1. A test circuit, comprising: A first auxiliary device having a first terminal coupled to the power supply voltage terminal and a second terminal coupled to the test connection terminal; as well as A second auxiliary device, having a first end coupled to the test connection end, and a second end coupled to ground; Wherein, the first auxiliary device may be connected in parallel to the first device under test, and the second auxiliary device may be connected in parallel to the second device under test; in: The first auxiliary device remains in a conducting state when the first device under test performs a conducting action; and The second auxiliary device remains in a conducting state when the second device under test performs a conducting action.
2. The test circuit as claimed in claim 1, wherein: The first auxiliary device remains in a conducting state when the first device under test performs a shut-down action.
3. The test circuit as claimed in claim 1, wherein: The second auxiliary device remains in a conducting state when the second device under test performs a shut-down action. 4 . The test circuit as claimed in claim 1 , wherein the first auxiliary device comprises a metal semiconductor oxide field effect transistor.
5. The test circuit as claimed in claim 1, wherein the second auxiliary device comprises a metal semiconductor oxide field effect transistor.
6. The test circuit of claim 1, wherein the first auxiliary device comprises an insulated gate bipolar transistor.
7. The test circuit of claim 1, wherein the second auxiliary device comprises an insulated gate bipolar transistor.
8. A test system, comprising the test circuit according to any one of claims 1 to 7, further comprising: A first device under test has a first terminal coupled to a power supply voltage terminal and a second terminal coupled to a test connection terminal; as well as The second device under test has a first end coupled to the test connection end and a second end coupled to the ground.
9. The test system of claim 8, further comprising a power supply circuit, the power supply circuit comprising a voltage source.
10. The test system as described in claim 8 further includes a switching signal circuit, which provides a first test auxiliary control signal, a second test auxiliary control signal, a first test control signal and a second test control signal for controlling the first auxiliary device, the second auxiliary device, the first device to be tested and the second device to be tested respectively.