A GaN device near-junction region thermal resistance test method and computer equipment

Abstract

The present invention discloses a method and computer equipment for testing the thermal resistance of a GaN device near junction region, the method comprising: using the same manufacturing process as the GaN device to be tested to manufacture a first test structure and a second test structure, the first test structure comprising a substrate layer, an AlN buffer layer, and a GaN layer, and the second test structure comprising a substrate layer; using the 3ω method to test the first test structure to obtain a comprehensive thermal conductivity, and calculating the on-chip thermal resistance of the GaN device; using the 3ω method to test the second test structure to obtain a comprehensive thermal conductivity, and calculating the bulk thermal resistance of the substrate layer; according to the 3ω method test results of the first test structure and the second test structure, calculating the comprehensive thermal conductivity of the GaN layer, and according to the comprehensive thermal conductivity of the GaN layer, calculating the structural thermal resistance of the GaN layer; based on the on-chip thermal resistance of the GaN device, the bulk thermal resistance of the substrate layer, and the structural thermal resistance of the GaN layer, calculating the contact thermal resistance of the AlN buffer layer. The present invention can efficiently test and obtain the thermal resistance of different material layers in the near junction region of the GaN device.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor thermal detection, and in particular relates to a GaN device near-junction region thermal resistance testing method and computer equipment. Background Art

[0002] GaN devices have the advantages of high electron mobility and large output current, but they will generate a lot of Joule heat when working at high current density, and the device heat source channel temperature will be much higher than the ambient temperature, which will have a great impact on the material and electrical properties of the device. Among them, the near-junction thermal resistance is one of the key parameters that directly affects the heat dissipation and actual operating temperature of GaN devices. How to reduce the near-junction thermal resistance of GaN devices has become a research hotspot that the industry focuses on. Among them, how to achieve accurate detection of the near-junction thermal resistance is an important basis for carrying out GaN device thermal management, thermal reliability evaluation, and thermal performance optimization design.

[0003] The existing technology uses the 3ω method to measure the temperature rise curve of the GaN device, and realizes the on-chip thermal resistance measurement of the GaN device by corresponding the slope difference in the curve with the device material structure. However, this method takes a long time to test, and because the inflection point of the temperature rise curve is not clear enough, it is difficult to determine the thermal resistance of different material layers in the near-junction area of ​​the device. Summary of the invention

[0004] The purpose of the present invention is to provide a method for testing the thermal resistance of a GaN device near the junction region, a computer device, a computer-readable storage medium and a computer program product, which can efficiently test and obtain the thermal resistance of different material layers in the near-junction region of a GaN device.

[0005] In order to achieve the above object, one aspect of the present invention provides a method for testing the near-junction thermal resistance of a GaN device, comprising:

[0006] Step S1: a thermal resistance test structure is manufactured by adopting the same manufacturing process as the GaN device to be tested, wherein the thermal resistance test structure includes a first test structure and a second test structure, wherein the first test structure includes a substrate layer, an AlN buffer layer arranged on the substrate layer, and a GaN layer arranged on the AlN buffer layer, and the second test structure includes a substrate layer, and metal test electrodes are arranged on the surfaces of the first test structure and the second test structure;

[0007] Step S2: The first test structure is tested using the 3ω method to obtain the comprehensive thermal conductivity of the first test structure. The on-chip thermal resistance of the GaN device is calculated as follows:

[0008]

[0009] in, is the thickness of the first test structure, is the comprehensive thermal conductivity of the first test structure, is the on-chip thermal resistance of the GaN device;

[0010] Step S3: The second test structure is tested using the 3ω method to obtain the comprehensive thermal conductivity of the second test structure. The bulk thermal resistance of the substrate layer is calculated as follows:

[0011]

[0012] in, is the thickness of the second test structure, is the comprehensive thermal conductivity of the second test structure, is the bulk thermal resistance of the substrate layer;

[0013] Step S4: According to the 3ω method test results of the first test structure and the second test structure, the comprehensive thermal conductivity of the GaN layer is calculated as follows:

[0014]

[0015] in, is the temperature rise of the metal test electrode when testing the first test structure, The temperature rise of the metal test electrode when testing the second test structure, is the resistance of the metal test electrode on the surface of the first test structure, is the peak value of the driving current when testing the first test structure, is the width of the metal test electrode, is the thickness of the GaN layer, is the comprehensive thermal conductivity of the GaN layer,

[0016] According to the comprehensive thermal conductivity of the GaN layer, the structural thermal resistance of the GaN layer is calculated as follows:

[0017] ,

[0018] in, is the structural thermal resistance of the GaN layer;

[0019] Step S5: Based on the on-chip thermal resistance of the GaN device, the bulk thermal resistance of the substrate layer, and the structural thermal resistance of the GaN layer, the contact thermal resistance of the AlN buffer layer is calculated as follows:

[0020]

[0021] in, is the thermal contact resistance of the AlN buffer layer.

[0022] Another aspect of the present invention provides a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0023] Another aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when executed by a processor.

[0024] Another aspect of the present invention provides a computer program product, comprising a computer program, which implements the steps of the above method when executed by a processor.

[0025] The test method, computer device, computer-readable storage medium and computer program product of the near-junction region thermal resistance of the GaN device according to the above aspects of the present invention can efficiently obtain the on-chip thermal resistance of the near-junction region of the GaN device, the bulk thermal resistance of the substrate layer, the structural thermal resistance of the GaN layer, and the contact thermal resistance of the AlN buffer layer, thereby obtaining the thermal resistance of different material layers in the near-junction region of the GaN device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings used in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work:

[0027] Figure 1 is a flow chart of a method for testing the near-junction thermal resistance of a GaN device according to an embodiment of the present invention;

[0028] Figure 2 It is a schematic diagram of the structure of the near-junction region of a GaN device;

[0029] Figure 3 is a schematic diagram of a thermal resistance test structure according to an embodiment of the present invention;

[0030] Figure 4 It is a structural diagram of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] In view of the difficulty in testing the thermal resistance of the near-junction region of GaN devices in the prior art, an embodiment of the present invention provides a method for thermal resistance of the near-junction region of GaN devices. According to the structural characteristics of the GaN device, two test structures, a substrate and a substrate + AlN buffer layer + GaN layer, are manufactured with the same process. The equivalent thermal conductivity of the two test structures is tested using the 3ω method, and the relevant thermal resistance of each layer of material in the near-junction region of the GaN device is calculated based on the test results.

[0033] Figure 1 FIG. 1 is a flow chart of a method for testing the near-junction thermal resistance of a GaN device according to an embodiment of the present invention. Figure 1 As shown, the method for testing the near-junction thermal resistance of a GaN device according to an embodiment of the present invention includes steps S1 to S5.

[0034] Step S1: GaN device test structure fabrication

[0035] The near-junction structure of GaN devices is as follows: Figure 2 As shown, it includes a substrate layer, an AlN buffer layer on the substrate layer, a GaN layer on the AlN buffer layer, an AlGaN layer on the GaN layer, and a source, gate, and drain structure on the AlGaN layer. The material of the substrate layer includes but is not limited to Si, SiC, diamond, etc., the material of the AlN buffer layer is AlN, etc., and the material of the AlGaN layer is Al x Ga 1-x N et al.

[0036] When the GaN device is working, a two-dimensional electron gas is formed near the interface between the AlGaN layer and the GaN layer, and a heat source is formed nearby. The heat generated is mainly generated by Figure 2 The marked heat source position is conducted along the GaN layer, AlN buffer layer, and substrate layer in turn and then diffuses to the package of the GaN device. The near-junction thermal resistance of the GaN device is the thermal resistance between the heat source area of ​​the device and the parts of the bottom area of ​​the substrate layer, including the thermal resistance within the chip, the body thermal resistance of the substrate layer, the structural thermal resistance of the GaN layer, and the contact thermal resistance of the AlN buffer layer.

[0037] Based on the above GaN device near-junction region structure, the embodiment of the present invention adopts the same manufacturing process conditions as the GaN device to be tested to manufacture a thermal resistance test structure. The thermal resistance test structure includes a first test structure and a second test structure. Figure 3 : is a schematic diagram of a thermal resistance test structure of an embodiment of the present invention, wherein (a) represents a first test structure, and (b) represents a second test structure. The first test structure includes a substrate layer, an AlN buffer layer, and a GaN layer, and the second test structure includes a substrate layer. Metal test electrodes are arranged on the first test structure and the second test structure, and the metal test electrodes include voltage collection and drive collection ports. The arrangement of the metal test electrodes includes but is not limited to being closely attached to the surfaces of the first and second test structures by sputtering, electroplating, physical adhesion, etc.

[0038] Step S2: First test structure thermal resistance test

[0039] The first test structure is tested using the 3ω method to obtain the comprehensive thermal conductivity of the first test structure. The 3ω method applies a driving current with an angular frequency of ω to a metal test electrode, measures a harmonic voltage signal, and calculates the comprehensive thermal conductivity based on the measured voltage signal. The specific test process of the 3ω method is not described here.

[0040] According to the comprehensive thermal conductivity of the first test structure obtained by the 3ω method, the on-chip thermal resistance of the GaN device is calculated as follows:

[0041]

[0042] In formula (1), is the thickness of the first test structure, that is, the thickness from the surface of the GaN layer to the bottom of the substrate layer, is the comprehensive thermal conductivity of the first test structure obtained by the 3ω method test, is the thermal resistance of the first test structure, that is, the on-chip thermal resistance of the GaN device, in m 2 °C / W.

[0043] Step S3: Thermal resistance test of the second test structure

[0044] The second test structure is tested using the 3ω method to obtain the comprehensive thermal conductivity of the second test structure. The test process is the same as that of the first test structure. Based on the comprehensive thermal conductivity of the second test structure obtained by the 3ω method, the bulk thermal resistance of the substrate layer of the GaN device is calculated as follows:

[0045]

[0046] In formula (2), is the thickness of the second test structure, that is, the thickness of the substrate layer, is the comprehensive thermal conductivity of the second test structure obtained by the 3ω method test, is the thermal resistance of the second test structure, that is, the bulk thermal resistance of the substrate layer, in m 2 °C / W.

[0047] Step S4: Calculation of thermal resistance of GaN layer structure

[0048] Figure 2The thickness of the AlN buffer layer shown is generally about 0.1um, while the thickness of the GaN layer is about 1.5um, and the thickness of the AlN buffer layer is much smaller than the thickness of the GaN layer. Therefore, the first test structure can be equivalent to a substrate + film structure, and the 3ω method substrate + film thermal conductivity test model and the 3ω method test results of the first and second test structures can be used to calculate the comprehensive thermal conductivity of the GaN layer, and the calculated comprehensive thermal conductivity can be converted to obtain the structural thermal resistance of the GaN layer.

[0049] The 3ω method substrate + film thermal conductivity measurement model is as follows:

[0050]

[0051] The subscript f represents the film parameters, s represents the parameters of the substrate material, is the temperature rise of the film (a constant independent of frequency), is the temperature rise of the substrate material.

[0052] The following formula can be obtained by converting the 3ω method substrate + film thermal conductivity test model:

[0053]

[0054] In the formula, is the temperature rise of the metal test electrode when testing the first test structure, The temperature rise of the metal test electrode when testing the second test structure, is the resistance of the metal test electrode on the surface of the first test structure, is the peak value of the driving current, is the width of the metal test electrode, is the thickness of the GaN layer, is the comprehensive thermal conductivity of the GaN layer.

[0055] Based on the comprehensive thermal conductivity of the GaN layer in formula (3) The thermal resistance of the GaN layer can be calculated according to the following formula: .

[0056]

[0057] Step S5: Calculation of thermal contact resistance of AlN buffer layer

[0058] The thermal resistance of the first test structure obtained based on formulas (1), (2) and (4) 、 Thermal resistance of the second test structure , GaN layer structure thermal resistance , the contact thermal resistance of the AlN buffer layer can be calculated. The specific calculation formula is as follows:

[0059]

[0060] is the thermal contact resistance of the buffer layer AlN structure, in m 2 °C / W.

[0061] According to the method for testing the thermal resistance of the near-junction region of a GaN device in the above-mentioned embodiment of the present invention, two test structures, a substrate and a substrate + AlN buffer layer + GaN layer, are manufactured using the same process, and the equivalent thermal conductivity of the two different test structures is tested using the 3ω method. Combined with the calculation of relevant algorithms, the on-chip thermal resistance of the near-junction region of the GaN device, the bulk thermal resistance of the substrate layer, the structural thermal resistance of the GaN layer, and the contact thermal resistance of the AlN buffer layer are obtained.

[0062] The thermal resistance test structure used in the embodiment of the present invention can also use the related structure formed in the GaN device manufacturing process without special manufacturing, providing a new solution for the thermal resistance test of the near-junction region of the GaN device. With the widespread application of GaN devices, the present invention can be directly applied to support the resistance characterization of GaN devices, device thermal design assurance and optimization, and has good engineering application value, thus forming huge social and economic benefits.

[0063] An embodiment of the present invention further provides a computer device, which may be a server, and its internal structure diagram may be as shown in FIG. Figure 4 As shown. The computer device includes a processor, a memory and a network interface connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store operating parameter data of each framework. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the steps of the method of the embodiment of the present invention are implemented.

[0064] Those skilled in the art will understand that Figure 4 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0065] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the method of the embodiment of the present invention are implemented.

[0066] An embodiment of the present invention further provides a computer program product, including a computer program, which implements the steps of the method of the embodiment of the present invention when executed by a processor.

[0067] The above description is only by way of illustration of certain exemplary embodiments of the present invention. It is undoubted that those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A method for testing the near-junction thermal resistance of a GaN device, characterized in that: include: Step S1: a thermal resistance test structure is manufactured by adopting the same manufacturing process as that of the GaN device to be tested, wherein the thermal resistance test structure comprises a first test structure and a second test structure, wherein the first test structure comprises a substrate layer, an AlN buffer layer arranged on the substrate layer, and a GaN layer arranged on the AlN buffer layer, wherein the thickness of the AlN buffer layer is much smaller than the thickness of the GaN layer, and the second test structure comprises a substrate layer, and metal test electrodes are arranged on the surfaces of the first test structure and the second test structure; Step S2: The first test structure is tested using the 3ω method to obtain the comprehensive thermal conductivity of the first test structure. The on-chip thermal resistance of the GaN device is calculated as follows: ， Wherein, d is the thickness of the first test structure, k is the comprehensive thermal conductivity of the first test structure, is the on-chip thermal resistance of the GaN device; Step S3: The second test structure is tested using the 3ω method to obtain the comprehensive thermal conductivity of the second test structure. The bulk thermal resistance of the substrate layer is calculated as follows: , in, is the thickness of the second test structure, is the comprehensive thermal conductivity of the second test structure, is the bulk thermal resistance of the substrate layer; Step S4: According to the 3ω method test results of the first test structure and the second test structure, the comprehensive thermal conductivity of the GaN layer is calculated as follows: , in, is the temperature rise of the metal test electrode when testing the first test structure, The temperature rise of the metal test electrode when testing the second test structure, is the resistance of the metal test electrode on the surface of the first test structure, is the peak value of the driving current when testing the first test structure, is the width of the metal test electrode, is the thickness of the GaN layer, is the comprehensive thermal conductivity of the GaN layer, According to the comprehensive thermal conductivity of the GaN layer, the structural thermal resistance of the GaN layer is calculated as follows: ， in, is the structural thermal resistance of the GaN layer; Step S5: Based on the on-chip thermal resistance of the GaN device, the bulk thermal resistance of the substrate layer, and the structural thermal resistance of the GaN layer, the contact thermal resistance of the AlN buffer layer is calculated as follows: , in, is the thermal contact resistance of the AlN buffer layer.

2. A computer device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method of claim 1.

3. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to claim 1 are implemented.

4. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to claim 1 are implemented.

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