Chip latch-up effect test system and method, electronic equipment and storage medium

Abstract

The invention provides a chip latch-up effect test system and method, electronic equipment and a storage medium, the test system comprises a circuit substrate, a fixing structure, a test structure, a power supply unit, an excitation source and a temperature alarm unit, when a chip latch-up effect test is carried out, the excitation source provides an excitation signal for a to-be-tested chip through the test structure, and the temperature alarm unit sends the excitation signal to the to-be-tested chip; the temperature alarm unit monitors the packaging body temperature of the to-be-tested chip and compares the packaging body temperature with a preset temperature so as to indicate whether the to-be-tested chip has a latch-up effect or not under the action of the current excitation signal according to a comparison result. The chip latch-up effect test is carried out based on the temperature change of the chip when the latch-up effect occurs, whether the latch-up effect exists in the chips of different packaging types or not can be accurately positioned and analyzed, the test time and cost are low, the test effect is obvious, and the test effect is not restrained by a site.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a chip latch effect testing system, method, electronic device and storage medium. Background Art

[0002] With the development of electronic technology, the integration of electronic circuits is getting higher and higher. The related voltage transients can cause semiconductor device failure, namely the latch-up effect. The latch-up effect can cause the device to form a short circuit between the power supply and the ground, causing large current, EOS and device damage, which is a potential serious problem affecting device reliability. Therefore, evaluating the chip's anti-latch ability through latch-up testing is of great significance to ensure the quality of the chip.

[0003] However, there are many existing chip latch effect testing solutions, but most of them have problems such as high testing cost, long testing time, and complicated solutions. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a chip latch effect test system, method, electronic device and storage medium, aiming to reduce the time and cost of chip latch effect testing, and provide a chip latch effect testing solution with obvious testing effect and not restricted by the site.

[0005] According to a first aspect of the present application, a chip latch effect testing system is provided, comprising:

[0006] Circuit board;

[0007] A fixing structure, arranged on the surface of the circuit substrate, for fixing the chip to be tested;

[0008] A test structure, disposed on the surface of the circuit substrate, coupled to a plurality of pins of the chip to be tested through the fixing structure;

[0009] A power supply unit, used to supply power to the chip under test;

[0010] An excitation source, used to provide an excitation signal to the chip under test through the test structure during testing;

[0011] The temperature alarm unit is used to monitor the package body temperature of the chip to be tested and compare the package body temperature of the chip to be tested with a predetermined temperature to indicate whether the chip to be tested has a latch effect under the current excitation signal according to the comparison result.

[0012] Optionally, the temperature alarm unit is configured to: generate an alarm when the temperature of the package body of the chip under test exceeds a predetermined temperature, so as to indicate that a latch effect exists in the chip under test under the action of the current excitation signal.

[0013] Optionally, the power supply unit is configured to stop supplying power to the chip under test when the temperature of the package body of the chip under test exceeds a predetermined temperature.

[0014] Optionally, the chip latch effect test system further includes:

[0015] The hollow structure is arranged in the central area of ​​the fixing structure. After the chip to be tested is fixed on the fixing structure, the heat dissipation surface of the package of the chip to be tested is exposed outside the circuit substrate through the hollow structure.

[0016] Optionally, the area of ​​the cavity structure is smaller than or equal to the heat dissipation surface area of ​​the package body of the chip to be tested.

[0017] Optionally, the temperature alarm unit comprises:

[0018] A temperature sensor is disposed on the heat dissipation surface of the package of the chip to be tested through the hollow structure, and the temperature sensor obtains the package temperature of the chip to be tested by monitoring the heat dissipation surface temperature of the package of the chip to be tested;

[0019] A temperature monitoring control circuit, the input end of which is coupled to the temperature sensor, receives the heat dissipation surface temperature of the package of the chip to be tested, compares it with the predetermined temperature, and generates a corresponding control signal according to the comparison result;

[0020] The alarm has an input end coupled to the temperature monitoring control circuit and receives the control signal.

[0021] Optionally, the power supply unit includes:

[0022] Power supply;

[0023] A current sensor, used to detect the current flowing through the power pin of the chip to be tested;

[0024] The current detection control circuit is coupled to the output end of the current sensor and is used to disconnect the power supply path for the power supply to supply power to the chip under test or control the power supply to stop supplying power to the chip under test when the current detected by the current sensor exceeds a preset current threshold.

[0025] Optionally, the current sensor detects the current flowing through the power pin of the chip to be tested by using the principle of electromagnetic induction.

[0026] Optionally, the fixing structure and the test structure are arranged on the same surface of the circuit substrate, the fixing structure is arranged in a central area of ​​the first surface of the circuit substrate, and the test structure is arranged in an edge area of ​​the first surface of the circuit substrate.

[0027] Optionally, the chip latch effect test system further includes:

[0028] A power indicator light, disposed on the second surface of the circuit substrate, the power indicator light being coupled to a power pin of the chip to be tested;

[0029] A program running indicator light is disposed on the second surface of the circuit substrate, and the program running indicator light is coupled to the first general input and output pin of the chip to be tested;

[0030] A program running abnormality indicator light is arranged on the second surface of the circuit substrate, and the program running abnormality indicator light is coupled to the second general input and output pin of the chip to be tested;

[0031] The power indicator light is used to indicate the power supply status of the chip under test provided by the power supply unit, and the program running indicator light and the program running abnormality indicator light are used to indicate the running status of the program in the chip under test.

[0032] Optionally, the power indicator light, the program running indicator light and the program running abnormality indicator light are all light emitting diodes;

[0033] When the power indicator light is in a normally on state, it indicates that the power supply unit supplies power to the chip under test normally; when the power indicator light is in an off state, it indicates that the power supply unit supplies power to the chip under test abnormally;

[0034] When the program running indicator light is in a flashing state and the program running abnormality indicator light is in an off state, it indicates that the program in the chip under test is running normally;

[0035] When the program running indicator light is in a constant on state, it indicates that the program in the chip under test stops running;

[0036] When the program running abnormality indicator light is in a normally on state, it indicates that the program running in the chip under test is abnormal.

[0037] Optionally, the chip latch effect test system further includes:

[0038] A reset button is connected to the reset pin of the chip under test and is used to implement a reset operation on the program running in the chip under test.

[0039] Optionally, the fixing structure fixes the chip to be tested by welding or in a detachable manner.

[0040] Optionally, the test structure includes a plurality of test pins, and the plurality of test pins are coupled to a plurality of pins of the chip to be tested in a one-to-one correspondence.

[0041] Optionally, the power supply unit further includes:

[0042] A display is used to numerically display the current detected by the current sensor.

[0043] Optionally, the excitation source includes an electrostatic discharge simulator, and the excitation signal is an electrostatic signal.

[0044] Optionally, the electrostatic discharge simulator comprises:

[0045] A high voltage power supply, used for providing a high voltage signal;

[0046] The control unit is used to control the discharge parameters of the high voltage power supply and output the electrostatic signal, wherein the discharge parameters include at least one of a discharge voltage, a discharge number and a discharge interval.

[0047] According to a second aspect of the present application, a chip latch effect testing method is provided, comprising:

[0048] After the chip to be tested is powered on, running the program pre-burned in the chip to be tested;

[0049] Applying an excitation signal to the test pin of the chip to be tested, while monitoring the package temperature of the chip to be tested;

[0050] The package body temperature of the chip to be tested is compared with a predetermined temperature, and it is determined whether a latching effect exists in the chip to be tested under the action of the current excitation signal according to the comparison result.

[0051] Optionally, when the package temperature of the chip to be tested exceeds a predetermined temperature, it is determined that the chip to be tested has a latch effect under the action of the current excitation signal, and the current test result is recorded;

[0052] When the package temperature of the chip to be tested does not exceed the predetermined temperature, it is determined that the chip to be tested does not have a latch effect under the action of the current excitation signal.

[0053] Optionally, when the package temperature of the chip to be tested does not exceed a predetermined temperature, it is determined that the chip to be tested does not have a latch effect under the action of the current excitation signal; and

[0054] The chip latch effect testing method further includes:

[0055] It is determined whether the program in the chip under test runs normally, and after the program runs normally or recovers to be normal, the excitation signal is increased.

[0056] According to a third aspect of the present application, a processor, a memory, and a program stored in the memory and executable on the processor are provided. When the program is executed by the processor, the steps of the chip latch effect testing method as described in any embodiment of the present application are implemented.

[0057] According to a fourth aspect of the present application, a storage medium is provided, on which a computer program or instruction is stored. When the computer program or instruction is executed by a processor, the steps of the chip latch effect testing method as described in any embodiment of the present application are implemented.

[0058] The beneficial effects of this application include at least:

[0059] The chip latch effect test scheme provided in the embodiment of the present application includes, when performing the chip latch effect test, using a temperature alarm unit to monitor the package body temperature of the chip to be tested and compare it with a predetermined temperature, so as to indicate whether the chip to be tested has a latch effect under the action of the current excitation signal according to the comparison result, which is equivalent to performing a chip latch effect test based on the temperature change of the chip when the latch effect occurs. The test scheme is simple, and while being able to accurately locate and analyze whether chips of different package types have a latch effect, it can also effectively avoid problems such as overheating, damage or even burning of the device. The test results are highly accurate and reliable, and the test time and cost are low. The test effect is obvious and is not restricted by the site.

[0060] In a further preferred example, an alarm is set when the package temperature of the chip to be tested exceeds a predetermined temperature to indicate that the chip to be tested has a latching effect under the action of the current excitation signal. Through this alarm action, the moment when the latching effect occurs in the chip can be intuitively and accurately indicated, which is convenient for subsequent processing.

[0061] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and do not limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 A schematic diagram showing an implementation of a chip latch effect test system provided according to an embodiment of the present application is shown;

[0063] Figure 2 Show Figure 1 A schematic diagram of an implementation of a temperature monitoring control circuit;

[0064] Figure 3 Show Figure 1 A schematic diagram of an implementation of a current detection control circuit;

[0065] Figure 4 A schematic diagram showing an implementation of a chip latch effect testing method provided in accordance with an embodiment of the present application is shown;

[0066] Figure 5 A schematic diagram showing the working process of a chip latch effect test system provided in accordance with an embodiment of the present application is shown;

[0067] Figure 6 A schematic diagram of an implementation of an electronic device provided according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0068] In order to facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0069] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0070] In the description of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments. "And / or" in this article is a description of the association relationship of the associated objects, indicating that there may be three relationships, for example, A and / or B, which can represent: A exists alone, A and B exist at the same time, and B exists alone. "Coupled" is a description of the connection relationship between the associated objects. For example, A is coupled to B, which can represent a direct connection between A and B, or an indirect connection between A and B through other devices / units / modules. "Multiple" refers to two or more than two. In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, the words "first", "second" and the like are used to distinguish the same items or similar items with substantially the same functions and effects. Those skilled in the art can understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not limit them to be necessarily different.

[0071] In addition, the same figure marks in the figures represent the same or similar structures, and thus their repeated description will be omitted. That is, the various parts in this specification are described in a combination of parallel and progressive manners, and each part focuses on the differences from other parts. The same or similar parts between the various parts can be referenced to each other.

[0072] Latch-up effect refers to the phenomenon that in semiconductor devices, due to certain electrical conditions, one or more PN junctions in the device are accidentally forward biased, thus forming an uncontrolled low-impedance path, causing a large current to flow through the device. This phenomenon is called latch-up effect. In CMOS (complementary metal oxide semiconductor) integrated circuits, latch-up effect is a common reliability problem.

[0073] With the continuous advancement of semiconductor technology, the chip line width is getting smaller and smaller. For example, in the CMOS (complementary metal oxide semiconductor) process, due to the limitations of the manufacturing process, there are usually some parasitic structures inside the chip, such as parasitic transistors of N-type channel and P-type channel. When these parasitic transistors are accidentally turned on, a latch state will be formed. When designing and manufacturing CMOS circuits, measures must be taken to prevent the occurrence of latch-up effects. Accurate latch-up effect testing of chips is the key to achieving everything.

[0074] refer to Figure 1 , Figure 1 FIG. 1 shows a schematic diagram of an implementation of a chip latch effect test system provided in accordance with an embodiment of the present application. Figure 1 In the example shown, the chip latch-up effect test system includes: a circuit substrate 10 , a fixing structure 20 , a test structure 30 , a power supply unit 40 , an excitation source 50 , and a temperature alarm unit 60 .

[0075] The fixing structure 20 is arranged on the surface of the circuit substrate 10, and is used to fix the chip to be tested and realize electrical connection with the circuit substrate 10; the test structure 30 is arranged on the surface of the circuit substrate 10, and is coupled with multiple pins of the chip to be tested through the fixing structure 20; the power supply unit 40 is coupled with the power pins of the chip to be tested, and is used to supply power to the chip to be tested; the excitation source 50 is used to provide an excitation signal to the chip to be tested through the test structure 30 during the test; the temperature alarm unit 60 is used to monitor the package body temperature of the chip to be tested, and compare the package body temperature of the chip to be tested with a predetermined temperature, so as to indicate whether there is a latch effect on the chip to be tested under the action of the current excitation signal according to the comparison result. For example, when it is detected that the package body temperature of the chip to be tested exceeds the predetermined temperature, it indicates that there is a latch effect on the chip to be tested under the action of the current excitation signal; when it is detected that the package body temperature of the chip to be tested does not exceed the predetermined temperature, it indicates that there is no latch effect on the chip to be tested under the action of the current excitation signal. That is, the chip latch effect test is performed based on the temperature change of the chip when the latch effect occurs. The test scheme is simple. While being able to accurately locate and analyze whether chips of different package types have latch effects, it can also effectively avoid problems such as overheating, damage, or even burning of the device. The test results are highly accurate and reliable, and the test time and cost are low. The test effect is obvious and is not restricted by the site.

[0076] In a specific implementation, the circuit substrate 10 includes a first surface and a second surface that are arranged opposite to each other, and the fixing structure 20 and the test structure 30 are arranged on the same surface of the circuit substrate 10. For example, the fixing structure 20 is arranged in the central area of ​​the first surface of the circuit substrate 10, and the test structure 30 is arranged in the edge area of ​​the first surface of the circuit substrate 10.

[0077] The circuit substrate 10 is, for example, a PCB board, and a plurality of signal transmission lines (such as traces) are arranged on the circuit substrate 10 to achieve electrical connection between corresponding structures, devices or units (such as the fixed structure 20 and the test structure 30).

[0078] Optionally, the fixing structure 20 fixes the chip to be tested in a detachable manner (such as plugging, pressing, etc.) or by welding, so that multiple pins of the chip to be tested are coupled to the test structure 30 through multiple signal transmission lines on the circuit substrate 10. The fixing structure 20 can be customized according to different packaging forms of the chip to be tested, so as to meet the test requirements of the chips to be tested in different packaging forms.

[0079] In some embodiments, the fixed structure 20 is, for example, a chip socket welded on the circuit substrate 10, and the fixed structure 20 can also be, for example, a multilayer structure including a first chip socket and a second chip socket, wherein the first chip socket is fixed to the circuit substrate 10 by welding, and the second chip socket is arranged on the first chip socket in a detachable manner (such as a pluggable manner). In this way, the testing of chips to be tested in different packaging forms can be achieved simply by replacing different second chip sockets, which is convenient and quick.

[0080] In other embodiments, the fixed structure 20 is, for example, a pad structure that provides a welding position, and the chip to be tested is fixed to the fixed structure 20 by welding. Optionally, in these examples, the size of the fixed structure 20 is substantially the same as the package size of the chip to be tested, and the positions of the pads in the fixed structure 20 correspond one-to-one to the pin positions of the chip to be tested.

[0081] The test structure 30 includes a plurality of test pins, which are coupled to the corresponding signal transmission line fixing structure 20 on the circuit substrate 10, so as to be coupled to the plurality of pins of the chip to be tested one by one through the fixing structure 20. Figure 1 In the example shown, the test structure 30 includes test pins T1 to T8. Of course, in other embodiments of the present application, the number of test pins included in the test structure 30 can also be other values, which are specifically set according to the number of pins of the chip to be tested.

[0082] In some examples, the chip latch effect test system further includes a plurality of indicator lights disposed on any surface of the circuit substrate 10, through which the latch effect test status of the chip to be tested can be better monitored. Figure 1 In the example shown, the multiple indicator lights include, for example, a power indicator light L1, a program running indicator light L2, and a program running abnormality indicator light L3, which are arranged on the second surface of the circuit substrate 10, wherein the power indicator light L1 is coupled to the power pin of the chip under test, the program running indicator light L2 is coupled to the first general input and output pin of the chip under test, and the program running abnormality indicator light L3 is coupled to the second general input and output pin of the chip under test, the power indicator light L1 is used to indicate the power supply status of the chip under test by the power supply unit 40, and the program running indicator light L2 and the program running abnormality indicator light L3 are used to indicate the running status of the program in the chip under test.

[0083] In some specific embodiments, the power indicator light L1, the program running indicator light L2, and the program running abnormal indicator light L3 are all light emitting diodes, and the power indicator light L1, the program running indicator light L2, and the program running abnormal indicator light L3 are configured to switch between at least two states of a constant light state, a flashing state, and an off state, so as to achieve corresponding status indications. For example, when the power indicator light L1 is in a constant light state, it indicates that the power supply unit 40 supplies normal power to the chip under test, and when the power indicator light L1 is in an off state, it indicates that the power supply unit supplies abnormal power to the chip under test; when the program running indicator light L2 is in a flashing state, and the program running abnormal indicator light L3 is in an off state, it indicates that the program in the chip under test is running normally; when the program running indicator light L2 is in a constant light state, it indicates that the program in the chip under test stops running; when the program running abnormal indicator light L3 is in a constant light state, it indicates that the program in the chip under test is running abnormally.

[0084] Furthermore, the chip latch effect test system further includes a reset button R disposed on any surface of the circuit substrate 10, the reset button R being coupled to the reset pin of the chip to be tested, for implementing a reset operation on the program running in the chip to be tested. Figure 1 In the example shown, the reset button R is, for example, disposed on the second surface of the circuit substrate 10 .

[0085] If the program of the chip under test runs abnormally due to static electricity, the program can be re-run after the chip under test is reset by pressing the reset button R on the circuit substrate 10; if the program of the chip under test runs abnormally under a certain static voltage level and the normal operation of the program cannot be restored by pressing the reset button R, it indicates that there is no latch-up effect on the chip under test under the static voltage, but it will affect the performance of the chip.

[0086] In some preferred embodiments, the temperature alarm unit 60 is configured to, for example, alarm when the package temperature of the chip under test exceeds a predetermined temperature, so as to indicate that the chip under test has a latch effect under the current excitation signal. Through this alarm action, the moment when the chip has a latch effect can be intuitively and accurately indicated, which is convenient for subsequent processing.

[0087] When implementing it, Figure 1In the example shown, the temperature alarm unit 60 includes: a temperature sensor 61, a temperature monitoring control circuit 62 and an alarm 63. The temperature sensor 61 is arranged on the heat dissipation surface of the package of the chip to be tested, and the temperature sensor 61 obtains the package temperature of the chip to be tested by monitoring the heat dissipation surface temperature of the package of the chip to be tested; the input end of the temperature monitoring control circuit 62 is coupled to the temperature sensor 61, receives the heat dissipation surface temperature of the package of the chip to be tested, and compares it with the predetermined temperature, and generates a corresponding control signal according to the comparison result; the input end of the alarm 63 is coupled to the output end of the temperature monitoring control circuit 62, and receives the control signal.

[0088] In this embodiment, since the heat dissipation surface of the package of the chip to be tested is closely connected to the substrate of the chip to be tested, according to thermal conductivity, the temperature of the heat dissipation surface of the package of the chip to be tested is equivalent to the temperature generated by the chip to be tested, so the temperature detected by the temperature sensor 61 will change with the change of the temperature of the chip to be tested.

[0089] In some embodiments, Figure 2 As shown, the temperature monitoring control circuit 62 includes a processing unit 621, a display screen 622, a control logic unit 623, an output actuator 624 and a relay 625, wherein the processing unit 621 is used to process the electrical signal detected by the temperature sensor 61 (such as amplification, filtering and linearization processing, etc.) to ensure the accuracy of the temperature data; the display screen 622 is used to intuitively display the current temperature of the chip to be tested; the control logic unit 623 is used to compare the received temperature with the set temperature. If the received temperature exceeds the set temperature, the control logic unit 623 will trigger the corresponding control action to the output actuator 624. At this time, the output actuator 624 will execute the closing relay 625 operation to turn on the circuit of the alarm 63, so that the alarm 63 will sound an alarm.

[0090] Optionally, the alarm 63 may be a buzzer, a light emitting diode or a combination thereof, or other devices that can realize a reminder or warning function.

[0091] In a further preferred example, the chip latch effect test system further includes a hollow structure 70 disposed in the central area of ​​the fixed structure 20. After the chip to be tested is fixed on the fixed structure 20, the heat dissipation surface of the package of the chip to be tested is exposed outside the circuit substrate 10 through the hollow structure 70. By providing the hollow structure 70, it is convenient to install the temperature sensor 61 in the temperature alarm unit 60 on the heat dissipation surface of the package of the chip to be tested, which is conducive to more accurate monitoring of the package temperature of the chip to be tested.

[0092] Optionally, the area of ​​the cavity structure 70 is smaller than or equal to the heat dissipation surface area of ​​the package of the chip to be tested.

[0093] In some preferred embodiments, the power supply unit 40 is further configured to stop supplying power to the chip under test when the temperature of the package body of the chip under test exceeds a predetermined temperature, so as to further protect the chip under test from being damaged.

[0094] When implementing it, Figure 1 As shown, the power supply unit 40 includes: a current sensor 41, a current detection control circuit 42 and a power supply 43. The current sensor 41 is used to detect the current flowing through the power pin of the chip to be tested. The current detection control circuit 42 is coupled to the output end of the current sensor 41 and the power supply 43 respectively, and is used to disconnect the power supply path of the power supply 43 to supply power to the chip to be tested or control the power supply 43 to stop supplying power to the chip to be tested when the current detected by the current sensor 41 exceeds a preset current threshold.

[0095] The current sensor 41 is, for example, a Hall effect sensor, which detects the current flowing through the power pin of the chip to be tested in a non-contact manner (such as using the principle of electromagnetic induction). Figure 1 As shown, the current sensor 41 is, for example, a ring structure, arranged around a wire coupled to the power pin of the chip to be tested, and the center of the current sensor 41 is aligned with the wire. When the current in the wire is perpendicular to the magnetic field, a voltage is generated on one side of the conductor. By measuring this voltage, the magnitude of the current flowing through the conductor can be determined. The sensor is non-contact, so it will not affect the chip to be tested, thereby improving the accuracy of the test results. Of course, in some other embodiments, the current detection of the power pin of the chip to be tested can also be achieved through a sampling resistor.

[0096] In some embodiments, Figure 3As shown, the current detection control circuit 42 includes, for example, a signal processing unit 421, a display 422, an execution control unit 423 and a circuit breaker 424. The display 422 is used to numerically display the current detected by the current sensor 41; the signal processing unit 421 is used to amplify, filter and shape the detected weak current signal, and the execution control unit 423 compares the processed current detection signal with a preset threshold value. If the detected current exceeds the set threshold value, or the package temperature of the chip to be tested exceeds the predetermined temperature, the execution control unit 423 will send a signal to the circuit breaker 424, and the circuit breaker 424 will disconnect the power supply path of the power supply 43 to supply power to the chip to be tested, so as to prevent the continuous large current from burning the chip to be tested. When the current value in the circuit returns to normal, the circuit breaker 424 will close again to restore the power supply path of the power supply 43 to supply power to the chip to be tested. Of course, the circuit breaker 424 may not be set in the current detection control circuit 42. When the detected current exceeds the set threshold, or the package temperature of the chip to be tested exceeds the predetermined temperature, the execution control unit 423 directly sends a signal to the power supply 43 to control the power supply 43 to stop supplying power to the chip to be tested by stopping working.

[0097] Optionally, the display 422 in the current detection control circuit 42 may also be provided in the power supply 43, or provided separately.

[0098] In some embodiments, the excitation source 50 includes, for example, an electrostatic test device, such as an electrostatic discharge simulator, and the excitation signal is an electrostatic signal. The electrostatic test device complies with the test procedures and discharge waveforms defined in IEC61000-4-2 or ISO 10605 standards, and can be used to generate and guide static electricity.

[0099] In a specific implementation, the electrostatic discharge simulator includes, for example, a high voltage power supply and a control unit ( Figure 1 (not shown in the figure), wherein the high-voltage power supply is used to provide an instantaneous high-voltage signal, and the control unit is coupled to the high-voltage power supply to control the discharge parameters of the high-voltage power supply (for example, including at least one of the discharge voltage, the number of discharges, and the discharge interval), and output an electrostatic signal. For example, the high-voltage power supply can be controlled to output a short discharge current waveform in which the voltage drops rapidly and the current rises rapidly, so as to realize the electrostatic signal output of the electrostatic discharge simulator. When the electrostatic signal is applied to any test pin in the test structure 30, the electrostatic signal will be transmitted to the corresponding pin of the chip to be tested through the corresponding test pin of the test structure 30, and will be conducted to the internal current of the chip to be tested through the corresponding pin of the chip to be tested, inducing a latch effect in the chip to be tested.

[0100] The voltage range of the instantaneous high voltage signal provided by the high voltage power supply is, for example, 0 to 30 KV.

[0101] Figure 5 The schematic diagram of the working process of the chip latch effect test system provided in accordance with the embodiment of the present application is shown below. Figure 5 The working process of the chip latch effect test system disclosed in the above embodiments is described in detail.

[0102] Exemplarily, taking the latch effect test of a chip to be tested with 8 pins as an example, the chip to be tested includes a power pin, a reset pin, a clock pin, a first general input and output pin, a second general input and output pin, a ground pin and an empty pin. The first general input and output pin of the chip to be tested is configured to determine whether the chip to be tested enters a program running state, and the second general input and output pin of the chip to be tested is configured to determine whether the chip to be tested is in an abnormal program running state.

[0103] Assume that after the chip under test is fixed on the fixed structure 20, the power pin of the chip under test is coupled to the test pin T1 in the test structure 30 through the fixed structure 20 and the corresponding signal transmission line, the reset pin of the chip under test is coupled to the test pin T2 in the test structure 30 through the fixed structure 20 and the corresponding signal transmission line, the clock pin of the chip under test is coupled to the test pin T3 in the test structure 30 through the fixed structure 20 and the corresponding signal transmission line, and the second general input and output pin of the chip under test is coupled to the test pin T4 in the test structure 30 through the fixed structure 20 and the corresponding signal transmission line. 20 and the corresponding signal transmission line are coupled to the test pin T4 in the test structure 30, the ground pin of the chip to be tested is coupled to the test pin T5 in the test structure 30 through the fixed structure 20 and the corresponding signal transmission line, the first general input and output pin of the chip to be tested is coupled to the test pin T7 in the test structure 30 through the fixed structure 20 and the corresponding signal transmission line, and the empty pin of the chip to be tested is coupled to the test pins (such as T6 and T8) in the test structure 30 through the fixed structure 20 and the corresponding signal transmission line.

[0104] Specifically, the workflow of the chip latch effect test system is as follows:

[0105] In step 501, the test is started.

[0106] After the preparations are ready, if the system is initially tested normally and the program to be run is successfully burned into the chip to be tested, the test can begin.

[0107] Optionally, when the chip under test needs to burn and run a program (referred to as a program), for example, a 7816 interface can be used for program burning. The burned program content includes, for example, Flash erasing, data verification, and algorithm calculation functions.

[0108] In step 502, the chip to be tested is powered on and the program runs normally.

[0109] After the chip under test is powered on, if the power indicator light L1 on the circuit substrate 10 lights up, it indicates that the chip under test is successfully powered on, and the chip under test automatically runs the program at this time; if the program running indicator light L2 on the circuit substrate 10 is in a flashing state and the program running abnormality indicator light L3 is off, it indicates that the program in the chip under test is running normally, and the program in the chip under test will execute Flash erasing, data verification and algorithm calculation functions in sequence.

[0110] In step 503, the voltage mode of the excitation source is set.

[0111] Setting the voltage mode of the excitation source includes setting the excitation source 50 to output a positive voltage or a negative voltage, and the initial output voltage of the excitation source 50. For example, the excitation source 50 is set to a positive-first-then-negative electrostatic voltage mode, and discharge starts from an initial output voltage of 1KV.

[0112] In step 504, the excitation source performs contact discharge on the test pin.

[0113] A test pin in the test structure 30 is selected, and the output end of the excitation source 50 is brought into contact with the test pin and discharged, so that the excitation signal is transmitted to the corresponding pin of the chip to be tested through the test pin. For example, the test pin T1 can be selected as the initial test pin and contact discharged, and after the test pin T1 is tested, the remaining test pins T2 to T8 are contact discharged in sequence.

[0114] In step 505, it is determined whether a latch-up effect occurs.

[0115] At the current excitation signal level, if the alarm 63 in the temperature alarm unit 60 generates an alarm, it can be determined that the chip under test has a latch effect under the current excitation signal, and step 510 is executed; if the alarm 63 in the temperature alarm unit 60 does not generate an alarm, it can be determined that the chip under test does not have a latch effect under the current excitation signal, and step 506 is executed.

[0116] Furthermore, when it is determined that the chip under test has a latch effect under the current excitation signal, the power supply unit 40 is controlled to stop supplying power to the chip under test, and the current currently detected by the current sensor 41 is displayed numerically through the display in the power supply unit 40 .

[0117] In step 506, it is determined whether the program runs normally.

[0118] If the program running indicator light L2 on the circuit substrate 10 is in a flashing state and the program running abnormal indicator light L3 is in an off state, it can be determined that the program in the current chip under test is running normally, and step 507 is executed; if the program running abnormal indicator light L3 on the circuit substrate 10 is in a normally bright state, it indicates that a branch of the program in the chip under test has an abnormality under the electrostatic interference of the excitation signal, so that it can be determined that the program in the current chip under test is running abnormally and stops running, and step 508 is executed.

[0119] In step 507, the output voltage of the excitation source is increased. The discharge parameters of the excitation source 50 are adjusted according to a preset step value, and then step 503 is performed so that the excitation source 50 outputs the excitation signal after step adjustment. The step value is, for example, 0.5 KV.

[0120] In step 508 , the chip under test is reset. The program of the chip under test is reset by using the reset button R on the circuit substrate 10 , and then step 509 is executed.

[0121] In step 509, it is determined whether the program is running normally. If the program running indicator light L2 on the circuit substrate 10 is in a flashing state, and the program running abnormal indicator light L3 is in an off state, it can be determined that the program in the current chip under test is running normally, and then step 507 is executed; if the program running abnormal indicator light L3 on the circuit substrate 10 is in a constant on state, it can be determined that the program in the current chip under test is running abnormally, and then step 511 is executed, that is, it is determined that there is an abnormality in the hardware of the chip under test, and then step 510 is executed.

[0122] In step 510 , the current test result is recorded, including recording the test pin where the latch effect currently occurs, the voltage value of the excitation signal currently output by the excitation source 50 , and the current value detected in the power supply unit 40 .

[0123] In step 512, it is determined whether the test is completed, including determining whether all chips that need to be tested for latch effect have been tested. If not, step 513 is executed to replace the sample (i.e., the chip to be tested) and then re-execute steps 502-512; otherwise, step 514 is executed to end the test.

[0124] In summary, the chip latch effect test scheme disclosed in the embodiment of the present application performs chip latch effect test based on the temperature change of the chip when the latch effect occurs. The test scheme is simple, and can accurately locate and analyze whether chips of different packaging types have latch effects. It can also effectively avoid problems such as overheating, damage or even burning of the device. The test results are highly accurate and reliable, and the test time and cost are low. The test effect is significant and is not restricted by the site.

[0125] It can be understood that the chip latch effect test system disclosed in the embodiment of the present application can be used to detect whether different chips to be tested have latch effects, with low cost and significant effect.

[0126] Furthermore, the present application also provides a chip latch effect test method, which can be applied to the chip latch effect test system disclosed in the above embodiments, such as Figure 4 As shown, during specific implementation, the method includes executing the following steps:

[0127] In step 410, after the chip under test is powered on, the program pre-burned in the chip under test is run.

[0128] In step 420 , an excitation signal is applied to the test pin of the chip under test, and the package temperature of the chip under test is monitored simultaneously.

[0129] In step 430, the package temperature of the chip to be tested is compared with a predetermined temperature, and it is determined whether the chip to be tested has a latch-up effect under the current excitation signal according to the comparison result.

[0130] When the package temperature of the chip to be tested exceeds a predetermined temperature, it is determined that the chip to be tested has a latch effect under the action of the current excitation signal, and the current test result is recorded.

[0131] When the package temperature of the chip under test does not exceed the predetermined temperature, it is determined that there is no latch effect in the chip under test under the action of the current excitation signal; at this time, it also includes: determining whether the program in the chip under test runs normally, and increasing the excitation signal after the program runs normally or returns to normal.

[0132] During specific implementation, the specific implementation of each step in the chip latch effect test method and the effective effects that can be obtained can be found in the aforementioned embodiments of the chip latch effect test system, which will not be described in detail here.

[0133] The present application also provides an electronic device, such as Figure 6 As shown, it includes a memory 610, a processor 620, and a program stored in the memory 610 and executable on the processor 620. When the program is executed by the processor 620, each process of each embodiment of the above-mentioned chip latch effect test method can be implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0134] In particular, according to the embodiments disclosed in the present application, any implementation process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), the above-mentioned functions defined in the system of the present application are executed.

[0135] It should be noted that the computer-readable medium shown in the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. Computer-readable storage media include, for example, but are not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0136] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the above-mentioned module, program segment or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0137] All or part of the steps, units or modules involved in the embodiments of the present application may be implemented by software (or instructions), or by controlling the relevant hardware by software (or instructions), and the instructions may be stored in a computer-readable storage medium and loaded and executed by a processor. The names of these units or modules do not, in some cases, constitute limitations on the units or modules themselves.

[0138] As another aspect, the present application further provides a storage medium, which may be included in the device described in the above embodiment; or may exist independently without being assembled into the device. The above storage medium carries one or more computer programs or instructions, and when the above one or more computer programs or instructions are executed, each process of each embodiment of the chip latch effect test method described in any embodiment of the present application can be implemented.

[0139] Since the instructions stored in the storage medium can execute the steps in the chip latch effect test method provided in the embodiment of the present application, the beneficial effects that can be achieved by the chip latch effect test method provided in the embodiment of the present application can be achieved. For details, please refer to the previous embodiment, which will not be repeated here. The specific implementation of each of the above operations can be referred to the previous embodiment, which will not be repeated here.

[0140] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present application, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present application.

Claims

1. A chip latch effect test system, comprising: Circuit board; A fixing structure, arranged on the surface of the circuit substrate, for fixing the chip to be tested; A test structure, disposed on the surface of the circuit substrate, coupled to a plurality of pins of the chip to be tested through the fixing structure; A power supply unit, used to supply power to the chip under test; An excitation source, used to provide an excitation signal to the chip under test through the test structure during testing; The temperature alarm unit is used to monitor the package body temperature of the chip to be tested and compare the package body temperature of the chip to be tested with a predetermined temperature to indicate whether the chip to be tested has a latch effect under the current excitation signal according to the comparison result.

2. The chip latch effect test system according to claim 1, wherein: The temperature alarm unit is configured to: generate an alarm when the package temperature of the chip under test exceeds a predetermined temperature, so as to indicate that the chip under test has a latch effect under the action of the current excitation signal.

3. The chip latch effect test system according to claim 2, wherein: The power supply unit is configured to stop supplying power to the chip under test when the temperature of the package body of the chip under test exceeds a predetermined temperature.

4. The chip latch effect test system according to claim 2, wherein: The chip latch effect test system also includes: The hollow structure is arranged in the central area of ​​the fixing structure. After the chip to be tested is fixed on the fixing structure, the heat dissipation surface of the package of the chip to be tested is exposed outside the circuit substrate through the hollow structure.

5. The chip latch effect test system according to claim 4, wherein: The area of ​​the cavity structure is smaller than or equal to the heat dissipation surface area of ​​the package of the chip to be tested.

6. The chip latch-up effect test system according to claim 4, wherein: The temperature alarm unit comprises: A temperature sensor is disposed on the heat dissipation surface of the package of the chip to be tested through the hollow structure, and the temperature sensor obtains the package temperature of the chip to be tested by monitoring the heat dissipation surface temperature of the package of the chip to be tested; A temperature monitoring control circuit, the input end of which is coupled to the temperature sensor, receives the heat dissipation surface temperature of the package of the chip to be tested, compares it with the predetermined temperature, and generates a corresponding control signal according to the comparison result; The alarm has an input end coupled to the temperature monitoring control circuit and receives the control signal.

7. The chip latch-up effect test system according to claim 3, wherein: The power supply unit comprises: Power supply; A current sensor, used to detect the current flowing through the power pin of the chip to be tested; The current detection control circuit is coupled to the output end of the current sensor and is used to disconnect the power supply path for the power supply to supply power to the chip under test or control the power supply to stop supplying power to the chip under test when the current detected by the current sensor exceeds a preset current threshold.

8. The chip latch-up effect test system according to claim 7, wherein: The current sensor detects the current flowing through the power pin of the chip to be tested by the principle of electromagnetic induction.

9. The chip latch effect test system according to claim 1, wherein: The fixing structure and the testing structure are arranged on the same surface of the circuit substrate. The fixing structure is arranged in the central area of ​​the first surface of the circuit substrate, and the testing structure is arranged in the edge area of ​​the first surface of the circuit substrate.

10. The chip latch-up effect test system according to claim 9, wherein: The chip latch effect test system also includes: A power indicator light, disposed on the second surface of the circuit substrate, the power indicator light being coupled to a power pin of the chip to be tested; A program running indicator light is disposed on the second surface of the circuit substrate, and the program running indicator light is coupled to the first general input and output pin of the chip to be tested; A program running abnormality indicator light is arranged on the second surface of the circuit substrate, and the program running abnormality indicator light is coupled to the second general input and output pin of the chip to be tested; The power indicator light is used to indicate the power supply status of the chip under test provided by the power supply unit, and the program running indicator light and the program running abnormality indicator light are used to indicate the running status of the program in the chip under test.

11. The chip latch-up effect test system according to claim 10, wherein: The power indicator light, the program running indicator light and the program running abnormality indicator light are all light emitting diodes; When the power indicator light is in a normally on state, it indicates that the power supply unit supplies power to the chip under test normally; when the power indicator light is in an off state, it indicates that the power supply unit supplies power to the chip under test abnormally; When the program running indicator light is in a flashing state and the program running abnormality indicator light is in an off state, it indicates that the program in the chip under test is running normally; When the program running indicator light is in a constant on state, it indicates that the program in the chip under test stops running; When the program running abnormality indicator light is in a normally on state, it indicates that the program running in the chip under test is abnormal.

12. The chip latch-up effect test system according to claim 10, wherein: The chip latch effect test system also includes: A reset button is connected to the reset pin of the chip under test and is used to implement a reset operation on the program running in the chip under test.

13. The chip latch-up test system according to claim 9, wherein: The fixing structure fixes the chip to be tested by welding or in a detachable manner.

14. The chip latch-up effect testing system according to claim 1, wherein: The test structure includes a plurality of test pins, and the plurality of test pins are coupled to a plurality of pins of the chip to be tested in a one-to-one correspondence.

15. The chip latch-up test system according to claim 7, wherein: The power supply unit further includes: A display is used to numerically display the current detected by the current sensor.

16. The chip latch-up test system according to claim 1, wherein: The excitation source includes an electrostatic discharge simulator, and the excitation signal is an electrostatic signal.

17. The chip latch-up effect testing system according to claim 16, wherein: The electrostatic discharge simulator comprises: A high voltage power supply, used for providing a high voltage signal; The control unit is used to control the discharge parameters of the high voltage power supply and output the electrostatic signal, wherein the discharge parameters include at least one of a discharge voltage, a discharge number and a discharge interval.

18. A chip latch effect testing method, comprising: After the chip to be tested is powered on, running the program pre-burned in the chip to be tested; Applying an excitation signal to the test pin of the chip to be tested, while monitoring the package temperature of the chip to be tested; The package body temperature of the chip to be tested is compared with a predetermined temperature, and it is determined whether a latching effect exists in the chip to be tested under the action of the current excitation signal according to the comparison result.

19. The chip latch-up testing method according to claim 18, wherein: When the package temperature of the chip to be tested exceeds a predetermined temperature, determining that the chip to be tested has a latch effect under the action of the current excitation signal, and recording the current test result; When the package temperature of the chip to be tested does not exceed the predetermined temperature, it is determined that the chip to be tested does not have a latch effect under the action of the current excitation signal.

20. The chip latch-up testing method according to claim 19, wherein: When the package temperature of the chip under test does not exceed a predetermined temperature, determining that the chip under test does not have a latch effect under the action of the current excitation signal; as well as The chip latch effect testing method further includes: It is determined whether the program in the chip under test runs normally, and after the program runs normally or recovers to be normal, the excitation signal is increased.

21. An electronic device, comprising: A processor, a memory, and a program stored in the memory and executable on the processor, wherein the program implements the steps of the method according to any one of claims 18 to 20 when executed by the processor.

22. A storage medium having a computer program or instruction stored thereon, wherein the computer program or instruction, when executed by a processor, implements the steps of the method according to any one of claims 18 to 20.

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