Integrated circuit bias test method and system based on ATE equipment

Abstract

The invention relates to the technical field of integrated circuits, in particular to an integrated circuit bias test method and system based on ATE equipment, and the method comprises the following steps: an upper computer is connected with the ATE equipment through a GPIB, upper computer software is started, and corresponding test items are started; controlling the ATE to perform a voltage bias test to obtain the lowest and highest operating voltages of the chip, and performing a frequency bias test to obtain the highest operating frequency of the chip; selecting a fixed voltage step value between the lowest operating voltage and the highest operating voltage of the chip to carry out a frequency bias test; and drawing a combined bias two-dimensional result graph according to a bias result to obtain the optimal working voltage and frequency range of the chip. According to the invention, the limit values of the power supply voltage and the clock frequency of the integrated circuit can be determined, and the boundary and redundancy conditions are detected. Performance degradation can be evaluated through a pulling deviation test before and after a reliability test.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an integrated circuit pull-out test method and system based on ATE equipment. Background Art

[0002] Before integrated circuits enter the market, wafers (CP) and finished products (FT) must be tested on automatic test equipment (ATE). Traditional ATE testing usually evaluates integrated circuits at normal or extreme temperature conditions using standard power supply voltages and clock frequencies. However, this method cannot fully cover all possible voltage and clock frequency combinations, so it is impossible to determine the normal operating boundary conditions of integrated circuits under these combinations. In the aging test of reliability testing, only by testing the finished product (FT) on ATE equipment before and after aging, it can only be determined whether the chip can work normally under standard power supply voltage and clock frequency, but it is impossible to understand the maximum clock frequency that the integrated circuit can withstand under different voltage conditions, and the degradation of the maximum clock frequency before and after aging.

[0003] There are some problems in the existing technology, which are reflected in the patent application with application number CN202410510482.9. The method described in the patent application mainly focuses on the testing technology of integrated circuits. However, it only provides a testing method, which has certain limitations in practical applications. Specifically, the method cannot fully cover all possible voltage and clock frequency combinations, so it cannot ensure the normal working ability of the chip under various extreme conditions during the test process.

[0004] Since this method fails to take into account the impact of different voltage and clock frequency combinations on chip performance, the performance of the chip under extreme voltage and clock frequency cannot be fully verified in actual applications. This means that although this method can test the functionality of the chip to a certain extent, it is still unknown whether the chip can maintain a stable and reliable working state under extreme working conditions. This limitation may lead to some unforeseen problems in actual applications, thus affecting the stability and reliability of the entire system. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention discloses an integrated circuit pull-off test method and system based on ATE equipment, which are used to solve the above problems.

[0006] The present invention is achieved through the following technical solutions: In a first aspect, the present invention provides an integrated circuit pull-off test method based on ATE equipment, comprising the following steps: The host computer is connected to the ATE equipment via GPIB, the host computer software is started, and the corresponding test items are started; Control ATE equipment to perform voltage deviation test to obtain the minimum and maximum operating voltage of the chip, and perform frequency deviation test to obtain the maximum operating frequency of the chip; Select a fixed voltage step value between the lowest and highest operating voltages of the chip to perform frequency deviation test; According to the results of the pull-bias, a combined pull-bias two-dimensional result diagram is drawn to obtain the optimal operating voltage and frequency range of the chip.

[0007] Furthermore, in the method, when the voltage is pulled, the following steps are included: The ATE equipment provides the nominal input clock frequency and power supply voltage for the device under test according to the integrated circuit data sheet; The ATE equipment provides test vectors to the device under test, runs the test vectors, and determines the test results of the device under test; If the test result is passed, the host computer will instruct the ATE equipment to gradually reduce the power supply voltage and repeat the test steps until the result is failed, so as to determine the minimum operating voltage of the integrated circuit and record it; The host computer gradually increases the power supply voltage of the ATE equipment, repeats the test steps until failure, and records the maximum operating voltage of the integrated circuit.

[0008] Furthermore, in the method, when the frequency is pulled off, the following steps are included: The ATE equipment provides the nominal input clock frequency and power supply voltage for the device under test according to the integrated circuit data sheet; The ATE equipment provides test vectors to the device under test, runs the test vectors, and determines the test results of the device under test; If the test result is passed, the host computer will gradually increase the input clock frequency of the ATE equipment, repeat the test steps until the result fails, and then calculate and record the maximum operating frequency of the integrated circuit under the input clock frequency.

[0009] Furthermore, in the process of implementing the method, when the combined biasing operation is performed, the host computer is used to control the automatic test equipment (ATE) to ensure that the frequency biasing operation is performed on each voltage point in the entire range from the lowest operating voltage to the highest operating voltage of the integrated circuit. This process helps to comprehensively evaluate the performance of the integrated circuit under different voltage conditions.

[0010] Furthermore, in the process of drawing the combined pull-off two-dimensional diagram, the host computer plays a vital role in generating a two-dimensional result diagram of the integrated circuit power supply voltage and clock frequency boundary conditions. In this diagram, the X-axis represents different voltage values, and the Y-axis represents different frequency values. In order to intuitively display the test results, the results that meet the test standard PASS will be marked in green, and the results that fail the test standard FAIL will be marked in red. In this way, the boundary conditions of the integrated circuit under different power supply voltage and clock frequency combinations can be clearly seen.

[0011] Furthermore, during the combined biasing process, the host computer software also has the function of automatically adjusting the test parameters according to the test results. Specifically, the host computer software will dynamically adjust the step value of voltage and frequency according to the previous test results. This adaptive adjustment mechanism can improve the efficiency and accuracy of the test and ensure that the performance limit of the integrated circuit is found in the shortest time.

[0012] Furthermore, during the entire test process, the host computer software will record the voltage, frequency and test result data of each test point in real time. These data include not only the instantaneous values ​​during the test, but also the final test results. All these data will be saved in a database for subsequent analysis and query. In this way, the integrity and traceability of the test data can be ensured, providing strong data support for the performance evaluation and fault diagnosis of integrated circuits.

[0013] In a second aspect, the present invention provides an integrated circuit pull-out test system based on ATE equipment, the system is used to implement the integrated circuit pull-out test method based on ATE equipment described in the first aspect, comprising: Host computer: connect GPIB and ATE equipment, operate it to perform voltage and frequency deviation test, evaluate the device under test, and record and count the results to generate a two-dimensional result graph; ATE equipment: provides bias power and clock signals to the device under test (DUT), inputs test vectors, and evaluates the results to confirm that the device functions properly; Device under test (DUT): used to provide a biased power supply voltage and a biased input clock on the ATE device to run the test vector and output the test results to the ATE device.

[0014] Furthermore, the system also includes a database module, the main function of which is to store and manage test data. This database module is closely connected to the host computer software and can receive and save the voltage, frequency and test result data of each test point in real time. In addition, the database module also has a powerful historical test data query and analysis function, through which users can easily find and analyze past test data, so as to better understand the performance and historical performance of the equipment.

[0015] Furthermore, the system also includes a user interface module, which is closely connected to the host computer software and is used to display real-time data and two-dimensional result graphs during the test. The user interface module is very user-friendly and provides rich interactive functions, allowing users to flexibly adjust the step value of voltage and frequency according to their needs and preferences. In addition, users can also select different test items and conditions through this module to meet various different test needs. Such a design not only improves the flexibility and convenience of the test, but also greatly improves the user experience.

[0016] The beneficial effects of the present invention are: The present invention provides an effective method to accurately determine the minimum and maximum power supply voltage thresholds of an integrated circuit under normal operating conditions. In addition, it can identify the maximum clock frequency that the integrated circuit can withstand and the highest operating limit under a specific power supply voltage and clock frequency combination. In this way, we can detect the performance boundaries of the integrated circuit in terms of power supply voltage and clock frequency in detail.

[0017] Furthermore, the present invention can also reveal the redundancy of the integrated circuit in terms of voltage and frequency, that is, the ability of the integrated circuit to maintain stable operation under conditions beyond the normal operating range. The detection of such redundancy is of great significance for evaluating the reliability of the integrated circuit and designing redundant protection measures.

[0018] By performing the pull-off test before and after some reliability tests, the present invention can help us understand the performance degradation of the integrated circuit after long-term operation or operation in harsh environments. This test helps to evaluate the stability and life of the integrated circuit in practical applications, thereby providing an important reference for the design and optimization of the integrated circuit. In this way, we can ensure the reliability and stability of the integrated circuit under various working conditions, thereby improving the performance and safety of the entire system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 It is an overall flow chart of the integrated circuit pull-bias testing method based on ATE equipment of the present invention; Figure 2 This is a voltage biasing flow chart of an embodiment of the present invention; Figure 3 This is a frequency deviation flow chart of an embodiment of the present invention; Figure 4 This is a voltage & frequency combination rate deviation flow chart of an embodiment of the present invention; Figure 5 It is a voltage and frequency diagram of the present invention taking the ADP32F035 chip as an example; Figure 6 It is a principle structure diagram of the integrated circuit pull-bias test system based on ATE equipment of the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] In one embodiment, referring to Figure 1 As shown, a method for testing integrated circuit pull-off based on ATE equipment is disclosed, comprising the following steps: The host computer is connected to the ATE equipment via GPIB, the host computer software is started, and the corresponding test items are started; Control ATE equipment to perform voltage deviation test to obtain the minimum and maximum operating voltage of the chip, and perform frequency deviation test to obtain the maximum operating frequency of the chip; Select a fixed voltage step value between the lowest and highest operating voltages of the chip to perform frequency deviation test; According to the results of the pull-bias, a combined pull-bias two-dimensional result diagram is drawn to obtain the optimal operating voltage and frequency range of the chip.

[0023] In this embodiment, first, ensure that the GPIB connection between the host computer and the ATE device is correct and that the communication protocols of both parties are consistent. Start the host computer software and open the corresponding test project. In the host computer software, select and execute the voltage deviation test program. The program automatically controls the ATE device to perform voltage deviation on the chip, starting from the nominal voltage of the chip, and gradually reducing and increasing the voltage until the minimum and maximum operating voltage thresholds of the chip are reached.

[0024] This embodiment records the performance of the chip under different voltages, especially the performance data at the lowest and highest operating voltages. These data will be used as reference standards for subsequent tests. Next, perform a frequency deviation test. Select the frequency deviation test program in the host computer software, and set the operating voltage of the chip to the lowest and highest voltage values ​​recorded previously. The ATE equipment will test the chip according to the set frequency range to determine the highest operating frequency of the chip.

[0025] This implementation records the performance of the chip at different frequencies, especially the data at the highest operating frequency. These data will be used for the subsequent voltage & frequency combination pull-out test. In the host computer software, set the voltage step value, which is used to perform the voltage & frequency combination pull-out test between the lowest and highest operating voltages of the chip. Generally, the smaller the step value, the more accurate the test result, but the test time will also increase accordingly.

[0026] This embodiment performs a voltage & frequency combination pull-off test. The ATE equipment will perform a comprehensive test on the chip according to the set voltage step value and frequency range, and record the performance of the chip under different voltage and frequency combinations.

[0027] After the test of this embodiment is completed, the host computer software will collect and organize all the test data. Using these data, a combined pull-off two-dimensional result graph is generated. This graph will show the performance of the chip under different voltage and frequency combinations, helping engineers evaluate the stability and reliability of the chip.

[0028] This embodiment analyzes the two-dimensional result graph to determine the optimal operating voltage and frequency range of the chip. These data are of great significance for chip design optimization, production process control and quality assurance of the final product.

[0029] This embodiment organizes the test results and analysis reports into documents for reference by relevant engineers and managers, ensuring that all relevant personnel understand the performance characteristics and potential risks of the chip so that they can take corresponding measures in subsequent design, production and application.

[0030] In one embodiment, if Figure 2 As shown, when voltage deviation is performed, the following steps are included: The ATE equipment provides the nominal input clock frequency and power supply voltage for the device under test according to the integrated circuit data sheet; The ATE equipment provides test vectors to the device under test, runs the test vectors, and determines the test results of the device under test; If the test result is passed, the host computer will instruct the ATE equipment to gradually reduce the power supply voltage and repeat the test steps until the result is failed, so as to determine the minimum operating voltage of the integrated circuit and record it; The host computer gradually increases the power supply voltage of the ATE equipment, repeats the test steps until failure, and records the maximum operating voltage of the integrated circuit.

[0031] In one embodiment, if Figure 3 As shown, when the frequency is pulled off, the following steps are included: The ATE equipment provides the nominal input clock frequency and power supply voltage for the device under test according to the integrated circuit data sheet; The ATE equipment provides test vectors to the device under test, runs the test vectors, and determines the test results of the device under test; If the test result is passed, the host computer will gradually increase the input clock frequency of the ATE equipment, repeat the test steps until the result fails, and then calculate and record the maximum operating frequency of the integrated circuit under the input clock frequency.

[0032] In the process of executing the above method, when it comes to the combined bias operation, we will also use the host computer to control the automatic test equipment (ATE). The purpose of this operation is to ensure that the frequency bias operation is performed on each voltage point in the entire range from the lowest operating voltage to the highest operating voltage of the integrated circuit. This process is of great significance for comprehensively evaluating and reviewing the performance of the integrated circuit under different voltage conditions.

[0033] In this embodiment, the host computer plays a vital role in the process of drawing the combined pull-off two-dimensional diagram. It is responsible for generating a two-dimensional result diagram of the integrated circuit power supply voltage and clock frequency boundary conditions. In this chart, the X-axis represents different voltage values, and the Y-axis represents different frequency values. In order to make the test results more intuitive and easy to understand, the results that meet the test standard PASS will be marked in green, and the results that fail the test standard FAIL will be marked in red. In this way, we can clearly observe the boundary conditions of the integrated circuit under different power supply voltage and clock frequency combinations, so as to better evaluate its performance and stability.

[0034] In one embodiment, referring to Figure 4As shown in the figure, the voltage & frequency combined frequency deviation process is as follows. During the execution of the combined deviation, the host computer software also has the function of automatically adjusting the test parameters according to the test results. Specifically, the host computer software will dynamically adjust the step value of voltage and frequency according to the previous test results. This adaptive adjustment mechanism can significantly improve the efficiency and accuracy of the test, ensuring that the performance limit of the integrated circuit is found in the shortest time. In this way, the host computer software can intelligently optimize the test process and avoid the tedious and inefficient manual adjustment of parameters. It can flexibly adjust the step value of voltage and frequency according to the actual test situation, so as to approach the optimal working state of the integrated circuit more quickly. This intelligent testing method not only improves the efficiency of the test, but also greatly reduces the time required for testing, making the entire test process more efficient and accurate.

[0035] In the present embodiment, the host computer software will record the voltage, frequency and test result data of each test point in real time during the whole test process. These data include not only the instantaneous value during the test process, but also the final test result. All these data will be stored in a database for subsequent analysis and query. In this way, the integrity and traceability of the test data can be ensured, and strong data support can be provided for the performance evaluation and fault diagnosis of the integrated circuit. In addition, the host computer software will also classify and mark these data in detail so that relevant information can be quickly located and retrieved when needed. This method of real-time recording and detailed classification not only improves the efficiency of data processing, but also enhances the reliability of data, thereby providing engineers with a more accurate and comprehensive reference basis when designing and optimizing integrated circuits.

[0036] In one embodiment, Figure 5 As shown, taking the ADP32F035 chip as an example, the ATE equipment uses the CHROMA3380 model. First, the highest and lowest operating voltages of the ADP32F035 chip are determined through a voltage bias test. The test results show that the highest operating voltage of the chip is 1.9 volts, while the lowest operating voltage is 1.6 volts. Next, through the frequency bias test, we obtained the highest clock frequency of the chip, which was 107 megahertz. Finally, through the combined bias test of voltage and frequency, the host computer draws a two-dimensional result graph of the combined bias. In this figure, the X-axis represents voltage and the Y-axis represents frequency. In this way, we can intuitively see the test results under different voltage and frequency combinations.

[0037] from Figure 5We can observe that when the ADP32F035 chip operates at the lowest voltage of 1.6 volts, its maximum input clock period is 58 nanoseconds, which is equivalent to a frequency of 17.24 megahertz. Since the PLL (phase-locked loop) inside the chip is fixed at 6 times the frequency, at 1.6 volts, the maximum clock frequency is 17.24 times 6, or 103.44 megahertz. At the highest operating voltage of 1.9 volts, the chip's maximum clock frequency reaches 107.14 megahertz. The nominal VDD voltage of the ADP32F035 chip is 1.8 volts, and the clock frequency is 60 megahertz. Figure 5 We can learn about the performance of the ADP32F035 integrated circuit under different working conditions. Under the nominal voltage and clock frequency, the maximum clock frequency of the ADP32F035 integrated circuit has a margin of 47 MHz, and the voltage margin range is between 1.6 volts and 1.9 volts.

[0038] In one embodiment, a pull-out test system for integrated circuits based on ATE equipment is provided, comprising: Host computer: connect GPIB to ATE equipment, operate it to perform voltage and frequency deviation tests, evaluate the device under test, and record and count the results to generate a two-dimensional result graph; ATE equipment: provides bias power and clock signals to the device under test (DUT), inputs test vectors, and evaluates the results to confirm that the device functions properly; Device under test (DUT): used to provide a biased power supply voltage and a biased input clock on the ATE device to run the test vector and output the test results to the ATE device.

[0039] In a specific embodiment of the present system, in addition to other components, a database module is also included. The main function of this database module is to store and manage test data. It is closely connected to the host computer software and can receive and save the voltage, frequency and test result data of each test point in real time. In addition, the database module also has a powerful historical test data query and analysis function, through which users can easily find and analyze past test data to better understand the performance and historical performance of the equipment. In this way, users can track and evaluate the operating status of the equipment in detail and make more informed decisions.

[0040] In another embodiment, the system also includes a user interface module. This module is closely connected to the host computer software and is used to display real-time data and two-dimensional result graphs during the test. The design of the user interface module is very user-friendly and provides rich interactive functions, allowing users to flexibly adjust the step values ​​of voltage and frequency according to their needs and preferences. In addition, users can also select different test items and conditions through this module to meet various different test requirements. Such a design not only improves the flexibility and convenience of the test, but also greatly improves the user experience. Users can easily make various settings and adjustments to make the test process more efficient and intuitive. Through the friendly user interface, users can understand the test results more intuitively, so as to make more accurate judgments and decisions.

[0041] In summary, the present invention provides an effective method to accurately determine the minimum and maximum power supply voltage thresholds of an integrated circuit under normal operating conditions. In addition, it can also identify the maximum clock frequency that the integrated circuit can withstand, as well as the highest operating limit under a specific power supply voltage and clock frequency combination. In this way, we can detect the performance boundaries of the integrated circuit in terms of power supply voltage and clock frequency in detail.

[0042] The present invention can also reveal the redundancy of the integrated circuit in terms of voltage and frequency, that is, the ability of the integrated circuit to maintain stable operation under conditions beyond the normal operating range. The detection of such redundancy is of great significance for evaluating the reliability of the integrated circuit and designing redundant protection measures.

[0043] By performing the pull-off test before and after some reliability tests, the present invention can help us understand the performance degradation of the integrated circuit after long-term operation or operation in harsh environments. This test helps to evaluate the stability and life of the integrated circuit in practical applications, thereby providing an important reference for the design and optimization of the integrated circuit. In this way, we can ensure the reliability and stability of the integrated circuit under various working conditions, thereby improving the performance and safety of the entire system.

[0044] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for testing integrated circuit pull-off based on ATE equipment, characterized in that: The following steps are involved: The host computer is connected to the ATE equipment via GPIB, the host computer software is started, and the corresponding test items are started; Control ATE equipment to perform voltage deviation test to obtain the minimum and maximum operating voltage of the chip, and perform frequency deviation test to obtain the maximum operating frequency of the chip; Select a fixed voltage step value between the lowest and highest operating voltages of the chip to perform frequency deviation test; According to the results of the pull-bias, a combined pull-bias two-dimensional result diagram is drawn to obtain the optimal operating voltage and frequency range of the chip.

2. The integrated circuit pull-off test method based on ATE equipment according to claim 1, characterized in that: In the method, when voltage biasing is performed, the following steps are included: The ATE equipment provides the nominal input clock frequency and power supply voltage for the device under test according to the integrated circuit data sheet; The ATE equipment provides test vectors to the device under test, runs the test vectors, and determines the test results of the device under test; If the test result is passed, the host computer will instruct the ATE equipment to gradually reduce the power supply voltage and repeat the test steps until the result is failed, so as to determine the minimum operating voltage of the integrated circuit and record it; The host computer gradually increases the power supply voltage of the ATE equipment, repeats the test steps until failure, and records the maximum operating voltage of the integrated circuit.

3. The integrated circuit pull-off test method based on ATE equipment according to claim 1, characterized in that: In the method, when the frequency is pulled off, the following steps are included: The ATE equipment provides the nominal input clock frequency and power supply voltage for the device under test according to the integrated circuit data sheet; The ATE equipment provides test vectors to the device under test, runs the test vectors, and determines the test results of the device under test; If the test result is passed, the host computer will gradually increase the input clock frequency of the ATE equipment, repeat the test steps until the result fails, and then calculate and record the maximum operating frequency of the integrated circuit under the input clock frequency.

4. The integrated circuit pull-off test method based on ATE equipment according to claim 1, characterized in that: In the method, during the combined deflection process, the host computer is simultaneously controlled to control the ATE test equipment to ensure that the frequency deflection operation is performed on each voltage point within the minimum to maximum operating voltage range of the integrated circuit.

5. The integrated circuit pull-off test method based on ATE equipment according to claim 1, characterized in that: In the method, in the process of drawing the combined bias two-dimensional graph, the host computer is responsible for generating a two-dimensional result graph of the integrated circuit power supply voltage and clock frequency boundary conditions, in which the X-axis represents the voltage value and the Y-axis represents the frequency value.

6. The integrated circuit pull-off test method based on ATE equipment according to claim 1, characterized in that: In the method, during the combined deflection process, the host computer software can also automatically adjust the test parameters according to the test results, and dynamically adjust the step values ​​of voltage and frequency according to the previous test results.

7. The integrated circuit pull-off test method based on ATE equipment according to claim 1, characterized in that: In the method, during the test process, the host computer software records the voltage, frequency and test result data of each test point in real time, and stores these data in a database.

8. An integrated circuit pull-out test system based on ATE equipment, the system is used to implement an integrated circuit pull-out test method based on ATE equipment as claimed in any one of claims 1 to 7, characterized in that: include Host computer: connect GPIB and ATE equipment, operate it to perform voltage and frequency deviation test, evaluate the device under test, and record and count the results to generate a two-dimensional result graph; ATE equipment: provides bias power and clock signals to the device under test (DUT), inputs test vectors, and evaluates the results to confirm that the device functions properly; Device under test (DUT): used to provide a biased power supply voltage and a biased input clock on the ATE device to run the test vector and output the test results to the ATE device.

9. The integrated circuit pull-off test system based on ATE equipment according to claim 8, characterized in that: The system also includes a database module for storing and managing test data. The database module is connected to the host computer software and can receive and save the voltage, frequency and test result data of each test point in real time. The database module also provides query and analysis functions for historical test data.

10. The integrated circuit pull-off test system based on ATE equipment according to claim 8, characterized in that: The system also includes a user interface module, which is connected to the host computer software and is used to display real-time data and two-dimensional result graphs during the test process. The user interface module also provides an interactive function, allowing the user to adjust the step value of voltage and frequency as needed, and select different test items and conditions.

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