A quantitative chip test management method, device and storage medium

Abstract

The present invention relates to the field of chip data processing technology, and specifically discloses a quantitative chip test management method, device and storage medium. The method monitors and records the internal key dynamic change parameters of the test chip to quantitatively evaluate the internal fluctuation index of the test chip, screens out chips with stable performance and performs subsequent packaging processing, thereby reducing the demand for after-sales maintenance and replacement of chips to improve the reliability of chip use, obtains packaging parameters of the pre-inspection chip packaging processing process, analyzes the packaging stability index of the pre-inspection chip, and provides data basis for optimizing the chip packaging process. Finally, the working parameters of the final inspection chip are obtained, and the working interference index of the final inspection chip is determined, which is helpful to identify problems encountered by the chip during operation and provide direction for improving chip design. Management feedback is thus performed on the final inspection chip test to complete the multi-dimensional test management process of the chip.

Description

Technical Field

[0001] The present invention relates to the field of chip data processing technology, and in particular to a quantitative chip test management method, device and storage medium. Background Art

[0002] With the continuous advancement and complexity of chip technology, effective management of the chip testing process, especially the management of dynamic changes and internal fluctuations, has become the focus of industry attention. Traditional chip testing management methods often rely on the measurement and analysis of chip static parameters, but cannot effectively test the dynamic changes inside the chip, which has a great negative impact on chip performance stability and reliability.

[0003] For example, the invention patent with announcement number CN104123212B discloses a system testing method for USB chips, which is used to perform system testing on USB3.0 chips, and includes the following steps: a. The detection coding module marks all logical states in the standard USB3.0 chip in sequence to generate corresponding marking functions; b. The detection coding module encodes the marking functions corresponding to the internal logical states of the chip according to the set coding rules to form standard coding values, and records the standard coding values ​​in the standard file library; c. During the simulation process of the USB3.0 chip to be tested, the detection module encodes the internal logical states of the USB3.0 chip to be tested according to the same coding rules, records the obtained coding values ​​in a temporary file, compares the coding value content with the standard coding value content, and searches for coding value contents with inconsistent comparison results.

[0004] For example, the invention patent with announcement number CN111966554B discloses a chip testing method and a computing chip; the chip testing method includes: receiving a test vector via an input interface of the computing chip to be tested; for each of the multiple cores to be tested in the computing chip, performing the following operations: transmitting the test data of the core to the core through a state machine of the computing chip, wherein the test data is generated based on the test vector; obtaining result data generated by the core based on the test data through the state machine; and outputting the test result via an output interface of the computing chip, wherein the test result is generated based on the result data of the multiple cores to be tested.

[0005] However, in the process of implementing the embodiments of the present application, it was found that the above-mentioned technology has at least the following technical problems: the current chip testing method usually only focuses on static testing and analysis in a single dimension, which makes the chip testing relatively one-sided. However, with the increasing complexity and diversity of modern electronic devices, one-sided chip testing will lead to low stability of the test chip, which is not conducive to the actual application of the chip. Summary of the invention

[0006] In view of the deficiencies in the prior art, the present invention provides a quantitative chip test management method, device and storage medium, which can effectively solve the problems involved in the above-mentioned background technology.

[0007] To achieve the above objectives, the present invention is implemented through the following technical solutions: The first aspect of the present invention provides a quantitative chip test management method, including: S1. Based on the test execution process of the test chip, monitor and record the internal key dynamic change parameters of the test chip during the test execution cycle, so as to quantitatively evaluate the internal fluctuation index of the test chip; S2. Compare the internal fluctuation index of the test chip with the internal fluctuation threshold. If the internal fluctuation index of the test chip is less than the internal fluctuation threshold, mark the test chip as a pre-inspection chip and perform packaging processing, obtain the packaging parameters of the pre-inspection chip, and analyze the packaging stability index of the pre-inspection chip; S3. Record the pre-inspection chip that has completed the packaging processing as the final inspection chip, obtain the working parameters of the final inspection chip, and determine the working interference index of the final inspection chip, thereby managing and feedback the final inspection chip test, and finally completing the chip test management process.

[0008] As a further method, the internal key dynamically changing parameters of the test chip during the test execution cycle specifically include various delay durations of each memory access of the test chip during the test execution cycle.

[0009] As a further method, the final inspection chip test is managed and fed back, and the chip test management process is finally completed. The specific analysis process is: the working interference index of the final inspection chip is compared with the working interference threshold. If the working interference index of the final inspection chip is greater than the working interference threshold, the chip test feedback system manages and feeds back the final inspection chip test, and finally completes the chip test management process.

[0010] The second aspect of the present invention provides a device for the quantitative chip test management method, characterized in that it includes: a chip, a processor, and a chip test feedback system; the chip is used to execute the test process; the processor is used to process the internal key dynamic change parameters of the test chip during the test execution cycle, the packaging parameters of the pre-inspection chip, and the working parameters of the final inspection chip, and transmit the determined working interference index of the final inspection chip to the chip test feedback system via the Internet; the chip test feedback system is used to receive the working interference index of the final inspection chip of the processor, and manage feedback on the final inspection chip test, and finally complete the chip test management process.

[0011] A third aspect of the present invention provides a computer-readable storage medium for storing a program, wherein the program, when executed by a processor, implements the quantitative chip test management method.

[0012] Compared with the prior art, the embodiments of the present invention have at least the following advantages or beneficial effects:

[0013] (1) The present invention provides a quantitative chip test management method, device and storage medium. By monitoring and recording the internal key dynamic change parameters of the test chip, the internal fluctuation index of the test chip is quantitatively evaluated, and the test chip with an internal fluctuation index less than the internal fluctuation threshold is marked as a pre-test chip, thereby screening out chips with stable performance and performing subsequent packaging processing, which can reduce the demand for after-sales maintenance and replacement of chips to improve the reliability of chip use, obtain the packaging parameters of the pre-test chip packaging process, and analyze the packaging stability index of the pre-test chip to provide a data basis for optimizing the chip packaging process. Finally, the working parameters of the final inspection chip are obtained, and the working interference index of the final inspection chip is determined, which helps to identify problems encountered by the chip during operation and provide direction for improving chip design. Management feedback is thus provided for the final inspection chip test to complete the multi-dimensional test management process of the chip.

[0014] (2) The present invention quantitatively evaluates the internal fluctuation index of the test chip to screen the test chip whose internal fluctuation index is less than the internal fluctuation threshold, thereby reducing the risk of performance degradation caused by internal fluctuations during the chip operation process and helping the various use links of the chip to operate more stably.

[0015] (3) The present invention can accurately evaluate the performance stability of the chip during operation by obtaining and analyzing the power consumption fluctuation amplitude, the total value of the power consumption fluctuation offset, and the average roughness of the ground plane to which the chip belongs, thereby reducing the error caused by the traditional testing method that relies only on a single indicator. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention is further described using the accompanying drawings, but the embodiments in the accompanying drawings do not constitute any limitation to the present invention. A person skilled in the art can obtain other drawings based on the following drawings without creative work.

[0017] Figure 1 The figure is a schematic flow chart of the method steps of the present invention.

[0018] Figure 2 It is a schematic diagram of the power consumption fluctuation curve involved in the present invention. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0020] Reference Figure 1 As shown, the first aspect of the present invention provides a quantitative chip test management method, including: S1. Based on the test execution process of the test chip, monitor and record the internal key dynamic change parameters of the test chip during the test execution cycle, so as to quantitatively evaluate the internal fluctuation index of the test chip; the above-mentioned test execution cycle refers to a time period during the test execution process of the test chip, and the specific test execution cycle duration is determined by the chip test engineer according to actual conditions.

[0021] In a specific embodiment, the present invention quantitatively evaluates the internal fluctuation index of the test chip to screen the test chip whose internal fluctuation index is less than the internal fluctuation threshold, thereby reducing the risk of performance degradation due to internal fluctuations during chip operation and helping each use link of the chip to operate more stably.

[0022] Specifically, the internal key dynamically changing parameters of the test chip during the test execution cycle include various delay durations of each memory access of the test chip during the test execution cycle. It should be explained that the various delay durations include row valid to pre-charge delay duration, row addressing to column addressing delay duration, read latency duration and row pre-charge duration. The total duration corresponding to each memory access is theoretically greater than the sum of various delay durations of each memory access.

[0023] Specifically, the internal fluctuation index of the test chip is compared with the internal fluctuation threshold. The specific process is: if the internal fluctuation index of the test chip is less than the internal fluctuation threshold, the test chip is marked as a pre-qualified chip and packaged; if the internal fluctuation index of the test chip is greater than or equal to the internal fluctuation threshold, the internal fluctuation status of the test chip is fed back; the above internal fluctuation threshold is formulated by chip test engineers based on the impact of the chip's historical internal fluctuations on chip performance, and represents the maximum value of the qualified range of the internal fluctuation index of the test chip; if the internal fluctuation index of a test chip is less than the internal fluctuation threshold, it indicates that the internal fluctuation of the test chip is within its normal operation and acceptable performance. range, will not have a significant impact on the overall performance of the test chip, so the test chip is marked as a pre-qualified chip and packaged; if the internal fluctuation index of a test chip is greater than or equal to the internal fluctuation threshold, it indicates that the internal fluctuation of the test chip exceeds its normal operation and acceptable performance range, and has a significant impact on the overall performance of the test chip, so feedback is given on the internal fluctuation status of the test chip. The specific feedback process is: the chip test feedback system generates an early warning log for the test chip, which contains the abnormal causes of the internal fluctuations of the test chip and the corresponding solutions. The chip test engineer can manage the test chip based on the early warning log of the test chip.

[0024] Furthermore, the internal fluctuation index of the test chip is quantitatively evaluated, and the specific analysis process is as follows: various delay durations of each memory access of the test chip during the test execution cycle are accumulated to obtain the total delay duration of each memory access of the test chip during the test execution cycle, and the total duration of each memory access of the test chip during the test execution cycle is obtained, and the total delay duration of each memory access of the test chip during the test execution cycle is sequentially subjected to ratio analysis and mean processing to obtain the average memory delay factor of the test chip during the test execution cycle; the various delay durations of each memory access of the test chip during the test execution cycle and the above delay durations are added together. The total duration of each memory access of the test chip during the test execution cycle can be extracted from the timing parameters of each memory access captured by the logic analyzer; the average memory delay factor of the test chip during the test execution cycle is obtained by the following process: the total delay duration of each memory access of the test chip during the test execution cycle is respectively analyzed with the total duration of each corresponding memory access to obtain the memory delay factors of the test chip during the test execution cycle, and then the memory delay factors of the test chip during the test execution cycle are averaged to obtain the average memory delay factor of the test chip during the test execution cycle.

[0025] The total delay duration of each memory access of the test chip within the memory execution end fluctuation time period is obtained, marked as the total delay duration of each fluctuation of the test chip within the memory execution end fluctuation time period, and a comprehensive analysis is performed with the fluctuation stable reference delay duration. It needs to be explained that the memory execution end fluctuation time period refers to the end time period of the test execution cycle, which is a part of the test execution cycle.

[0026] Thus, the internal fluctuation index of the test chip is obtained. In this embodiment, the internal fluctuation index of the test chip is obtained by comprehensive analysis of the average memory delay factor of the test chip in the test execution cycle and the total delay duration of each fluctuation of the test chip in the memory execution end fluctuation time period, and is used to evaluate the internal fluctuation degree of the test chip. The specific expression is:

[0027] ;

[0028] in, is the internal fluctuation index of the test chip. If the total delay duration of each fluctuation of the test chip within the fluctuation time period at the end of memory execution deviates greatly from the reference delay duration of fluctuation stability, it indicates that the internal structure of the chip is not yet stable, which will cause the average memory delay factor of the test chip to increase, and together lead to large internal fluctuations of the test chip, which is not conducive to the stability of the chip. Therefore, the internal fluctuation index of the test chip is quantitatively evaluated by the average memory delay factor of the test chip in the test execution cycle and the total delay duration of each fluctuation of the test chip within the fluctuation time period at the end of memory execution. Potential performance instability can be discovered in the early stages of the chip, which helps to take corrective measures in time and avoid more serious problems in the chip application stage.

[0029] To test the average memory delay factor of the chip during the test execution cycle, the memory access performance of the chip can be evaluated by quantifying the average memory delay factor. A lower average memory delay factor means a faster memory access speed, indicating that the memory access performance of the chip is relatively stable.

[0030] is the total delay duration of the xth fluctuation of the test chip within the memory execution end fluctuation time period. The total delay duration of each fluctuation of the test chip within the memory execution end fluctuation time period can reflect the stability of the internal structure of the chip. If the deviation between the total delay duration of each fluctuation of the test chip within the memory execution end fluctuation time period and the fluctuation stability reference delay duration is small, it reflects that the internal structure of the test chip tends to be stable.

[0031] It is the reference delay time for fluctuation stability, which represents the reference value of the total delay time for analyzing each fluctuation, extracted from the chip design specifications.

[0032] It is the influence factor corresponding to the unit value of the average memory delay factor preset in the chip management information library, which represents the influence degree of the unit value of the average memory delay factor on the internal fluctuation index of the test chip. The fitting curve corresponding to the average memory delay factor can be obtained by fitting the relationship between the historical chip cache size, the historical chip processing rate and the average memory delay factor, and the fitting curve corresponding to the average memory delay factor is brought into the fitting curve according to the real-time chip cache size and the chip processing rate, thereby obtaining the influence factor corresponding to the unit value of the average memory delay factor in this example. The value range of this value in this example is 0 to 1.

[0033] It is the influence factor corresponding to the unit value of the total delay deviation time of fluctuation preset in the chip management information library, which represents the influence degree of the unit value of the total delay deviation time of fluctuation on the internal fluctuation index of the test chip. The fitting curve corresponding to the total delay deviation time of fluctuation can be obtained by fitting the relationship between the historical memory clock cycle time, the historical chip ambient temperature and the total delay deviation time of fluctuation, and the fitting curve corresponding to the total delay deviation time of fluctuation is brought into the fitting curve according to the real-time memory clock cycle time and the ambient temperature of the chip, so as to obtain the influence factor corresponding to the unit value of the total delay deviation time of fluctuation in this example. The value range of this value in this example is 0 to 1.

[0034] It should be explained that the above-mentioned chip management information base refers to a database that stores relevant parameters during the chip testing process.

[0035] x is the number of the total delay time of each wave, , p is the total number of fluctuations in total delay time.

[0036] S2. Compare the internal fluctuation index of the test chip with the internal fluctuation threshold. If the internal fluctuation index of the test chip is less than the internal fluctuation threshold, mark the test chip as a pre-qualified chip and perform packaging processing to obtain the packaging parameters of the pre-qualified chip, thereby analyzing the packaging stability index of the pre-qualified chip.

[0037] Specifically, the analysis of the packaging stability index of the pre-qualified chip has the following specific analysis process: according to the packaging parameters of the pre-qualified chip, the weight of the pre-qualified chip at the end time of the packaging inspection cycle and the weight of the pre-qualified chip at the beginning time of the packaging inspection cycle are extracted, and difference processing is performed to obtain the additional packaging weight of the pre-qualified chip during the packaging inspection cycle; the above-mentioned packaging inspection cycle represents a cycle for inspecting the packaging performance of the pre-qualified chip, and its specific duration is determined by the chip testing engineer according to actual conditions; the weight of the pre-qualified chip at the end time of the packaging inspection cycle and the weight of the pre-qualified chip at the beginning time of the packaging inspection cycle can be obtained by weighing with a high-precision electronic balance; it should be explained that the additional packaging weight of the pre-qualified chip during the packaging inspection cycle refers to the weight of the pre-qualified chip at the end time of the packaging inspection cycle minus the weight of the pre-qualified chip at the beginning time of the packaging inspection cycle.

[0038] According to the packaging parameters of the pre-qualified chip, a chip scan image of the pre-qualified chip at the end time of the packaging inspection cycle is extracted to locate the center position points of each solder ball in the pre-qualified chip, and a one-to-one correspondence is made with the preset center position points of each solder ball in the pre-qualified chip, thereby obtaining the offset distances of each solder ball of the pre-qualified chip through distance measurement, and the total offset distance of the solder balls of the pre-qualified chip is obtained by accumulation processing; the chip scan image of the pre-qualified chip at the end time of the packaging inspection cycle is obtained by scanning with an X-ray fluoroscopy device; the preset center position points of each solder ball in the pre-qualified chip are extracted from the design files provided by the chip design engineer.

[0039] The contour shape diagram of each heat dissipation hole in the pre-qualified chip is extracted from the chip scanning image at the end time point of the packaging inspection cycle of the pre-qualified chip, and area analysis and mean processing are performed in sequence to obtain the average area of ​​the heat dissipation holes of the pre-qualified chip. The average area of ​​the heat dissipation holes of the pre-qualified chip is specifically obtained by: directly detecting the edges in the image through an edge detection algorithm, and extracting the contour shape diagram of each heat dissipation hole in the pre-qualified chip through threshold processing and contour connection, and then using automatic computer-aided design software to calculate the area of ​​the contour shape diagram of each heat dissipation hole in the pre-qualified chip, thereby obtaining the area of ​​each heat dissipation hole in the pre-qualified chip, and after mean processing the area of ​​each heat dissipation hole in the pre-qualified chip, the average area of ​​the heat dissipation holes of the pre-qualified chip is obtained.

[0040] The package stability index of the pre-qualified chip is obtained by comprehensive analysis. In this embodiment, the package stability index of the pre-qualified chip is obtained by comprehensive analysis of the total distance of solder ball offset, the average area of ​​the heat dissipation hole and the package additional weight during the package detection cycle of the pre-qualified chip. It is a numerical value used to determine the package stability of the pre-qualified chip. The specific expression is:

[0041] ;

[0042] in, It is the packaging stability index of the pre-examination chip. If the additional weight of the package of the pre-examination chip is too large, it will affect the positioning accuracy of the solder balls and the design space of the heat dissipation holes. The solder ball offset may further cause the heat dissipation holes to be blocked or reduced, thereby reducing the heat dissipation performance of the chip. At the same time, the solder ball offset will lead to poor electrical connection between the chip and the substrate, increasing the risk of chip failure, thereby jointly affecting the packaging stability performance of the pre-examination chip. The comprehensive quantitative evaluation of the additional weight of the package of the pre-examination chip, the total distance of the solder ball offset and the average area of ​​the heat dissipation holes improves the accuracy and objectivity of the chip packaging quality evaluation, and provides different dimensional indicators for testing chip quality.

[0043] The package weight is added to the pre-qualified chip during the packaging inspection cycle. Too much package weight will increase the overall weight of the chip, which may have a negative impact on the installation and layout of the pre-qualified chip during application.

[0044] The total distance of solder ball offset of the pre-qualified chip is too large, which may lead to poor electrical connection between the pre-qualified chip and the substrate, and have a negative impact on signal transmission and stability.

[0045] It is the average area of ​​the heat dissipation holes of the pre-qualified chip. If the average area of ​​the heat dissipation holes is too small, the heat generated by the pre-qualified chip during operation cannot be dissipated in time, causing the temperature of the pre-qualified chip to be too high, affecting the performance and service life of the pre-qualified chip.

[0046] Defines the distance for solder ball offset, indicating the maximum value of the total distance of solder ball offset analysis, which is determined by chip test engineers based on chip performance.

[0047] The reference area of ​​the heat dissipation holes indicates the reference value for analyzing the average area of ​​the heat dissipation holes, which is determined by chip test engineers based on chip performance.

[0048] It is the impact factor corresponding to the unit value of the package additional weight preset in the chip management information library, which represents the degree of influence of the unit value of the package additional weight on the package stability index of the pre-examined chip. The fitting curve corresponding to the package additional weight is obtained by fitting the relationship between the historical chip packaging material density, the historical chip packaging volume and the package additional weight, and the fitting curve corresponding to the package additional weight is brought into the fitting curve according to the real-time chip packaging material density and the chip packaging volume, thereby obtaining the impact factor corresponding to the unit value of the package additional weight in this example. The value range of this value in this example is 0 to 1.

[0049] It is the correction factor corresponding to the total distance of solder ball offset preset in the chip management information library, which represents the numerical value of the degree of correction for the change of the total distance of solder ball offset. The fitting curve corresponding to the total distance of solder ball offset is obtained by fitting the relationship between the historical thermal expansion coefficient of chip packaging material, the historical average temperature of chip packaging and the total distance of solder ball offset. The fitting curve corresponding to the total distance of solder ball offset is brought into the fitting curve according to the real-time thermal expansion coefficient of chip packaging material and the average temperature of chip packaging, thereby obtaining the correction factor corresponding to the total distance of solder ball offset in this example. The value range of this numerical value in this example is 0 to 1.

[0050] It is the correction factor corresponding to the average area of ​​the heat dissipation holes preset in the chip management information library, which represents the numerical value of the degree of correction for the change in the average area of ​​the heat dissipation holes. The fitting curve corresponding to the average area of ​​the heat dissipation holes is obtained by fitting the relationship between the historical maximum diameter of the heat dissipation holes of the chip, the historical number of heat dissipation holes of the chip and the average area of ​​the heat dissipation holes. The fitting curve corresponding to the average area of ​​the heat dissipation holes is brought into the fitting curve according to the real-time maximum diameter of the chip heat dissipation holes and the number of chip heat dissipation holes, thereby obtaining the correction factor corresponding to the average area of ​​the heat dissipation holes in this example. The value range of this numerical value in this example is 0 to 1.

[0051] In this exemplary embodiment, the change table of the packaging stability index of the pre-qualified chip and its corresponding parameters is shown in Table 1:

[0052] Table 1 Pre-qualified chip packaging stability index and its corresponding parameter changes

[0053]

[0054] In this example embodiment, the value of the influence factor corresponding to the unit value of the additional weight of the package is 0.3, the value of the correction factor corresponding to the total distance of the solder ball offset is 0.4, the value of the correction factor corresponding to the average area of ​​the heat dissipation hole is 0.5, the solder ball offset limit distance is set to 0.5 mm, and the reference area of ​​the heat dissipation hole is set to 2 square millimeters. It can be clearly understood from Table 1 that the smaller the additional weight of the package, the smaller the total distance of the solder ball offset and the smaller the deviation of the average area of ​​the heat dissipation hole, the greater the package stability index.

[0055] S3. The pre-inspected chip that has completed the packaging process is recorded as the final inspection chip, the working parameters of the final inspection chip are obtained, and the working interference index of the final inspection chip is determined, thereby managing and feedback is provided on the final inspection chip test, and finally completing the chip test management process.

[0056] In a specific embodiment, the present invention can accurately evaluate the performance stability of the chip during operation by acquiring and analyzing the power consumption fluctuation amplitude, the total value of the power consumption fluctuation offset and the average roughness of the ground plane to which the final inspection chip belongs, thereby reducing the error caused by the traditional testing method that relies only on a single indicator.

[0057] Specifically, the management feedback of the final inspection chip test is performed to finally complete the chip test management process. The specific analysis process is: the working interference index of the final inspection chip is compared with the working interference threshold. If the working interference index of the final inspection chip is greater than the working interference threshold, the chip test feedback system will manage the final inspection chip test and finally complete the chip test management process. The above-mentioned working interference threshold is formulated by the chip test engineer based on historical test conditions. If the working interference index of the final inspection chip is greater than the working interference threshold, it indicates that the final inspection chip may have a greater negative impact on adjacent chips during operation, and therefore management feedback is required for the final inspection chip. Specifically, it means: the chip test feedback system generates specific problem feedback, pointing out the reason why the working interference index of the final inspection chip exceeds the working interference threshold. The chip test engineer improves and perfects its process based on the reason. If the working interference index of the final inspection chip is less than or equal to the working interference threshold, it indicates that the final inspection chip has little negative impact on the adjacent chips during operation. Therefore, there is no need to provide management feedback for the final inspection chip. The above-mentioned test management process of the chip is finally completed, which refers to the quantitative analysis of the internal fluctuation index of the test chip, the packaging stability index of the pre-inspection chip and the working interference index of the final inspection chip, and the management feedback of the chip test, which is the chip test management process.

[0058] It needs to be explained that the above-mentioned chip test feedback system needs to know the chip test process data in real time, and analyze the chip performance in all aspects through the chip test feedback system.

[0059] Specifically, the working interference index of the final inspection chip is determined by the specific analysis process as follows: according to the working parameters of the final inspection chip, the power consumption fluctuation curve of the final inspection chip in the chip working sub-cycle is extracted. The above chip working sub-cycle represents the cycle of the working state of the detection chip, and its specific duration is determined by the chip test engineer according to the actual situation; the above power consumption fluctuation curve is as follows: Figure 2 As shown in the figure, it is generated by the matrix laboratory software according to the actual power consumption data of the chip test. The horizontal axis is the measurement time point in minutes, and the vertical axis is the power consumption in watts. This curve clearly shows the power consumption fluctuation trend of the final inspection chip during the working sub-cycle, which provides an important reference for in-depth understanding of the energy consumption characteristics of the final inspection chip and optimizing energy consumption management.

[0060] Each power consumption detection point is marked from the power consumption fluctuation curve of the final inspection chip in the chip working sub-cycle, and the slope of each power consumption detection point is obtained through data processing, and the mean operation and variance processing are performed in sequence to obtain the power consumption fluctuation amplitude of the final inspection chip in the chip working sub-cycle; the above-mentioned power consumption detection points refer to Figure 2On the horizontal axis measurement time point of the power consumption fluctuation curve, a number of measurement time points are randomly marked, which are the power consumption detection points; the slope of each power consumption detection point obtained by data processing refers to analyzing the power consumption fluctuation curve by matrix laboratory software, thereby generating a function f(t) corresponding to the power consumption fluctuation curve, which represents the relationship between the change of power consumption and the change of measurement time point. In a specific embodiment, it is assumed that the power consumption detection points are , , , as well as , then the slopes of each power consumption detection point are , , , as well as , then the slope of the power consumption detection point is , then the power consumption fluctuation range can be obtained by the following formula: , where c is the number of each power consumption detection point, .

[0061] Locate and obtain the standard power consumption fluctuation curve of the working position point of the final inspection chip within the chip working sub-cycle, perform a curve offset comparison with the power consumption fluctuation curve of the final inspection chip within the chip working sub-cycle, count the offset values ​​of the power consumption fluctuation curve of the final inspection chip within the chip working sub-cycle on the vertical axis, and accumulate to obtain the total value of the power consumption fluctuation offset of the final inspection chip within the chip working sub-cycle; the standard power consumption fluctuation curve of the working position point of the final inspection chip within the chip working sub-cycle is extracted from the chip design specifications; the above-mentioned curve offset comparison with the power consumption fluctuation curve of the final inspection chip within the chip working sub-cycle refers to performing difference processing on the vertical coordinate values ​​corresponding to each measurement time point on the power consumption fluctuation curve of the final inspection chip within the chip working sub-cycle and the vertical coordinate values ​​corresponding to each measurement time point on the standard power consumption fluctuation curve, and performing absolute value processing on the result of the difference processing to obtain the offset values ​​on the vertical axis of the power consumption fluctuation curve of the final inspection chip within the chip working sub-cycle.

[0062] A number of performance detection position points are randomly arranged on the ground plane to which the final inspection chip belongs, and the roughness value of each performance detection position point of the ground plane to which the final inspection chip belongs is obtained, and matched with the roughness corresponding to each roughness value interval in the chip management information library, thereby obtaining the roughness of each performance detection position point of the ground plane to which the final inspection chip belongs, and the average roughness of the ground plane to which the final inspection chip belongs is obtained by mean processing, and the working interference index of the final inspection chip is obtained by comprehensive judgment; the roughness value of each performance detection position point of the ground plane to which the final inspection chip belongs can be measured by a digital roughness measuring instrument; the roughness of each performance detection position point of the ground plane to which the final inspection chip belongs, the specific matching process is: each roughness value interval corresponds to the roughness, and the roughness value interval to which the roughness value of each performance detection position point of the ground plane to which the final inspection chip belongs is retrieved, and the roughness corresponding to the roughness value interval is the roughness of each performance detection position point of the ground plane to which the final inspection chip belongs.

[0063] Furthermore, the working interference index of the final inspection chip, in this embodiment, is obtained by comprehensively analyzing the power consumption fluctuation amplitude, the total value of the power consumption fluctuation offset and the average roughness of the ground plane of the final inspection chip in the chip working sub-cycle, and is used to evaluate the degree of interference of the final inspection chip to the adjacent chips. The specific expression is:

[0064] ;

[0065] in, It is the working interference index of the final inspection chip. If the power consumption fluctuation range of the final inspection chip is large, the performance of the final inspection chip is unstable, which leads to an increase in the total value of the power consumption fluctuation offset. At the same time, the working state of the final inspection chip is negatively affected, thereby accelerating the aging of the internal components of the final inspection chip and increasing the roughness of the ground plane of the final inspection chip. Therefore, it is necessary to comprehensively and quantitatively evaluate the influence of the power consumption fluctuation range, the total value of the power consumption fluctuation offset and the average roughness on the working interference index of the final inspection chip. Strengthening the test analysis of the final inspection chip is of great significance to improving the design process of the chip and improving the stability of the chip operation.

[0066] It is the fluctuation range of power consumption of the final inspection chip during the chip working sub-cycle. A high fluctuation range of power consumption may make it difficult for the power supply system of the final inspection chip to supply power stably, affecting the voltage stability of adjacent chips.

[0067] It is the total value of the power consumption fluctuation offset of the final inspection chip during the chip working sub-cycle. When the total value of the power consumption fluctuation offset is large, it may indicate that the energy efficiency of the final inspection chip is reduced, and adjacent chips may be affected by the same factors, resulting in a decrease in the overall energy efficiency of the working environment to which the chip belongs.

[0068] To finally inspect the average roughness of the ground plane to which the chip belongs. A rough ground plane may cause poor contact between chips, affecting signal transmission and power supply, thereby affecting the performance of adjacent chips.

[0069] Roughness limit value, which represents the maximum value of the average roughness of the ground plane to which the chip is evaluated, extracted from the chip design specifications.

[0070] It is the impact factor corresponding to the unit value of the power consumption fluctuation amplitude preset in the chip management information library, which represents the degree of influence of the unit value of the power consumption fluctuation amplitude on the working interference index of the final inspection chip. The fitting curve corresponding to the power consumption fluctuation amplitude is obtained by fitting the relationship between the historical chip workload, the historical chip operating frequency and the power consumption fluctuation amplitude, and the fitting curve corresponding to the power consumption fluctuation amplitude is introduced according to the real-time chip workload and the chip operating frequency, thereby obtaining the impact factor corresponding to the unit value of the power consumption fluctuation amplitude in this example. The value range of this value in this example is 0 to 1.

[0071] It is the impact factor corresponding to the unit value of the total power consumption fluctuation offset preset in the chip management information library, which represents the degree of influence of the unit value of the total power consumption fluctuation offset on the working interference index of the final inspection chip. The fitting curve corresponding to the total power consumption fluctuation offset is obtained by fitting the relationship between the historical chip power supply fluctuation amplitude, the historical chip temperature change amplitude and the total power consumption fluctuation offset. The real-time chip power supply fluctuation amplitude and the chip temperature change amplitude are brought into the fitting curve corresponding to the total power consumption fluctuation offset, thereby obtaining the impact factor corresponding to the unit value of the total power consumption fluctuation offset in this example. The value range of this value in this example is 0 to 1.

[0072] It is the correction factor corresponding to the average roughness preset in the chip management information library, which represents the numerical value of the correction degree of the average roughness change. The fitting curve corresponding to the average roughness is obtained by fitting the relationship between the historical chip usage time, the environmental humidity of the historical chip and the average roughness. The fitting curve corresponding to the average roughness is brought into the fitting curve according to the real-time chip usage time and the environmental humidity of the chip, thereby obtaining the correction factor corresponding to the average roughness in this example. The value range of this value in this example is 0 to 1.

[0073] In this exemplary embodiment, the variation table of the working interference index of the final inspection chip and its corresponding parameters is shown in Table 2:

[0074] Table 2 Changes of the working interference index of the final inspection chip and its corresponding parameters

[0075]

[0076] In this example embodiment, the value of the influence factor corresponding to the unit value of the power consumption fluctuation amplitude is 0.7, the value of the influence factor corresponding to the unit value of the total value of the power consumption fluctuation offset is 0.6, the value of the correction factor corresponding to the average roughness is 0.5, and the roughness limit value is set to 3.5. It can be seen from Table 2 that the power consumption fluctuation amplitude, the total value of the power consumption fluctuation offset and the average roughness are positively correlated, and the change trend of the other two parameters can be predicted more accurately by monitoring the change of one of the parameters.

[0077] In a specific embodiment, the present invention provides a quantitative chip test management method, device and storage medium, which monitors and records the internal key dynamic change parameters of the test chip to quantitatively evaluate the internal fluctuation index of the test chip, and marks the test chip with an internal fluctuation index less than the internal fluctuation threshold as a pre-inspection chip, thereby screening out chips with stable performance and performing subsequent packaging processing, which can reduce the demand for after-sales maintenance and replacement of chips to improve the reliability of chip use, obtain the packaging parameters of the pre-inspection chip packaging process, and analyze the packaging stability index of the pre-inspection chip to provide data basis for optimizing the chip packaging process, and finally obtain the working parameters of the final inspection chip to determine the working interference index of the final inspection chip, which helps to identify problems encountered by the chip during operation and provide direction for improving chip design, thereby managing feedback on the final inspection chip test to complete the multi-dimensional test management process of the chip.

[0078] The second aspect of the present invention provides a device for the quantitative chip test management method, characterized in that it includes: a chip, a processor, and a chip test feedback system; the chip is used to execute the test process; the processor is used to process the internal key dynamic change parameters of the test chip during the test execution cycle, the packaging parameters of the pre-inspection chip, and the working parameters of the final inspection chip, and transmit the determined working interference index of the final inspection chip to the chip test feedback system via the Internet; the chip test feedback system is used to receive the working interference index of the final inspection chip of the processor, and manage feedback on the final inspection chip test, and finally complete the chip test management process.

[0079] A third aspect of the present invention provides a computer-readable storage medium for storing a program, wherein the program, when executed by a processor, implements the quantitative chip test management method.

[0080] The above contents are merely examples and explanations of the structure of the present invention. The technicians in this technical field may make various modifications or additions to the specific embodiments described or replace them in a similar manner. As long as they do not deviate from the structure of the invention or exceed the scope defined by the present invention, they should all fall within the protection scope of the present invention.

Claims

1. A quantitative chip test management method, characterized in that: include: S1. Based on the test execution process of the test chip, monitor and record the internal key dynamic change parameters of the test chip during the test execution cycle, so as to quantitatively evaluate the internal fluctuation index of the test chip; S2. Compare the internal fluctuation index of the test chip with the internal fluctuation threshold. If the internal fluctuation index of the test chip is less than the internal fluctuation threshold, mark the test chip as a pre-qualified chip and perform packaging processing, obtain the packaging parameters of the pre-qualified chip, and analyze the packaging stability index of the pre-qualified chip; S3. The pre-inspected chip that has completed the packaging process is recorded as the final inspection chip, the working parameters of the final inspection chip are obtained, and the working interference index of the final inspection chip is determined, thereby managing and feedback is given to the final inspection chip test, and finally completing the chip test management process. The working interference index of the final inspection chip is obtained by comprehensively analyzing the power consumption fluctuation amplitude, the total value of the power consumption fluctuation offset, and the average roughness of the ground plane of the final inspection chip in the chip working sub-cycle, and is used to evaluate the degree of interference of the final inspection chip on the adjacent chips. The specific expression is: ； Among them, GX is the working interference index of the final inspection chip, m_avg is the power consumption fluctuation amplitude of the final inspection chip in the chip working sub-cycle, BC is the total value of the power consumption fluctuation offset of the final inspection chip in the chip working sub-cycle, ICH is the average roughness of the ground plane to which the final inspection chip belongs, ICH J is the roughness limit value, fg1 is the influencing factor corresponding to the unit value of the power consumption fluctuation amplitude preset in the chip management information library, fg2 is the influencing factor corresponding to the unit value of the total power consumption fluctuation offset preset in the chip management information library, and fg3 is the correction factor corresponding to the average roughness preset in the chip management information library.

2. A quantitative chip test management method according to claim 1, characterized in that: The internal key dynamically changing parameters of the test chip during the test execution cycle specifically include various delay durations of each memory access of the test chip during the test execution cycle.

3. A quantitative chip test management method according to claim 2, characterized in that: The internal fluctuation index of the quantitative evaluation test chip is specifically analyzed as follows: The various delay durations of each memory access of the test chip in the test execution cycle are accumulated to obtain the total delay duration of each memory access of the test chip in the test execution cycle, and the total duration of each memory access of the test chip in the test execution cycle is obtained, and the total delay duration of each memory access of the test chip in the test execution cycle is sequentially subjected to ratio analysis and mean processing to obtain the average memory delay factor of the test chip in the test execution cycle; The total delay duration of each memory access of the test chip within the memory execution end fluctuation time period is obtained, marked as the total delay duration of each fluctuation of the test chip within the memory execution end fluctuation time period, and comprehensively analyzed with the fluctuation stable reference delay duration, thereby obtaining the internal fluctuation index of the test chip.

4. A quantitative chip test management method according to claim 3, characterized in that: The internal fluctuation index of the test chip is compared with the internal fluctuation threshold, and the specific process is as follows: If the internal fluctuation index of the test chip is less than the internal fluctuation threshold, the test chip is marked as a pre-qualified chip and packaged. If the internal fluctuation index of the test chip is greater than or equal to the internal fluctuation threshold, the internal fluctuation status of the test chip is fed back.

5. A quantitative chip test management method according to claim 1, characterized in that: The specific analysis process of analyzing the packaging stability index of the pre-qualified chip is as follows: According to the packaging parameters of the pre-qualified chip, the weight of the pre-qualified chip at the end time of the packaging inspection cycle and the weight of the pre-qualified chip at the start time of the packaging inspection cycle are extracted, and the difference processing is performed to obtain the packaging additional weight of the pre-qualified chip during the packaging inspection cycle; According to the packaging parameters of the pre-qualified chip, a chip scan image of the pre-qualified chip at the end time of the packaging inspection cycle is extracted to locate the center position point of each solder ball in the pre-qualified chip, and a one-to-one correspondence is made with the preset center position point of each solder ball in the pre-qualified chip, thereby obtaining the offset distance of each solder ball of the pre-qualified chip through distance measurement, and the total offset distance of the solder ball of the pre-qualified chip is obtained by accumulation processing; The contour shape diagram of each heat dissipation hole in the pre-qualified chip is extracted from the chip scanning image at the end time of the packaging inspection cycle of the pre-qualified chip, and the area analysis and mean processing are performed in sequence to obtain the average area of ​​the heat dissipation holes of the pre-qualified chip. Based on this comprehensive analysis, the packaging stability index of the pre-qualified chip is obtained.

6. A quantitative chip test management method according to claim 1, characterized in that: The specific analysis process of determining the working interference index of the final inspection chip is as follows: According to the working parameters of the final inspection chip, the power consumption fluctuation curve of the final inspection chip in the chip working sub-cycle is extracted, and each power consumption detection point is marked from the power consumption fluctuation curve of the final inspection chip in the chip working sub-cycle. The slope of each power consumption detection point is obtained through data processing, and mean operation and variance processing are performed in sequence to obtain the power consumption fluctuation amplitude of the final inspection chip in the chip working sub-cycle; Locate and obtain the standard power consumption fluctuation curve of the working position point of the final inspection chip within the chip working sub-cycle, compare the curve offset with the power consumption fluctuation curve of the final inspection chip within the chip working sub-cycle, count the offset values ​​of the power consumption fluctuation curve of the final inspection chip within the chip working sub-cycle on the vertical axis, and accumulate to obtain the total value of the power consumption fluctuation offset of the final inspection chip within the chip working sub-cycle; A number of performance detection position points are randomly arranged on the ground plane where the final inspection chip belongs, and the roughness value of each performance detection position point on the ground plane where the final inspection chip belongs is obtained. The roughness is matched with the roughness corresponding to each roughness value interval in the chip management information library, thereby obtaining the roughness of each performance detection position point on the ground plane where the final inspection chip belongs. The average roughness of the ground plane where the final inspection chip belongs is obtained by mean processing, and the working interference index of the final inspection chip is obtained by comprehensive judgment.

7. A quantitative chip test management method according to claim 1, characterized in that: The management feedback of the final inspection chip test is finally completed, and the chip test management process is completed. The specific analysis process is as follows: The working interference index of the final inspection chip is compared with the working interference threshold. If the working interference index of the final inspection chip is greater than the working interference threshold, the chip test feedback system will manage feedback on the final inspection chip test and finally complete the chip test management process.

8. A device using a quantitative chip test management method as claimed in any one of claims 1 to 7, characterized in that: include: Chips, processors, chip test feedback system; The chip is used to perform a test process; The processor is used to process the internal key dynamic change parameters of the test chip during the test execution cycle, the packaging parameters of the pre-test chip, and the working parameters of the final test chip, and transmit the determined working interference index of the final test chip to the chip test feedback system via the Internet; The chip test feedback system is used to receive the working interference index of the final inspection chip of the processor, and to manage feedback on the final inspection chip test, and finally complete the chip test management process.

9. A computer-readable storage medium for storing a program, wherein when the program is executed by a processor, the program implements a quantitative chip test management method as claimed in any one of claims 1 to 7.

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