Low dropout regulator

Abstract

The invention discloses a low dropout linear regulator, which comprises a first power tube connected between a power supply end and a feedback node; the second power tube is connected between the power supply end and an output node, and the output node is used for providing output voltage for an external load; the error amplifier is connected with the feedback node to receive the feedback voltage and is used for driving the first power tube and the second power tube according to a comparison result of the feedback voltage and the reference voltage; and the feedback clamping circuit is connected with the feedback node and the output node and is used for clamping the feedback voltage to be equal to the output voltage. In the low-voltage linear voltage regulator, the first power tube can work in a low-current and small-bandwidth state to save static power consumption and reduce the complexity of a compensation circuit, so that the stability of a loop is improved, meanwhile, the quiescent current of the circuit is reduced, and the efficiency of the circuit is improved.

Description

Technical Field

[0001] The invention relates to the technical field of power supply, and in particular to a low voltage difference linear regulator. Background Art

[0002] Low Dropout Regulator (LDO) is widely used in power management IC (PMIC) of portable electronic devices such as smartphones, tablets and wearable devices. With the development of technology, these electronic devices have higher and higher requirements for power management ICs, requiring both high efficiency to extend battery life and low quiescent current to reduce standby power consumption. In addition, the complexity and versatility of portable electronic devices also require LDO to have good compensation effect to ensure its stability under various load conditions.

[0003] Figure 1 FIG. 2 shows a schematic circuit diagram of a conventional low voltage dropout linear regulator. Figure 1 As shown, the low-dropout linear regulator 100 includes a power tube Q1, an error amplifier EA, and a compensation circuit 110. Among them, the power tube Q1 is the main output tube of the chip, connected to the current conduction path between the input voltage Vin and the output voltage Vout. The inverting input terminal of the error amplifier EA is used to receive a reference voltage VREF, the non-inverting input terminal of the error amplifier EA is connected to the output voltage Vout, and the output terminal of the error amplifier EA is connected to the control terminal of the power tube Q1. The error amplifier EA is mainly used to obtain the difference between the output voltage Vout and the reference voltage VREF, and control the conduction state of the power tube Q1 according to the difference feedback, so as to realize the negative feedback closed-loop regulation of the output voltage. The compensation circuit 110 is connected between the input voltage Vin and the output terminal of the error amplifier EA, and is used to adjust the frequency response of the system, increase the phase margin, and thus improve the loop stability of the system.

[0004] See also Figure 1, the on-chip main pole wp of the existing low-dropout linear regulator 100 is 1 / (R1*Cc), the on-chip dynamic zero wz is 1 / (Rc*Cc), and the output pole wo is 1 / (Ro*Co), where R1 is the output impedance of the error amplifier EA, Rc is the resistance value of the dynamic compensation resistor in the compensation circuit 110, Cc is the capacitance value of the compensation capacitor in the compensation circuit 110, Ro is the output current impedance, and Co is the capacitance value of the output capacitor. In traditional designs, the general compensation idea is to let the on-chip dynamic zero wz of the LDO compensate the output node wo. The closer the two are, the more stable the system is. However, when the range of the output capacitance Co is wide (for example, 1 to 10 μF) or the load current range is large (0 to 300 mA), the range of variation of the output pole wo becomes very large. At this time, in order to achieve a better compensation effect, the compensation circuit 110 often needs to be designed to be more complex and consumes a large static power consumption.

[0005] Therefore, traditional LDO designs have certain limitations in reducing quiescent current and improving loop stability. Improving loop stability will lead to excessively high quiescent current, which in turn increases standby power consumption and shortens battery life. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a low voltage drop linear regulator, which can improve loop stability while reducing the quiescent current of the circuit, thereby helping to improve circuit efficiency.

[0007] According to one aspect of the present invention, there is provided a low voltage difference linear regulator, comprising: a first power tube connected between a power supply terminal and a feedback node; a second power tube connected between the power supply terminal and an output node, the output node being used to provide an output voltage to an external load; an error amplifier connected to the feedback node to receive a feedback voltage, and being used to drive the first power tube and the second power tube according to a comparison result between the feedback voltage and a reference voltage; and a feedback clamping circuit connected to the feedback node and the output node, and being used to clamp the feedback voltage and the output voltage to be equal.

[0008] Optionally, a width-to-length ratio of the second power tube is greater than a width-to-length ratio of the first power tube.

[0009] Optionally, it further includes: a buffer, the output of the error amplifier is connected to the input end of the buffer and the control end of the first power tube, and the output end of the buffer is connected to the control end of the second power tube.

[0010] Optionally, the feedback clamp circuit includes: a first transistor, a first end of the first transistor is connected to the feedback node; a second transistor, a first end of the second transistor is connected to the output node, and a control end of the first transistor is connected to the control end and the second end of the second transistor; a third transistor, a first end and a control end of the third transistor are connected to the second end of the first transistor, and a second end of the third transistor is connected to ground; and a fourth transistor, a first end of the fourth transistor is connected to the second end of the second transistor, a control end of the fourth transistor is connected to the control end of the third transistor, and a second end of the fourth transistor is connected to ground.

[0011] Optionally, it also includes: a bias current source connected between the first end of the third transistor and ground.

[0012] Optionally, the method further includes: a first compensation capacitor connected between the first end of the third transistor and ground.

[0013] Optionally, it also includes: a compensation circuit connected between the power supply terminal and the output terminal of the error amplifier, wherein the compensation circuit is used to provide zero-point compensation.

[0014] Optionally, the compensation circuit includes a second compensation capacitor and a compensation resistor connected in series between the power supply terminal and the output terminal of the error amplifier.

[0015] Optionally, the compensation resistor is a dynamic resistor.

[0016] Optionally, the first transistor and the second transistor are both PMOS transistors, and the third transistor and the fourth transistor are both NMOS transistors.

[0017] In summary, an embodiment of the present invention provides an LDO with a master-slave architecture, which uses a second power tube to drive an external large current and large capacitance, and uses a first power tube to perform feedback loop control of the circuit. Therefore, the first power tube can operate in a low current and small bandwidth state to save static power consumption and reduce the complexity of the compensation circuit, thereby improving the loop stability while reducing the static current of the circuit, which helps to improve the circuit efficiency.

[0018] In addition, the LDO of the embodiment of the present invention also adopts a feedback clamping circuit to make the bias states of the first power tube and the second power tube completely consistent, ensuring the consistent working conditions of the two power tubes, so that their current driving capabilities and voltage characteristics are more matched, ensuring the accuracy of the output voltage, and helping to improve the performance and stability of the entire LDO.

[0019] In addition, the master-slave architecture LDO of the embodiment of the present invention can also improve the transient response capability of the circuit. When the load current changes suddenly, the first power tube and the second power tube respond simultaneously to stabilize the output voltage more quickly and reduce the sudden change and noise of the output voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0021] Figure 1 A schematic circuit diagram of a conventional low dropout linear regulator is shown.

[0022] Figure 2 FIG. 4 shows a schematic circuit diagram of a low voltage dropout linear regulator according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings.Where possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0024] In the specification, it should be noted that similar reference numerals that have been used to represent similar parts in other drawings are used for these elements as much as possible. In the following description, when functions and configurations known to those skilled in the art are not related to the basic configuration of the present disclosure, their detailed description will be omitted. The terms described in the specification should be understood as follows.

[0025] The advantages and features of the present disclosure and their implementation methods will be described through the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments described herein. Rather, these embodiments are provided to make the present disclosure comprehensive and complete, so as to fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0026] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings used to describe the embodiments of the present disclosure are merely examples, and the present disclosure is therefore not limited to the illustrated details. Similar reference numerals always represent similar elements. In the following description, when it is determined that a detailed description of a related known function or construction will inevitably obscure the focus of the present disclosure, the detailed description will be omitted.

[0027] As those skilled in the art can fully understand, the features of the various embodiments of the present disclosure can be partially or completely combined or combined with each other, and can interoperate and technically drive each other in various ways. The embodiments of the present disclosure can be performed independently of each other, or can be performed together in a mutually dependent relationship.

[0028] In the present application, a MOS tube (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first end, a second end and a control end. When the MOS tube is in the on state, current flows from the first end to the second end. The first end, the second end and the control end of a PMOS tube are the source, the drain and the gate, respectively, and the first end, the second end and the control end of an NMOS tube are the drain, the source and the gate, respectively.

[0029] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] Figure 2 Schematic circuit diagram of a low voltage drop linear regulator according to an embodiment of the present invention is shown. Figure 2 The low voltage dropout linear regulator 200 of the present invention includes a first power tube Q1, a second power tube Q2, an error amplifier EA, a buffer BUF, an output capacitor Co, a compensation circuit 210 and a feedback clamping circuit 220.

[0031] Among them, the first end of the first power tube Q1 is connected to the power supply terminal Vin, the second end of the first power tube Q1 is connected to the feedback node A1, and the control end of the first power tube Q1 is connected to the output end of the error amplifier EA. The first end of the second power tube Q2 is connected to the power supply terminal Vin, the second end of the second power tube Q2 is connected to the output node A2, the output node A2 is used to provide an output voltage Vout and an output current Io to an external load, and the control end of the second power tube Q2 is connected to the output end of the buffer BUF. The output capacitor Co is connected between the output parasitic inductance Lo and the ground, and is used to shape and filter the output voltage Vout.

[0032] In an exemplary embodiment, the first power tube Q1 and the second power tube Q2 are PMOS tubes. Of course, the present invention is not limited to this. In other embodiments, the first power tube Q1 and the second power tube Q2 may also be other types of transistors, such as NMOS transistors, NPN Darlington transistors, and NPN bipolar transistors.

[0033] The error amplifier EA has a non-inverting input terminal, an inverting input terminal and an output terminal. The inverting input terminal of the error amplifier EA is used to receive a reference voltage VREF. The non-inverting input terminal of the error amplifier EA is connected to a feedback node A1 to receive a feedback voltage VFB. The output terminal of the error amplifier EA is connected to the control terminal of the first power tube Q1 and the input terminal of the buffer BUF.

[0034] The compensation circuit 210 is connected between the power supply terminal Vin and the output terminal of the error amplifier EA. The compensation circuit 210 is used to obtain an on-chip dynamic zero point inside the circuit to compensate the frequency of the system. No matter how the output current Io changes, the unit gain bandwidth clock of the system is within the set interval, so that a higher phase margin can be obtained, achieving higher stability in a wide range of full loads.

[0035] Furthermore, the compensation circuit 210 includes a compensation capacitor Cc and a compensation resistor Rc connected in series between the power supply terminal Vin and the output terminal of the error amplifier EA. For example, the compensation resistor Rc is a dynamic resistor, and a dynamic zero point can be obtained inside the circuit by adjusting the resistance value of the compensation resistor Rc.

[0036] The feedback clamping circuit 220 is connected to the feedback node A1 and the output node A2, and is used to make the feedback voltage VFB equal to the output voltage Vout by clamping, thereby making the drain voltage of the first power tube Q1 and the drain voltage of the second power tube Q2 be clamped equal, ensuring that the bias state of the second power tube Q2 can completely follow the first power tube Q1, ensuring that the working conditions of the two power tubes are consistent, so that their current driving capabilities and voltage characteristics are more matched, which helps to improve the performance and stability of the entire LDO.

[0037] Further, the feedback clamp circuit 220 of the present embodiment includes a transistor MP1, a transistor MP2, a transistor MN1, and a transistor MN2. Among them, the transistors MP1 and MP2 are PMOS transistors, and the transistors MN1 and MN2 are NMOS transistors. The first end of the transistor MP1 is connected to the feedback node A1, the control end of the transistor MP1 is connected to the control end and the second end of the transistor MP2, and the first end of the transistor MP2 is connected to the output node A2. The control end and the first end of the transistor MN1 are connected to the second end of the transistor MP1, the first end of the transistor MN2 is connected to the second end of the transistor MP2, the control end of the transistor MN2 is connected to the first end and the control end of the transistor MN1, and the second ends of the transistors MN1 and MN2 are connected to the ground. In the present embodiment, the transistors MP1, the transistors MP2, the transistors MN1, and the transistors MN2 constitute a feedback sampling current mirror, through which the voltage of the feedback node A1 and the voltage of the output node A2 are clamped to be equal.

[0038] Furthermore, the low voltage drop linear regulator 200 also includes a bias current source Ibias and a compensation capacitor Cm. The bias current source Ibias is connected between the first end of the transistor MN1 and the ground, and is used to provide a bias current for the first power tube Q1. The compensation capacitor Cm is connected between the first end of the transistor MN1 and the ground, and is used to provide a load capacitance for the first power tube Q1.

[0039] In this embodiment, the error amplifier EA and the first power tube Q1 constitute a feedback control loop of the low voltage drop linear regulator 200. Since the output voltage Vout and the feedback voltage VFB are clamped to be equal by the feedback clamp circuit 220, the voltage value of the output voltage Vout can be controlled by the feedback control loop. For example, the feedback control loop mainly compares the feedback voltage VFB with the reference voltage VREF through the error amplifier EA, and then controls the gate voltage of the first power tube Q1 and the second power tube Q2 according to the difference between the two. Among them, the first power tube Q1 is directly driven by the output of the error amplifier EA, and the second power tube Q2 is driven by the signal amplified by the output of the error amplifier EA through the buffer BUF. For example, when the load changes and causes the output voltage Vout to drop, the feedback voltage VFB is also pulled down accordingly, and then the difference between the feedback voltage VFB and the reference voltage VREF is reduced, so the output of the error amplifier EA will also decrease, thereby increasing the gate-source voltage difference between the first power tube Q1 and the second power tube Q2, so that the output current Io increases, and then the output voltage Vout rises to a normal voltage level.

[0040] It should be noted that Figure 2 The control loop of the low voltage dropout linear regulator 200 is an exemplary circuit diagram. In other embodiments, a series voltage divider resistor may be added to the feedback node A1 to divide the voltage. Of course, other functional modules may also be added to the low voltage dropout linear regulator 200, and this embodiment does not limit this.

[0041] Further, the width-to-length ratio of the second power tube Q2 is greater than that of the first power tube Q1, so the second power tube Q2 can be used to drive external large current and large capacitance, while the feedback control loop of the first power tube Q1 can operate at low current and small bandwidth. For example, the area ratio of the second power tube Q2 to the first power tube Q1 is N:1. When the circuit is working, the load current of the first power tube Q1 is Ibias+Io / N, where Io is the output current of the second power tube Q2. Therefore, compared with the second power tube Q2, the load current of the first power tube Q1 is reduced by N times, so the first power tube Q1 can operate in a low current state, and because the load capacitance of the first power tube Q1 is fixed (that is, provided by the internal compensation capacitor Cm), the loop stability of the first power tube Q1 can be guaranteed by using a relatively simple compensation method. Therefore, the LDO of the present invention can save static power consumption and reduce the complexity of the compensation circuit, so that the static current of the circuit can be reduced while improving the loop stability, which helps to improve the circuit efficiency.

[0042] In summary, an embodiment of the present invention provides an LDO with a master-slave architecture, which uses a second power tube to drive an external large current and large capacitance, and uses a first power tube to perform feedback loop control of the circuit. Therefore, the first power tube can operate in a low current and small bandwidth state to save static power consumption and reduce the complexity of the compensation circuit, thereby improving the loop stability while reducing the static current of the circuit, which helps to improve the circuit efficiency.

[0043] In addition, the LDO of the embodiment of the present invention also adopts a feedback clamping circuit to make the bias states of the first power tube and the second power tube completely consistent, ensuring the consistent working conditions of the two power tubes, so that their current driving capabilities and voltage characteristics are more matched, ensuring the accuracy of the output voltage, and helping to improve the performance and stability of the entire LDO.

[0044] In addition, the master-slave architecture LDO of the embodiment of the present invention can also improve the transient response capability of the circuit. When the load current changes suddenly, the first power tube and the second power tube respond simultaneously to stabilize the output voltage more quickly and reduce the sudden change and noise of the output voltage.

[0045] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0046] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present invention.

Claims

1. A low dropout linear regulator, comprising: A first power tube is connected between the power supply terminal and the feedback node; A second power tube, connected between the power supply terminal and an output node, wherein the output node is used to provide an output voltage to an external load; an error amplifier connected to the feedback node to receive a feedback voltage, and used to drive the first power tube and the second power tube according to a comparison result between the feedback voltage and a reference voltage; as well as A feedback clamping circuit is connected to the feedback node and the output node, and is used to clamp the feedback voltage and the output voltage to be equal.

2. The low dropout linear regulator according to claim 1, wherein: The width-to-length ratio of the second power tube is greater than the width-to-length ratio of the first power tube.

3. The low voltage dropout linear regulator according to claim 2, wherein: Also includes: A buffer, the output of the error amplifier is connected to the input end of the buffer and the control end of the first power tube, and the output end of the buffer is connected to the control end of the second power tube.

4. The low dropout linear regulator according to claim 1, wherein: The feedback clamping circuit comprises: a first transistor, a first terminal of the first transistor being connected to the feedback node; a second transistor, a first terminal of the second transistor being connected to the output node, and a control terminal of the first transistor being connected to a control terminal and a second terminal of the second transistor; a third transistor, a first terminal and a control terminal of the third transistor being connected to the second terminal of the first transistor, and a second terminal of the third transistor being connected to ground; and A fourth transistor, wherein a first end of the fourth transistor is connected to the second end of the second transistor, a control end of the fourth transistor is connected to the control end of the third transistor, and a second end of the fourth transistor is connected to ground.

5. The low dropout linear regulator according to claim 4, wherein: Also includes: A bias current source is connected between the first terminal of the third transistor and ground.

6. The low dropout linear regulator according to claim 5, wherein: Also includes: A first compensation capacitor is connected between the first end of the third transistor and ground.

7. The low dropout linear regulator according to claim 1, wherein: Also includes: A compensation circuit is connected between the power supply terminal and the output terminal of the error amplifier, and the compensation circuit is used to provide zero point compensation.

8. The low dropout linear regulator according to claim 7, wherein: The compensation circuit includes a second compensation capacitor and a compensation resistor connected in series between the power supply terminal and the output terminal of the error amplifier.

9. The low dropout linear regulator according to claim 8, wherein: The compensation resistor is a dynamic resistor.

10. The low dropout linear regulator according to claim 4, wherein: The first transistor and the second transistor are both PMOS transistors, and the third transistor and the fourth transistor are both NMOS transistors.

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