Server case system and computer equipment

Abstract

The invention relates to a server case system and computer equipment. The system comprises a server mainboard, a backboard and a signal relay device, wherein a controller is arranged on the server mainboard; the first ends of the plurality of back plates are connected with the controller through the connecting device; the first ends of the plurality of signal relay devices are connected with the second ends of the plurality of backboards through the connecting devices; the connecting device comprises a first cable and a second cable, the first end of the first cable is connected with the second end of the controller, the second end of the first cable is connected with the first ends of the multiple backboards, the first end of the second cable is connected with the second ends of the multiple backboards, and the second end of the second cable is connected with the first ends of the multiple signal relay devices; wherein the first cable is a low-speed / high-speed cable, and the second cable is a high-speed cable. By the adoption of the system, interaction of the controller, the backboard and the signal relay equipment can be met, meanwhile, the number of cables is reduced, and the occupied space of a server case is small.

Description

Technical Field

[0001] The present application relates to the technical field of servers, and in particular to a server chassis system and computer equipment. Background Art

[0002] With the rapid development of science and technology, big data has penetrated into every industry and business function today. With the rapid increase in the amount of information, more and more data needs to be processed, and the demand for servers is also increasing. As a type of computer, the server provides computing, storage, data exchange and other services to Internet users, and is an important component node in the Internet era. Servers not only have high computing speeds, long running times, and large data throughput, but also increasingly complex design solutions to meet the diverse needs of customers. However, with the complexity of server design solutions, the interfaces, cables and other components in the server are overly complex, which can easily lead to a decrease in the server's signal transmission performance and heat dissipation performance. Summary of the invention

[0003] Based on this, it is necessary to provide a server chassis system and computer equipment that can occupy less server space in order to solve the above technical problems.

[0004] In order to solve the above technical problems, in a first aspect, a server chassis system is provided, the system comprising:

[0005] A server mainboard, on which a controller is arranged;

[0006] Backplane, there are multiple backplanes, and the first ends of the multiple backplanes are connected to the controller through a connecting device;

[0007] A signal relay device, wherein there are multiple signal relay devices, and the first ends of the multiple signal relay devices are connected to the second ends of the multiple backplanes through a connecting device;

[0008] The connecting device includes a first cable and a second cable, wherein a first end of the first cable is connected to a second end of the controller, a second end of the first cable is connected to first ends of a plurality of backplanes, a first end of the second cable is connected to second ends of the plurality of backplanes, and a second end of the second cable is connected to first ends of a plurality of signal relay devices;

[0009] The first cable is a low-speed / high-speed cable, and the second cable is a high-speed cable.

[0010] In one of the embodiments, the system further includes a hard disk device, which is disposed on a backplane and is connected to the signal relay device and the backplane respectively through preset high-speed and low-speed cables.

[0011] In one embodiment, the preset high-speed and low-speed cables include a plurality of sub-high-speed cables and a plurality of sub-low-speed cables, and the hard disk device is connected to the signal relay device and the backplane through the preset high-speed and low-speed cables respectively, including:

[0012] The first end of the hard disk device is connected to the second end of the backplane through multiple sub-low-speed cables, the second end of the hard disk device is connected to the first end of the signal relay device through multiple sub-high-speed cables, and the second end of the backplane is connected to the first end of the signal relay device through multiple sub-low-speed cables.

[0013] In one embodiment, the controller includes at least a first interface and a second interface, the first interface is connected to a target device disposed on a server mainboard; the second interface is connected to a target device disposed on a backplane and a signal relay device.

[0014] In one embodiment, the target device includes a first target device, a second target device and a third target device, the first target device is arranged on a server mainboard, the second target device is arranged on a backplane, the third target device is arranged on a signal relay device, and the second interface is connected with the target devices arranged on the backplane and the signal relay device, including:

[0015] The second interface is connected to the first end of the second target device, and the second end of the second target device is connected to the first end of the third target device.

[0016] In one of the embodiments, a third interface is provided at the first end of the backplane, and a fourth interface is provided at the first end of the signal relay device;

[0017] The second interface is connected to the third interface via a target cable;

[0018] The third interface is connected to the first end of the second target device through the target cable, and the second end of the second target device is connected to the fourth interface through the target cable;

[0019] The fourth interface is connected to the first end of the third target device through the target cable;

[0020] Wherein, the backplane further includes a first control module, and the signal relay device number includes a second control module;

[0021] A first end of the first control module is connected to the third interface, and a second end of the first control module is connected to a first end of the second target device;

[0022] The first end of the second control module is connected to the fourth interface, and the second end of the second control module is connected to the first end of the third target device.

[0023] In one embodiment, the first control module includes a first signal control module and a first switch control module, and the second control module includes a second signal control module and a second switch control module;

[0024] The first signal control module and the second signal control module are used to control the on and off of the digital signals of the second target device and the third target device respectively;

[0025] The first switch control module and the second switch control module are used to control the on and off of the clock signals of the second target device and the third target device respectively.

[0026] In one embodiment, a first crystal oscillator, a first pin, and a first trigger are disposed at a first end of the backplane, and a second crystal oscillator, a second pin, and a second trigger are disposed at a second end of the backplane:

[0027] The output end of the first crystal oscillator is connected to the input end of the first trigger, and the output end of the first trigger is connected to the first pin;

[0028] The output end of the second crystal oscillator is connected to the input end of the second trigger, and the output end of the second trigger is connected to the second pin.

[0029] In one embodiment, the first crystal oscillator is used to generate a first baseband signal, the first crystal oscillator transmits the first baseband signal to a first trigger, the first trigger is used to generate a first frequency-divided signal according to the first baseband signal, the first trigger transmits the first frequency-divided signal to a first pin, and the first pin is connected to a first cable;

[0030] The first frequency-divided signal is transmitted to the controller through the first cable, and the controller is used to determine the connection state of the first cable between the controller and the backplane according to the first frequency-divided signal;

[0031] The second crystal oscillator is used to generate a second base frequency signal, the second crystal oscillator transmits the second base frequency signal to a second trigger, the second trigger is used to generate a second frequency-divided signal according to the second base frequency signal, the second trigger transmits the second frequency-divided signal to a second pin, and the second pin is connected to the second cable;

[0032] The second frequency-divided signal is transmitted to the control chip on the signal relay device through the second cable, and the control chip is used to determine the connection state of the second cable between the signal relay device and the backplane according to the second frequency-divided signal.

[0033] In order to solve the above technical problem, in a second aspect, a server chassis device is provided, and the server chassis device includes any one of the above server chassis systems.

[0034] Different from the prior art, the present application sets up a server chassis system including: a server mainboard, a backplane and a signal relay device, wherein a controller is set on the server mainboard; the first ends of multiple backplanes are connected to the controller through a connecting device; the first ends of multiple signal relay devices are connected to the second ends of multiple backplanes through a connecting device; the connecting device includes a first cable and a second cable, wherein the first end of the first cable is connected to the second end of the controller, the second end of the first cable is connected to the first end of multiple backplanes, the first end of the second cable is connected to the second end of multiple backplanes, and the second end of the second cable is connected to the first end of multiple signal relay devices; wherein the first cable is a low-speed / high-speed cable, and the second cable is a high-speed cable. The use of this system can reduce the number of interfaces and occupy less server space while satisfying the interaction between the controller, the backplane and the signal relay device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a structural block diagram of a server chassis system in the prior art;

[0036] Figure 2 It is a schematic diagram of the structure of a backplane and a signal relay device in the prior art;

[0037] Figure 3 A schematic diagram of the structure of a server chassis system in one embodiment;

[0038] Figure 4 A schematic diagram of the structure of a server chassis system in yet another embodiment;

[0039] Figure 5 A schematic diagram of the structure of a server chassis system in yet another embodiment;

[0040] Figure 6 It is a structural schematic diagram of a backplane and a signal relay device in yet another embodiment;

[0041] Figure 7 A schematic diagram of the structure of a server chassis system in yet another embodiment;

[0042] Figure 8 The figure is a diagram of the internal structure of a server chassis device in one embodiment. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0044] See also Figure 1In the prior art, for the design of multiple boards (backplane and Retimer card shown in the figure) in a chassis, since the BMC (baseboard management controller) needs to manage each board uniformly through I2C (bidirectional serial bus), for the separated boards, the BMC (baseboard management controller) and other boards (backplane and Retimer card shown in the figure) are generally connected through a low-speed cable (I2C), and each board is allocated a low-speed cable to monitor, read and write operations on this board. In this way, the BMC (baseboard management controller) must reserve an I2C for each board to be managed to do corresponding management work. When there are many boards, a corresponding number of I2C interfaces are required, resulting in a waste of BMC interfaces. In addition, since the BMC connects each board through cables, when the number of boards is large, it will cause a lot of cables. One is that it occupies the space in the server chassis, which will cause the chassis space to be messy and affect the diversion of the heat dissipation wind. The many cables make it difficult to manage the cables, and the cables are easily damaged, causing quality problems of the whole machine.

[0045] See also Figure 2 In the prior art, for the topology design of high-speed signals, taking PCIE signals as an example, a Retimer card (signal relay device) is used when the line is too long. The Retimer card (signal relay device) is then connected to the backplane through a cable, and then the PCIE disk is inserted into the backplane. In this way, the high-speed signal of the Retimer card passes through the interface to the high-speed cable, then through the cable to the backplane interface, and then from the backplane to the interface of the PCIE disk. After passing through multiple interfaces and the wiring on the backplane, it will cause great loss, which is very unfriendly to high-speed signals.

[0046] In order to solve the above technical problems, the present application provides a server chassis system, which includes: a server mainboard, a backplane and a signal relay device, wherein a controller is arranged on the server mainboard; there are multiple backplanes, and the first ends of the multiple backplanes are connected to the controller through a connecting device; there are multiple signal relay devices, and the first ends of the multiple signal relay devices are connected to the second ends of the multiple backplanes through a connecting device. The use of this system can reduce the number of interfaces and occupy less server space while satisfying the interaction between the controller, the backplane and the signal relay device.

[0047] Embodiment 1

[0048] In the embodiments disclosed in this application, there are Figure 3 The server chassis system shown includes a server mainboard (management board), a backplane, a signal relay device, and a connecting device.

[0049] The server motherboard is used to carry various devices installed on the server motherboard, including a controller, which may specifically be a baseboard management controller (BMC), a processor, a heat sink, and other devices.

[0050] Multiple backplanes are used to provide interfaces corresponding to expansion slots on the server mainboard and to install various expansion cards to increase the functions and performance of the server. The figure shows that the multiple backplanes include backplane 1, backplane 2, and backplane n.

[0051] Multiple signal relay devices, optionally, the signal relay device can be a Retimer card, which is a signal conditioning chip, and its function is to balance and enhance the signal. It is similar to a PHY chip. When the signal passes through the Retimer card, the signal is reconstructed by the clock inside the Retimer card, which can increase the signal transmission energy, and then continue to transmit, which can improve the reliability of the server chassis system. The figure shows that multiple relay devices include Retimer card 1, Retimer card 2, and Retimer card n.

[0052] In order to achieve the coupling of the components in the embodiment, the present application is also provided with a connecting device. In this embodiment, the connecting device includes a first cable 11 and a second cable 12. The first end of the first cable 11 is connected to the second end of the controller, that is, the output end of the controller, the second end of the first cable 11 is connected to the first ends of multiple backplanes, the first end of the second cable 12 is connected to the second ends of the multiple backplanes, and the second end of the second cable 12 is connected to the first ends of multiple signal relay devices.

[0053] In this embodiment, the connection device includes a first cable 11 and a second cable 12. In this embodiment, the second cable is a high-speed cable and the first cable is a low-speed cable. As shown in the figure, the second cable 12 includes a plurality of high-speed cables and the first cable 11 includes a plurality of low-speed cables. Among them, the second cable 12 can be a high-speed cable connecting the original backplane and the signal relay device, and the first cable 11 can be an I2C serial communication bus.

[0054] In this embodiment, the connection between the backplane set on the server mainboard and the signal relay device is achieved by borrowing the high-speed cable connecting the original backplane and the signal relay device, and the connection between the controller set on the server mainboard and multiple backplanes is achieved by using low-speed cables. There is no need to additionally set up connecting cables for the connection between the backplane and the signal relay device, and using low-speed cables to achieve the connection between the controller set on the server mainboard and multiple backplanes can also reduce costs.

[0055] Furthermore, in the embodiment, a backplane and a signal relay device are connected in series through an interface, thereby reducing the number of interface arrangements in the server and further releasing available space in the server.

[0056] In this implementation, when the first cable 11 and the second cable 12 can both be high-speed cables, the first cable 11 and the second cable 12 can both be high-speed cables connecting the original backplane and the signal relay device. In this embodiment, by using the high-speed cable connecting the original backplane and the signal relay device to realize the connection between the controller and the backplane and the signal relay device set on the server motherboard, the space occupied by the cables in the server can be reduced, thereby improving the performance of the server.

[0057] And compare Figure 1 In the present application, a plurality of interfaces are arranged on a controller provided on a server mainboard, and are connected to a plurality of backplanes and signal relay devices one by one, that is, one interface corresponds to one backplane or one interface corresponds to one signal relay device. In the present application, a backplane and a signal relay device are connected in series through one interface, thereby reducing the number of interface arrangements in the server and further releasing the available space of the server.

[0058] Embodiment 2

[0059] In the embodiments disclosed in this application, there are Figure 4 The server chassis system shown includes a server mainboard (management board), a backplane, a signal relay device, a connection device, a hard disk device, and preset high-speed and low-speed cables.

[0060] The server motherboard is used to carry various devices installed on the server motherboard, including a controller, which may specifically be a baseboard management controller (BMC), a processor, a heat sink, and other devices.

[0061] Multiple backplanes, which are used to provide interfaces corresponding to the expansion slots on the server motherboard and are used to install various expansion cards to increase the functions and performance of the server.

[0062] Multiple signal relay devices, optionally, the signal relay device can be a Retimer card, the Retimer card is a signal conditioning chip, the function of which is signal balancing and enhancement.

[0063] In this embodiment, the connecting device includes a first cable 11 and a second cable 12. The first end of the first cable 11 is connected to the second end of the controller, that is, the output end of the controller, the second end of the first cable 11 is connected to the first ends of multiple backplanes, the first end of the second cable 12 is connected to the second ends of the multiple backplanes, and the second end of the second cable 12 is connected to the first ends of multiple signal relay devices.

[0064] The hard disk device 30 is arranged on the backplane, and can be arranged on the side of the backplane close to the signal relay device. The gray filled block shown in the figure is the hard disk device 30, and the hard disk device can be a hard disk such as SSD, PCIE, etc. The hard disk device 30 is connected to the signal relay device and the backplane respectively through the preset high-speed and low-speed cables 13.

[0065] Specifically, the preset high-speed and low-speed cables include multiple sub-high-speed cables and multiple sub-low-speed cables. The first end of the hard disk device 30 is connected to the second end of the backplane through multiple sub-low-speed cables 133, the second end of the hard disk device 30 is connected to the first end of the signal relay device through multiple sub-high-speed cables 131, and the second end of the backplane is connected to the first end of the signal relay device through multiple sub-low-speed cables 132.

[0066] In the present application, a preset high-speed and low-speed cable is set to connect the signal relay device, the backplane, and the hard disk device, wherein the sub-high-speed cable in the preset high-speed and low-speed cables does not pass through the backplane, but directly connects the signal relay device and the hard disk device, and the low-speed signals of the signal relay device and the hard disk device are respectively connected to the backplane through the sub-low-speed cables in the preset high-speed and low-speed cables. In this way, the connector on the high-speed signal link and the high-speed signal loss on the PCB (printed circuit board) are saved, more cables can be introduced, and the stability of the high-speed link is objectively increased.

[0067] It is understandable that this application only takes the hard disk device set on the backplane 1 as an example to describe the connection relationship between the backplane 1, the hard disk device, and the signal relay device (Retimer card 1). In actual applications, there can be multiple hard disk devices arranged on multiple backplanes.

[0068] It can be understood that the preset high-speed and low-speed cables and hard disk devices in this embodiment can also be applied to the server chassis system in Example 1 of the present application.

[0069] Embodiment 3

[0070] In the embodiments disclosed in this application, there are Figure 5 The server chassis system shown includes a server mainboard, a backplane, a signal relay device, a connection device, and a target device.

[0071] The server motherboard is used to carry various devices installed on the server motherboard, including a controller, which may specifically be a baseboard management controller (BMC), a processor, a heat sink, and other devices.

[0072] In this embodiment, an interface is set on the controller set on the server mainboard, including at least a first interface 141 and a second interface 142. The first interface 141 is connected to the target device set on the server mainboard; the second interface 142 is connected to the target device set on the backplane and the signal relay device.

[0073] Multiple backplanes, which are used to provide interfaces corresponding to the expansion slots on the server motherboard and are used to install various expansion cards to increase the functions and performance of the server.

[0074] Multiple signal relay devices, optionally, the signal relay device can be a Retimer card, the Retimer card is a signal conditioning chip, the function of which is signal balancing and enhancement.

[0075] The connection device includes a first cable 11 and a second cable 12. The first end of the first cable 11 is connected to the second end of the controller, that is, the output end of the controller, the second end of the first cable 11 is connected to the first ends of multiple backplanes, the first end of the second cable 12 is connected to the second ends of the multiple backplanes, and the second end of the second cable 12 is connected to the first ends of multiple signal relay devices. In this embodiment, the first cable 11 and the second cable 12 are both high-speed cables.

[0076] The target devices include a first target device 15, a second target device 16 and a third target device 17, wherein the first target device 15 is set on a server mainboard, the second target device 16 is set on a backplane, the third target device 17 is set on a signal relay device, the second interface 142 is connected to the first end of the second target device 16, and the second end of the second target device 16 is connected to the first end of the third target device 17.

[0077] Here, the first target device 15 may be an I2C master device, and the second target device 16 and the third target device 17 may be I2C slave devices. By respectively setting the I2C master and slave devices on the server mainboard, the backplane, and the signal relay device, the I2C master device may send a stop condition to the slave device to stop signal and data transmission. By setting the I2C master and slave devices, high-speed data transmission capability may be achieved through simple system connection, which provides convenience and efficiency for the design of the server chassis system.

[0078] See also Figure 5 as well as Figure 6In one embodiment, a third interface 18 is provided at the first end of the backplane, and a fourth interface 19 is provided at the first end of the signal relay device; the second interface 142 is connected to the third interface 18 through a target cable 40; the third interface 18 is connected to the first end of the second target device 16 through the target cable 40, and the second end of the second target device 16 is connected to the fourth interface 19 through the target cable 40; the fourth interface 19 is connected to the first end of the third target device 17 through the target cable 40.

[0079] The backplane also includes a first control module 20, and the signal relay device number includes a second control module 21; the first end of the first control module 20 is connected to the third interface 18, and the second end of the first control module 20 is connected to the first end of the second target device 16; the first end of the second control module 21 is connected to the fourth interface 19, and the second end of the second control module 21 is connected to the first end of the third target device 17.

[0080] In this embodiment, by setting the third interface 18, the first control module 20, the fourth interface 19, and the second control module 21 between the I2C master device and the I2C slave device, the first end of the third interface 18 is connected to the control end of the I2C master device, and the second end of the third interface 18 is connected to the first control module and then connected to the I2C slave device. With such a setting, the I2C link status can be monitored, the I2C slave device that is hung up can be determined according to the I2C link status, and the I2C slave device that is hung up can be isolated. Due to the connection relationship between the control module and the target device in series, when the I2C slave device at the back end of any link fails, it is monitored and isolated in time, and at the same time, it will not affect the I2C slave devices in other links. Therefore, this structural design can greatly improve the accuracy of I2C link control, thereby improving the management efficiency of I2C links.

[0081] In one embodiment, the first control module 20 includes a first signal control module (not shown) and a first switch control module, and the second control module 21 includes a second signal control module and a second switch control module; the first signal control module and the second signal control module are respectively used to control the on and off of the digital signals of the second target device 16 and the third target device 17; the first switch control module and the second switch control module are respectively used to control the on and off of the clock signals of the second target device 16 and the third target device 17.

[0082] The first switch control module and / or the second switch control module are used to control the digital signal on and off of the I2C slave device connected to the first switch control module and / or the second switch control module in the I2C link according to the acquired signal, and the input end of the first switch control module and / or the second switch control module is connected to the data output end of the upper-level device and the data input end of the lower-level device, and the output end of the first switch control module and / or the second switch control module is connected to the I2C slave device through the I2C_SDASlave signal. Among them, the I2C_SDA Slave signal is the data signal of the I2C slave device.

[0083] The first signal control module and / or the second signal control module are used to control the on and off of the clock signal of the I2C slave device connected to the first signal control module and / or the second signal control module in the I2C link according to the acquired signal, and the input end of the first signal control module and / or the second signal control module is connected to the clock output end of the upper-level device and the clock input end of the next-level device, and the output end of the first signal control module and / or the second signal control module is connected to the I2C slave device through the I2C_SCLSlave signal, wherein the I2C_SCL Slave signal is the clock signal of the I2C slave device.

[0084] In this way, by using the first signal control module and the second signal control module to respectively control the on and off of the digital signals of the second target device 16 and the third target device 17; the first switch control module and the second switch control module are respectively used to control the on and off of the clock signals of the second target device 16 and the third target device 17, the accuracy of data transmission and signal transmission can be achieved.

[0085] Embodiment 4

[0086] In the embodiments disclosed in this application, there are Figure 7 The server chassis system shown includes a server mainboard, a backplane, a signal relay device, a connecting device, a first crystal oscillator, a first pin, a first trigger, a second crystal oscillator, a second pin and a second trigger.

[0087] The server motherboard is used to carry various devices installed on the server motherboard, including a controller, which may specifically be a baseboard management controller (BMC), a processor, a heat sink, and other devices.

[0088] Multiple backplanes, which are used to provide interfaces corresponding to the expansion slots on the server motherboard and are used to install various expansion cards to increase the functions and performance of the server.

[0089] Multiple signal relay devices, optionally, the signal relay device can be a Retimer card, the Retimer card is a signal conditioning chip, the function of which is signal balancing and enhancement.

[0090] The connection device includes a first cable 11 and a second cable 12. The first end of the first cable 11 is connected to the second end of the controller, that is, the output end of the controller, the second end of the first cable 11 is connected to the first ends of multiple backplanes, the first end of the second cable 12 is connected to the second ends of the multiple backplanes, and the second end of the second cable 12 is connected to the first ends of multiple signal relay devices. In this embodiment, the first cable 11 and the second cable 12 are both high-speed cables.

[0091] In this embodiment, a first crystal oscillator 23 , a first pin 27 and a first trigger 25 are disposed at the first end of the backplane, and a second crystal oscillator 24 , a second pin 28 and a second trigger 26 are disposed at the second end of the backplane.

[0092] Specifically, the output end of the first crystal oscillator 23 is connected to the input end of the first trigger 25 , the output end of the first trigger 25 is connected to the first pin 27 ; the output end of the second crystal oscillator 24 is connected to the input end of the second trigger 26 , and the output end of the second trigger 26 is connected to the second pin 28 .

[0093] The first crystal oscillator 23 is used to generate a first baseband signal, which transmits the first baseband signal to the first trigger 25. The first trigger 25 is used to generate a first frequency-divided signal based on the first baseband signal. The first trigger 25 transmits the first frequency-divided signal to the first pin 27. The first pin 27 is connected to the first cable 11. The first frequency-divided signal is transmitted to the controller (BMC) through the first cable 11. The controller is used to determine the connection status of the first cable 11 between the controller and the backplane based on the first frequency-divided signal.

[0094] The second crystal oscillator 24 is used to generate a second baseband signal, which transmits the second baseband signal to the second trigger 26. The second trigger 26 is used to generate a second frequency-divided signal according to the second baseband signal. The second trigger 26 transmits the second frequency-divided signal to the second pin 28. The second frequency-divided signal is transmitted to the control chip on the signal relay device through the second cable 12. The control chip determines the connection status of the second cable 12 between the signal relay device and the backplane according to the second frequency-divided signal.

[0095] In the present application, by providing a first crystal oscillator 23, a first pin 27 and a first trigger 25 at the first end of the backplane, and providing a second crystal oscillator 24, a second pin 28 and a second trigger 26 at the second end of the backplane, it is possible to transmit the first baseband signal generated by the first crystal oscillator 23 to the first trigger 25 to obtain a first frequency-divided signal, and transmit the first frequency-divided signal to the first pin 27, and the first pin 27 is connected to the first cable 11, so as to transmit the first frequency-divided signal to the controller on the server motherboard, and the controller on the server motherboard determines whether the first cable is connected correctly according to the first frequency-divided signal; similarly, The second baseband signal generated by the second crystal oscillator 24 is transmitted to the second trigger 26 to obtain a first frequency-divided signal, and the first frequency-divided signal is transmitted to the second pin 28. The second pin 28 is connected to the second cable 12, so that the second frequency-divided signal is transmitted to the control chip on the signal relay device. The control chip on the signal relay device determines whether the second cable is connected correctly according to the second frequency-divided signal. In this way, the detection of multiple cables in a multi-connection device is realized, and the used triggers, crystal oscillators and other components are very small in size, which can further save the internal space of the server chassis on the basis of ensuring the connection reliability of the connection device.

[0096] In this application, the controller set on the server motherboard is connected to the backplane and the signal relay device by using the high-speed cable connecting the original backplane and the signal relay device, which can reduce the space occupied by the cable on the server, save cables, facilitate cable management, facilitate operators to plug and unplug cables, reduce the space occupied by cables in the chassis, reduce the impact of cables on heat dissipation, and release the server system space so that the server system space can be used for other designs. In addition, the I2C interface of the BMC is saved, and the BMC can be used for more complex systems.

[0097] By setting a preset high-speed and low-speed cable to connect the signal relay device, the backplane, and the hard disk device, wherein the sub-high-speed cable in the preset high-speed and low-speed cables does not pass through the backplane, but directly connects the signal relay device and the hard disk device, and the low-speed signals of the signal relay device and the hard disk device are respectively connected to the backplane through the sub-low-speed cables in the preset high-speed and low-speed cables. In this way, the connector on the high-speed signal link and the high-speed signal loss on the PCB (printed circuit board) are saved, and more cables can be introduced, which objectively increases the stability of the high-speed link. Through the above implementation mode, the present application solves the problem of insufficient BMC I2C interface, reduces the cables in the frame, solves the problems of complex cables in the frame, easy damage of cables, and too many cables affecting heat dissipation. It solves the problem that the high-speed link loss is too large and the routing cannot be too long.

[0098] In one embodiment, a temperature detection chip can also be set on the upstream of the server motherboard, and the temperature of each component in the server system can be monitored in real time through the chip. The controller on the server can obtain the temperature information of each component in the server system in real time through the connector and I2C, thereby realizing real-time monitoring of the temperature of each component in the server system, and adjusting the heat dissipation strategy according to the temperature data to reduce power consumption, thereby achieving the purpose of energy saving and environmental protection.

[0099] Among them, the baseboard management controller (BMC) set on the server motherboard obtains the temperature information of each component in the server system through the GPIO reading method or the I2C reading method, thereby realizing real-time monitoring of the temperature of each component in the server system. Exemplarily, the response signal of each I / O interface on each signal relay device can be obtained through the I2C driver chip connected to the motherboard; each interface response signal is parsed to obtain the array corresponding to each I / O interface on each signal relay device.

[0100] In one embodiment, the temperature detection chip can be located at the front end of the server motherboard. The front end of the server motherboard can be the air inlet of the motherboard, and the copper cladding and routing on the motherboard position for wiring and placing the temperature detection chip can be hollowed out to prevent heat from other components from being transferred to the temperature detection chip and affecting the measurement accuracy. The temperature detection chip is installed at this position; the temperature detection chip is connected to the BMC (baseboard management controller) through the I2C channel, and the original data is transmitted to the BMC (baseboard management controller) chip, and the BMC (baseboard management controller) chip performs data correction. In this way, the accuracy of temperature detection can be improved.

[0101] Specifically, the temperature detection chip can obtain the real-time working temperature of each component in the server chassis system, such as the processor on the mainboard, the network switch, etc. during the working process. The I2C bus can determine whether the current working temperature is the working temperature of the server chassis system when it is operating normally based on the working temperature. If the real-time working temperature of a certain component during the working process is not within the normal working temperature range of the server chassis system when it is operating normally, the location information of the component is obtained, a warning message is issued, and it is displayed on the configuration interface.

[0102] In one embodiment, a server chassis device is provided, including the above-mentioned server chassis system. The internal structure diagram thereof can be shown as follows: Figure 8 As shown. Those skilled in the art can understand that Figure 8 The structure shown in the figure is only a block diagram of a partial structure related to the present application scheme, and does not constitute a limitation on the server chassis device to which the present application scheme is applied. The specific server chassis device may include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0103] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A server chassis system, characterized in that: include: A server mainboard, wherein a controller is arranged on the server mainboard; A backplane, wherein the backplane is multiple, and the first ends of the multiple backplanes are connected to the controller through a connecting device; A signal relay device, wherein there are multiple signal relay devices, and the first ends of the multiple signal relay devices are connected to the second ends of the multiple backplanes through a connecting device; The connecting device includes a first cable and a second cable, wherein a first end of the first cable is connected to a second end of the controller, a second end of the first cable is connected to a first end of the plurality of backplanes, a first end of the second cable is connected to a second end of the plurality of backplanes, and a second end of the second cable is connected to a first end of the plurality of signal relay devices; The first cable is a low-speed / high-speed cable, and the second cable is a high-speed cable.

2. The system according to claim 1, characterized in that The system further comprises a hard disk device, which is arranged on a backplane and is connected to a signal relay device and a backplane respectively through preset high-speed and low-speed cables.

3. The system according to claim 2, characterized in that The preset high-speed and low-speed cables include a plurality of sub-high-speed cables and a plurality of sub-low-speed cables, and the hard disk device is connected to the signal relay device and the backplane through the preset high-speed and low-speed cables respectively, including: The first end of the hard disk device is connected to the second end of the backplane through the multiple sub-low-speed cables, the second end of the hard disk device is connected to the first end of the signal relay device through the multiple sub-high-speed cables, and the second end of the backplane is connected to the first end of the signal relay device through the multiple sub-low-speed cables.

4. The system according to claim 1, characterized in that The controller comprises at least a first interface and a second interface, wherein the first interface is connected to a target device arranged on a server mainboard; and the second interface is connected to a target device arranged on a backplane and a signal relay device.

5. The system according to claim 4, characterized in that The target device includes a first target device, a second target device and a third target device, the first target device is arranged on a server mainboard, the second target device is arranged on a backplane, the third target device is arranged on a signal relay device, and the second interface is connected with the target devices arranged on the backplane and the signal relay device, including: The second interface is connected to a first end of a second target device, and a second end of the second target device is connected to a first end of a third target device.

6. The system according to claim 5, characterized in that The first end of the backplane is provided with a third interface, and the first end of the signal relay device is provided with a fourth interface; The second interface is connected to the third interface via a target cable; The third interface is connected to a first end of a second target device via a target cable, and a second end of the second target device is connected to a fourth interface via a target cable; The fourth interface is connected to the first end of the third target device through the target cable; Wherein, the backplane further includes a first control module, and the signal relay device number includes a second control module; The first end of the first control module is connected to the third interface, and the second end of the first control module is connected to the first end of the second target device; A first end of the second control module is connected to the fourth interface, and a second end of the second control module is connected to a first end of the third target device.

7. The system according to claim 6, characterized in that The first control module includes a first signal control module and a first switch control module, and the second control module includes a second signal control module and a second switch control module; The first signal control module and the second signal control module are used to control the on and off of digital signals of the second target device and the third target device respectively; The first switch control module and the second switch control module are used to control the on and off of the clock signals of the second target device and the third target device respectively.

8. The system according to claim 1, characterized in that The first end of the backplane is provided with a first crystal oscillator, a first pin and a first trigger, and the second end of the backplane is provided with a second crystal oscillator, a second pin and a second trigger: The output end of the first crystal oscillator is connected to the input end of the first trigger, and the output end of the first trigger is connected to the first pin; The output end of the second crystal oscillator is connected to the input end of the second trigger, and the output end of the second trigger is connected to the second pin.

9. The system according to claim 8, characterized in that The first crystal oscillator is used to generate a first baseband signal, the first crystal oscillator transmits the first baseband signal to a first trigger, the first trigger is used to generate a first frequency-divided signal according to the first baseband signal, the first trigger transmits the first frequency-divided signal to a first pin, and the first pin is connected to the first cable; Transmitting a first frequency-divided signal to a controller through the first cable, wherein the controller is configured to determine a connection state of the first cable between the controller and the backplane according to the first frequency-divided signal; The second crystal oscillator is used to generate a second base frequency signal, the second crystal oscillator transmits the second base frequency signal to a second trigger, the second trigger is used to generate a second frequency-divided signal according to the second base frequency signal, the second trigger transmits the second frequency-divided signal to a second pin, and the second pin is connected to the second cable; The second frequency-divided signal is transmitted to a control chip on the signal relay device through the second cable, and the control chip is used to determine the connection state of the second cable between the signal relay device and the backplane according to the second frequency-divided signal.

10. A server chassis device, characterized in that: The server chassis device comprises the server chassis system as described in any one of claims 1-9.

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