Data processing method and system, electronic equipment and storage medium

Abstract

The invention discloses a data processing method and system, electronic equipment and a storage medium, which are applied to a production test, a master equipment end and a slave equipment end carry out data transmission through an SPI interface, and the slave equipment end is coupled with a storage device to be tested, the method comprises the following steps: the master equipment end transmits a target command to the slave equipment end through the SPI interface, sending the target command to the to-be-tested storage device from the device end, and obtaining a command execution result fed back by the to-be-tested storage device; and the master device end responds to a reply signal sent by the slave device end through the GPIO pin and sends a result request command to the slave device end, so that the slave device end returns a command execution result. According to the invention, on the basis of the SPI transmission protocol, data transmission is carried out through the SPI interface, and the reply signal is transmitted through the additional GPIO pin, so that the slave device end can actively inform the master device end to complete confirmation reply to the master device end, and high efficiency, reliability and integrity of data transmission are ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of production testing, and in particular to a data processing method, system, electronic equipment and storage medium. Background Art

[0002] In the production test process of electronic products, in order to improve production efficiency, an SPI (Serial Peripheral Interface) interface is usually used to transmit data to a circuit board that drags multiple storage devices to be tested from the device end.

[0003] In actual operation, the researchers of this application found that the UART (Universal Asynchronous Receiver and Transmitter) interface is generally used to complete the card activation for production testing. However, the amount of effective data transmitted by the UART interface of the UFS (Univeral Flash Storage) controller is low, which affects the efficiency, reliability and integrity of data transmission. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a data processing method, system, electronic device and storage medium, which can enable a master device to receive a confirmation message notification from a slave device.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a data processing method, which is applied to a master device end in production testing, wherein the master device end and the slave device end perform data transmission through an SPI interface, and the slave device end is coupled to a storage device to be tested, and the method comprises: the master device end transmits a target command to the slave device end through the SPI interface, so that the slave device end sends the target command to the storage device to be tested, and obtains a command execution result fed back by the storage device to be tested; the master device end responds to a reply signal sent by the slave device end through a GPIO pin, and sends a result request command to the slave device end, so that the slave device end returns the command execution result.

[0006] In one embodiment of the present application, the master device transmits the target command to the slave device through the SPI interface, including: the master device encapsulates the target command according to the command packet format corresponding to the SPI interface to obtain a target command packet, and transmits the target command packet to the slave device through the SPI interface.

[0007] In one embodiment of the present application, the master device sends a result request command to the slave device in response to a reply signal sent by the slave device through a GPIO pin, so that the slave device returns the command execution result, including: the master device sends a result request command to the slave device through the SPI interface in response to the voltage of the reply signal sent through the GPIO pin being higher than a preset voltage, so that the slave device returns the command execution result.

[0008] To solve the above technical problems, another technical solution adopted in the present application is: to provide a data processing method, which is applied to a slave device end in production testing, wherein the slave device end and the master device end perform data transmission through an SPI interface, and the slave device end is coupled to a storage device to be tested, and the method comprises: the slave device end receives a target command sent by the master device end through the SPI interface, and sends the target command to the storage device to be tested, and obtains a command execution result fed back by the storage device to be tested; the slave device end sends a reply signal corresponding to the target command to the master device end through a GPIO pin, so that the master device end sends a result request command to the slave device end; the slave device end responds to the result request command and sends the command execution result to the master device end.

[0009] In one embodiment of the present application, the slave device receives a target command sent by the master device through the SPI interface, sends the target command to the storage device under test, and obtains a command execution result fed back by the storage device under test, including: the slave device parses and activates a first task corresponding to the target command, and verifies first data corresponding to the first task; when the first data is verified to be correct, the first task enters a first state, the slave device sends the first data to the storage device under test, and obtains the first command execution result fed back by the storage device under test; the first task enters a second state, the slave device receives second data and verifies the second data; when the second data is verified to be correct, the slave device sends the second data to the storage device under test, and obtains the second command execution result fed back by the storage device under test.

[0010] In one embodiment of the present application, the slave device sends a reply signal corresponding to the target command to the master device via a GPIO pin, including: the slave device caches the command execution result in a FIFO queue of the SPI interface, and pulls up the voltage of the GPIO pin to form the reply signal.

[0011] In one embodiment of the present application, the slave device end caches preset data in the FIFO queue of the SPI interface; after the slave device end receives the target command sent by the master device end through the SPI interface, the slave device end replies to the master device end with the preset data, so that the master device end receives the preset data; the slave device end responds to the preset data sent by the master device end, and sends a reply signal corresponding to the target command to the master device end through the GPIO pin.

[0012] In one embodiment of the present application, during data transmission, the target command is encapsulated as a target command packet, wherein the checksum in the target command packet is used to verify data integrity, and the checksum is determined by the sum of the remaining byte groups in the target command packet, and the remaining bytes include at least the request command code and parameters corresponding to the target command.

[0013] To solve the above technical problems, another technical solution adopted in the present application is: providing a data processing system, including a master device end and at least one slave device end; the slave device end is coupled to the master device end, and each of the slave device ends is coupled to a storage device to be tested; wherein the master device end transmits a target command to the slave device end through an SPI interface, so that the slave device end sends the target command to the storage device to be tested, and obtains the command execution result fed back by the storage device to be tested; the master device end also responds to a reply signal sent by the slave device end through a GPIO pin, and sends a result request command to the slave device end, so that the slave device end returns the command execution result.

[0014] In order to solve the above technical problems, another technical solution adopted in the present application is: to provide an electronic device, including a processor and a memory, wherein the processor is coupled to the memory and executes instructions when working to implement the above data processing method.

[0015] In order to solve the above technical problems, another technical solution adopted in the present application is: providing a computer storage medium, wherein the computer storage medium stores a computer program, and the computer program is executed to implement the above data processing method.

[0016] Different from the current technology, the data processing method provided by the present application is applied to the master device end in production testing, wherein the master device end and the slave device end perform data transmission through the SPI interface, the slave device end is coupled to the storage device to be tested, and the method comprises: the master device end transmits the target command to the slave device end through the SPI interface, so that the slave device end sends the target command to the storage device to be tested, and obtains the command execution result fed back by the storage device to be tested; the master device end responds to the reply signal sent by the slave device end through the GPIO pin, sends a result request command to the slave device end, so that the slave device end returns the command execution result. That is, the technical solution of the present application performs data transmission through the SPI interface on the basis of the SPI transmission protocol, and transmits the reply signal through the additional GPIO pin, so that the slave device end can actively notify the master device end and complete the reply of the confirmation message to the master device end, thereby ensuring the efficiency, reliability and integrity of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0018] Figure 1 It is a flowchart of the first embodiment of the data processing method in this application;

[0019] Figure 2 It is a structural diagram of an embodiment of the pin connection between the master device end and the slave device end in the present application;

[0020] Figure 3 It is a communication flow diagram of an embodiment of a communication framework in the present application;

[0021] Figure 4 It is a flowchart of the second embodiment of the data processing method in this application;

[0022] Figure 5 It is a flowchart of an embodiment of step S21 in this application;

[0023] Figure 6 It is a structural diagram of an embodiment of a data processing system in the present application;

[0024] Figure 7 It is a structural schematic diagram of an embodiment of an electronic device in the present application;

[0025] Figure 8 It is a structural diagram of an embodiment of a computer storage medium in the present application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be appreciated that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the art without making creative work are within the scope of protection of the present application.

[0027] Reference to "embodiments" in an application means that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0028] The steps in the embodiments of the present application do not necessarily have to be processed in the described order of steps. The steps can be selectively rearranged, or the steps in the embodiments can be deleted, or the steps in the embodiments can be added as needed. The step descriptions in the embodiments of the present application are only optional sequence combinations and do not represent all step sequence combinations in the embodiments of the present application. The order of steps in the embodiments cannot be considered as a limitation of the present application.

[0029] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0030] The current data transmission method for production testing needs to reduce production costs and improve production efficiency. The UART (Universal Asynchronous Receiver and Transmitter) interface of the UFS controller is used to complete the card opening. However, the production tool needs to use an interface with a higher transmission speed than the UART interface. The UART interface of the UFS controller currently supports 115200, and the valid data is less than 10KB. In other words, the amount of valid data transmitted by the UART interface of the UFS (Univeral Flash Storage) controller is low, which affects the efficiency, reliability and integrity of data transmission.

[0031] Therefore, a data processing method is provided. Under the SPI transmission protocol, a master device end and a slave device end perform data transmission through an SPI interface. On this basis, a GPIO (General-purpose input / output) pin is additionally added, so that the slave device end can actively send a reply signal to the master device end through the GPIO pin, thereby enabling the master device end and the slave device end to realize a reliable data transmission solution of seamlessly converting the SPI transmission protocol to UART, thereby improving the efficiency of data transmission.

[0032] See also Figure 1 , Figure 1 It is a flowchart of the first embodiment of the data processing method of the present application.

[0033] like Figure 1 As shown, the data processing method is applied to the master device in the production test, wherein the master device and the slave device perform data transmission via the SPI interface, and the slave device is coupled to the storage device to be tested. The data processing method includes the following steps:

[0034] S11, the master device transmits the target command to the slave device through the SPI interface, so that the slave device sends the target command to the storage device under test and obtains the command execution result fed back by the storage device under test.

[0035] Among them, the master device end is the master device defined in the SPI transmission protocol, the slave device end is the slave device defined in the SPI transmission protocol, and the SPI interface is the data transmission interface defined in the SPI transmission protocol.

[0036] Specifically, based on the SPI transmission protocol, the master device transmits the target command to the slave device through the SPI interface. After receiving the target command, the slave device forwards the target command to the storage device under test, so that the storage device under test returns the command execution result to the slave device after receiving the target command.

[0037] In some embodiments, there are four pins between the master device and the slave device, namely, MOSI (Master Output Slave Input) pin, MISO (Master Input Slave Output) pin, SCK (Serial Clock) pin and CS (Chip Select) pin; wherein, the MOSI pin is used for data transmission from the master device to the slave device, the MISO pin is used for data transmission from the slave device to the master device, the SCK pin is used for sending the clock control signal generated by the master device to the slave device, and the CS pin is a chip selection pin, which is used by the master control end to control the enable signal and select among multiple slave devices.

[0038] S12. The master device sends a result request command to the slave device in response to the reply signal sent by the slave device through the GPIO pin, so that the slave device returns the command execution result.

[0039] Among them, the GPIO pin is an additional pin added between the master device end and the slave device end.

[0040] Specifically, after receiving the command execution result from the slave device, the slave device generates a reply signal and transmits it to the master device through the GPIO pin. The master device responds to the reply signal sent by the slave device through the GPIO pin, so that the master device sends a result request command to the slave device. After receiving the result request command, the slave device returns the command execution result to the master device.

[0041] Because production testing usually needs to ensure the transmission reliability of the SPI transmission protocol at high temperatures, and the SPI transmission protocol itself does not have a handshake protocol, that is, there is no reception confirmation message notification, and it cannot guarantee the efficiency, reliability and integrity of the transmitted data. The SPI (Serial Peripheral Interface) protocol can support a maximum transmission speed of about 50MB. Therefore, in project development, the master device often uses the SPI interface to transmit data to a slave device (such as MCU, microcontroller) on a circuit board with 8 storage devices to be tested (such as UFS). The UFS between each MCU is operated in parallel, which improves production efficiency and reduces overall costs.

[0042] Therefore, in this embodiment, the master device and the slave device perform data transmission via the SPI interface. After the master device sends the target command to the slave device via the SPI interface, the slave device sends the target command to the storage device to be tested and receives the corresponding command execution result. The slave device then sends a reply signal to notify the master device via the GPIO pin, and the master device then sends a result request command to obtain the command execution result returned by the slave device. On the basis of adopting the SPI transmission protocol, the present application adds an additional GPIO pin to the master device and the slave device. The master device can receive the reply signal corresponding to the target command sent by the slave device via the GPIO pin, so that the slave device actively notifies the master device, ensures the efficiency, reliability and integrity of the transmitted data, reduces the waiting time of the master device, and improves the communication efficiency between the master device and the slave device.

[0043] like Figure 2 As shown, Figure 2 FIG. 1 is a schematic diagram of a structure of an embodiment of pin connection between a master device end and a slave device end. Figure 2 As shown, the master device end can be an FPGA (Field Programmable Gate Array), and the slave device end can be an MCU (Microcontroller Unit). Based on the SPI transmission protocol, the programmable array logic unit and the microcontroller unit are connected through the MOSI pin, the MISO pin, the SCK pin and the CS pin; in order to enable the slave device end to actively notify the master device end, an additional GPIO pin is added between the programmable array logic unit and the microcontroller unit, so that the slave device end can actively reply to the master device end through the GPIO pin.

[0044] In some embodiments, before the master device transmits the target command to the slave device through the SPI interface, it also includes: the master device encapsulates the target command according to the command packet format corresponding to the SPI interface to obtain a target command packet, and then transmits the target command packet to the slave device through the SPI interface.

[0045] Among them, the command packet format corresponding to the SPI interface is the command packet format corresponding to the SPI transmission protocol.

[0046] Specifically, based on the SPI transmission protocol corresponding to the SPI interface, the master device end encapsulates the target command according to the command packet format corresponding to the SPI transmission protocol to obtain the corresponding target command packet. The master device end then transmits the target command packet to the slave device end through the SPI interface, completing the data transmission process sent by the master device end and received by the slave device end.

[0047] In some embodiments, the command packet format includes a command packet and a data packet, wherein the command packet may be composed of K bytes, the first K-2 bytes are the command code and parameters, and the last 2 bytes are the checksum. For example, the command packet has 16 bytes, the first 14 bytes are the command code and parameters, and the last two bytes are the checksum. In a 16-byte command packet, the checksum is calculated as follows: the first 14 bytes are grouped into groups of two bytes each, and can be divided into 7 groups of bytes; the sum obtained by adding the 7 groups of bytes is removed from the overflowed high bits, and only two bytes are retained, and the retained two bytes are used as the checksum.

[0048] The command packet can be divided into a command request packet and a command reply packet. The command request packet may include a request command code, multiple parameters, and a checksum. The request command code may be two bytes, the parameters may be two bytes or four bytes or set according to the actual situation, and the checksum is two bytes. The format of the command request packet is shown in Table 1:

[0049]

[0050] Table 1: Command request packet format

[0051] The command reply packet may include a reply command code, multiple parameters, an error code, and a checksum, wherein the reply command code may be two bytes, the parameter may be two bytes or four bytes or set according to the actual situation, the error code is two bytes, and the checksum is two bytes. The format of the command reply packet is shown in Table 2:

[0052]

[0053] Table 2: Command reply packet format.

[0054] Data packets can be divided into two types. One is the first data packet, which is 16 bytes. The format of the first data packet is consistent with the command packet format, that is, the first 14 bytes are the command code and return value, and the last two bytes are the checksum, which is used to transmit data in the command packet; the other is the second data packet, which is 528 bytes. The second data packet consists of 512 bytes of data and a 16-byte checksum. The format of the second data packet is shown in Table 3:

[0055]

[0056] Table 3: Second Data Packet Format The 16-byte checksum structure in the second data packet is shown in Table 4:

[0057]

[0058] Table 4: 16-byte checksum format in the second data packet

[0059] When a large amount of data is transmitted, the 528-byte second data packet ensures that too many checksums are generated during the large data transmission to affect the transmission of other data.

[0060] See also Figure 3 , Figure 3 A communication flow diagram of an embodiment of a communication framework.

[0061] like Figure 3 As shown, the first step: the tool end (such as a computer) sends data (such as 514 bytes of data) to the programmable array logic unit through a network cable (such as an RJ45 network cable); the second step: the programmable array logic unit encapsulates the data into 16 bytes of data and sends it to the micro control unit; the third step: when the micro control unit receives the 16 bytes of data, it will also reply a preset data to the programmable array logic unit, so that the programmable array logic unit notifies the tool end; the fourth step: the micro control unit identifies the target command sent by the programmable array logic unit, and executes seamless delivery of 16 bytes of data to the storage device to be tested (such as UFS, Univeral Flash Storage, universal flash memory); the fifth step: the micro control unit receives the 16 bytes of data replied by the storage device to be tested, that is, replies to the command execution result, and caches the command execution result corresponding to the target command in the FIFO (First Input First ) of the SPI interface Output, first-in-first-out) queue, and pull up the GPIO pin voltage connected to the microcontroller unit and the programmable array logic unit; Step 6: The programmable array logic unit detects that the GPIO pin voltage is pulled high, and then notifies the tool end that the microcontroller unit has completed the execution of the target command and can issue a result request command; Step 7: The tool end issues the result request command; Step 8: After receiving the result request command issued by the tool end, the programmable array logic unit forwards the result request command to the microcontroller unit;

[0062] Step 9: The microcontroller unit responds to the result request command and returns the command execution result cached in the FIFO queue of the SPI interface to the programmable array logic unit; Step 10: The programmable array logic unit returns the command execution result to the tool end to complete the communication process.

[0063] In some embodiments, in response to the voltage of the reply signal sent through the GPIO pin being higher than a preset voltage, the master device sends a result request command to the slave device through the SPI interface, so that the slave device returns the command execution result.

[0064] Among them, the reply signal is generated by pulling up the voltage of the GPIO pin after the device receives the command execution result fed back by the storage device under test, that is, pulling up the GPIO pin is the reply signal, and the preset voltage is the measurement standard for whether the GPIO pin voltage is pulled up. If it is higher than the preset voltage, it indicates that the voltage of the reply signal is pulled up.

[0065] Specifically, before the master device responds to the reply signal sent by the slave device through the GPIO pin, it needs to detect the voltage corresponding to the reply signal sent by the slave device through the GPIO pin. When the voltage of the reply signal is higher than the preset voltage, the master device will respond to the reply signal sent by the slave device through the GPIO pin, and then the master device will send a result request command to the slave device through the SPI interface, so that the slave device returns the command execution result to the master device.

[0066] See also Figure 4 , Figure 4 It is a flowchart of the second embodiment of the data processing method of the present application.

[0067] like Figure 4 As shown, the data processing method is applied to the slave device in the production test, wherein the slave device and the master device perform data transmission via the SPI interface, and the slave device is coupled to the storage device to be tested. The data processing method includes:

[0068] S21, receiving the target command sent by the master device through the SPI interface from the slave device, sending the target command to the storage device to be tested, and obtaining the command execution result fed back by the storage device to be tested.

[0069] Among them, the master device end is the master device defined in the SPI transmission protocol, the slave device end is the slave device defined in the SPI transmission protocol, and the SPI interface is the data transmission interface defined in the SPI transmission protocol.

[0070] Specifically, based on the SPI transmission protocol, after the master device sends the target command through the SPI interface, the slave device receives the target command sent by the master device, and the slave device forwards the received target command to the storage device under test, so that the storage device under test returns the command execution result to the slave device after receiving the target command.

[0071] In some embodiments, the SPI interface between the master device end and the slave device end has four pins, namely, MOSI (Master Output Slave Input) pin, MISO (Master Input Slave Output) pin, SCK (Serial Clock) pin and CS (Chip Select) pin; wherein, the MOSI pin is used for data transmission from the master device end to the slave device end, the MISO pin is used for data transmission from the slave device end to the master device end, the SCK pin is used for sending the clock control signal generated by the master device end to the slave device end, and the CS pin is a chip selection pin, which is used by the master control end to control the enable signal and select among multiple slave device ends.

[0072] S22, the slave device sends a reply signal corresponding to the target command to the master device through the GPIO pin, so that the master device sends a result request command to the slave device.

[0073] Among them, based on the SPI transmission protocol, a GPIO pin is added on the basis of the existing MOSI pin, MISO pin, SCK pin and CS pin, so that the slave device can actively send a reply signal to the master device through the additional GPIO pin.

[0074] Specifically, after receiving the command execution result fed back by the storage device under test from the slave device, the slave device generates a reply signal corresponding to the target command, and sends the reply signal to the master device through the GPIO pin, so that after receiving the reply signal, the master device can send a result request command to the slave device.

[0075] In some embodiments, after obtaining the command execution result from the device, the command execution result is cached in the FIFO (First Input First Output) queue of the SPI interface, and the voltage of the GPIO pin is pulled high to form a reply signal; after the master device detects the reply signal, the master device sends a result request command to the slave device.

[0076] S23. The slave device responds to the result request command and sends the command execution result to the master device.

[0077] The result request command is sent by the master device and is used to obtain the command execution result of the slave device sending the target command to the storage device under test.

[0078] Specifically, after sending a result request command from the master device to the slave device, the slave device responds to the result request command and sends the command execution result cached in the FIFO queue to the master device, completing the communication between the master device and the slave device.

[0079] In some embodiments, during the data transmission process between the master device and the slave device, the target command is encapsulated as a target command packet, wherein the checksum in the target command packet is used to verify the integrity of the corresponding data, and the checksum is determined by the sum of the remaining byte groups in the target command packet, and the remaining bytes include at least the request command code and parameters corresponding to the target command, as described above and will not be repeated here.

[0080] In this embodiment, the master device end and the slave device end perform data transmission via the SPI interface. After the master device end sends the target command to the slave device end via the SPI interface, the slave device end sends the target command to the storage device to be tested and receives the corresponding command execution result. The slave device end then sends a reply signal to notify the master device end via the GPIO pin, so that the master device end receives the reply signal and sends a result request command to the slave device end. The slave device end responds to the result request command and sends the command execution result cached in the FIFO queue to the master device end. That is, on the basis of adopting the SPI transmission protocol, the present application adds an additional GPIO pin to the master device end and the slave device end. The slave device end can send a reply signal corresponding to the target command to the master device end via the GPIO pin, so that the slave device end actively notifies the master device end, ensures the efficiency, reliability and integrity of the transmitted data, reduces the waiting time of the master device end, and improves the communication efficiency between the master device end and the slave device end.

[0081] See also Figure 5 , Figure 5 It is a flowchart of an embodiment of step S21.

[0082] like Figure 5 As shown, the following steps are included:

[0083] S211. Parse and activate a first task corresponding to the target command from the device side, and verify first data corresponding to the first task.

[0084] Among them, the target command packet corresponding to the target command may include a command packet and a data packet, each command packet has a corresponding data packet, the first task may be the command packet sent first, and the first data may be the data packet corresponding to the command packet sent first; the first data is verified, that is, verified through the checksum in the data packet, to determine whether the data of the data packet received from the device end is correct and complete.

[0085] Specifically, after receiving the target command from the device side, the target command is parsed, the parsed first task is activated, and the first data corresponding to the first task is verified.

[0086] S212: When the first data is verified to be correct, the first task enters a first state, sends the first data from the device end to the storage device under test, and obtains a first command execution result fed back by the storage device under test.

[0087] Among them, the correct first data verification means that the data received from the device end is correct and complete, the first state means that the first task enters the start processing state, and the first command execution result is the execution result of sending the first data from the device end to the storage device to be tested.

[0088] Specifically, when the first data is verified from the device side, and when the first data is verified correctly, the first task enters the start processing state, that is, the first data with correct verification is sent from the device side to the storage device to be tested, and after the storage device to be tested receives the first data, the first command execution result corresponding to the first data fed back by the storage device to be tested is received.

[0089] In some embodiments, if the first data verification error occurs, an error code is added to the command reply packet corresponding to the target command, thereby notifying the master device of the first data verification error, so that the slave device waits to receive a new command from the master device.

[0090] S213: The first task enters a second state and waits, receives second data from the device, and verifies the second data.

[0091] The second state refers to a waiting state for new commands or new data after the first task processes the first data. The new data may be second data, which is new data sent by the master device.

[0092] Specifically, after receiving the first command execution result fed back by the storage device to be tested from the slave device, the first task enters a waiting state, waiting for the second task or second data sent by the master device to the slave device; if the second data is received, the same verification steps as before are performed; if the second command is received, the data corresponding to the second command is subjected to the same verification steps as before; wherein, the data corresponding to the second command may also be the second data.

[0093] S214. When the second data is verified to be correct, the slave device sends the second data to the storage device under test, and obtains a second command execution result fed back by the storage device under test.

[0094] The correctness of the second data verification means that the new data received from the device end is correct and complete, and the second command execution result is the execution result of sending the second data from the device end to the storage device to be tested.

[0095] Specifically, when the second data is verified from the device side and if the second data is verified to be correct, the first task enters a new round of start processing state, that is, the second data with correct verification is sent from the device side to the storage device to be tested, and after the storage device to be tested receives the second data, the first task receives the second command execution result corresponding to the second data fed back by the storage device to be tested.

[0096] In some embodiments, if the second data verification error occurs, an error code is added to the command reply packet corresponding to the target command, thereby notifying the master device of the second data verification error, so that the slave device waits to receive a new command from the master device.

[0097] In some embodiments, after receiving the first command execution result from the device side, the first command execution result is cached in the FIFO queue of the SPI interface, and after receiving the second command execution result, the second command execution result is cached in the FIFO queue of the SPI interface, and the first task enters a completed state.

[0098] In this embodiment, the first task corresponding to the target command received from the device end is set to multi-state execution, so that when the master device end and the slave device end communicate, breakpoint resumption can be achieved, thereby improving data transmission efficiency.

[0099] See also Figure 6 , Figure 6 It is a structural diagram of an embodiment of a data processing system in the present application.

[0100] like Figure 6 As shown, a data processing system 300 is provided, including a master device end 310 and at least one slave device end 320, the slave device end 320 is coupled to the master device end 310, and each slave device end is coupled to a storage device to be tested.

[0101] Among them, the master device end 310 transmits the target command to the slave device end 320 through the SPI interface, so that the slave device end 320 sends the target command to the storage device under test and obtains the command execution result fed back by the storage device under test; the master device end 310 also responds to the reply signal sent by the slave device end through the GPIO pin, and sends a result request command to the slave device end 320, so that the slave device end 320 returns the command execution result.

[0102] See also Figure 7 , Figure 7 It is a structural diagram of an embodiment of an electronic device in the present application.

[0103] like Figure 7 As shown, an electronic device 400 is provided, including a processor 410 and a memory 420. The processor is coupled to the memory 420 and executes instructions when working to implement the above data processing method.

[0104] See also Figure 8 , Figure 8 It is a structural diagram of an embodiment of a computer storage medium in the present application.

[0105] like Figure 8 As shown, a computer storage medium 500 is provided, and the computer storage medium 500 stores a computer program 510, and the computer program is executed to implement the above-mentioned data processing method.

[0106] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the system implementation described above is only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0107] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0108] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0109] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program code.

[0110] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A data processing method, characterized in that: A master device end used in production testing, wherein the master device end and the slave device end perform data transmission via an SPI interface, the slave device end is coupled to a storage device to be tested, and the method comprises: The master device transmits the target command to the slave device through the SPI interface, so that the slave device sends the target command to the storage device under test and obtains the command execution result fed back by the storage device under test; The master device sends a result request command to the slave device in response to a reply signal sent by the slave device through a GPIO pin, so that the slave device returns the command execution result.

2. The method according to claim 1, characterized in that The master device transmits the target command to the slave device through the SPI interface, including: The master device encapsulates the target command according to the command packet format corresponding to the SPI interface to obtain a target command packet, and transmits the target command packet to the slave device through the SPI interface.

3. The method according to claim 1, characterized in that The master device sends a result request command to the slave device in response to a reply signal sent by the slave device through a GPIO pin, so that the slave device returns the command execution result, including: In response to the voltage of the reply signal sent through the GPIO pin being higher than a preset voltage, the master device sends a result request command to the slave device through the SPI interface, so that the slave device returns the command execution result.

4. A data processing method, characterized in that: A slave device end used in production testing, wherein the slave device end and the master device end perform data transmission via an SPI interface, the slave device end is coupled to a storage device to be tested, and the method comprises: The slave device receives the target command sent by the master device through the SPI interface, sends the target command to the storage device under test, and obtains the command execution result fed back by the storage device under test; The slave device sends a reply signal corresponding to the target command to the master device through a GPIO pin, so that the master device sends a result request command to the slave device; The slave device sends the command execution result to the master device in response to the result structure command.

5. The method according to claim 4, characterized in that The slave device receives the target command sent by the master device through the SPI interface, sends the target command to the storage device under test, and obtains the command execution result fed back by the storage device under test, including: The slave device parses and activates a first task corresponding to the target command, and verifies first data corresponding to the first task; When the first data is verified to be correct, the first task enters a first state, the slave device sends the first data to the storage device under test, and obtains a first command execution result fed back by the storage device under test; The first task enters a second state and waits, and the slave device receives second data and verifies the second data; When the second data is verified to be correct, the slave device sends the second data to the storage device under test, and obtains a second command execution result fed back by the storage device under test.

6. The method according to claim 4, characterized in that The slave device sends a reply signal corresponding to the target command to the master device through a GPIO pin, including: The slave device caches the command execution result in the FIFO queue of the SPI interface, and pulls up the voltage of the GPIO pin to form the reply signal.

7. The method according to claim 4, characterized in that During the data transmission process, the target command is encapsulated as a target command packet, wherein the checksum in the target command packet is used to verify data integrity, and the checksum is determined by the sum of the remaining byte groups in the target command packet, and the remaining bytes include at least the request command code and parameters corresponding to the target command.

8. A data processing system, characterized in that: include: Main device side; At least one slave device end, the slave device end is coupled to the master device end, and each of the slave device ends is coupled to a storage device to be tested; Among them, the master device transmits the target command to the slave device through the SPI interface, so that the slave device sends the target command to the storage device under test and obtains the command execution result fed back by the storage device under test; the master device also responds to the reply signal sent by the slave device through the GPIO pin, sends a result request command to the slave device, so that the slave device returns the command execution result.

9. An electronic device, characterized in that: The invention comprises a processor and a memory, wherein the processor is coupled to the memory and executes instructions when working to implement the data processing method according to any one of claims 1 to 7.

10. A computer storage medium, characterized in that: The computer storage medium stores a computer program, and the computer program is executed to implement the data processing method according to any one of claims 1 to 7.

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