USB host chip based on PCIe interface

Abstract

The invention provides a USB (Universal Serial Bus) host chip based on a PCIe (Peripheral Component Interconnect Express) interface, which comprises a PCIe subsystem used for realizing data transmission between an upstream root complex and a USB subsystem; the USB subsystem is used for receiving data transmission between downstream USB equipment and the PCIe subsystem; the configuration management subsystem is used for completing initial configuration of the PCIe subsystem and the USB subsystem, polling and monitoring abnormal events generated by the PCIe subsystem and the USB subsystem and processing the abnormal events; wherein the PCIe subsystem and the USB subsystem are connected through an AXI bus bridge formed by two pairs of master-slave structures, and the two AXI bus bridges are respectively used for transmitting control information flow and data information flow. According to the USB host chip provided by the invention, the PCIe controller and the USB host controller are directly connected through the AXI interface, so that the transmission delay is smaller, the scale of a logic circuit is reduced, and the die area of the chip is further reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a USB host chip based on a PCIe interface. Background Art

[0002] The USB (Universal Serial Bus) interface has the characteristics of plug-and-play, and the current maximum speed is up to 40G (USB4.0), and it is increasingly being adopted by high-speed mobile devices. As computer motherboard expansion devices, such high-speed mobile devices often use the popular PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) interface expansion. The PCIe interface uses an end-to-end connection method, and its link uses high-speed differential signals for data transmission. The latest PCIe6.0 version can reach 64GT / s per channel. Therefore, high-speed USB host chips based on the PCIe interface have emerged as the main control chip for computer high-speed USB expansion cards.

[0003] Most of the existing USB host chip solutions based on PCIe interface use PCIe3.0 controllers, and the single-channel rate is only 8GT / s. Multiple channels are needed to increase the bandwidth. In addition, the PCIe controller and the USB host controller are connected in a bus matrix, which has a larger transmission delay and increases the chip die (bare chip) area. In addition, in order to be compatible with old USB devices, the USB host controller in the existing related chip solutions implements a low version of the USB protocol, which increases the processing delay and die area. Summary of the invention

[0004] In view of the problems existing in the prior art, the present invention provides a USB host chip based on the PCIe interface, which realizes higher speed, lower latency and smaller die area of ​​the USB host, thereby reducing costs and improving efficiency.

[0005] The technical solution adopted by the present invention is as follows: A USB host chip based on a PCIe interface, comprising:

[0006] The PCIe subsystem is used to receive PCIe data sent by the upstream root complex, process it into payload data and then transmit it to the USB subsystem; and receive payload data transmitted by the USB subsystem, process it into PCIe data and then transmit it to the upstream root complex;

[0007] The USB subsystem is used to receive USB data sent by a downstream USB device, process it into payload data, and then transmit it to the PCIe subsystem; and receive payload data transmitted by the PCIe subsystem, process it into USB data, and then transmit it to the downstream USB device;

[0008] The configuration management subsystem is interconnected with the PCIe subsystem and the USB subsystem respectively, and is used to complete the initialization configuration of the PCIe subsystem and the USB subsystem, and to poll and monitor the abnormal events generated by the PCIe subsystem and the USB subsystem and process them;

[0009] Among them, the PCIe subsystem and the USB subsystem are connected by an AXI bus bridge composed of two pairs of master-slave structures, which are used to transmit control information flow and data information flow respectively.

[0010] As a preferred solution, the PCIe subsystem includes:

[0011] PCIe physical layer interface module, interconnected with the upstream root complex, used to implement the physical layer functions specified by the PCIe standard protocol;

[0012] The PCIe controller module is connected to the PCIe physical layer interface module and the PCIE2AXI bus interface module respectively, and is used to implement the transaction layer and data link layer functions specified in the PCIe standard protocol and the configuration space auxiliary function as a PCIe terminal device;

[0013] The PCIE2AXI bus interface module includes an AXI4 host interface and an AXI4 slave interface, which are used to connect to the USB subsystem.

[0014] As a preferred solution, the USB subsystem includes:

[0015] USB2AXI bus interface module, including AXI4 host interface and AXI4 slave interface, used to complete the connection with the PCIe subsystem;

[0016] The USB host controller module is connected to the USB physical layer interface module and the USB2AXI bus interface module respectively, and is used to implement the transaction layer, transport layer and link layer functions specified in USB3.0 and above standard protocols;

[0017] The USB physical layer interface module is interconnected with downstream USB devices to implement the physical layer functions specified in USB3.0 and above standard protocols.

[0018] As a preferred solution, the AXI4 host interface in the PCIE2AXI bus interface module is connected to the AXI4 slave interface in the USB2AXI bus interface module for transmitting control information flow; the AXI4 slave interface in the PCIE2AXI bus interface module is connected to the AXI4 host interface in the USB2AXI bus interface module for transmitting data information flow.

[0019] As a preferred solution, the configuration management subsystem includes:

[0020] The clock reset generation module is used to generate the clock and reset signals required for the operation of each module of the chip;

[0021] The top-level configuration module is used to implement the global configuration of the chip;

[0022] The built-in FLASH memory module is connected to the configuration host controller module and is used to store initialization configuration instruction information;

[0023] The configuration host controller module is used to control the power-on initialization configuration of the entire chip according to the configuration instructions, and to process the out-of-band event signals transmitted by the PCIe subsystem and the USB subsystem;

[0024] The AHB2APB bus bridge module is used to provide a bus bridge for converting an AHB interface to multiple APB interfaces; wherein the AHB interface is connected to the configuration host controller module, and the multiple APB interfaces are respectively connected to the top-level configuration module, the PCIe subsystem, and the USB subsystem.

[0025] As a preferred solution, the USB2AXI bus interface module uses an asynchronous FIFO to perform asynchronous transition on clocks of different frequencies, and inputs the generated back pressure signal to the USB host controller module to establish a back pressure mechanism.

[0026] As a preferred solution, the working process of the USB host chip includes configuring the plane information flow, which is as follows:

[0027] After the USB host chip is powered on, the configuration host controller module completes the initialization of the PCIe subsystem and the USB subsystem according to the initialization configuration instruction information stored in the embedded FLASH memory module.

[0028] As a preferred solution, the working process of the USB host chip includes controlling the information flow, which is as follows:

[0029] After the USB host chip is connected to the system host, the USB host chip acts as a PCIe terminal device, and the root complex initiates an enumeration process to discover and configure the functional specifications of the PCIe terminal device; and the system host initializes the USB host controller module based on the xHCI protocol and supports the enumeration process when the USB device is connected, which is used to discover and configure the functional specifications of the USB device.

[0030] As a preferred solution, the working process of the USB host chip includes an upstream data information flow, which is as follows:

[0031] The USB host controller module initiates a data write request to the PCIe controller module, which then drives the AXI4 host write interface of the USB2AXI bus interface module to initiate a data write request. The PCIe controller module responds to the write request through the AXI4 slave write interface of the PCIE2AXI bus interface module. The write request is passed to the upstream root complex through the PCIe protocol conversion of the PCIe controller module and the PCIe physical layer interface module. Then, driven by the driver, the system host receives the data sent by the USB device into the system memory.

[0032] As a preferred solution, the working process of the USB host chip includes the downstream data information flow, which is as follows:

[0033] The USB host controller module initiates a data read request to the PCIe controller module, which then drives the AXI4 host read interface of the USB2AXI bus interface module to initiate a data read request. The PCIe controller module responds to the above read request through the AXI4 slave read interface of the PCIE2AXI bus interface module. The read request is transmitted to the upstream root complex through the PCIe protocol conversion of the PCIe controller module and the PCIe physical layer interface module. Then, driven by the driver, the system host sends the data in the system memory to the USB device.

[0034] Compared with the prior art, the beneficial effects of adopting the above technical solution are as follows: the USB host chip proposed by the present invention can use a faster PCIe4.0 port, and the PCIe controller and the USB host controller are directly connected by an AXI interface, which reduces the transmission delay and reduces the scale of the logic circuit, thereby reducing the chip die area. In addition, the USB subsystem in the USB host chip of the present invention is tailored in terms of the supported protocols, and only supports USB3.0 / 3.1 / 3.2, so that the USB host is faster, has lower latency, and has a smaller die area, thereby reducing costs and improving efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1This is a schematic diagram of a USB host chip based on a PCIe interface proposed in an embodiment of the present invention.

[0036] Figure 2 A USB host chip initialization flow chart is provided for an embodiment of the present invention.

[0037] Figure 3 A USB host chip upstream workflow diagram is provided for an embodiment of the present invention.

[0038] Figure 4 A USB host chip downstream workflow diagram is provided for an embodiment of the present invention. DETAILED DESCRIPTION

[0039] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar modules or modules with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be construed as limitations on the present application. On the contrary, the embodiments of the present application include all changes, modifications and equivalents that fall within the spirit and connotation of the appended claims.

[0040] In order to overcome the problems of transmission delay and large die area in the prior art, the embodiment of the present invention proposes a USB host chip based on the PCIe interface, please refer to Figure 1 The USB host chip includes a PCIe subsystem, a USB subsystem and a configuration management subsystem. Specifically, the PCIe subsystem is used to receive PCIe data sent by an upstream root complex, and transmit the data to the USB subsystem after processing into payload data; and receive payload data transmitted by the USB subsystem, and transmit the data to the upstream root complex after processing into PCIe data; the USB subsystem is used to receive USB data sent by a downstream USB device, and transmit the data to the PCIe subsystem after processing into payload data; and receive payload data transmitted by the PCIe subsystem, and transmit the data to the downstream USB device after processing into USB data; the configuration management subsystem is interconnected with the PCIe subsystem and the USB subsystem respectively, and is used to complete the initialization configuration of the PCIe subsystem and the USB subsystem, and to poll and monitor the abnormal events generated by the PCIe subsystem and the USB subsystem and process them.

[0041] In this embodiment, the PCIe subsystem and the USB subsystem are connected by an AXI bus bridge consisting of two pairs of master-slave structures, which are used to transmit control information flow and data information flow respectively. The PCIe subsystem and the USB subsystem are directly connected by an AXI interface, which has a smaller transmission delay and reduces the scale of the logic circuit. The USB host chip mainly implements a high-speed USB host high-speed interface expansion chip and an attached physical layer port to achieve a one-to-one connection. Its application side is connected to a high-speed PCIe controller and an attached physical layer port, and is widely used in fields that require high-speed data interfaces, such as high-speed mobile hard disks, ultra-high-definition camera equipment, and VR equipment.

[0042] Please continue to refer to Figure 1 , the PCIe subsystem mainly includes a PCIe controller module, a PCIe physical layer interface module and a PCIE2AXI bus interface module. Among them, the PCIe physical layer interface module is mainly used to interconnect with the upstream root complex to realize the physical layer functions specified by the PCIe standard protocol, including the encapsulation and disassembly of physical layer messages, line encoding and decoding, scrambling and descrambling, signal equalization and other processing. In one embodiment, the PCIe physical layer module specification is a single Lane (i.e. x1). The PCIe controller module is connected to the PCIe physical layer interface module and the PCIE2AXI bus interface module respectively, and is used to realize the transaction layer and data link layer functions specified by the PCIe standard protocol, as well as the auxiliary functions such as the configuration space of the PCIe terminal device. The PCIE2AXI bus interface module includes an AXI host interface and an AXI slave interface, which transmit the control information flow and data information flow of the chip respectively, thereby completing the docking of the PCIe subsystem and the USB subsystem.

[0043] In this embodiment, the PCIe controller module and PCIe physical layer interface module of the PCIe subsystem mainly support the PCIe4.0 standard protocol and are backward compatible with PCIe3.0 / 2.0 / 1.0, with a maximum rate of 16G. In one embodiment, the PCIe controller module and the PCIe physical layer interface module are connected via a standard PIPE interface, and the data bit width is 128 bits.

[0044] Please continue to refer to Figure 1The USB subsystem includes a USB host controller module, a USB physical layer interface module and a USB2AXI bus interface module. Among them, the USB host controller module is connected to the USB physical layer interface module and the USB2AXI bus interface module to implement the transaction layer, transport layer and link layer functions specified in the USB standard protocol. The USB physical layer interface module is interconnected with the downstream USB device to implement the physical layer functions specified in the USB standard protocol, mainly including the encapsulation and disassembly of physical layer messages, line encoding and decoding, code synchronization alignment and other processing. In one embodiment, the USB physical layer interface module has a specification of 2 Lanes (i.e. x2), and the x1 and x2 modes are configurable. The USB2AXI bus interface module includes an AXI4 host interface and an AXI4 slave interface, which transmit the data information flow and control information flow of the chip respectively, thereby completing the docking of the USB subsystem and the PCIe subsystem.

[0045] In this embodiment, the USB host controller module and the USB physical layer interface module of the USB subsystem support USB3.2, and are backward compatible with USB3.1 / 3.0, but do not support USB2.0 / 1.0, with a maximum rate of 20G. By tailoring the supported USB protocols, the USB host chip can be made faster, with lower latency and a smaller die area. In one embodiment, the USB host controller module and the USB physical layer interface module are connected via a standard PIPE interface, and the data bit width is 64 bits.

[0046] Furthermore, the PCIe subsystem and the USB subsystem are connected by an AXI bus bridge consisting of two pairs of master-slave structures, which are used to transmit control information flow and data information flow respectively. Specifically, the AXI4 host interface in the PCIE2AXI bus interface module is connected to the AXI4 slave interface in the USB2AXI bus interface module for transmitting control information flow; the AXI4 slave interface in the PCIE2AXI bus interface module is connected to the AXI4 host interface in the USB2AXI bus interface module for transmitting data information flow. By adopting the connection method proposed in this embodiment, the connection rate index between the USB subsystem and the PCIe subsystem can reach up to 20G.

[0047] In this embodiment, in a USB host chip, a PCIe subsystem and a USB subsystem are directly connected via an AXI bus, forming a data transmission path between an upstream root complex and a downstream USB device, which can effectively improve the data transmission rate. The USB host chip also includes a configuration management subsystem for completing the configuration of the USB host chip.

[0048] Please continue to refer to Figure 1, the configuration management subsystem includes a configuration host controller module, a clock reset generation module, a top-level configuration module and an embedded FLASH memory module. Specifically, the clock reset generation module is used to generate the clock and reset signals required for the operation of each module of the chip. The top-level configuration module, as the global configuration register module of the entire chip, has an APB (Advanced Peripheral Bus) interface. The embedded FLASH memory module is connected to the configuration host controller module and is used to store initialization configuration instruction information, and has an AHB (Advanced High-performance Bus) interface. The configuration host controller module, in this embodiment, uses an AHB host controller that can execute custom configuration instructions to control the power-on initialization configuration of the entire chip according to the configuration instructions, and to process out-of-band event signals transmitted from the PCIe subsystem and the USB subsystem. In order to realize the interconnection between the configuration host control module and other modules, an AHB2APB bus bridge module is also proposed in this embodiment, which is used to provide a bus bridge for converting an AHB interface to multiple APB interfaces; wherein the AHB interface is connected to the configuration host controller module, and multiple APB interfaces are respectively connected to the top-level configuration module, the PCIe subsystem and the USB subsystem.

[0049] In the connection between the AHB2APB bus bridge module and the PCIe subsystem and the USB subsystem, the PCIe controller module, the PCIe physical layer interface module, the USB host controller module, and the USB physical layer interface module each provide an APB slave interface, which is connected to the APB interface port output by the AHB2APB bus bridge module to receive the configuration sent by the configuration host controller module. In this embodiment, the configuration host controller module accesses each module with an APB / AHB interface and an embedded FLASH memory module according to the set address. Table 1 gives an address encoding example.

[0050] Table 1 Address code

[0051] Module Name Base Address Address size Embedded FLASH memory module 0x20000000 64K Top-level configuration module 0x40000000 4K PCIe controller module 0x50000000 64K PCIe physical layer interface module 0x51000000 8K USB Host Controller Module 0x52000000 64K USB physical layer interface module 0x53000000 8K

[0052] In one embodiment, the PCIe subsystem and the USB subsystem can be connected to the configuration host controller module through an out-of-band parallel event signal interface. When the out-of-band event signal is valid, the configuration host controller module executes the corresponding event processing routine to ensure the normal operation of the USB host chip.

[0053] In one embodiment, after the USB host chip is powered on and reset, the clock reset generation module outputs a 100M AHB clock for driving the configuration host controller module and each AHB interface after multiplication / division by the internal PLL (PhaseLocked Loop) based on the 100M reference clock input by the pin, a 50M APB clock for driving the APB interface of each module, a 125M clock for driving the PCIe controller module, a 156.25M clock for driving the USB host controller module, and a 100M reference clock for the PCIe physical layer interface module and the USB physical layer interface module respectively.

[0054] In the USB subsystem, the USB2AXI bus interface module uses an asynchronous FIFO to perform asynchronous transitions on clocks of different frequencies, and inputs the generated back-pressure signal to the USB host controller module to establish a back-pressure mechanism.

[0055] In one embodiment, the configuration management subsystem further includes a JTAG interface module as a test and debugging interface for the entire chip.

[0056] Generally, the USB host chip proposed in this embodiment acts as a PCIe terminal device in the entire computing system, with its upstream involving the PCIe root complex, system host and system content, and its downstream connecting USB devices. For ease of description, in the subsequent process, the direction of data from the root complex to the USB host chip is called the downstream direction, and the direction of data from the USB host chip to the root complex is called the upstream direction. The following is a further explanation of the data information flow / control information flow involved in the working process of the USB host chip, including the configuration plane information flow, control information flow, upstream data information flow and downstream data information flow. Specifically:

[0057] For the configuration plane information flow, after the USB host chip is powered on, the internal modules of the USB subsystem and PCIe subsystem need to be initialized and configured before they can work. Therefore, the host controller module needs to be configured to complete the initialization configuration of the PCIe subsystem and the USB subsystem according to the initialization configuration instruction information stored in the embedded FLASH memory module. For corresponding, please refer to Figure 2 , this embodiment also provides a specific initialization process:

[0058] Step 101: After the chip is powered on and reset, the configuration management subsystem is reset and evacuated, and the configuration host controller module starts to read the configuration instructions in the embedded FLASH memory module and run them.

[0059] Step 102: configure the host controller module to execute instructions to configure the PCIe subsystem to reset and evacuate.

[0060] Step 103: configure the host controller module to execute instructions to configure the USB subsystem to reset and evacuate.

[0061] Step 104, configure the host controller module to execute instructions to configure the PCIe subsystem initialization. In this embodiment, the PCIe subsystem initialization includes: PCIe physical layer interface module parameter initialization configuration; PCIe controller module configuration space, global parameter initialization configuration; PCIe link training enable configuration; after initialization, the PCIe interface of the USB host chip is in normal working state.

[0062] Step 105, configure the host controller module to execute the instruction to configure the USB subsystem initialization. In this embodiment, the USB subsystem initialization includes: USB physical layer interface module parameter initialization configuration; USB host controller module global parameter initialization configuration; after initialization, the USB interface of the USB host chip is in normal working state.

[0063] Step 106: After configuring the host controller module to execute the initialization instruction, poll and monitor the generation and processing of abnormal events of the PCIe subsystem and the USB subsystem.

[0064] In this embodiment, the abnormal events generated by the PCIe subsystem mainly include PCIe link offline and PCIe link serious errors. After the abnormal event occurs, the host controller module is configured to reset the PCIe subsystem or clear the serious error alarm state according to the corresponding event processing routine. Similarly, the abnormal events generated by the USB subsystem mainly include USB host abnormal shutdown and USB link fatal errors. After the abnormal event occurs, the host controller module is configured to reset the USB subsystem or clear the fatal error state according to the corresponding event processing routine.

[0065] For the control information flow, since the USB host chip acts as a PCIe terminal device in the entire computer system, the root complex will initiate an enumeration process driven by the driver running on the system host to discover and configure the functional specifications of the PCIe terminal device. At the same time, the driver supports the standard eXtensible Host Controller Interface (xHCI) protocol. The system host will initialize the USB host controller module based on the xHCI protocol and support the enumeration process when the USB device is connected, which is used to discover and configure the functional specifications of the USB device. In this process, the channel formed by connecting the AXI4 host interface in the PCIE2AXI bus interface module and the AXI4 slave interface in the USB2AXI bus interface module is used to transmit the control information flow.

[0066] For the upstream data information flow, the USB host controller module, driven by the driver running on the system host, initiates a write data request to the PCIe controller module, which then drives the AXI4 host write interface of the USB2AXI bus interface module to initiate a write data request. The PCIe controller module responds to the above write request through the AXI4 slave write interface of the PCIE2AXI bus interface module. The write request is passed to the upstream root complex through the PCIe protocol conversion of the PCIe controller module and the PCIe physical layer interface module. Then, driven by the driver, the system host receives the data sent by the USB device into the system memory along the upstream path. Please refer to Figure 3 In this embodiment, the specific upstream working process of the USB host chip is given, which is as follows:

[0067] Step 201: A USB device downstream of a USB host chip sends a data packet to a USB physical layer interface module. It should be noted that the data packet sent by the USB device refers to a transfer packet defined by the USB protocol, including a control transfer packet, a bulk transfer packet, an interrupt transfer packet, and a synchronous transfer packet.

[0068] Step 202: After receiving the data packet through the USB physical layer interface module, the USB host control module decapsulates, analyzes and processes the data packet layer by layer according to the protocol, which mainly implements the protocol layer and data link layer functions in the USB standard protocol.

[0069] Step 203, the USB host controller module sends the processed transmission packet payload data to the PCIe host controller module through the USB2AXI interface module. When sending data, the AXI4 host interface in the USB2AXI interface module sends the transmission packet payload data to the AXI4 slave interface of the PCIE2AXI bus interface module in a request-initiating manner, and then sends it to the PCIe controller module.

[0070] Step 204: The PCIe controller module performs PCIe transaction layer packet conversion processing on the received transaction layer packet payload data. In this process, PCIe protocol conversion is mainly performed, and the payload data is encapsulated into a PCIe transaction layer packet and then sent to the PCIe physical layer interface module.

[0071] Step 205: After receiving the PCIe transaction layer packet, the PCIe physical layer interface module performs physical layer packet encapsulation, encoding and other processing, and then sends it to the upstream root complex.

[0072] For the downstream data information flow, driven by the driver running on the system host, the USB host controller module initiates a read data request to the PCIe controller module, which then drives the AXI4 host read interface of the USB2AXI bus interface module to initiate a read data request. The PCIe controller module responds to the above read request through the AXI4 slave read interface of the PCIE2AXI bus interface module. The read request is passed to the upstream root complex through the PCIe protocol conversion of the PCIe controller module and the PCIe physical layer interface module. Then, driven by the driver, the system host sends the data in the system memory to the USB device along the downstream path. Please refer to Figure 4 In this embodiment, the specific downstream workflow of the USB host chip is given, which is as follows:

[0073] Step 301: The root complex upstream of the USB host chip sends a data packet to the PCIe physical layer interface module. It should be noted that the data packet sent by the root complex refers to the transaction layer packet defined by the PCIe protocol, including memory space, input and output space, configuration space access request transaction layer packets and messages.

[0074] Step 302: The PCIe controller module receives the data packet through the PCIe physical layer interface module and decapsulates, analyzes, and processes it layer by layer according to the protocol. In this step, the PCIe controller module mainly completes the transaction layer and data link layer functions in the standard protocol layer. The processing actions are divided into the following two categories according to the transaction packet type: the memory space and input and output space access request transaction layer packet and the message transaction layer packet will be converted into an AXI transaction packet and sent to the USB subsystem; the configuration space access request transaction layer packet will be converted into an access to the internal configuration space of the PCIe controller module.

[0075] Step 303: The PCIe controller module sends the processed transaction layer packet payload data to the USB host controller module through the PCIE2AXI interface module.

[0076] In this embodiment, when sending data, the AXI4 slave interface of the PCIE2AXI bus interface module sends the transaction layer packet payload data to the AXI4 host interface of the USB2AXI bus interface module in response to the request, and then sends it to the USB host controller module.

[0077] Step 304: The USB host controller module converts the received transaction layer packet payload data into a USB transmission packet. In this step, the USB host controller mainly performs USB protocol conversion, encapsulates the payload data into a USB transmission packet, and then sends it to the USB physical layer interface module; wherein the USB transmission packet types include control transmission packets, bulk transmission packets, interrupt transmission packets, and synchronous transmission packets.

[0078] Step 305: After receiving the USB transmission packet, the USB physical layer interface module performs physical layer packet encapsulation, encoding and other processing, and then sends it to the downstream USB device.

[0079] The USB host chip proposed in the embodiment of the present invention supports a faster PCIe4.0 port. The PCIe controller and the USB host controller are directly connected using an AXI interface, which reduces the transmission delay and reduces the scale of the logic circuit, thereby reducing the chip die area. At the same time, the USB subsystem in the USB host chip is tailored in terms of the supported protocols, and only supports USB3.0 / 3.1 / 3.2. The implemented USB host chip has a higher speed, lower latency, and a smaller die area, which can effectively reduce costs and improve efficiency.

[0080] For those skilled in the art, the specific meanings of the above terms in the present invention can be understood in specific situations; the drawings in the embodiments are used to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0081] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A USB host chip based on PCIe interface, characterized in that: include: The PCIe subsystem is used to receive PCIe data sent by the upstream root complex, process it into payload data, and then transmit it to the USB subsystem; and receiving the payload data transmitted by the USB subsystem, processing it into PCIe data and sending it to the upstream root complex; The USB subsystem is used to receive USB data sent by the downstream USB device, process it into payload data, and then transmit it to the PCIe subsystem; and receiving the payload data transmitted by the PCIe subsystem, processing it into USB data and sending it to the downstream USB device; The configuration management subsystem is interconnected with the PCIe subsystem and the USB subsystem respectively, and is used to complete the initialization configuration of the PCIe subsystem and the USB subsystem, and to poll and monitor the abnormal events generated by the PCIe subsystem and the USB subsystem and process them; Among them, the PCIe subsystem and the USB subsystem are connected by an AXI bus bridge composed of two pairs of master-slave structures, which are used to transmit control information flow and data information flow respectively.

2. The USB host chip based on PCIe interface according to claim 1, characterized in that: The PCIe subsystem includes: PCIe physical layer interface module, used to interconnect with the upstream root complex and implement the physical layer functions specified by the PCIe standard protocol; The PCIe controller module is connected to the PCIe physical layer interface module and the PCIE2AXI bus interface module respectively, and is used to implement the transaction layer and data link layer functions specified in the PCIe standard protocol and the configuration space auxiliary function as a PCIe terminal device; The PCIE2AXI bus interface module includes an AXI4 host interface and an AXI4 slave interface, which are used to connect to the USB subsystem.

3. The USB host chip based on PCIe interface according to claim 2, characterized in that: The USB subsystem includes: USB2AXI bus interface module, including AXI4 host interface and AXI4 slave interface, used to complete the connection with the PCIe subsystem; The USB host controller module is connected to the USB physical layer interface module and the USB2AXI bus interface module respectively, and is used to implement the transaction layer, transport layer and link layer functions specified in the USB3.0 and above standard protocols; The USB physical layer interface module is used to interconnect with downstream USB devices and implement the physical layer functions specified by USB3.0 and above standard protocols.

4. The USB host chip based on PCIe interface according to claim 3, characterized in that: The AXI4 host interface in the PCIE2AXI bus interface module is connected to the AXI4 slave interface in the USB2AXI bus interface module for transmitting control information flow; the AXI4 slave interface in the PCIE2AXI bus interface module is connected to the AXI4 host interface in the USB2AXI bus interface module for transmitting data information flow.

5. The USB host chip based on PCIe interface according to claim 1, characterized in that: The configuration management subsystem includes: The clock reset generation module is used to generate the clock and reset signals required for the operation of each module of the chip; The top-level configuration module is used to implement the global configuration of the chip; The built-in FLASH memory module is connected to the configuration host controller module and is used to store initialization configuration instruction information; The configuration host controller module is used to control the power-on initialization configuration of the entire chip according to the configuration instructions, and to process the out-of-band event signals transmitted by the PCIe subsystem and the USB subsystem; The AHB2APB bus bridge module is used to provide a bus bridge for converting an AHB interface to multiple APB interfaces; wherein the AHB interface is connected to the configuration host controller module, and the multiple APB interfaces are respectively connected to the top-level configuration module, the PCIe subsystem, and the USB subsystem.

6. The USB host chip based on PCIe interface according to claim 3 or 4, characterized in that: The USB2AXI bus interface module uses an asynchronous FIFO to perform asynchronous transition on clocks of different frequencies, and inputs the generated back pressure signal to the USB host controller module to establish a back pressure mechanism.

7. The USB host chip based on PCIe interface according to claim 5, characterized in that: The working process of the USB host chip includes configuration plane information flow, which is as follows: After the USB host chip is powered on, the configuration host controller module completes the initialization of the PCIe subsystem and the USB subsystem according to the initialization configuration instruction information stored in the embedded FLASH memory module.

8. The USB host chip based on PCIe interface according to claim 1, characterized in that: The working process of the USB host chip includes controlling the information flow, which is as follows: After the USB host chip is connected to the system host, the USB host chip acts as a PCIe terminal device, and the root complex initiates an enumeration process to discover and configure the functional specifications of the PCIe terminal device; The system host initializes the USB host controller module based on the xHCI protocol and supports the enumeration process when the USB device is connected, which is used to discover and configure the functional specifications of the USB device.

9. The USB host chip based on PCIe interface according to claim 3 or 4, characterized in that: The working process of the USB host chip includes the upstream data information flow, which is as follows: The USB host controller module initiates a data write request to the PCIe controller module, which then drives the AXI4 host write interface of the USB2AXI bus interface module to initiate a data write request. The PCIe controller module responds to the write request through the AXI4 slave write interface of the PCIE2AXI bus interface module. The write request is passed to the upstream root complex through the PCIe protocol conversion of the PCIe controller module and the PCIe physical layer interface module. Then, driven by the driver, the system host receives the data sent by the USB device into the system memory.

10. The USB host chip based on PCIe interface according to claim 3 or 4, characterized in that: The working process of the USB host chip includes the downstream data information flow, which is as follows: The USB host controller module initiates a data read request to the PCIe controller module, which then drives the AXI4 host read interface of the USB2AXI bus interface module to initiate a data read request. The PCIe controller module responds to the above read request through the AXI4 slave read interface of the PCIE2AXI bus interface module. The read request is transmitted to the upstream root complex through the PCIe protocol conversion of the PCIe controller module and the PCIe physical layer interface module. Then, driven by the driver, the system host sends the data in the system memory to the USB device.

Images