Device simulation method for integrated circuit

Abstract

The invention relates to the technical field of circuit data processing, in particular to a device simulation method for an integrated circuit. The method comprises the following steps: acquiring integrated circuit device data, and generating a device main feature matrix through multi-dimensional topological feature extraction and redundant feature elimination; performing hierarchical analysis on the main feature matrix of the device, generating a device hierarchical embedding graph matrix, and determining a device hierarchical structure through hierarchical clustering of a module graph theory; predicting a potential element link probability in the main feature matrix of the device, and carrying out topology analysis to generate an element link relationship; based on the device hierarchical structure and the element link relationship, constructing a device unit, and generating a simulation circuit device unit; performing circuit integration simulation on the simulation circuit device unit, performing defect optimization in combination with the data of the integrated circuit device, and finally obtaining the optimized data of the integrated circuit device; according to the invention, a more accurate and more reliable device simulation method for an integrated circuit can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit data processing, and in particular to a device simulation method for integrated circuits. Background Art

[0002] The development of device simulation methods for integrated circuits has gone through multiple stages, each of which is accompanied by specific challenges and defects. The initial stage was the classic manual design stage, where designers mainly relied on manual design and analysis, which resulted in long design cycles, high costs, and difficulty in coping with growing complexity. With the advancement of computer technology, the model building stage based on analog calculations emerged, and designers began to use numerical simulation and simulation techniques to build mathematical models of circuit devices. However, these models have accuracy limitations, especially when dealing with complex devices, and consume a lot of computing resources. Subsequently, the simulation model stage based on physical principles introduced more physical principles, such as quantum mechanics and semiconductor physics, to build more accurate device models. Although these models are more accurate, they also require more computing resources and high accuracy requirements for model parameters. Recently, with the development of machine learning and artificial intelligence technologies, these technologies have been applied to device simulation to improve the accuracy and efficiency of device simulation by training models. However, this approach requires a large amount of data for training and raises issues of model interpretability and credibility. Summary of the invention

[0003] Based on this, it is necessary to provide a device simulation method for integrated circuits to solve at least one of the above technical problems.

[0004] To achieve the above object, a device simulation method for an integrated circuit comprises the following steps:

[0005] Step S1: obtaining integrated circuit device data; extracting multi-dimensional topological features from the integrated circuit device data, and removing redundant features to generate a device main feature matrix;

[0006] Step S2: performing embedding hierarchical analysis on the device main feature matrix to generate a device hierarchical embedding graph matrix; performing module graph hierarchical clustering on the device hierarchical embedding graph matrix to generate a device hierarchical structure;

[0007] Step S3: predicting the potential component link probability of the device main feature matrix, and performing component link relationship topology analysis to generate component link relationships;

[0008] Step S4: constructing device units for the device main feature matrix based on the device hierarchy and component link relationship to generate simulation circuit device units;

[0009] Step S5: Perform circuit integration simulation on the simulation circuit device unit according to the integrated circuit device data, and optimize defective devices to obtain optimized integrated circuit device data.

[0010] The present invention ensures that the device main feature matrix retains only the most relevant and representative features through multi-dimensional topological feature extraction and redundant feature elimination. This not only reduces the data dimension and computational complexity, but also improves the accuracy and efficiency of subsequent analysis. By using embedded hierarchical analysis and module graph hierarchical clustering, the device hierarchy is automatically generated, providing an in-depth understanding of the device function and connection relationship. This automated method can more accurately identify the hierarchy and module division of the device, reducing manual intervention and potential errors. Through potential component link probability prediction and topological analysis, a data-driven component link relationship is generated. This method not only improves the prediction accuracy of the link relationship, but also allows the identification of potential connection patterns and interactions in complex circuits. The device main feature matrix is ​​constructed in units in combination with the device hierarchy and component link relationship to generate a simulation circuit device unit. This method ensures that the construction of the device unit more accurately reflects the actual structure and function of the device, thereby improving the authenticity and reliability of the simulation circuit. Circuit integration simulation is performed based on the simulation circuit device unit, and combined with defective device optimization. This method not only simulates the actual situation during the circuit integration process, but also automatically optimizes the defective device, thereby improving the overall performance and reliability of the integrated circuit. Through precise feature extraction and redundancy elimination, the data quality and computational efficiency are optimized. Manual operations and potential subjectivity are reduced, and the accuracy and consistency of analysis are improved. Complex component link relationships and connection patterns are more accurately identified. More realistic and reliable simulation circuit device units are generated. The performance and reliability of integrated circuits in practical applications are improved. This method has significant advantages in integrated circuit design and optimization, and can better cope with the design and optimization challenges of complex circuits compared to traditional technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic flow chart of steps of a device simulation method for an integrated circuit;

[0012] Figure 2 for Figure 1 Detailed implementation steps of step S2 in the flowchart;

[0013] Figure 3 for Figure 1 Detailed implementation steps of step S3 in FIG.

[0014] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0015] The technical method of the present invention is described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by technicians in this field without creative work are within the scope of protection of the present invention.

[0016] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor methods and / or microcontroller methods.

[0017] It should be understood that, although the terms "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are used only to distinguish one unit from another unit. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed associated items.

[0018] To achieve this, please refer to Figures 1 to 3 , a device simulation method for an integrated circuit, comprising the following steps:

[0019] Step S1: obtaining integrated circuit device data; extracting multi-dimensional topological features from the integrated circuit device data, and removing redundant features to generate a device main feature matrix;

[0020] Step S2: performing embedding hierarchical analysis on the device main feature matrix to generate a device hierarchical embedding graph matrix; performing module graph hierarchical clustering on the device hierarchical embedding graph matrix to generate a device hierarchical structure;

[0021] Step S3: predicting the potential component link probability of the device main feature matrix, and performing component link relationship topology analysis to generate component link relationships;

[0022] Step S4: constructing device units for the device main feature matrix based on the device hierarchy and component link relationship to generate simulation circuit device units;

[0023] Step S5: Perform circuit integration simulation on the simulation circuit device unit according to the integrated circuit device data, and optimize defective devices to obtain optimized integrated circuit device data.

[0024] The present invention ensures that the device main feature matrix retains only the most relevant and representative features through multi-dimensional topological feature extraction and redundant feature elimination. This not only reduces the data dimension and computational complexity, but also improves the accuracy and efficiency of subsequent analysis. By using embedded hierarchical analysis and module graph hierarchical clustering, the device hierarchy is automatically generated, providing an in-depth understanding of the device function and connection relationship. This automated method can more accurately identify the hierarchy and module division of the device, reducing manual intervention and potential errors. Through potential component link probability prediction and topological analysis, a data-driven component link relationship is generated. This method not only improves the prediction accuracy of the link relationship, but also allows the identification of potential connection patterns and interactions in complex circuits. The device main feature matrix is ​​constructed in units in combination with the device hierarchy and component link relationship to generate a simulation circuit device unit. This method ensures that the construction of the device unit more accurately reflects the actual structure and function of the device, thereby improving the authenticity and reliability of the simulation circuit. Circuit integration simulation is performed based on the simulation circuit device unit, and combined with defective device optimization. This method not only simulates the actual situation during the circuit integration process, but also automatically optimizes the defective device, thereby improving the overall performance and reliability of the integrated circuit. Through precise feature extraction and redundancy elimination, the data quality and computational efficiency are optimized. Manual operations and potential subjectivity are reduced, and the accuracy and consistency of analysis are improved. Complex component link relationships and connection patterns are more accurately identified. More realistic and reliable simulation circuit device units are generated. The performance and reliability of integrated circuits in practical applications are improved. This method has significant advantages in integrated circuit design and optimization, and can better cope with the design and optimization challenges of complex circuits compared to traditional technologies.

[0025] In the embodiment of the present invention, reference Figure 1 The above is a schematic flow chart of the steps of the device simulation method for integrated circuits of the present invention. In this example, the device simulation method for integrated circuits includes the following steps:

[0026] Step S1: obtaining integrated circuit device data; extracting multi-dimensional topological features from the integrated circuit device data, and removing redundant features to generate a device main feature matrix;

[0027] In an embodiment of the present invention, data of integrated circuit devices are extracted from an integrated circuit design database or design file. These data generally include the geometric layout of the device, electrical connection information, material properties and electrical performance. In order to extract the multidimensional topological features of the device, advanced data analysis tools, such as the Pandas library and the NumPy library in Python, are used to process and transform the data. Specific operations include calculating the edge, node and surface geometric features of the device and extracting the complexity index of the electrical connection. In the multidimensional feature extraction process, principal component analysis (PCA) or other dimensionality reduction techniques are applied to eliminate redundant features. The generated device main feature matrix must meet the following requirements: each row of the matrix represents a device, and each column represents an extracted feature. Through feature selection techniques, such as variance-based feature selection methods, it is ensured that only the most representative features are retained in the matrix to reduce data redundancy and improve the efficiency of subsequent analysis.

[0028] Step S2: performing embedding hierarchical analysis on the device main feature matrix to generate a device hierarchical embedding graph matrix; performing module graph hierarchical clustering on the device hierarchical embedding graph matrix to generate a device hierarchical structure;

[0029] In an embodiment of the present invention, the obtained device main feature matrix is ​​embedded in a hierarchical analysis, and the feature matrix is ​​mapped to a low-dimensional space using graph embedding technology to generate a device hierarchical embedding graph matrix. This process can be implemented with the help of a graph neural network (GNN) model, taking advantage of its ability to capture graph structure information. The generated graph matrix reflects the hierarchical relationship between devices. In graph theory analysis, modular graph theory techniques, such as the Louvain method or spectral clustering, are applied to perform modular clustering on the graph matrix. In specific implementation, the modularity of each module is calculated, and the modules are optimized to generate a hierarchical structure of the device. This structure describes the hierarchical relationship and module division of the device in the design.

[0030] Step S3: predicting the potential component link probability of the device main feature matrix, and performing component link relationship topology analysis to generate component link relationships;

[0031] In an embodiment of the present invention, the main feature matrix of the device is used to predict the probability of potential component links, and a statistical model or machine learning algorithm, such as a Bayesian network or a deep learning model, is used to predict the connection relationship between different devices. This step uses the data in the feature matrix to calculate the connection probability between each pair of devices. In the link relationship topology analysis, a component link relationship diagram is constructed, and the algorithms in graph theory, such as the Kruskal algorithm or the Prim algorithm, are used to perform topological optimization on the device connections to generate the final component link relationship. Ensure that all connections are accurately predicted, and the generated topology diagram can accurately represent the connection and strength of each component.

[0032] Step S4: constructing device units for the device main feature matrix based on the device hierarchy and component link relationship to generate simulation circuit device units;

[0033] In the embodiment of the present invention, the device unit is constructed for the device main feature matrix based on the device hierarchy and the link relationship of the components. This process first organizes the device feature matrix according to the hierarchy and link relationship of the device to construct the device unit of the simulation circuit. The simulation is performed using circuit simulation tools such as SPICE or Cadence, and the functions and behaviors of the circuit units are defined by these tools. During the simulation process, the device is functionally verified and the performance is analyzed to generate a simulation circuit device unit. The unit should be able to reflect the electrical behavior and connection characteristics of the actual circuit.

[0034] Step S5: Perform circuit integration simulation on the simulation circuit device unit according to the integrated circuit device data, and optimize defective devices to obtain optimized integrated circuit device data.

[0035] In an embodiment of the present invention, the generated simulation circuit device unit is subjected to circuit integration simulation, and the integrated circuit behavior analysis is performed using circuit simulation software. During the simulation process, defects that will appear in the circuit are detected, and their impact on the overall circuit performance is analyzed. For the identified defects, the design is optimized, the device parameters are adjusted, or the circuit layout is modified to improve the performance. The optimization process can use automated tools based on genetic algorithms or particle swarm optimization algorithms to ensure that the circuit performance meets the design requirements. Ultimately, the optimized integrated circuit device data will be reflected in the optimized circuit design to ensure the reliability and performance of the circuit.

[0036] Preferably, step S1 comprises the following steps:

[0037] Step S11: obtaining integrated circuit device data;

[0038] Step S12: extracting geometric features from the integrated circuit device data to obtain device geometric feature data;

[0039] Step S13: extracting topological features from the integrated circuit device data to obtain device topological link feature data;

[0040] Step S14: performing feature space fusion on the device geometric feature data and the device topological link feature data to generate a fused feature space matrix;

[0041] Step S15: Eliminate redundant features from the fused feature space matrix to generate a device main feature matrix.

[0042] The benefit of the present invention lies in that by extracting geometric features and topological features from integrated circuit device data and fusing these feature data, the geometric and connection features of the device can be fully captured. This multi-level feature extraction and fusion method is more comprehensive than a single feature extraction method and can more accurately describe the complexity and functional characteristics of the device. After generating the fused feature space matrix, feature redundant components are eliminated, which helps to reduce redundant data and retain the most representative and informative features. This process can improve the accuracy and computational efficiency of subsequent analysis. Through the fusion and redundancy elimination of feature space, the generated device main feature matrix contains the most informative feature data, which provides a reliable data basis for subsequent hierarchical analysis, prediction and optimization. The main feature matrix with integrated geometric and topological features makes the device simulation and optimization process more accurate. This method can better capture the performance and potential problems of the device in practical applications, thereby improving the quality and reliability of integrated circuit design. By integrating geometric and topological features, sophisticated feature processing and comprehensive feature matrix generation, a comprehensive and efficient method is provided to describe and optimize integrated circuit devices. Compared with the prior art, this method can more accurately capture the complexity of the device and improve the accuracy and efficiency of subsequent analysis and optimization.

[0043] In an embodiment of the present invention, device data is extracted from an integrated circuit design database, which generally includes the geometric layout, material properties, electrical connections, and performance parameter information of the device. Data acquisition can be performed by querying integrated circuit design documents and schematics, and extracted using electronic design automation (EDA) tools such as Cadence Allegro, Mentor Graphics, or Synopsys. These tools support the export of files containing detailed geometric and electrical information of the device from design files, such as database files in neutral formats (such as ODB++ or IPC-2581), to ensure that the acquired data is complete and in a standard format. Geometric feature extraction is performed on the integrated circuit device data. The shape, size, and layout geometric information of the device are processed using computer vision technology or geometric analysis tools. Specific operations include: applying image processing algorithms, such as edge detection and contour extraction, to obtain the geometric boundaries of the device. Geometric feature extraction is performed using the OpenCV library in Python or the image processing toolbox in MATLAB. The extracted geometric feature data includes the length, width, height, surface shape of the device and its position on the circuit board. These features will be stored in the form of feature vectors in a geometric feature data matrix. Topological feature extraction is performed on the data of the integrated circuit device, with the focus on analyzing the electrical connection relationship between the devices. By parsing the circuit schematic and connection diagram, the pin connections of each device and the nodes in the circuit are identified. Using network graph analysis tools, such as Graph-tool or NetworkX library, the devices and their connection relationships are represented as graph structures, and topological feature data is extracted. Topological features include the connection strength, network density and connection paths between devices. These features reflect the connection structure of the circuit and are saved in the form of a topological link feature data matrix. The device geometric feature data and topological link feature data are fused in feature space. First, ensure that the two feature data have the same dimension and format, and standardize them if necessary. Use feature fusion techniques, such as principal component analysis (PCA) or feature-level fusion methods, to integrate geometric feature data and topological feature data in the same feature space. This process can be achieved with the help of the fusion tool in Python's Scikit-learn library. The final generated fused feature space matrix will contain comprehensive information of geometric and topological features, laying the foundation for subsequent data analysis and model training. The generated fused feature space matrix is ​​subjected to feature redundant component elimination to extract the most representative features. Apply feature selection techniques, such as variance-based feature selection or recursive feature elimination (RFE) to identify and remove redundant or irrelevant features. Use the Scikit-learn library in Python to perform feature selection by first calculating the variance of each feature and then removing features with variances below a set threshold.The final device main feature matrix will only retain the features that have a significant impact on the performance of the integrated circuit to reduce the complexity of the data and improve the accuracy of the model.

[0044] Preferably, step S2 comprises the following steps:

[0045] Step S21: performing graph structure mapping processing on the device main feature matrix to obtain a feature representative atlas;

[0046] Step S22: performing embedding hierarchical analysis on the feature representative atlas to generate a device hierarchical embedding graph matrix;

[0047] Step S23: performing module main body identification on the device hierarchical embedding diagram matrix to obtain independent functional module data;

[0048] Step S24: Perform graph-theoretic hierarchical clustering on the independent functional module data to generate a device hierarchy structure.

[0049] The invention is beneficial in that a feature representative atlas is obtained by mapping the device main feature matrix to a graph structure. This mapping method converts complex feature data into a graph structure, making the relationship between features more intuitive and easy to analyze. The graph structure can effectively capture the dependencies and interactions between features, providing a richer perspective for subsequent analysis. By embedding the feature representative atlas, a device hierarchical embedded graph matrix is ​​generated. This step can express the hierarchical relationship in the graph structure in an embedded manner, so as to better understand the performance of features at different levels. This hierarchical analysis can reveal the structural hierarchy and association of features, which is helpful for further module identification and functional analysis. Independent functional module data is obtained by identifying the module body of the device hierarchical embedded graph matrix. This process can identify modules with independent functions and clarify the role and position of each module in the overall system. This modular processing helps to analyze and optimize circuit functions in a more fine-grained manner. The device hierarchy is generated using a graph theory hierarchical clustering method. Graph theory hierarchical clustering can automatically identify and divide the hierarchical structure of the device based on the relationship between modules, providing a systematic hierarchical view. This method can clearly display the functional hierarchy and module relationship of the device, facilitating further design and optimization. By mapping feature data into a graph structure, performing hierarchical analysis, module identification, and graph hierarchical clustering, a systematic and automated way to process and optimize integrated circuit devices is provided. Compared with traditional methods, this method can more accurately capture the complex relationship between features, identify independent functional modules, and clearly display the hierarchical structure of the device, thereby improving the accuracy and efficiency of the analysis.

[0050] As an example of the present invention, refer to Figure 2 As shown, in this example, step S2 includes:

[0051] Step S21: performing graph structure mapping processing on the device main feature matrix to obtain a feature representative atlas;

[0052] In an embodiment of the present invention, the main feature matrix of the device is converted into a graph structure to establish a feature representative atlas. First, each row in the feature matrix is ​​regarded as a node in the graph, and each node represents a feature vector of a device. The similarity between the features is used as the weight of the edge to calculate the similarity between the feature vectors, for example, using the cosine similarity or Euclidean distance method. The edge weight of the graph can be determined by calculating the distance or similarity of each pair of feature vectors. With the help of a graph structure building tool, such as the graph building function in the NetworkX library, these nodes and edges are created into a weighted graph. The generated feature representative atlas will describe the structured relationship of the device features for subsequent analysis and processing.

[0053] Step S22: performing embedding hierarchical analysis on the feature representative atlas to generate a device hierarchical embedding graph matrix;

[0054] In an embodiment of the present invention, an embedding hierarchical analysis is performed on the generated feature representative atlas. First, the graph embedding technology is applied to map the nodes in the graph structure into a low-dimensional vector space. A graph neural network (GNN) model, such as GraphSAGE or GAT, is used to learn the embedding of nodes. By training the graph neural network, a low-dimensional embedding vector for each node is obtained, which retains the structure of the graph and the relationship between the nodes. Next, the embedding vector is used to generate a device hierarchical embedding graph matrix, which reflects the relative position and structural information of the nodes in the low-dimensional space. This process can be implemented using the PyTorchGeometric library in Python to ensure that the graph structure information can be effectively embedded and the hierarchical features of the graph are maintained.

[0055] Step S23: performing module main body identification on the device hierarchical embedding diagram matrix to obtain independent functional module data;

[0056] In an embodiment of the present invention, the module body is identified on the device hierarchical embedding graph matrix to extract the independent functional modules of the circuit. First, a community detection algorithm, such as the Louvain method or the Girvan-Newman algorithm, is used to analyze the module structure in the graph matrix. The community detection algorithm identifies closely connected subsets in the graph by optimizing the modularity function, each subset representing a functional module. The community detection function in the NetworkX library in Python is applied to identify and extract the nodes and edges of each module. The data of each functional module includes its nodes and connections in the hierarchical embedding graph matrix, reflecting the independent functional units in the circuit and their internal relationship structure.

[0057] Step S24: Perform graph-theoretic hierarchical clustering on the independent functional module data to generate a device hierarchy structure.

[0058] In an embodiment of the present invention, graph theory hierarchical clustering is performed on the data of independent functional modules to generate a hierarchical structure of the device. First, a similarity matrix of each functional module is constructed to calculate the distance or similarity between modules. A hierarchical clustering algorithm, such as agglomerative hierarchical clustering or divisive hierarchical clustering, is used to cluster the functional modules. The hierarchical clustering algorithm constructs a hierarchical tree diagram by gradually merging or splitting modules to display the clustering levels of the modules. During specific implementation, the hierarchical clustering function in the Scikit-learn library in Python is used to perform hierarchical clustering analysis on the modules to generate a tree diagram or cluster diagram of the device hierarchy. Ultimately, the resulting hierarchical structure will show the hierarchical relationship between the functional modules, which will help understand the overall structure and functional division of the device.

[0059] Preferably, step S22 includes the following steps:

[0060] Step S221: Performing preliminary hierarchical clustering on the feature representative graph to obtain preliminary clustering results;

[0061] Step S222: constructing a hierarchical structure for the preliminary clustering results to generate a hierarchical structure diagram;

[0062] Step S223: performing inter-category matrix similarity calculation on the hierarchical structure diagram to obtain category similarity; when the category similarity is greater than a preset similarity threshold, performing structural modularity optimization on the hierarchical structure diagram based on the category similarity to obtain a similarity matrix hierarchical diagram;

[0063] Step S224: performing matrix topology analysis on the similar matrix hierarchy graph to generate a device hierarchy embedding graph matrix.

[0064] The benefit of the present invention is that by performing hierarchical preliminary clustering on the feature representative graph, the feature data can be preliminarily divided into groups with similar features. This preliminary clustering provides basic data for subsequent structure construction, so that the generated hierarchical structure graph can more accurately reflect the relationship and hierarchy between the features. This process allows the function and structure of the device to be organized more systematically and provides a clear view. The matrix similarity between categories is calculated for the hierarchical structure graph, and the structural modularity is optimized when the category similarity is greater than a preset threshold. This method can improve the accuracy and modularity of the hierarchical structure graph by automatically identifying and optimizing categories with high similarity. This dynamic optimization process can effectively adjust and improve the hierarchical structure graph to make it more consistent with actual data characteristics. The similar matrix hierarchical graph generated after structural modularity optimization provides an optimization basis for subsequent matrix topological analysis. This optimized graph can better reflect the actual relationship between categories, thereby improving the effect and accuracy of matrix topological analysis. Matrix topological analysis is performed on the similar matrix hierarchical graph to generate a device hierarchical embedding graph matrix. This process can more accurately extract the hierarchical structure characteristics of the device by performing topological analysis on the optimized graph, and provide a more reliable data basis for subsequent simulation and optimization. Through preliminary clustering, optimized structure, dynamic adjustment and precise analysis, a systematic method is provided to process and optimize the feature data of integrated circuits. Compared with traditional technologies, this method can more comprehensively capture the relationship between features, dynamically optimize the hierarchical structure, and generate an accurate device hierarchical embedding matrix, thereby improving the accuracy and reliability of circuit simulation.

[0065] In an embodiment of the present invention, a hierarchical preliminary clustering is performed on a feature representative graph. First, a similarity matrix of a feature representative graph is constructed, by calculating the similarity between nodes, for example, using cosine similarity or Euclidean distance. Using these similarity information, a hierarchical clustering algorithm, such as agglomerative hierarchical clustering, is applied. This method gradually merges the most similar nodes by calculating the distance between each pair of nodes to form a preliminary hierarchical structure. During implementation, the AgglomerativeClustering module in the Scikit-learn library of Python is used to perform hierarchical clustering, and an appropriate distance metric is set. The preliminary clustering results finally obtained show the preliminary classification and hierarchical relationship of the nodes in the graph, laying the foundation for subsequent structural optimization and detailed analysis. The preliminary clustering results are hierarchically constructed to generate a hierarchical structure diagram. Using the nodes and clustering relationships in the preliminary clustering results, a hierarchical structure diagram is constructed, which shows the hierarchical relationship of each cluster. A hierarchical graph construction tool, such as the networkx library in Python, is applied to create a tree structure diagram in which each node represents a functional module and each edge represents the hierarchical relationship between modules. The hierarchical depth of the nodes reflects the hierarchical relationship of the modules, and the connection of the edges represents the direct relationship between the modules. The DiGraph class in networkx can be used to generate a directed graph to display the hierarchical structure, ensuring that the graphical representation accurately reflects the hierarchical relationship in the preliminary clustering results. The inter-category matrix similarity calculation is performed on the hierarchical graph. First, the node set of each category in the hierarchical graph is extracted, the category similarity matrix is ​​constructed, and the similarity between each pair of categories is calculated. This process can use matrix similarity calculation methods such as Jaccard similarity or cosine similarity. During implementation, the scipy.spatial.distance module in Python is used to calculate the similarity and generate a category similarity matrix. If the category similarity is greater than the preset threshold, the structural modularity is optimized. This step uses a community detection algorithm (such as the Louvain algorithm) to optimize the modularity and improve the consistency between categories. The optimized similarity matrix hierarchy graph shows a more optimized module division and structural relationship. The optimized similarity matrix hierarchy graph is subjected to matrix topological analysis. First, the topological structure of the graph is deeply understood through topological analysis methods in graph theory, such as the shortest path algorithm, centrality analysis, or connected component analysis. Use the networkx library in Python to perform topological analysis on the graph and calculate various topological indicators of the graph, such as node centrality and graph connectivity. The resulting device hierarchy embedding graph matrix will show the optimized device hierarchy, reflecting the position and importance of each module in the overall system. Through this analysis, the hierarchy of the system can be determined and the design and function allocation of the system can be optimized.

[0066] Preferably, step S3 comprises the following steps:

[0067] Step S31: Projecting the device main feature matrix into a high-dimensional feature space to obtain a projection feature matrix;

[0068] Step S32: performing component group density-based clustering on the projection feature matrix to generate potential component group data;

[0069] Step S33: predicting the component link probability of the device main feature matrix based on the potential component group data to obtain the predicted component link probability;

[0070] Step S34: performing a component link relationship topological analysis on the device main feature matrix based on the predicted component link probability to generate a component link relationship.

[0071] The invention is beneficial in that a projection feature matrix is ​​obtained by projecting the main feature matrix of the device into a high-dimensional feature space. This process maps the original high-dimensional data into a lower-dimensional space, so that complex feature relationships can be simplified and visualized. This projection method helps to reveal the inherent structure and pattern in the data and reduce the computational complexity. By performing density-based clustering of the projected feature matrix, potential component group data can be identified and generated. Density-based clustering methods (such as DBSCAN or HDBSCAN) perform well in processing data with noise and uneven distribution, and can more accurately identify potential component groups without noise interference. Based on the potential component group data, the device main feature matrix is ​​subjected to component link probability prediction to obtain predicted component link probability. This step predicts the link probability between devices by analyzing the relationship between potential component groups, so that all connection modes can be identified in advance and the circuit design and configuration can be optimized. Based on the predicted component link probability, the device main feature matrix is ​​subjected to component link relationship topological analysis to generate component link relationship. This analysis can systematically describe the actual connection relationship between components, provide a clear topological view, and help understand the circuit structure and further optimize it. Through high-dimensional feature space projection, density-based clustering, link probability prediction and topological analysis, a systematic method is provided to process and optimize the device characteristics of integrated circuits. Compared with traditional technologies, this method can more effectively process high-dimensional data, accurately identify component groups, dynamically predict connection relationships, and generate detailed topological views, thereby improving the accuracy and efficiency of circuit simulation and design.

[0072] As an example of the present invention, refer to Figure 3 As shown, in this example, step S3 includes:

[0073] Step S31: Projecting the device main feature matrix into a high-dimensional feature space to obtain a projection feature matrix;

[0074] In an embodiment of the present invention, the main feature matrix of the device is projected into a high-dimensional feature space. First, a high-dimensional data dimensionality reduction technique is selected, such as principal component analysis (PCA) or t-distributed random neighbor embedding (t-SNE). When applying PCA, the main feature dimensions are extracted by calculating the principal components and performing a linear transformation on the main feature matrix of the device, thereby reducing the dimension of the data and obtaining a projected feature matrix. During implementation, the sklearn.decomposition.PCA module in Python is used to perform PCA processing, and an appropriate number of principal components is set to retain 95% of the data variance. If t-SNE is used, the sklearn.manifold.TSNE module is used to project the data into a two-dimensional or three-dimensional space to more intuitively visualize the relationship between the data. The final generated projection feature matrix represents the data contained in the feature space after dimensionality reduction, which is convenient for subsequent analysis and processing.

[0075] Step S32: performing component group density-based clustering on the projection feature matrix to generate potential component group data;

[0076] In an embodiment of the present invention, the projection feature matrix is ​​subjected to component group density-based clustering. A density-based clustering algorithm, such as DBSCAN (Density-Based Spatial Clustering of Applications with Noise), is selected. First, the local density of each point in the projection feature matrix is ​​calculated and the density distribution of the data points is determined. The parameters of the DBSCAN algorithm are set, including the minimum number of samples and the distance threshold. Using the sklearn.cluster.DBSCAN module in Python, DBSCAN clustering is run to identify density peaks in the data and classify them into potential component groups. The clustering results will provide potential component group data, showing how data points are divided into different groups based on their density relationships.

[0077] Step S33: predicting the component link probability of the device main feature matrix based on the potential component group data to obtain the predicted component link probability;

[0078] In an embodiment of the present invention, the potential component group data is subjected to feature vector mapping to obtain a potential component group feature matrix. First, feature extraction is performed on each potential component group to convert it into a feature vector. Feature extraction techniques, such as principal component analysis (PCA) or linear discriminant analysis (LDA), can be used to map high-dimensional data to a low-dimensional space so as to more efficiently represent the characteristics of the component group. Using the sklearn.decomposition.PCA module or the sklearn.discriminant_analysis.LinearDiscriminantAnalysis module in Python, the potential component group data is mapped to a low-dimensional feature space according to the selected mapping technique. The generated potential component group feature matrix will contain the feature vectors of each component group processed by the mapping, providing a data basis for subsequent similarity evaluation. Similarity evaluation is performed on the potential component group feature matrix and the device main feature matrix. First, the similarity between the two feature matrices is calculated. Similarity measurement methods, such as cosine similarity, Euclidean distance or Pearson correlation coefficient can be used. During specific implementation, the cosine or euclidean function in the scipy.spatial.distance module of Python is used to calculate the similarity of each pair of feature vectors. The potential component group feature matrix is ​​compared with the device main feature matrix one by one to generate a matrix similarity data set, in which each element represents the similarity between the corresponding feature vectors. These similarity data are used for subsequent potential connection mapping. Based on the matrix similarity data, the potential component group feature matrix and the device main feature matrix are mapped to potential connections. By analyzing the matrix similarity data, the potential connection between the feature vectors in the potential component group feature matrix and the feature vectors in the device main feature matrix is ​​identified. The potential connection relationship between the feature vector pairs is determined using a mapping method such as the nearest neighbor algorithm (k-NN) or a matching algorithm. The specific operation can be matched using Python's sklearn.neighbors.KNeighborsClassifier or scipy.optimize.linear_sum_assignment to generate a component potential connection matrix, in which each element represents a potential connection relationship. The component connection probability is predicted for the component potential connection matrix. Based on the generated component potential connection matrix, a prediction model is applied to estimate the connection probability of each pair of components. The prediction can be completed using logistic regression, support vector machine (SVM) or graph neural network (GNN) models. During implementation, the component potential connection matrix is ​​first used as the input feature of the model, and the prediction model is trained to fit the actual connection probability.Use sklearn.linear_model.LogisticRegression, sklearn.svm.SVC in Python, or the GNN model in the PyTorch Geometric library for training. After training, use the model to predict the component potential connection matrix and generate predicted component link probability data.

[0079] Step S34: performing a component link relationship topological analysis on the device main feature matrix based on the predicted component link probability to generate a component link relationship.

[0080] In an embodiment of the present invention, the predicted component link probability is converted into a weighted undirected graph to construct a preliminary topological structure. First, the edges of the graph are constructed according to the predicted component link probability, wherein the weight of each edge is equal to the predicted probability. Use the networkx library in Python to create an undirected graph, call the networkx.Graph class to build the graph structure, and connect each pair of components to the graph through the add_edge method, and the weight of the edge is set to the predicted connection probability. The preliminary topological structure can be visualized by the networkx.draw function to show the connection relationship and its strength between devices, and provide basic data for subsequent analysis. Weak link filtering is performed on the preliminary topological structure to generate a strong link topological structure. First, a similarity threshold is set, and edges with predicted link probabilities lower than the threshold are filtered out according to the threshold. Using the networkx library of Python, the networkx.Graph.remove_edges_from method is applied to delete all edges with weights lower than the threshold in the graph. This operation ensures that only strong link relationships with high connection probabilities are retained, and the generated strong link topological structure shows the main connection relationships between devices. The connected_components function in the networkx library is used to perform connectivity analysis on the graph to identify all connected components in the graph. Calculate the number of nodes for all connected components and determine the component with the largest number of nodes as the largest connected component. Apply the max function and len function in networkx to calculate the number of nodes in each connected component to obtain the largest connected component. Extract all nodes and edges in the largest connected component and build a subgraph containing these nodes and edges. Use the subgraph method in the networkx library to create a subgraph of the largest connected component for further analysis. Use the networkx.draw function to visualize the key subgraph and observe its internal structure and connection relationship. Perform betweenness centrality analysis on the key subgraph to obtain key link data. Betweenness centrality measures the importance of a node in the network, that is, the frequency of the node on all shortest paths. Use the betweenness_centrality function in the networkx library to calculate the betweenness centrality of each node in the key subgraph. Betweenness centrality analysis can identify key nodes and important links. Further perform degree centrality analysis based on the betweenness centrality data, use the degree_centrality function in networkx to calculate the degree centrality of the node and determine the number of connections of the node. The key node data finally obtained shows the most important nodes and their link relationships in the key subgraph. Combine the key link data and key node data, integrate this information into the device main feature matrix, and establish the actual connection relationship between devices. Use the networkx library in Python to update the device main feature matrix and generate a topological graph containing key links and key nodes.Through graph analysis and visualization tools, such as the networkx.draw function, the final component link relationship diagram is displayed, clearly reflecting the main connection relationships and topological structures between devices.

[0081] Preferably, step S33 includes the following steps:

[0082] Step S331: Perform feature vector mapping on the potential component group data to obtain a potential component group feature matrix;

[0083] Step S332: performing similarity evaluation on the potential component group feature matrix and the device main feature matrix to obtain matrix similarity data;

[0084] Step S333: performing potential connection mapping on the potential component group feature matrix and the device main feature matrix based on the matrix similarity data to generate a component potential connection matrix;

[0085] Step S334: performing component connection probability prediction on the component potential connection matrix to obtain predicted component link probability.

[0086] The invention is beneficial in that a potential component group feature matrix is ​​generated by mapping the feature vectors of the potential component group data. This process converts the potential component group data into a structured feature matrix so that the features of the component group can be analyzed in a unified feature space. This mapping helps to analyze the characteristics of the potential component group more systematically and provides a solid foundation for subsequent connection mapping and probability prediction. By performing similarity evaluation on the potential component group feature matrix and the device main feature matrix, matrix similarity data is obtained. This step can quantify the similarity between the potential component group and the main feature matrix and identify potential correlations and associations. This evaluation can improve the understanding of the relationship between devices, thereby providing accurate data support for connection mapping. Based on the matrix similarity data, potential connection mapping is performed on the potential component group feature matrix and the device main feature matrix to generate a component potential connection matrix. This process maps the potential connection relationship into a new matrix by analyzing the similarity of the feature matrix, helping to reveal the potential connection mode and interaction. The generated component potential connection matrix is ​​subjected to connection probability prediction to obtain the predicted component link probability. This step can identify and optimize the connection relationship in the circuit in advance by predicting the connection probability, helping to design a more reliable and efficient circuit. Through feature vector mapping, similarity evaluation, potential connection mapping and probability prediction, a systematic and dynamic processing method is provided for device simulation of integrated circuits. This method can more comprehensively identify and analyze the potential connection relationship between components, and improve the accuracy and optimization effect of circuit design through accurate probability prediction. Compared with traditional technologies, this method can more effectively handle complex connection patterns and improve the ability of circuit simulation and optimization.

[0087] In an embodiment of the present invention, the potential component group data is subjected to feature vector mapping to obtain a potential component group feature matrix. First, feature extraction is performed on each potential component group to convert it into a feature vector. Feature extraction techniques, such as principal component analysis (PCA) or linear discriminant analysis (LDA), can be used to map high-dimensional data to a low-dimensional space so as to more efficiently represent the characteristics of the component group. Using the sklearn.decomposition.PCA module or the sklearn.discriminant_analysis.LinearDiscriminantAnalysis module in Python, the potential component group data is mapped to a low-dimensional feature space according to the selected mapping technique. The generated potential component group feature matrix will contain the feature vectors of each component group processed by the mapping, providing a data basis for subsequent similarity evaluation. Similarity evaluation is performed on the potential component group feature matrix and the device main feature matrix. First, the similarity between the two feature matrices is calculated. Similarity measurement methods, such as cosine similarity, Euclidean distance or Pearson correlation coefficient can be used. During specific implementation, the cosine or euclidean function in the scipy.spatial.distance module of Python is used to calculate the similarity of each pair of feature vectors. The potential component group feature matrix is ​​compared with the device main feature matrix one by one to generate a matrix similarity data set, in which each element represents the similarity between the corresponding feature vectors. These similarity data are used for subsequent potential connection mapping. Based on the matrix similarity data, the potential component group feature matrix and the device main feature matrix are mapped to potential connections. By analyzing the matrix similarity data, the potential connection between the feature vectors in the potential component group feature matrix and the feature vectors in the device main feature matrix is ​​identified. The potential connection relationship between the feature vector pairs is determined using a mapping method such as the nearest neighbor algorithm (k-NN) or a matching algorithm. The specific operation can be matched using Python's sklearn.neighbors.KNeighborsClassifier or scipy.optimize.linear_sum_assignment to generate a component potential connection matrix, in which each element represents a potential connection relationship. The component connection probability is predicted for the component potential connection matrix. Based on the generated component potential connection matrix, a prediction model is applied to estimate the connection probability of each pair of components. The prediction can be completed using logistic regression, support vector machine (SVM) or graph neural network (GNN) models. During implementation, the component potential connection matrix is ​​first used as the input feature of the model, and the prediction model is trained to fit the actual connection probability.Use sklearn.linear_model.LogisticRegression, sklearn.svm.SVC in Python, or the GNN model in the PyTorch Geometric library for training. After training, use the model to predict the component potential connection matrix and generate predicted component link probability data.

[0088] Preferably, step S34 includes the following steps:

[0089] Step S341: constructing a weighted undirected graph of the predicted element link probabilities to obtain a preliminary topological structure;

[0090] Step S342: filtering weak links on the preliminary topology structure to generate a strong link topology structure;

[0091] Step S343: Performing connectivity analysis on the strong link topology structure to obtain the maximum connected component;

[0092] Step S344: identifying key subgraphs of the preliminary topological structure based on the maximum connected component to obtain key subgraphs;

[0093] Step S345: performing betweenness centrality analysis on the key subgraph to obtain key link data; performing degree centrality analysis on the key subgraph according to the key link data to generate key node data;

[0094] Step S346: Perform component link relationship topology analysis on the device main feature matrix based on the key link data and the key node data to generate component link relationships.

[0095] The invention is beneficial in that a preliminary topological structure is obtained by constructing a weighted undirected graph for the predicted component link probability. This step can effectively convert the link probability between components into the edge weight of the graph, so that the graph structure can accurately reflect the potential connection strength and relationship between each component. This weighted graph construction method can more carefully depict the interactive relationship between components. By filtering the preliminary topological structure with weak links, a strong link topological structure is generated. This process can remove weak links with connection strengths lower than a preset threshold, making the graph structure clearer and highlighting important connection relationships. This filtering method helps to eliminate noise and focus on the main connections, thereby improving the accuracy of topological analysis. Connectivity analysis is performed on the strong link topological structure to obtain the maximum connected component. This analysis step can identify the main connected areas in the graph, ensuring that the analysis focuses on the parts with actual connectivity. This helps to focus on the most important subgraphs, thereby improving the efficiency of the analysis and the reliability of the results. By identifying the key subgraphs for the maximum connected component, and performing betweenness centrality and degree centrality analysis on the key subgraphs, key link data and key node data are obtained respectively. These steps can identify the core subgraphs and key nodes in the graph, providing an in-depth understanding of the component connection structure. This detailed analysis helps optimize circuit design, identify key components and connections, and thus improve circuit performance. Based on key link data and key node data, the device main feature matrix is ​​subjected to a topological analysis of the component link relationship to generate a component link relationship. This comprehensive analysis method can combine key data with the main feature matrix to generate accurate component link relationships, which helps to deeply understand the overall structure and connection mode of the circuit and optimize the circuit design. A systematic topological analysis method is provided through weighted undirected graph construction, weak link filtering, connectivity analysis, key subgraph identification and centrality analysis. This method can more comprehensively identify and optimize key connections and nodes in integrated circuits. Compared with traditional technologies, it can improve the accuracy and optimization effect of circuit simulation, thereby supporting more accurate circuit design and performance improvement.

[0096] In an embodiment of the present invention, the predicted component link probability is converted into a weighted undirected graph to construct a preliminary topological structure. First, the edges of the graph are constructed according to the predicted component link probability, wherein the weight of each edge is equal to the predicted probability. Use the networkx library in Python to create an undirected graph, call the networkx.Graph class to build the graph structure, and connect each pair of components to the graph through the add_edge method, and the weight of the edge is set to the predicted connection probability. The preliminary topological structure can be visualized by the networkx.draw function to show the connection relationship and its strength between devices, and provide basic data for subsequent analysis. Weak link filtering is performed on the preliminary topological structure to generate a strong link topological structure. First, a similarity threshold is set, and edges with predicted link probabilities lower than the threshold are filtered out according to the threshold. Using the networkx library of Python, the networkx.Graph.remove_edges_from method is applied to delete all edges with weights lower than the threshold in the graph. This operation ensures that only strong link relationships with high connection probabilities are retained, and the generated strong link topological structure shows the main connection relationships between devices. The connected_components function in the networkx library is used to perform connectivity analysis on the graph to identify all connected components in the graph. Calculate the number of nodes for all connected components and determine the component with the largest number of nodes as the largest connected component. Apply the max function and len function in networkx to calculate the number of nodes in each connected component to obtain the largest connected component. Extract all nodes and edges in the largest connected component and build a subgraph containing these nodes and edges. Use the subgraph method in the networkx library to create a subgraph of the largest connected component for further analysis. Use the networkx.draw function to visualize the key subgraph and observe its internal structure and connection relationship. Perform betweenness centrality analysis on the key subgraph to obtain key link data. Betweenness centrality measures the importance of a node in the network, that is, the frequency of the node on all shortest paths. Use the betweenness_centrality function in the networkx library to calculate the betweenness centrality of each node in the key subgraph. Betweenness centrality analysis can identify key nodes and important links. Further perform degree centrality analysis based on the betweenness centrality data, use the degree_centrality function in networkx to calculate the degree centrality of the node and determine the number of connections of the node. The key node data finally obtained shows the most important nodes and their link relationships in the key subgraph. Combine the key link data and key node data, integrate this information into the device main feature matrix, and establish the actual connection relationship between devices. Use the networkx library in Python to update the device main feature matrix and generate a topological graph containing key links and key nodes.Through graph analysis and visualization tools, such as the networkx.draw function, the final component link relationship diagram is displayed, clearly reflecting the main connection relationships and topological structures between devices.

[0097] Preferably, step S4 comprises the following steps:

[0098] Step S41: grouping the device main feature matrix into integrated modules according to the device hierarchy to obtain integrated circuit module feature data;

[0099] Step S42: Arrange virtual circuit connections for component link relationships to generate virtual connection circuits;

[0100] Step S43: performing circuit device simulation driving processing on the integrated circuit module characteristic data and the virtual connection circuit to obtain a simulation circuit device unit.

[0101] The invention is beneficial in that the device main feature matrix is ​​grouped into integrated modules according to the device hierarchy to generate integrated circuit module feature data. This process can systematically group the relevant functional modules in the circuit, so that the feature data of the complex circuit is more structured and easy to analyze and optimize. Integrated module grouping helps to simplify circuit design, improve the modularization of the circuit, and support more efficient circuit design and verification. Virtual connection circuits are generated by virtual circuit connection arrangement of component link relationships. This process can simulate the actual connection situation in the circuit and help to perform detailed connection arrangement and verification before the actual circuit is built. Virtual circuit connection arrangement can find potential connection problems in the simulation stage and reduce the number of design iterations and costs. Circuit device simulation drive processing is performed on the integrated circuit module feature data and the virtual connection circuit to obtain a simulation circuit device unit. This processing step can combine the module feature data and the virtual connection circuit to realize the actual performance prediction and verification of the circuit through simulation drive technology. The simulation circuit device unit can provide detailed information about the circuit performance and support design optimization and verification. By combining module grouping, virtual connection arrangement and simulation drive processing, a systematic design process is formed. This method not only improves the efficiency of circuit design, but also enhances the accuracy of design verification. The systematic design process can identify and solve design problems at an early stage, reducing uncertainty in the design process. By integrating module grouping, virtual circuit connection arrangement and simulation-driven processing, an efficient and systematic circuit design and verification method is provided. This method can improve the modularity and systematization of circuit design, improve the accuracy of simulation, reduce design iteration and verification costs, and support more accurate circuit design and optimization compared to traditional technologies.

[0102] In an embodiment of the present invention, the device main feature matrix is ​​grouped into integrated modules according to the device hierarchy to generate integrated circuit module feature data. First, the devices in the device main feature matrix are grouped by module using the module level defined in the device hierarchy. The groupby function in the pandas library in Python can be used to aggregate the data in the device main feature matrix according to the modules in the hierarchy. The device features in each module are summarized, and the mean and standard deviation statistical indicators are calculated to generate feature data for each integrated circuit module. These feature data will show the overall characteristics of each module, provide an in-depth understanding of each module in the circuit design, and provide basic data for subsequent simulation and optimization processing. The component link relationship is arranged for virtual circuit connection to generate a virtual connection circuit. First, the component link relationship data obtained previously is used to construct a connection diagram of the virtual circuit. A graphical tool or circuit design software, such as KiCad or Altium Designer, is used to visualize the devices and the connection relationship between them. Through the connection function of the software, the connection between the devices is configured, and these connections are converted into virtual connections of the circuit diagram. The connection relationship diagram can be constructed using the Graph object in the networkx library, and the circuit structure can be visualized through the networkx.draw function. The virtual connection circuit shows the actual connection relationship between each component and provides a detailed virtual model for circuit simulation. The circuit device simulation drive processing is performed on the integrated circuit module characteristic data and the virtual connection circuit to obtain the simulation circuit device unit. First, use circuit simulation software, such as SPICE (Simulation Program with Integrated Circuit Emphasis) for simulation processing. Import the integrated circuit module characteristic data into the simulation software, and set the simulation parameters of the circuit, including the component model, working conditions and input signals. Use the simulation function in SPICE to perform DC analysis, AC analysis and transient analysis to evaluate the performance and stability of the circuit. During the simulation process, the software will calculate based on the module characteristic data and the configuration of the virtual connection circuit to generate a simulation circuit device unit. The simulation results show the behavior and performance of the circuit under different conditions, providing a basis for verification and optimization of the circuit design.

[0103] Preferably, step S5 comprises the following steps:

[0104] Step S51: extracting device location from integrated circuit device data to obtain circuit device layout location;

[0105] Step S52: performing circuit integration simulation on the simulation circuit device unit based on the circuit device layout positioning to obtain a simulated integrated circuit;

[0106] Step S53: constructing a simulation environment field for the analog integrated circuit to generate a simulation circuit working environment field;

[0107] Step S54: simulating the circuit operation of the analog integrated circuit according to the simulated circuit operation environment field, and monitoring the performance of each device in the circuit to obtain circuit device performance data;

[0108] Step S55: When the circuit device performance data is less than a preset circuit device performance threshold, defective device optimization is performed on the simulated circuit device unit based on the circuit device performance data to obtain optimized integrated circuit device data.

[0109] The invention is beneficial in that the circuit device layout positioning is obtained by extracting the device positioning of the integrated circuit device data. This process can accurately determine the position of each device in the circuit, thereby ensuring the accuracy and rationality of the circuit layout. This detailed layout positioning helps to reduce problems caused by improper layout in the simulation and integration stages. Based on the circuit device layout positioning, the simulation circuit device unit is simulated for circuit integration to obtain a simulated integrated circuit. This step can combine device positioning with circuit simulation to provide a more realistic circuit integration effect. This integrated simulation can help to discover and solve layout-related problems in the simulation stage and optimize circuit design. By constructing a simulation environment field for the simulated integrated circuit, a simulated circuit working environment field is generated. This process can provide realistic working environment conditions for the circuit and help evaluate the performance of the circuit under actual working conditions. This environment field construction can simulate the performance of the circuit under various environmental factors and improve the comprehensiveness and accuracy of the simulation. According to the simulated circuit working environment field, the circuit operation of the simulated integrated circuit is simulated, and the performance of each device in the circuit is monitored. This process can monitor the circuit performance in real time during the simulation stage, identify performance bottlenecks and problems in a timely manner, and provide detailed performance data. This real-time monitoring helps to quickly discover and solve design problems and improve the overall reliability of the circuit. When the circuit device performance data is less than the preset circuit device performance threshold, the defective device optimization is performed on the simulated circuit device unit based on the circuit device performance data to obtain optimized integrated circuit device data. This process can automatically identify and optimize devices that do not meet performance standards during the simulation phase, thereby improving the overall performance and reliability of the circuit. The optimization process can be adjusted based on specific performance data, making the optimization more accurate and effective. Through precise device layout positioning, circuit integration simulation combined with layout, simulation environment field construction, real-time performance monitoring and defective device optimization, a comprehensive and detailed circuit simulation and optimization method is provided. This method can accurately simulate circuit behavior, optimize design, and improve circuit performance and reliability during the simulation phase.

[0110] In an embodiment of the present invention, device location extraction is performed on the integrated circuit device data to obtain the circuit device layout location. First, the location information of each device is extracted from the integrated circuit device data, usually including the coordinates or position labels of the device on the circuit board. Use an electronic design automation (EDA) tool, such as Cadence or Mentor Graphics, to read the device data and mark the position of each device in the circuit diagram. The data can be processed by the pandas library in Python to extract and format the device location data. The generated circuit device layout location data will display the actual position of each device on the circuit board in the form of coordinates, providing a layout basis for subsequent circuit integration simulation. Circuit integration simulation is performed on the simulation circuit device unit based on the circuit device layout location. First, use circuit simulation software, such as Cadence OrCAD or HSPICE, to import the circuit device layout location data into the simulation tool. Through the layout function in the simulation software, the simulation circuit device unit is arranged according to the layout location data, and the connection mode and working conditions of the circuit are set. Perform integrated simulation of the integrated circuit to simulate the behavior of the circuit under actual layout conditions. The simulation results will show the electrical performance of the circuit and verify whether the device layout meets the design requirements. This simulation process helps to evaluate the overall performance and stability of the circuit after integration. The simulation environment field is constructed for the analog integrated circuit to generate the simulation circuit working environment field. First, the simulation environment is configured according to the working environment conditions of the circuit, such as temperature, power supply voltage and signal noise. Use the environment modeling function of the simulation tool to set the parameters of the simulation environment. The environment setting function in the SPICE simulation software can be used to create a simulation environment field that is consistent with the actual working environment. Set the external conditions in the simulation model to ensure that the simulation environment can accurately reflect the performance of the circuit under actual working conditions. The generated simulation circuit working environment field will provide a virtual working condition to facilitate the comprehensive evaluation of circuit performance. According to the simulation circuit working environment field, the circuit operation of the analog integrated circuit is simulated and the performance of each device in the circuit is monitored. First, the constructed simulation environment field is applied to the circuit simulation software to perform the circuit operation simulation. Use SPICE or Cadence simulation tools to perform time domain or frequency domain analysis to monitor the working status and performance indicators of each device in the circuit. The software will output detailed circuit device performance data, including voltage, current, power and signal integrity information. With this data, the performance of the circuit in the actual working environment can be evaluated and performance bottlenecks or anomalies can be found. When the circuit device performance data is less than the preset circuit device performance threshold, defective device optimization is performed to obtain optimized integrated circuit device data. First, based on the performance monitoring data, identify the devices that do not meet the performance standards. Use circuit optimization tools, such as the optimization module in ANSYS or Cadence, to adjust device parameters, rewire or replace devices for optimization.The optimization process involves adjusting the parameters of resistors, capacitors, and other components in the circuit design to improve the overall circuit performance. The optimized circuit simulation is performed to verify the optimization effect. If the optimized circuit performance meets the preset threshold, the final optimized integrated circuit device data is generated. This data shows the performance of the optimized circuit and ensures the reliability and efficiency of the circuit design.

[0111] Preferably, optimizing defective devices for simulated circuit device units based on circuit device performance data comprises the following steps:

[0112] Adjusting the initial compensation parameters of the circuit device performance data according to the preset standard device performance data to obtain initial compensation data;

[0113] Perform differential evolution analysis on the initial compensation data to generate candidate compensation data;

[0114] Perform particle swarm optimization local search on candidate compensation data to obtain local optimized candidate compensation data;

[0115] Performing post-compensation performance evaluation on simulation circuit device units based on local optimization candidate compensation data to generate local compensation performance results;

[0116] Using the local compensation performance results, the search parameters of the candidate compensation data are adjusted to obtain optimized adjusted search parameters;

[0117] Repeat the above steps until the local compensation performance result is greater than or equal to the preset standard device performance data;

[0118] The defective device of the simulation circuit device unit is optimized according to the local compensation performance result to obtain the optimized integrated circuit device data.

[0119] The benefit of the present invention lies in the use of differential evolution and particle swarm optimization advanced algorithms to dynamically adjust compensation parameters, which enables the optimization process to be continuously improved according to actual performance data. Dynamic optimization can effectively deal with the uncertainty and complexity of circuit device performance, gradually approach the ideal performance standard, and improve the optimization effect. Through differential evolution analysis of initial compensation data and particle swarm optimization local search of candidate compensation data, the above steps implement a multi-level optimization strategy. This strategy can optimize from both global and local levels, effectively improve the compensation effect, and ensure that the final optimization result is more robust and accurate. The local compensation performance results are used to adjust the search parameters and perform continuous iterative optimization. This real-time adjustment based on actual performance data can more flexibly deal with performance fluctuations of circuit devices and ensure that the optimization process is closely connected with actual needs. The adaptive adjustment strategy in the optimization process (such as adjusting the search parameters according to the local compensation performance results) can automatically adjust the behavior of the optimization algorithm so that it can maintain high efficiency at different stages and conditions. This adaptive mechanism improves the flexibility and effect of optimization and can handle complex circuit design problems. It is possible to effectively optimize defective devices for simulated circuit device units and ultimately obtain optimized integrated circuit device data. This optimization can significantly improve the performance of circuit devices, meet the preset standard performance data, and improve the quality and reliability of the overall circuit design. Through the advanced algorithms of differential evolution and particle swarm optimization combined with real-time performance data for dynamic and adaptive optimization, a more efficient and accurate optimization strategy is provided in the device simulation method of integrated circuits. This method not only improves the flexibility and accuracy of optimization, but also effectively improves the overall performance and reliability of integrated circuits.

[0120] In an embodiment of the present invention, the circuit device performance data is first adjusted for initial compensation parameters according to preset standard device performance data. A circuit simulation tool, such as Cadence or SPICE, is used to compare the standard device performance data with the circuit device performance data. The optimization algorithm of the scipy.optimize library in Python is used to calculate the initial compensation parameters, which include the adjustment values ​​of resistance, capacitance and inductance. By adjusting these parameters, the circuit device performance data is close to the standard performance data. After the initial compensation data is generated, it is used as the basic data for further optimization to ensure that the performance of the circuit design is close to the standard requirements. The initial compensation data is subjected to differential evolution analysis to generate candidate compensation data. Differential evolution is a global optimization algorithm for finding the optimal solution. In this step, the DEAP (Distributed Evolutionary Algorithms in Python) library is used for differential evolution analysis. First, a fitness function is defined to evaluate the impact of the initial compensation data on the circuit performance. The differential evolution algorithm is applied to generate new candidate compensation data. These candidate data include adjusted resistance, capacitance and inductance values. In the process of differential evolution, the compensation parameters are continuously optimized through multiple generations of iterations to find the best compensation data. Particle swarm optimization (PSO) is used to search the candidate compensation data locally to obtain the locally optimized candidate compensation data. Particle swarm optimization is an intelligent optimization algorithm for local search. The local search is implemented using ParticleSwarmOptimizer in the scikit-opt library. First, the candidate compensation data is used as the initial position of the particle, and the fitness function is set to evaluate the performance of each particle. The particle speed and position are updated through the particle swarm optimization algorithm, and compensation data with better performance are iteratively searched. The local optimization process will generate locally optimized compensation data, further improve the circuit performance, and obtain a more accurate compensation solution. The performance of the simulated circuit device unit after compensation is evaluated based on the locally optimized candidate compensation data. Using circuit simulation software such as SPICE or Cadence, the locally optimized candidate compensation data is applied to the circuit design to adjust the parameters of the circuit components. The performance simulation of the circuit is performed to evaluate the performance of the circuit under the new compensation data, including voltage, current, power, and signal integrity indicators. The simulation results generate local compensation performance results, which show the closeness of the circuit performance after compensation to the preset standard device performance data, providing a basis for subsequent parameter adjustment and optimization. Use the local compensation performance results to adjust the search parameters of the candidate compensation data to obtain the optimized adjusted search parameters. Analyze the gap between the local compensation performance results and the preset standard device performance data, and use the optimization algorithm to adjust the search parameters to further improve the compensation data. The mathematical operations in the numpy library and the optimization functions in the scipy.optimize library can be used to fine-tune the parameters.The adjusted search parameters are used to update the settings in the differential evolution and particle swarm optimization algorithms in the hope of better matching the standard performance requirements. The optimized and adjusted search parameters obtained will be used for the next round of optimization iterations. Repeat the above steps until the local compensation performance results are greater than or equal to the preset standard device performance data. After each round of optimization, the new local compensation performance results are evaluated using circuit simulation software. If the performance results still do not meet the preset standards, return to the first step for differential evolution analysis and further particle swarm optimization of the candidate compensation data. This process continuously adjusts and optimizes the compensation parameters until the local compensation performance results meet or exceed the standard performance data. Each optimization cycle ensures that the final optimization results meet the design requirements by analyzing the local compensation performance results and adjusting the search parameters. Defective device optimization is performed on the simulated circuit device units based on the local compensation performance results. The circuit is adjusted using the final compensation data to eliminate performance defects. The optimized compensation data is applied to the circuit design and the simulation is rerun to verify the circuit performance. Based on the optimized performance data, the circuit design is modified to ensure that the circuit meets the expected performance standards. The final optimized integrated circuit device data reflects the optimized circuit design and ensures the reliability and efficiency of the circuit in practical applications.

[0121] Therefore, the embodiments should be regarded as illustrative and non-restrictive from all points, and the scope of the present invention is limited by the appended claims rather than the above description, and it is therefore intended that all changes falling within the meaning and range of equivalent elements of the application documents are included in the present invention.

[0122] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. A device simulation method for an integrated circuit, characterized in that: The following steps are involved: Step S1: obtaining integrated circuit device data; extracting multi-dimensional topological features from the integrated circuit device data, and removing redundant features to generate a device main feature matrix; Step S2: performing embedding hierarchical analysis on the device main feature matrix to generate a device hierarchical embedding graph matrix; performing module graph hierarchical clustering on the device hierarchical embedding graph matrix to generate a device hierarchical structure; Step S3: predicting the potential component link probability of the device main feature matrix, and performing component link relationship topology analysis to generate component link relationships; Step S4: constructing device units for the device main feature matrix based on the device hierarchy and component link relationship to generate simulation circuit device units; Step S5: Perform circuit integration simulation on the simulation circuit device unit according to the integrated circuit device data, and optimize defective devices to obtain optimized integrated circuit device data.

2. The device simulation method for integrated circuit according to claim 1, characterized in that: Step S1 includes the following steps: Step S11: obtaining integrated circuit device data; Step S12: extracting geometric features from the integrated circuit device data to obtain device geometric feature data; Step S13: extracting topological features from the integrated circuit device data to obtain device topological link feature data; Step S14: performing feature space fusion on the device geometric feature data and the device topological link feature data to generate a fused feature space matrix; Step S15: Eliminate redundant features from the fused feature space matrix to generate a device main feature matrix.

3. The device simulation method for integrated circuit according to claim 1, characterized in that: Step S2 includes the following steps: Step S21: performing graph structure mapping processing on the device main feature matrix to obtain a feature representative atlas; Step S22: performing embedding hierarchical analysis on the feature representative atlas to generate a device hierarchical embedding graph matrix; Step S23: performing module main body identification on the device hierarchical embedding diagram matrix to obtain independent functional module data; Step S24: Perform graph-theoretic hierarchical clustering on the independent functional module data to generate a device hierarchy structure.

4. The device simulation method for integrated circuit according to claim 3, characterized in that: Step S22 includes the following steps: Step S221: performing preliminary hierarchical clustering on the feature representative atlas to obtain preliminary clustering results; Step S222: constructing a hierarchical structure for the preliminary clustering results to generate a hierarchical structure diagram; Step S223: performing inter-category matrix similarity calculation on the hierarchical structure diagram to obtain category similarity; when the category similarity is greater than a preset similarity threshold, performing structural modularity optimization on the hierarchical structure diagram based on the category similarity to obtain a similarity matrix hierarchical diagram; Step S224: performing matrix topology analysis on the similar matrix hierarchy graph to generate a device hierarchy embedding graph matrix.

5. The device simulation method for integrated circuit according to claim 1, characterized in that: Step S3 includes the following steps: Step S31: Projecting the device main feature matrix into a high-dimensional feature space to obtain a projection feature matrix; Step S32: performing component group density-based clustering on the projection feature matrix to generate potential component group data; Step S33: predicting the component link probability of the device main feature matrix based on the potential component group data to obtain the predicted component link probability; Step S34: performing a component link relationship topological analysis on the device main feature matrix based on the predicted component link probability to generate a component link relationship.

6. The device simulation method for integrated circuit according to claim 5, characterized in that: Step S33 includes the following steps: Step S331: Perform feature vector mapping on the potential component group data to obtain a potential component group feature matrix; Step S332: performing similarity evaluation on the potential component group feature matrix and the device main feature matrix to obtain matrix similarity data; Step S333: performing potential connection mapping on the potential component group feature matrix and the device main feature matrix based on the matrix similarity data to generate a component potential connection matrix; Step S334: performing component connection probability prediction on the component potential connection matrix to obtain predicted component link probability.

7. The device simulation method for integrated circuit according to claim 5, characterized in that: Step S34 includes the following steps: Step S341: constructing a weighted undirected graph of the predicted element link probabilities to obtain a preliminary topological structure; Step S342: filtering weak links on the preliminary topology structure to generate a strong link topology structure; Step S343: Performing connectivity analysis on the strong link topology structure to obtain the maximum connected component; Step S344: identifying key subgraphs of the preliminary topological structure based on the maximum connected component to obtain key subgraphs; Step S345: performing betweenness centrality analysis on the key subgraph to obtain key link data; performing degree centrality analysis on the key subgraph according to the key link data to generate key node data; Step S346: Perform component link relationship topology analysis on the device main feature matrix based on the key link data and the key node data to generate component link relationships.

8. The device simulation method for integrated circuit according to claim 1, characterized in that: Step S4 includes the following steps: Step S41: grouping the device main feature matrix into integrated modules according to the device hierarchy to obtain integrated circuit module feature data; Step S42: Arrange virtual circuit connections for component link relationships to generate virtual connection circuits; Step S43: performing circuit device simulation driving processing on the integrated circuit module characteristic data and the virtual connection circuit to obtain a simulation circuit device unit.

9. The device simulation method for integrated circuit according to claim 1, characterized in that: Step S5 includes the following steps: Step S51: extracting device location from integrated circuit device data to obtain circuit device layout location; Step S52: performing circuit integration simulation on the simulation circuit device unit based on the circuit device layout positioning to obtain a simulated integrated circuit; Step S53: constructing a simulation environment field for the analog integrated circuit to generate a simulation circuit working environment field; Step S54: simulating the circuit operation of the simulated integrated circuit according to the simulated circuit operation environment field, and monitoring the performance of each device in the circuit to obtain circuit device performance data; Step S55: When the circuit device performance data is less than a preset circuit device performance threshold, defective device optimization is performed on the simulated circuit device unit based on the circuit device performance data to obtain optimized integrated circuit device data.

10. The device simulation method for integrated circuit according to claim 9, characterized in that: Optimizing defective devices for simulated circuit device units based on circuit device performance data includes the following steps: Adjusting the initial compensation parameters of the circuit device performance data according to the preset standard device performance data to obtain initial compensation data; Perform differential evolution analysis on the initial compensation data to generate candidate compensation data; Perform particle swarm optimization local search on candidate compensation data to obtain local optimized candidate compensation data; Performing post-compensation performance evaluation on simulation circuit device units based on local optimization candidate compensation data to generate local compensation performance results; Using the local compensation performance results, the search parameters of the candidate compensation data are adjusted to obtain optimized adjusted search parameters; Repeat the above steps until the local compensation performance result is greater than or equal to the preset standard device performance data; The defective device of the simulation circuit device unit is optimized according to the local compensation performance result to obtain the optimized integrated circuit device data.

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