Method and device for interconnection line evaluation and storage medium

Abstract

The embodiment of the invention provides an interconnection line evaluation method and device and a storage medium. The method comprises the following steps: acquiring an interconnection line network corresponding to a circuit structure of a target chip, wherein the interconnection line network comprises a plurality of nodes and a plurality of interconnection lines connected with the plurality of nodes; and based on the steady state stress of the plurality of nodes, determining the first interconnection line service life of the plurality of interconnection lines. In this way, the accuracy, reliability and efficiency of chip life prediction can be improved.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to methods, devices, and storage media for interconnect evaluation. Background Art

[0002] Chip interconnects are an important component of ultra-large-scale integrated circuit chips. They connect the chip's external power supply to the chip's core logic circuits and transmit energy and signals to the chip. Currently, copper is commonly used as the interconnect material in chip manufacturing processes. However, metal interconnects will undergo electromigration under long-term current drive, that is, metal atoms diffuse and accumulate toward the high-voltage end of the interconnect under the action of current, leaving vacancies at the low-voltage end. When the accumulation or vacancies reach a certain level, the interconnect will short or open. When the number of interconnect failures accumulates to a certain level, the entire chip will fail. With the reduction in the feature size of integrated circuits and the increase in device density, the size of interconnects has also decreased. The current chip electromigration assessment method can no longer meet the needs of chip design and manufacturing. Summary of the invention

[0003] In a first aspect of the present disclosure, a method for interconnection line evaluation is provided. The method comprises: obtaining an interconnection line network corresponding to a circuit structure of a target chip, the interconnection line network comprising a plurality of nodes and a plurality of interconnections connecting the plurality of nodes; and determining a first interconnection line life of each of the plurality of interconnections based on a steady-state stress of each of the plurality of nodes.

[0004] In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor and a memory coupled to the processor. The memory has instructions stored therein, and when the instructions are executed by the processor, the electronic device executes the method according to the first aspect of the present disclosure.

[0005] In a third aspect of the present disclosure, a computer-readable storage medium is provided. The computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the method according to the first aspect of the present disclosure is implemented.

[0006] It will be understood from the following description that according to an embodiment of the present disclosure, an interconnection network corresponding to a circuit structure of a target chip is obtained, the interconnection network includes a plurality of nodes and a plurality of interconnections connecting the plurality of nodes; and based on the steady-state stress of each of the plurality of nodes, the first interconnection life of each of the plurality of interconnections is determined. In this way, the physical steady-state stress of the node and the interconnection network of the chip can be used to determine the interconnection life, thereby improving the accuracy, reliability and efficiency of estimating the chip life.

[0007] It should be understood that the contents described in the summary of the present invention are not intended to limit the key features or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0009] Figure 1 A schematic diagram showing an example environment in which various embodiments of the present disclosure can be implemented;

[0010] Figure 2 A flow chart showing a method for interconnect line evaluation according to some embodiments of the present disclosure is shown;

[0011] Figure 3 A schematic diagram showing an example of a connection method of nodes and interconnection lines according to some embodiments of the present disclosure;

[0012] Figure 4 A flowchart showing an example of a method for determining interconnect lifetime according to some embodiments of the present disclosure;

[0013] Figure 5 A schematic diagram showing an example of a percentage relationship between chip life and number of samples according to some embodiments of the present disclosure;

[0014] Figure 6 A schematic diagram showing an example of the relationship between chip life and cumulative probability according to some embodiments of the present disclosure;

[0015] Figure 7 A flowchart showing an example of a method of determining the lifetime of a segment of an interconnect according to some embodiments of the present disclosure; and

[0016] Figure 8 A block diagram of an electronic device is shown in which one or more embodiments of the present disclosure may be implemented. DETAILED DESCRIPTION

[0017] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0018] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0019] As briefly mentioned above, as the feature size of integrated circuits decreases and the device density increases, the size of interconnects also decreases, and the current chip electromigration evaluation methods can no longer meet the needs of chip design and manufacturing.

[0020] According to some traditional solutions, the life of each interconnection line in the chip interconnection network can be calculated, and the minimum life is taken as the final predicted life of the entire chip. However, the interconnection lines of the chip usually adopt a redundant network structure to improve the reliability of the chip interconnection lines. Even if a few interconnection lines in the interconnection network fail, it will not cause the failure of the entire chip.

[0021] Since the above life calculation scheme does not take into account the actual network structure of the interconnection lines, it will make an overly conservative prediction of the chip life, resulting in the need for repeated iterations of chip design to modify the geometric parameters of the interconnection lines, increase the number of through holes, etc. in order to achieve the expected chip life. This increases the difficulty of design and manufacturing, and may even make it difficult for the chip design to pass the final sign-off, affecting the tape-out progress.

[0022] According to some conventional solutions, a method for calculating the lifetime of an interconnect line based on a transient physical model may be used to estimate the lifetime of the interconnect line by establishing a stress balance physical model within the interconnect line and solving differential equations.

[0023] Although the above scheme takes into account the actual interconnect network structure, it needs to solve differential equations, which has low computational efficiency and is difficult to meet the needs of electromigration failure assessment of large-scale chips.

[0024] To this end, an embodiment of the present disclosure proposes a chip interconnection line electromigration failure assessment method. According to an embodiment of the present disclosure, an interconnection line network corresponding to a circuit structure of a target chip is obtained, and the interconnection line network includes a plurality of nodes and a plurality of interconnections of the plurality of nodes. Further, based on the steady-state stress of each of the plurality of nodes, the first interconnection line life of each of the plurality of interconnections is determined.

[0025] According to the embodiments of the present disclosure, when determining the interconnection life of the interconnection line, the interconnection line network corresponding to the circuit structure of the target chip is taken into account, so that the predicted interconnection line is closer to the actual result. At the same time, the steady-state stress on the nodes in the interconnection line network is also taken into account, so that the solution of differential equations is avoided, thereby improving the accuracy, reliability and efficiency of the interconnection line life prediction.

[0026] Various example implementations of the scheme will be described in detail below with reference to the accompanying drawings.

[0027] See first Figure 1 , which shows a schematic diagram of an example environment 100 in which various embodiments of the present disclosure can be implemented. The example environment 100 may generally include an electronic device 110.

[0028] like Figure 1 As shown, the electronic device 110 obtains the interconnection network file 131 of the chip to be processed 130 as input. In some embodiments, the interconnection network file 131 may be an interconnection network netlist file (netlist file), or an interconnection network layout file (GDS file).

[0029] In some embodiments, the electronic device 110 may also interact with a client (not shown). For example, the electronic device 110 may receive an input message from the client and output a feedback message to the client. In some embodiments, the input message from the client may specify the number of chips, the interconnection network file 131 of the chip, etc. The electronic device 110 may analyze the number of chips specified in the input message, the interconnection network file 131 of the chip, etc., for example, perform simulation calculations based on the interconnection network of the chip to determine the chip life 140 of the chip.

[0030] In some embodiments, the external power source 120 can supply power to the chip 130 to be processed while the electronic device 110 is calculating the chip life 140 of the chip 130 to be processed.

[0031] In the example environment 100, the electronic device 110 can be any type of device with computing capabilities, including a terminal device or a server device. The terminal device can be any type of mobile terminal, fixed terminal or portable terminal, including a mobile phone, a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet computer, a media computer, a multimedia tablet, a personal communication system (PCS) device, a personal navigation device, a personal digital assistant (PDA), an audio / video player, a digital camera / camcorder, a positioning device, a television receiver, a radio broadcast receiver, an e-book device, a gaming device, or any combination of the foregoing, including accessories and peripherals of these devices or any combination thereof. The server device can include, for example, a computing system / server, such as a mainframe, an edge computing node, a computing device in a cloud environment, and the like.

[0032] It should be understood that the structure and function of the environment 100 are described for exemplary purposes only, and do not imply any limitation on the scope of the present disclosure. Example embodiments according to the present disclosure will be described in detail below with reference to the accompanying drawings.

[0033] Figure 2 FIG. 2 is a flow chart of a method 200 for interconnect evaluation according to some embodiments of the present disclosure. In some embodiments, the method 200 may be performed as follows: Figure 1 The electronic device 110 shown executes. It should be understood that the method 200 may further include additional blocks not shown and / or may omit one (or some) of the blocks shown, and the scope of the present disclosure is not limited in this respect.

[0034] In block 210, the electronic device 110 obtains an interconnection network corresponding to the circuit structure of the target chip. The interconnection network includes a plurality of nodes and a plurality of interconnections connecting the plurality of nodes, wherein the plurality of nodes indicate contact points or end points of a predetermined type in the circuit structure.

[0035] In some embodiments, the electronic device 110 may obtain an interconnection network file for representing the circuit structure of the target chip, such as an interconnection network netlist file or an interconnection network layout file. The electronic device 110 may then generate an interconnection network corresponding to the circuit structure of the target chip based on the interconnection network file.

[0036] For example, the upper and lower ends of the through-holes in the interconnect network in the interconnect network netlist file or the interconnect network layout file, the contact points connected to the external power supply 120, and the contact points connected to the core circuit layer of the chip can be equivalent to nodes. The resistance value of the interconnect between the nodes can be equivalent to the resistance in the interconnect network. The connected external power supply 120 can be used as the power supply in the interconnect network, and the node connected to the external power supply 120 is connected to the interconnect network. The core logic layer of the chip can be simplified to an equivalent current source, by connecting the nodes of the core logic circuit layer of the chip to the interconnect network. Thus, the interconnect network corresponding to the chip circuit structure can be obtained.

[0037] In some embodiments, the chip is generally a multi-layer stacked structure, and the electronic device 110 can split the interconnect network into one or more interconnect networks corresponding to each layer of the structure based on the hierarchical structure of the chip. Furthermore, the electronic device 110 can further split the interconnect network corresponding to each layer of the structure based on the circuit structure of each layer in the chip to obtain one or more sub-interconnect networks. In this article, "sub-interconnect network" is sometimes also referred to as an "interconnect tree".

[0038] In some embodiments, the electronic device 110 can further split the interconnection network corresponding to each layer structure using a breadth-first method. Alternatively or additionally, the interconnection network can be represented in the form of a graph structure, for example, nodes in the interconnection network can be represented as nodes in the graph structure, and interconnections in the interconnection network can be represented as edges in the graph structure. Accordingly, the interconnection tree can also be represented in the form of a graph structure.

[0039] In the embodiment of the present disclosure, there are no common nodes between different interconnection line trees, and when the interconnection line tree is represented in the form of a graph structure, the interconnection line tree may be a connected graph.

[0040] In some embodiments, the electronic device 110 may use a random number generator to randomly generate a random number for each interconnection line in a target chip within a predetermined numerical range as a random sample of a target chip, that is, the number of generated random numbers is the same as the number of interconnections in the target chip. Alternatively or additionally, the predetermined numerical range may be 0 to 1, and the random number generation method may be to uniformly generate random numbers within the numerical range of 0 to 1.

[0041] It should be noted that the method for determining the number of random samples will be introduced below and will not be repeated here.

[0042] At block 220 , the electronic device 110 determines first interconnect lifespans of respective ones of the plurality of interconnects based on respective steady-state stresses of the plurality of nodes.

[0043] It should be understood that since there are multiple nodes and multiple interconnects connecting the multiple nodes in the interconnect network, each node may be connected to one or more interconnects, and therefore, the steady-state stress at each node may include compressive stress and tensile stress. Since the directions of compressive stress and tensile stress are different, positive and negative signs may be used to represent the direction of tensile stress and the direction of compressive stress, respectively. For example, in this article, positive steady-state stress is taken as tensile stress, and negative steady-state stress is taken as compressive stress.

[0044] Next, the method for determining the steady-state stress at a node in an interconnect network is described. Figure 3 , Figure 3 An example of the connection mode of nodes and interconnection lines according to some embodiments of the present disclosure is shown. It should be understood that the determination mode of the steady-state stress at other nodes is the same as the determination mode of the steady-state stress at this node.

[0045] like Figure 3 As shown, interconnection lines 320 , 330 , and 340 are connected to node 310 , and electronic device 110 may determine the steady-state stress at node 310 based on the voltage value at node 310 and the voltage values ​​at nodes at both ends of interconnection lines 320 , 330 , and 340 .

[0046] For example, the electronic device 110 may determine the steady-state stress at a node by the following formula:

[0047]

[0048] Among them, σ i is the stress value at node i, Z * is the equivalent charge number of the interconnect, e is the charge of a single electron, Ω is the single atom volume of the interconnect, j∈Tree i Represents the interconnection tree containing node i i All interconnected line segments j in A j and l j are the cross-sectional area and length of the interconnection segment j, and are the voltage values ​​at both ends of the interconnection line segment j, V i is the voltage value at node i. It should be understood that, except for the voltage value, the parameters in the above formula can be calibrated by experiments.

[0049] In some embodiments, the voltage value at each node in the interconnect network can be determined by using nodal analysis, modified nodal analysis, etc. Of course, other appropriate methods can also be used to determine the voltage at the node, which is not limited by the embodiments of the present disclosure.

[0050] Thus, the electronic device 110 can determine the voltage values ​​of each of the multiple nodes in the interconnection network, and determine the steady-state stress of each of the multiple nodes based on the voltage values ​​of each of the multiple nodes.

[0051] In the embodiment of the present disclosure, determining the first interconnection life of the interconnection can be divided into two cases: a case where there are failed interconnections in the interconnection network and a case where there are no failed interconnections in the interconnection network.

[0052] Next, the method for determining the first interconnection life of the interconnection by the electronic device 110 when there is a failed interconnection in the interconnection network is first introduced. Figure 4 , Figure 4 An example of a method 400 for determining the lifetime of an interconnect according to some embodiments of the present disclosure is shown. In some embodiments, the method 400 may be performed as follows: Figure 1 The electronic device 110 is shown to perform.

[0053] At block 410 , the electronic device 110 may update the interconnect network based on the failed interconnect in response to determining that a failed interconnect exists in the interconnect network.

[0054] Under long-term current drive, the interconnect will undergo electromigration, that is, metal atoms diffuse and accumulate toward the high voltage end of the interconnect under the action of current, leaving vacancies at the low voltage end. When the accumulation or vacancies reach a certain level, the interconnect will be short-circuited or open-circuited. A failed interconnect is an interconnect with a short circuit or open circuit. Alternatively, the interconnect with the shortest lifespan among all the interconnects in the interconnect network can be regarded as a failed interconnect.

[0055] In some embodiments, the electronic device 110 may remove the failed interconnection line from the interconnection line network, and update the interconnection line network after removing the failed interconnection line based on the circuit structure of the chip.

[0056] At block 420 , the electronic device 110 may determine steady-state stresses of respective nodes in the updated interconnect network based on respective first voltage values ​​of the plurality of nodes in the updated interconnect network.

[0057] It should be understood that the electronic device 110 determines the first voltage value of each of the multiple nodes in the updated interconnect network, and determines the steady-state stress of each of the multiple nodes in the updated interconnect network in the same way as the above-mentioned method of determining the voltage value and steady-state stress at a node, which will not be repeated here.

[0058] At block 430 , the electronic device 110 may determine a first average interconnect lifespan of each of the plurality of interconnects in the updated interconnect network based on the first current value of each of the plurality of interconnects in the updated interconnect network.

[0059] In some embodiments, the first current value of each of the plurality of interconnections in the updated interconnection network may also be determined by using a nodal analysis method, a modified nodal analysis method, etc. Of course, other appropriate methods may also be used to determine the current value at the interconnection, which is not limited by the embodiments of the present disclosure.

[0060] Taking determining a first average interconnection life of an interconnection as an example, the electronic device 110 can determine the first average interconnection life of the interconnection by the following formula:

[0061]

[0062] Where MTTF is the mean-time-to-failure life of the interconnect, A is the cross-sectional area of ​​each interconnect to be evaluated, C and n are calibration parameters obtained by calibration of experimental data, J is the current density on the interconnect, and E is the a is the activation energy of electromigration of interconnects, k b is the Boltzmann constant, T m is the temperature of the environment in which the interconnection line is located when the chip is working. It should be understood that, except for the current density on the interconnection line, the parameters in the above formula can be calibrated by experiment.

[0063] In some embodiments, the current density on the interconnect line may be determined based on the current value on the interconnect line and the cross-sectional area of ​​the interconnect line.

[0064] At block 440 , the electronic device 110 may determine a first interconnect lifetime of each of a plurality of interconnects in the updated interconnect network based on the steady-state stress, the first average interconnect lifetime, the second interconnect lifetime, and the lifetime of the failed interconnect.

[0065] Here, the second interconnection line lifetime indicates lifetimes of a plurality of interconnections in the interconnection line network before updating.

[0066] In some embodiments, the electronic device 110 may determine the minimum lifetime value among the second interconnection lifetimes of the plurality of interconnections in the interconnection network before updating as the lifetime of the failed interconnection.

[0067] In some embodiments, the electronic device 110 determines the first interconnect life of each of the multiple interconnects in the updated interconnect network, which may include: 1) the electronic device 110 determines the first interconnect life of the multiple interconnects in the updated interconnect network based on the life of the failed interconnect, the second interconnect life, and the first average interconnect life in response to determining that the steady-state stress is greater than the steady-state stress threshold.

[0068] For example, in this case, the electronic device 110 may determine the lifetime of the first interconnection line by the following formula:

[0069]

[0070]

[0071] The upper index k represents the number of failed interconnection segments in the interconnection network, and the lower index j represents the interconnection line. is the lifetime (time-to-failure) of interconnect j when there are k failed interconnect segments in the interconnect network, T k is the time when the kth failed interconnection line appears in the interconnection network, is the absolute value of the tensile stress in the steady-state stress of the nodes at both ends of interconnect j when there are k failed interconnect segments in the interconnect network, σ c is the absolute value of the tensile stress threshold, η j is the random number of interconnect j generated by the random number generator, is the logarithmic variance of the interconnect life following the log-normal distribution, J is the current density on the interconnect, E a is the activation energy of electromigration of interconnects, k b is the Boltzmann constant, T m is the temperature of the interconnection line. A random sample of the target chip corresponds to a set of random numbers, and the number of random numbers in the set of random numbers is the same as the number of interconnection line segments in the target chip.

[0072] Additionally, or alternatively, in some embodiments, the electronic device 110 determining the first interconnect lifetime of each of the multiple interconnects in the updated interconnect network may include: 2) the electronic device 110 determines the first interconnect lifetime of the multiple interconnects in the updated interconnect network based on the lifetime of the failed interconnect and the second interconnect lifetime in response to determining that the steady-state stress is less than or equal to a steady-state stress threshold.

[0073] For example, in this case, the electronic device 110 may determine the lifetime of the first interconnection line by the following formula:

[0074]

[0075] The upper index k represents the number of failed interconnection segments in the interconnection network, and the lower index j represents the interconnection line. is the lifetime (time-to-failure) of interconnect j when there are k failed interconnect segments in the interconnect network, T k is the time when the kth failed interconnection line appears in the interconnection network, is the absolute value of the tensile stress in the steady-state stress of the nodes at both ends of interconnect j when there are k failed interconnect segments in the interconnect network, σ c is the absolute value of the tensile stress threshold, η j is the random number of interconnect j generated by the random number generator, is the logarithmic variance of the interconnect life following the log-normal distribution, J is the current density on the interconnect, E a is the activation energy of electromigration of interconnects, k b is the Boltzmann constant, T m is the temperature of the interconnection line. A random sample of the target chip corresponds to a set of random numbers, and the number of random numbers in the set of random numbers is the same as the number of interconnection line segments in the target chip.

[0076] The above lists two exemplary methods 1) and 2 for the electronic device 110 to determine the first interconnection life of each of the plurality of interconnections in the updated interconnection network. In some embodiments, any one of the above two methods or a combination of the two methods can be selected to determine the first interconnection life. It should be understood that when determining the steady-state stress and the steady-state stress threshold at each node, that is, determining whether the absolute value of the steady-state stress of the interconnection is greater than the absolute value of the steady-state stress threshold, that is, whether there is a positive integer p such that σ k-p >σ c , thereby determining TTF k The calculation formula is whether to use the formula in 1) or the formula in 2), wherein the value of k can be 0 to the total number of failed interconnects in the chip when the final chip fails.

[0077] In some embodiments, the electronic device 110 may determine the failed interconnect in the updated interconnect network based on the first interconnect lifetimes of the plurality of interconnects in the updated interconnect network. For example, the electronic device 110 may determine the minimum lifetime value among the first interconnect lifetimes of the plurality of interconnects in the updated interconnect network as the lifetime of the failed interconnect.

[0078] Next, the electronic device 110 determines the first interconnection lifespan of the interconnection when there is no failed interconnection in the interconnection network.

[0079] Specifically, in response to determining that there is no failed interconnection in the interconnection network, the electronic device 110 determines a second current value for each of the plurality of interconnections. Further, based on the second current value, a second average interconnection life for each of the plurality of interconnections is determined. Further, based on the steady-state stress and the second average interconnection life, a first interconnection life for each of the plurality of interconnections is determined.

[0080] For example, the electronic device may use the following formula to determine the lifetime of the first interconnection line of each of the plurality of interconnections:

[0081]

[0082] Among them, TTF 0 is the lifetime of the interconnect when there is no failed interconnect segment in the interconnect network, σ 0 is the absolute value of the tensile stress in the steady-state stress of the nodes at both ends of the interconnect when there is no failed interconnect segment in the interconnect network, σ c is the absolute value of the tensile stress threshold, η is the random number of the interconnect generated by the random number generator, is the logarithmic variance of the interconnect life following a log-normal distribution, MTTF 0 is the average life of the interconnect when there is no failed interconnect in the interconnect network.

[0083] It should be understood that the determination method of the second current value and the second average interconnection line life can refer to the determination method of the first current value and the first average interconnection line life, which will not be repeated here.

[0084] In some embodiments, the electronic device 110 may also determine the chip lifetime of a random sample of the target chips based on the first interconnection line lifetime.

[0085] In some embodiments, when the electronic device 110 determines the chip lifetime of a random sample of target chips based on the first interconnection lifetime, the minimum lifetime value among the first interconnection lifetimes of multiple interconnections may be determined as the chip lifetime of a random sample of the target chip.

[0086] In this way, when determining the chip life of a random sample of target chips, the interconnection network corresponding to the circuit structure of the target chip is taken into account, so that the predicted chip life is closer to the actual result. At the same time, the steady-state stress on the nodes in the interconnection network is also taken into account, which avoids solving differential equations, thereby improving the accuracy, reliability and efficiency of chip life prediction.

[0087] As mentioned above, the electronic device 110 can generate multiple random samples for the target chip using a random number generator. In some embodiments, the electronic device 110 can determine the respective chip lifespans for the multiple random samples, determine the standard deviation and the average value of the chip lifespans of the multiple random samples based on the respective chip lifespans of the multiple random samples, and then determine the target number of random samples that meet the statistical requirements based on the standard deviation and the average value, and in response to the number of the multiple random samples being greater than or equal to the target number, perform statistics on the chip lifespans of the multiple random samples.

[0088] In some embodiments, the electronic device 110 increases the number of random samples in response to the number of the multiple random samples being less than the target number, and re-determines the number corresponding to the increased random samples until the number of the increased random samples is greater than or equal to the target number. In some embodiments, when the number of the multiple random samples is less than the target number, the electronic device 110 may generate new random samples for the target chip using a random number generator to increase the number of random samples.

[0089] For example, the target number may be determined based on the following formula:

[0090]

[0091] Among them, N is the target number, θ is the corresponding Percentage coordinate value, s N is the sample standard deviation when the sample size is N, is the average value of sample life when the number of samples is N, and ∈ is the upper limit of the deviation between the estimated value of the average chip life and the actual chip life.

[0092] When the number of random samples of target chips is greater than the target number, the confidence level that the upper limit of the deviation between the estimated value of the average life of the target chips and the true chip life is less than ∈ is (1-α)×100%.

[0093] For example, the statistical results of the chip life of multiple random samples of the target chip can refer to Figure 5 and Figure 6 . Figure 5 An example of a percentage relationship 500 of chip lifetime and number of samples according to some embodiments of the present disclosure is shown. Figure 6 An example of a relationship 600 between chip lifetime and cumulative probability according to some embodiments of the present disclosure is shown. Figure 5 In the figure, the darker left portion 510 represents the statistical result of the chip life obtained by the traditional method, and the lighter right portion 520 represents the statistical result of the chip life obtained by the method provided in the embodiment of the present disclosure. Figure 6 In the figure, the darker left half 610 represents the statistical result of the chip life obtained by the traditional method, and the lighter right half 620 represents the statistical result of the chip life obtained by the method provided by the embodiment of the present disclosure. In this way, the chip life can be predicted based on the statistical method and the above-mentioned method for determining the chip life, so that the prediction result has statistical accuracy, thereby making the prediction result more reliable.

[0094] In some embodiments, the target chip may be one of a group of chips in a plurality of groups of chips, and each group of chips may include one or more target chips. Therefore, the electronic device 110 may respectively determine the chip life of each chip in each group of chips in the above manner, and perform statistics on the chip life of the plurality of groups of chips for full chip electromigration failure assessment of large-scale chips, for example, chip design sign-off, manufacturing layout verification, etc.

[0095] In some embodiments, the method for evaluating interconnects disclosed herein can be combined with a traditional method, so that a user can set a chip failure threshold between the chip lifespans obtained by the two methods according to actual chip design and manufacturing requirements, thereby providing the user with more options.

[0096] The method for evaluating an interconnection line according to the present disclosure can also be used to determine the life of an interconnection line. Figure 7 , Figure 7 An example of a method 700 for determining the lifetime of a segment of an interconnect according to some embodiments of the present disclosure is shown. In some embodiments, the method 700 may be performed by Figure 1 The electronic device 100 shown performs.

[0097] In box 710, the electronic device 110 can determine the steady-state stress of each node on the interconnect tree where the interconnect is located based on the voltage of the node on the interconnect tree. In box 720, the electronic device 110 can determine the method of calculating the interconnect life of the interconnect based on the steady-state stress of each node on the interconnect tree. In box 730, the electronic device 110 can determine the life of the interconnect based on the current of the interconnect and the life of the failed interconnect in the interconnect tree. It should be understood that the implementation process of the above steps can refer to the relevant process in the aforementioned embodiment, which will not be repeated here.

[0098] In this way, the life of each interconnection line can be determined by taking into account the interconnection line network corresponding to the circuit structure of the chip and the tensile stress of the nodes in the connection network, thereby accurately predicting the life of the interconnection line and the life of the chip.

[0099] Figure 8 8 is a block diagram of a server or electronic device 800 in which one or more embodiments of the present disclosure may be implemented. The electronic device 800 may be used to implement, for example, Figure 1 The electronic device 110 shown. It should be understood that Figure 8 The electronic device 800 shown is merely exemplary and should not constitute any limitation on the functionality and scope of the embodiments described herein.

[0100] like Figure 8As shown, the electronic device 800 is in the form of a general electronic device. The components of the electronic device 800 may include, but are not limited to, one or more processors 810 or processing units, a memory 820, a storage device 830, one or more communication units 840, one or more input devices 850, and one or more output devices 860. The processing unit may be an actual or virtual processor and is capable of performing various processes according to a program stored in the memory 820. In a multi-processor system, multiple processing units execute computer executable instructions in parallel to improve the parallel processing capability of the electronic device 800.

[0101] The electronic device 800 typically includes a plurality of computer storage media. Such media may be any available media accessible to the electronic device 800, including but not limited to volatile and non-volatile media, removable and non-removable media. The memory 820 may be a volatile memory (e.g., a register, a cache, a random access memory (RAM)), a non-volatile memory (e.g., a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. The storage device 830 may be a removable or non-removable medium, and may include a machine-readable medium, such as a flash drive, a disk, or any other medium, which may be capable of being used to store information and / or data (e.g., training data for training) and may be accessed within the electronic device 800.

[0102] The electronic device 800 may further include additional removable / non-removable, volatile / non-volatile storage media. Figure 8 As shown in , a disk drive for reading or writing from a removable, non-volatile disk (e.g., a "floppy disk") and an optical drive for reading or writing from a removable, non-volatile optical disk may be provided. In these cases, each drive may be connected to the bus (not shown) by one or more data media interfaces. The memory 820 may include a computer program product 825 having one or more program modules that are configured to perform various methods or actions of various embodiments of the present disclosure.

[0103] The communication unit 840 implements communication with other electronic devices through a communication medium. Additionally, the functions of the components of the electronic device 800 can be implemented with a single computing cluster or multiple computing machines that can communicate through a communication connection. Therefore, the electronic device 800 can operate in a networked environment using a logical connection with one or more other servers, a network personal computer (PC), or another network node.

[0104] The input device 850 may be one or more input devices, such as a mouse, a keyboard, a tracking ball, etc. The output device 860 may be one or more output devices, such as a display, a speaker, a printer, etc. The electronic device 800 may also communicate with one or more external devices (not shown) through the communication unit 840 as needed, such as a storage device, a display device, etc., communicate with one or more devices that allow a user to interact with the electronic device 800, or communicate with any device that allows the electronic device 800 to communicate with one or more other electronic devices (e.g., a network card, a modem, etc.). Such communication may be performed via an input / output (I / O) interface (not shown).

[0105] According to an exemplary implementation of the present disclosure, a computer-readable storage medium is provided, on which one or more computer instructions are stored, wherein the one or more computer instructions are executed by a processor to implement the method described above.

[0106] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products implemented according to the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0107] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processing unit of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0108] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0109] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple implementations of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of a module, program segment or instruction includes one or more executable instructions for realizing the logical function of the specification. In some implementations as replacements, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be realized by a special hardware-based system that performs the function or action of the specification, or can be realized by a combination of special hardware and computer instructions.

[0110] The above descriptions of various implementations of the present disclosure are exemplary, non-exhaustive, and not limited to the disclosed implementations. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described implementations. The selection of terms used herein is intended to best explain the principles of the implementations, practical applications, or improvements to the technology in the marketplace, or to enable other persons of ordinary skill in the art to understand the implementations disclosed herein.

Claims

1. A method for interconnect evaluation, characterized in that include: Acquire an interconnection line network corresponding to the circuit structure of the target chip, wherein the interconnection line network includes a plurality of nodes and a plurality of interconnections connecting the plurality of nodes; as well as Based on the steady-state stresses of the plurality of nodes, first interconnect lifespans of the plurality of interconnects are determined.

2. The method for interconnection line evaluation according to claim 1, characterized in that The method further comprises: In response to determining that a failed interconnect line exists in the interconnect line network, updating the interconnect line network based on the failed interconnect line; and Based on the updated first voltage values ​​of the respective multiple nodes in the interconnect network, steady-state stresses of the respective multiple nodes in the updated interconnect network are determined.

3. The method for interconnection line evaluation according to claim 2, characterized in that: Determining the steady-state stress of each of the plurality of nodes in the updated interconnect network based on the first voltage value of each of the plurality of nodes in the updated interconnect network includes: For a node among the multiple nodes in the updated interconnection line network, the steady-state stress of the node is determined based on the first voltage value of the node and the first voltage values ​​of nodes at both ends of the interconnection line connected to the node.

4. The method for interconnection line evaluation according to claim 2, characterized in that: Determining a first interconnection line life of each of the plurality of interconnections based on the respective steady-state stresses of the plurality of nodes comprises: Determining a first average interconnect life of each of the plurality of interconnects in the updated interconnect network based on the first current value of each of the plurality of interconnects in the updated interconnect network; and The first interconnect lifetime of each of a plurality of interconnects in the updated interconnect network is determined based on the steady-state stress, the first average interconnect lifetime, a second interconnect lifetime, and the lifetime of the failed interconnect, wherein the second interconnect lifetime indicates the lifetime of a plurality of interconnects in the interconnect network before updating.

5. The method for interconnection line evaluation according to claim 4, characterized in that: Determining the first interconnect lifetime of each of a plurality of interconnects in the updated interconnect network based on the steady-state stress, the first average interconnect lifetime, the second interconnect lifetime, and the lifetime of the failed interconnect comprises at least one of the following: In response to determining that the steady-state stress is greater than a steady-state stress threshold, determining the first interconnect lifetime of each of a plurality of interconnects in the updated interconnect network based on the lifetime of the failed interconnect, the second interconnect lifetime, and the first average interconnect lifetime; as well as In response to determining that the steady-state stress is less than or equal to the steady-state stress threshold, the first interconnect lifetime of each of a plurality of interconnects in the updated interconnect network is determined based on the lifetime of the failed interconnect and the second interconnect lifetime.

6. The method for interconnection line evaluation according to claim 4, characterized in that: The lifetime of the failed interconnect is determined as follows: The minimum lifespan value among the second interconnection line lifespans of the plurality of interconnections in the interconnection line network before updating is determined as the lifespan of the failed interconnection line.

7. The method for interconnection line evaluation according to claim 1, characterized in that: Determining a first interconnection line life of each of the plurality of interconnections based on the respective steady-state stresses of the plurality of nodes comprises: In response to determining that no failed interconnects exist in the network of interconnects, determining a second current value for each of the plurality of interconnects; determining a second average interconnect life of each of the plurality of interconnects based on the second current value; and The first interconnect lifetime of each of the plurality of interconnects is determined based on the steady-state stress and the second average interconnect lifetime.

8. The method for interconnection line evaluation according to claim 1, characterized in that: The method further comprises: Based on the first interconnection line lifetime, a chip lifetime of the target chip is determined.

9. The method for interconnection line evaluation according to claim 8, characterized in that: The method further comprises: Acquire multiple random samples of the target chip; Determine the chip lifespans for each of the plurality of random samples; Determining a standard deviation and an average of the chip lifespans of the plurality of random samples based on the respective chip lifespans of the plurality of random samples; determining a target number based on the standard deviation and the mean; and In response to the number of the plurality of random samples being greater than or equal to the target number, statistics are collected on the chip lifespan of each of the plurality of random samples.

10. The method for interconnection line evaluation according to claim 9, characterized in that: Also includes: In response to the number of the plurality of random samples being less than the target number, increasing the number of the plurality of random samples; as well as The target number corresponding to the increased plurality of random samples is determined again until the number of the increased plurality of random samples is greater than or equal to the target number.

11. The method for interconnection line evaluation according to claim 1, characterized in that: The plurality of nodes indicate predetermined types of contact points or endpoints in the circuit structure.

12. An electronic device, characterized in that: include: at least one processing unit; as well as At least one memory, the at least one memory being coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, the instructions causing the electronic device to perform the method according to any one of claims 1 to 11 when executed by the at least one processing unit.

13. A computer-readable storage medium, characterized in that: A computer program is stored thereon, characterized in that the computer program can be executed by a processor to implement the method according to any one of claims 1 to 11.

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