OPC verification method
By conducting regional division and layered inspection of the layout, the existing OPC verification methods are solved, and the inspection efficiency and product yield are improved.
Patent Information
- Application Number
- CN202411215443.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2024-12-13
AI Technical Summary
The existing OPC verification methods are difficult to efficiently identify layout design problems and OPC correction abnormalities, especially under large chip sizes, which are prone to missed design abnormalities, affecting product yield.
By dividing the layout area, the figure is divided into sub-rules and regular figures, and OPC verification is performed separately. Layered inspection and model fitting errors are used to determine the error tolerance, and error tolerances are set independently to improve inspection efficiency.
It realizes timely detection of layout design problems and OPC correction abnormalities, avoids omissions, and improves product yield and inspection efficiency, especially under large chip sizes.
Smart Images
Figure CN119129520A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor integrated circuit manufacturing method, and in particular to an optical proximity correction (OPC) verification method. Background Art
[0002] As the size of layout design continues to decrease, the optical proximity effect may result in the inability to obtain the desired pattern on the wafer, and the OPC technology must be used to solve this problem.
[0003] In the existing conventional OPC verify, the logic and SRAM areas are first distinguished, and each area needs to be checked for common check items such as pinch and bridge of the critical dimension (CD). Different areas have different error tolerances due to different design rules. However, the verify warning results of the existing methods cannot efficiently identify the design problem points of the sub-rule graphics in the logic area or SRAM area and the high-risk points caused by the inadequate OPC correction of the on-rule graphics during the review, which is not conducive to timely discovering layout design problems and OPC correction abnormalities, affecting the final product yield, especially when the number of errors reported for large chips is large, it is easier to miss layout design abnormalities and high-risk points caused by design abnormalities or unoptimized OPC recipe settings. Summary of the invention
[0004] The technical problem to be solved by the present invention is to provide an OPC verification method, which can enhance the efficient inspection of layout anomalies and the inspection of OPC correction anomalies, so that layout design problems and OPC correction anomalies can be discovered in time without omissions, thereby improving product yield and improving inspection efficiency when the chip size is large.
[0005] To solve the above technical problems, the OPC verification method provided by the present invention comprises the following steps:
[0006] Step 1: Divide the map into regions and obtain the selected regions.
[0007] Step 2: Differentiate the patterns in the selected area based on design rules to divide the patterns into subrule patterns and on rule patterns.
[0008] Step three: marking the sub-regular graphic to form a sub-regular graphic mark.
[0009] A halo region with a first diameter is formed by taking the center of the sub-regular pattern mark as the origin and the halo region is used as a first marker region layer of the sub-regular pattern.
[0010] The negated area of the first marking area layer in the selected area of the layout is used as the second marking area layer of the regular upper pattern.
[0011] Step 4: Perform OPC verification on the patterns of the first mark area layer and the second mark area layer respectively.
[0012] The OPC verification items for the first mark area layer include a first critical dimension check; the first critical dimension check adopts a layered check, and a first error tolerance of each layer check of the first critical dimension is determined by multiplying a set value of a design rule by a corresponding percentage.
[0013] A further improvement is that the first error tolerances corresponding to each layer of the first verification specification value (spec) are respectively ±5%, ±10% and ±15% of the set value of the design rule.
[0014] A further improvement is that the first verification specification value of each layer check of the first critical dimension check is respectively the set value of the design rule plus the corresponding first error tolerance.
[0015] A further improvement is that the OPC verification items for the second mark area layer include a second critical dimension check; and a second error tolerance of the second critical dimension is determined by a model fitting error.
[0016] A further improvement is that the second error tolerance of the second critical dimension is the model fitting error of the one-dimensional graphic ±2dbu, where dbu represents a layout database unit, such as a layout grid width.
[0017] A further improvement is that the second verification specification value of the second critical dimension check is respectively the set value of the design rule plus the corresponding second error tolerance.
[0018] A further improvement is that, in step 1, the selected area includes a logic area and a storage area.
[0019] A further improvement is that the storage area includes an SRAM area.
[0020] A further improvement is that, in step 2, a graph that meets the following definition is used as the sub-regular graph:
[0021] The minimum critical dimension is smaller than the set value of the design rule;
[0022] The minimum interval is smaller than the set value of the design rule;
[0023] Setting value for graphics with non-45 degree bevel edges;
[0024] The package size of the hole layer is smaller than the set value of the design rule.
[0025] A further improvement is that the first value is 2 to 4 times the optical diameter.
[0026] The present invention divides the graphics area of the selected area into sub-regular graphics and regular graphics on the basis of dividing the layout into regions such as logical regions and storage regions, and marks the sub-regular graphics to form sub-regular graphics marks, extracts a first marking region layer corresponding to the sub-regular graphics through the sub-regular graphics marks, and obtains a second marking region layer corresponding to the regular graphics by negating the first marking region layer;
[0027] When performing OPC verification on the selected area, the graphics of the first mark area layer and the second mark area layer will be verified separately, so that the first mark area layer and the second mark area layer can independently set corresponding error tolerances. By setting multiple first error tolerances, the present invention can use a layered inspection method to implement a first critical dimension inspection of the first mark area layer. The layered inspection can efficiently detect abnormal problems, especially efficiently detect abnormal problems in printing design.
[0028] The present invention can also set the second error tolerance of the second critical dimension inspection of the second mark area layer to be determined by the model fitting error. The model fitting error is related to the OPC correction abnormality, and can effectively check and correct the OPC abnormality problem; and, the setting of the second error tolerance of the present invention can achieve the number of error points of the second critical dimension inspection to be less than that of the existing method, thereby improving efficiency, but will not cause missed detection problems, and the early warning is safe and effective.
[0029] Therefore, the present invention can enhance the efficient inspection of layout anomalies and can also enhance the inspection of OPC correction anomalies, so that layout design problems and OPC correction anomalies can be discovered in a timely manner without omissions, thereby improving product yield and improving inspection efficiency when the chip size is larger. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:
[0031] Figure 1A It is the actual graph at a position during pinch inspection in the existing OPC verification method;
[0032] Figure 1BIs the current OPC verification method a pinch check and Figure 1A an actual pattern at another location having the same simulated value;
[0033] Figure 2 is a flow chart of an OPC verification method according to an embodiment of the present invention;
[0034] Figure 3A-3C It is a graphic obtained by layered inspection of the first critical dimension inspection in the OPC verification method according to an embodiment of the present invention;
[0035] Figure 4 This is a graph that passes the second critical dimension inspection of the OPC verification method according to the embodiment of the present invention but fails the inspection of the existing OPC verification method. DETAILED DESCRIPTION
[0036] like Figure 2 FIG. 1 is a flow chart of an OPC verification method according to an embodiment of the present invention. The OPC verification method according to an embodiment of the present invention comprises the following steps:
[0037] Step 1: Divide the map into regions and obtain the selected regions.
[0038] In the embodiment of the present invention, the selected area includes a logic area and a storage area.
[0039] In some embodiments, the storage area includes an SRAM area.
[0040] Step 2: Differentiate the patterns in the selected area based on design rules to divide the patterns into sub-regular patterns and regular patterns.
[0041] In the embodiment of the present invention, a graph that meets the following definition is regarded as the sub-regular graph:
[0042] The minimum critical dimension is smaller than the set value of the design rule;
[0043] The minimum interval is smaller than the set value of the design rule;
[0044] Setting value for graphics with non-45 degree bevel edges;
[0045] The package size of the hole layer is smaller than the set value of the design rule.
[0046] That is, through the above four definitions, the sub-regular figure can be found. The figure that does not belong to the sub-regular figure is a regular figure.
[0047] The design rules define the minimum values of various sizes in the layout graphics, such as the minimum width of line graphics, the minimum width of the spacing graphics between line graphics, etc. When comparing with the set values of the design rules, the sizes of graphics of the same type need to be selected for comparison.
[0048] Step three: marking the sub-regular graphic to form a sub-regular graphic mark.
[0049] A halo region with a first diameter is formed by taking the sub-regular pattern mark center as the origin and the halo region is used as the first mark region layer of the sub-regular pattern. In some embodiments, the first diameter is 2 to 4 times the optical diameter.
[0050] The negated area of the first marking area layer in the selected area of the layout is used as the second marking area layer of the regular upper pattern.
[0051] Step 4: Perform OPC verification on the patterns of the first mark area layer and the second mark area layer respectively.
[0052] The OPC verification items for the first mark area layer include a first critical dimension check; the first critical dimension check adopts a layered check, and a first error tolerance of each layer check of the first critical dimension is determined by multiplying a set value of a design rule by a corresponding percentage.
[0053] In some embodiments, the first error tolerance corresponding to each layer of the first verification specification value is respectively ±5%, ±10% and ±15% of the setting value of the design rule. In other embodiments, the first error tolerance corresponding to each layer can also be modified as needed.
[0054] The first verification specification value of each layer check of the first critical dimension check is respectively the set value of the design rule plus the corresponding first error tolerance.
[0055] By setting multiple layers of the second verification specification value, the efficiency of detecting abnormal problems in the first critical dimension inspection is improved. This is because after the second verification specification value is layered, the types of abnormal points detected in each layer are usually different, so different types of design problems can be quickly discovered. In the existing method, all graphics are checked using the same verification specification value. After checking many abnormal points, it is often impossible to check each abnormal point, and only spot checks can be performed. Spot checks often have the adverse effect of missed inspections, making it difficult to find design problems, and ultimately inevitably affecting the efficiency of detecting design problems.
[0056] In the embodiment of the present invention, the OPC verification items for the second mark area layer include a second critical dimension check; and a second error tolerance of the second critical dimension is determined by a model fitting error.
[0057] In some embodiments, the second error tolerance of the second critical dimension is a model fitting error of the one-dimensional pattern ±2dbu, where dbu represents a layout database unit.
[0058] The second verification specification value of the second critical dimension check is respectively the set value of the design rule plus the corresponding second error tolerance.
[0059] In the embodiment of the present invention, step 4 needs to be performed after the OPC correction is completed.
[0060] Compared with the prior art, in which the second error tolerance of the second critical dimension is the set value of the design rule multiplied by a set percentage, the range of the second verification specification value finally obtained in the embodiment of the present invention will be narrowed, so the number of high-risk points detected will also be reduced, but compared with the existing method, the high-risk points not detected in the second critical dimension inspection in the embodiment of the present invention are actually safe and effective. Therefore, the embodiment of the present invention can improve the efficiency of the second critical dimension inspection without affecting the safety and effectiveness of the inspection results.
[0061] In the embodiment of the present invention, on the basis of dividing the layout into regions such as logic regions and storage regions, the graphics of the selected region are divided into sub-regular graphics and regular graphics, and the sub-regular graphics are marked to form sub-regular graphics marks, and a first marked region layer corresponding to the sub-regular graphics is extracted through the sub-regular graphics marks, and a second marked region layer corresponding to the regular graphics is obtained by negating the first marked region layer;
[0062] When performing OPC verification on the selected area, the graphics of the first mark area layer and the second mark area layer will be verified separately, so that the first mark area layer and the second mark area layer can independently set corresponding error tolerances. By setting multiple first error tolerances, the present invention can use a layered inspection method to implement a first critical dimension inspection of the first mark area layer. The layered inspection can efficiently detect abnormal problems, especially efficiently detect abnormal problems in printing design.
[0063] The embodiment of the present invention can also set the second error tolerance of the second critical dimension inspection of the second mark area layer to be determined by the model fitting error. The model fitting error is related to the OPC correction abnormality, and can effectively check and correct the OPC abnormality problem; and the setting of the second error tolerance of the embodiment of the present invention can achieve the number of error points of the second critical dimension inspection to be smaller than that of the existing method, thereby improving efficiency, but will not cause missed detection problems, and the early warning is safe and effective.
[0064] Therefore, the embodiments of the present invention can enhance the efficient inspection of layout anomalies and can also enhance the inspection of OPC correction anomalies, so that layout design problems and OPC correction anomalies can be discovered in a timely manner without omissions, thereby improving product yield and improving inspection efficiency when the chip size is larger.
[0065] In advanced technology nodes, the size of chip design is getting smaller and smaller, and the graphics complexity is getting higher and higher. The existing opcverify simulation check for key CDs distinguishes between logic and SRAM areas. However, it is not practical to check these points one by one when there are tens of thousands of opc verify warning points for design violations of layout rules or process hotspot problems caused by insufficient optimization of OPC recipes. Random inspections are likely to miss process hotspots with unpredictable risks, and the inspection efficiency is seriously affected when the chip size is large. The embodiments of the present invention can well improve the disadvantages of conventional opcverify practices.
[0066] The embodiment of the present invention can perform more efficient inspection on the design anomaly problem of the layout and can more easily expose the process hot spots caused by the OPC correction anomaly: first, the design layout is divided into SRAM / LOGIC areas, and then the key dimension line width (line) and space (space) of the original design layout graphics are checked according to the design rule of this layer, and the position of all graphics violating the design rule is marked by a standard recognition language, and a region (region) with a halo size of a is formed with the center of the mark as the origin, which is called the sub rule area, i.e., the first marking area layer, and the other areas are the on rule area, i.e., the second marking area layer, and a is the first value; the inspection spec of the opc verify of the key dimension in the sub rule area, i.e., the first verification specification value, is set at different levels; the inspection spec of the opc verify of the key dimension in the on rule area, i.e., the second verification specification value, is reasonably set based on the one-dimensional (1D) model fitting error + / - 2dbu and combined with the 1D wafer data.
[0067] The necessity of separately checking the sub rule graph and the on rule graph areas in the embodiment of the present invention is described below:
[0068] Combined with specific data, the technical problems existing in the existing OPC verify method are further explained as follows:
[0069] Taking the ion implantation layer as an example, in the existing method, during the pinch check, the "corner-to-corner" graphics of the sub rule and the graphics of the on rule are mixed together without distinction. The pinch check is for graphics with simulation values less than the set line width. When the number of errors reaches thousands and cannot be checked one by one, it is impossible to effectively separate the errors from the on rule graphics, which is not conducive to the discovery of high-risk hotspots of the on rule. The design rule of an ion implantation layer of a certain product is b / b(nm), the pinch spec is set to 95%*b, and the number of pinch errors is 2990. They are sorted from small to large according to the simulation value. The error results are shown in Table 1 and the two error graphics are shown in Table 1. Figure 1A and Figure 1B shown.
[0070] Table 1
[0071]
[0072]
[0073] In Table 1, OPC verify check item indicates the check item of OPC verification, and the check item pinch is taken as an example for explanation.
[0074] Check spec represents the verification specification value. The spec is set as the design rule multiplied by a percentage, that is, 95%*b, where b is the value of the design rule.
[0075] Pinch simulation value indicates the simulation value.
[0076] "Sub rule? Manual review required" means judging whether it is a sub-rule pattern based on the inspection results.
[0077] As can be seen from Table 1, the number of pinch errors is 2990, which are sorted from small to large according to the simulation value. Each error point is represented by Pinch_wp_sequence number, which is one of 1 to 2990.
[0078] like Figure 1A As shown, it is the actual graph of a position when the pinch check is performed in the existing OPC verification method, that is, the n+1th point in Table 1; Figure 1B The figure shows the pinch check in the existing OPC verification method. Figure 1A The actual graph of another position with the same simulation value is the n+2th point in Table 1. Figure 1A As shown, the n+1th point is a layout design problem; Figure 1BAs shown, the n+2th point is the on rule graph. If it is much smaller than the opc verify spec setting, it is an abnormal OPC correction and the OPC program needs to be analyzed. If the conventional opcverify method is used, the n+1th point may not be viewed due to the random inspection when the number of errors is large, and the design problem cannot be discovered. In the embodiment of the present invention, the subrule graph and the on rule graph are used to perform area separation inspection, so that the above n+1th point and the n+2th point can be distinguished.
[0079] Figure 1A In , the corresponding figure is the diagonal figure formed by lines 101a and 101b; Figure 1B The figure in is the line figure 101b. As shown in Table 1, Figure 1A The line widths d101 and Figure 1B The line width d102 of the line pattern 101b in is the same as the simulation (simu) value.
[0080] but, Figure 1A The graphics are sub rule. The sub rule graphics are layout issues and cannot be solved by non-OPC corrections. The customer needs to be notified to take corresponding measures. Figure 1B The graph is the on rule graph. If the on rule graph has a small error value, it is an OPC correction problem and needs to optimize the OPC recipe to solve it.
[0081] The necessity of performing the verify spec hierarchical setting when checking the critical CD in the sub rule area in the embodiment of the present invention is described as follows:
[0082] It is generally believed that there should be no sub rule graphics or a small number of sub rule graphics in the layout, but the actual situation is that there is a high probability of sub rule graphics in the SRAM area. There are a large number of sub rules of various sizes in the line or space layer or the customer split chip in the multi-project wafer (MPW). Taking the ion implantation layer as an example, because some layers in the ion implantation layer are generated by logical operations, there will be a large number of diagonal graphics or there may be some line / space sub rule problems due to design problems. Some graphics may have mask rule check (mrc) problems when the simulation value is small after OPC. It is more efficient to perform layered inspection on the verify spec that reports errors in the sub rule area to find sub rule and OPC mrc problems. The examples shown in the following Table 2 can quickly find design problems through layered settings. The existing traditional methods use random inspection when the number of errors is large, which may miss non-compliant designs or abnormal designs.
[0083] Table 2
[0084]
[0085] Different from Table 1, in Table 2, the OPC verify check item also performs pinch check, but it is divided into areas, namely, sub rule area and on rule area. The necessity of distinguishing between sub rule area and on rule area has been described above.
[0086] At the same time, the spec in the sub rule area is divided into three layers, namely spec1, spec2 and spec3. It can be seen that the nth point is obtained by checking spec2, and the n+1th point is obtained by checking spec3. In other embodiments, more different spec values can be set as needed.
[0087] like FIG. 3A to FIG. 3C , which is a graph obtained by layered inspection of the first critical dimension inspection in the OPC verification method according to an embodiment of the present invention; Figure 3A In FIG. 1 , line 101 d is a pattern detected by using spec1. The line width of line 101 d , namely the key dimension d103 , meets the range requirement of spec1 and is therefore detected.
[0088] Figure 3B In FIG. 1 , line 101e is a pattern detected by using spec2. The line width of line 101e, i.e., key dimension d104, meets the range requirement of spec2, and thus is detected.
[0089] Figure 3C In FIG. 1 , the diagonal figure formed by lines 101a and 101b is a figure detected by using spec3. The diagonal line width d101 meets the range requirement of spec3 and is therefore detected.
[0090] Depend on FIG. 3A to FIG. 3C As shown, different spec layers can detect different abnormal problems, such as Figure 3C The abnormal problems shown can be detected directly without sampling out from a large number of problem points.
[0091] As shown in Table 1, the actual graphics at the positions of wp_n+1, i.e., the n+1th point, and wp_n+2, i.e., the n+2th point, have the same simu value, but different problems: using the existing conventional opc verify method, since spot checks are used when the number of errors is large, the n+1th point may not be found, and the design problem cannot be guaranteed to be discovered. As shown in Table 2, the embodiment of the present invention checks the sub rule area and the on rule area separately, and performs hierarchical checks on the verify spec with errors in the sub rule area, so that the efficiency of discovering sub rule and OPC mrc problems is higher.
[0092] Therefore, in the embodiment of the present invention, the sub rule area verify spec is hierarchically set to efficiently detect abnormal problems.
[0093] The following is an explanation of how the on rule graph can improve efficiency when performing key CD checks in an embodiment of the present invention:
[0094] For on rule graphics, the opc verify spec for key CDs such as pinch check is set to the model fitting error range + / -2dbu of the design rule + 1D graphics of the layer. This value is different from the existing conventional opc verify spec with an error tolerance of 5% of the design rule. The error graphics of the two are compared as follows:
[0095] Taking the metal layer as an example, assuming that the design rule of this layer is 100 / 100nm, the layout grid point, i.e., DBU, is 0.5nm, and the 1D modeling fitting is + / -2.5nm, then the spec for pinch check in the OPC Verify of the embodiment of the present invention can be set to 100-5-1=94nm, which is smaller than the conventional 95nm set by percentage, so the inspection efficiency will be improved. However, after actual wafer confirmation, the error graph between the simulation value of 94nm-95nm is safe, that is, although the embodiment of the present invention does not check the high-risk points with specs between 94nm-95nm, these points are actually safe, and these points need to be checked in the existing method, but these points do not need to be detected in the embodiment of the present invention, so the detection efficiency of the embodiment of the present invention will be improved.
[0096] like Figure 4 As shown, it is a graph that the second critical dimension inspection of the OPC verification method according to the embodiment of the present invention passes but the existing OPC verification method fails; Figure 4In the figure, when the pinch check is performed on line 101f, a warning will be issued when the conventional verification is used for this point, but the verification method of the embodiment of the present invention is used to check that the set spec is met and no warning will be issued; during the actual wafer verification, the results of this point are fine under both nominal and process window conditions (PW conditions).
[0097] like Figure 4 As shown, the on rule area verify spec setting method adopted in the embodiment of the present invention will make the method of the embodiment of the present invention have fewer error points than the existing conventional method. For example: when the on rule graphics perform OPC verification on the key CD, the verify spec is set to the model fitting error + / - 2dbu of the design + 1D diagram of the layer. After actual silicon wafer verification, this kind of setting of the non-gate related layers of the line / space for the early warning of the OPC verify verification point is effective and safe. The on rule area verify spec setting method will reduce some error points compared with the conventional setting method. The reduced error points meet the process requirements after wafer verification. This setting method is reasonable and effective.
[0098] Therefore, the on rule area verify spec setting method adopted in the embodiment of the present invention can reduce some error points compared with the conventional setting method. The reduced error points meet the process requirements after wafer verification, and the setting method is reasonable and effective.
[0099] In summary, the OPC Verify method according to the embodiment of the present invention can efficiently detect abnormalities in drawing design and high-risk points caused by abnormal OPC corrections compared to the existing traditional OPC Verify method.
[0100] In the method of the embodiment of the present invention, the on rule graphic performs opcverify on the key CD, and the verify spec is set to the model fitting error+ / -2dbu of the design+1D diagram of the layer. After actual verification, this kind of setting of the non-gate related layer of the line / space for the early warning of the opc verify verification point is effective and safe.
[0101] As shown in Table 2, the verify spec of the sub rule critical size in the embodiment of the present invention needs to be set in levels, so as to quickly identify the sub rule area and its severity.
[0102] Next, the OPC verification method of the embodiment of the present invention is further described by taking the metal layer as an example:
[0103] Read the layout data, and use the OPC program to divide the layout into two areas through the SRAM identification layer: SRAM area and logic area.
[0104] The SRAM area and the logic area are checked for critical dimensions respectively, that is, according to the design rule of this layer, the minimum critical dimension (minimum CD), minimum spacing (minimum space), non 45grade skew edge (non 45grade skew edge), and hole enclosure inspection values are set in the OPC program, and the design dimension checks are performed on the SRAM area and the logic area respectively. The positions that do not meet the design rules are marked, and the center of the mark is used as the origin to expand into an area with a halo value of 2 to 3 times the optical radius, which is called the sub rule area, and the other areas are on rule areas.
[0105] Use the OPC recipe to correct the optical proximity effect of the layout and obtain the layout after OPC.
[0106] Perform OPC Verify on the layout after OPC. If the graphics that do not meet the inspection specifications are located in the sub rule area, the prefix sr is added before the inspection item to distinguish them. If the graphics that do not meet the inspection specifications are located in the on rule area, the conventional practice is consistent.
[0107] As can be seen from the above, the existing traditional OPC verification method performs regional inspections on the SRAM area and the logic area, and the key CD inspection settings of each area are all based on the design rule to set the error tolerance; however, in advanced technology nodes, when the chip size is large, the graphics complexity is high, and the number of errors is large, this existing inspection method cannot review the error points one by one, which may lead to design anomalies in the layout and the risk of not being able to discover high-risk points due to inadequate OPC correction. The OPC verification method of the embodiment of the present invention introduces a sub rule marker region, i.e., the first marker region layer, and an on rule marker region, i.e., the second marker region layer, and sets the error tolerance for the simulation results in the sub rule marker region to enhance the efficient inspection of layout anomalies; by inspecting the key CD in the on rule marker region, the error tolerance is preferably the model fitting error + / - 1dbu of the 1D graphic, so as to enhance the inspection of the OPC correction anomalies of the key CD of the on rule graphic.
[0108] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.
Claims
1. An OPC verification method, It is characterized in that The steps include: Step 1: Divide the map into regions and obtain selected regions; Step 2: differentiating the patterns in the selected area based on the design rules to divide the patterns into sub-regular patterns and regular patterns; Step 3: marking the sub-regular pattern to form a sub-regular pattern mark; Taking the sub-regular pattern mark center as the origin, expanding to form a halo region with a first diameter, and using the halo region as a first mark region layer of the sub-regular pattern; Using the negated area of the first marking area layer in the selected area of the layout as the second marking area layer of the regular upper pattern; Step 4: performing OPC verification on the graphics of the first mark area layer and the second mark area layer respectively; The OPC verification items for the first mark area layer include a first critical dimension check; the first critical dimension check adopts a layered check, and a first error tolerance of each layer check of the first critical dimension is determined by multiplying a set value of a design rule by a corresponding percentage.
2. The OPC verification method according to claim 1, Features: The first error tolerances corresponding to the various layers of the first verification specification values are respectively ±5%, ±10% and ±15% of the set value of the design rule.
3. The OPC verification method according to claim 1 or 2, Features: The first verification specification value of each layer check of the first critical dimension check is respectively the set value of the design rule plus the corresponding first error tolerance.
4. The OPC verification method according to claim 1, Features: The OPC verification items for the second mark area layer include a second critical dimension check; and a second error tolerance of the second critical dimension is determined by a model fitting error.
5. The OPC verification method as claimed in claim 4, Features: The second error tolerance of the second critical dimension is a model fitting error of the one-dimensional pattern of ±2dbu, where dbu represents a layout database unit.
6. The OPC verification method according to claim 4 or 5, Features: The second verification specification value of the second critical dimension check is respectively the set value of the design rule plus the corresponding second error tolerance.
7. The OPC verification method according to claim 1, Features: In step 1, the selected area includes a logic area and a storage area.
8. The OPC verification method according to claim 7, Features: The storage area includes an SRAM area.
9. The OPC verification method according to claim 1, Features: In step 2, a graph that meets the following definition is used as the sub-regular graph: The minimum critical dimension is smaller than the set value of the design rule; The minimum interval is smaller than the set value of the design rule; Setting value for graphics with non-45 degree bevel edges; The package size of the hole layer is smaller than the set value of the design rule.
10. The OPC verification method according to claim 1, Features: The first value is 2 to 4 times the optical diameter.