Display panel and electronic equipment

Abstract

The invention discloses a display panel and electronic equipment. The display panel comprises a light-emitting element and a pixel circuit connected with the light-emitting element. The pixel circuit comprises a driving transistor of which the gate is connected with a first node, the first pole is connected with a second node and the second pole is connected with a third node; the grid electrode of the first light-emitting control transistor is connected with the light-emitting control signal line, the first pole is connected with the first power supply signal line, and the second pole is connected with the second node; the grid electrode of the bias transistor is connected with the first control signal line, the first pole is connected with the second node through a connecting line, and the second pole is connected with the bias signal line; the connecting lines and the light-emitting control signal lines are insulated and crossed; a first shield line at the crossing position, a portion of the first shield line being located between the connecting line and the light emission control signal line; and the first shielding line is connected with the target signal line, and shields the connecting line and the light-emitting control signal line based on a target signal accessed by the target signal line.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and more specifically, to a display panel and an electronic device. Background Art

[0002] The main component of an electronic device to realize the display function is the display panel. In the display panel, the light-emitting element is controlled by the pixel circuit adjacent to the light-emitting element to perform light-emitting display. When the existing display panel performs light-emitting display, in order to make the light-emitting elements with different light-emitting areas have a relatively consistent light-emitting brightness when displaying the same brightness, it is necessary to set a bias transistor connected to the driving transistor in the pixel circuit to adjust the bias state of the driving transistor.

[0003] Although adding a bias transistor in the pixel circuit can adjust the bias state of the driving transistor, the added bias transistor will bring additional line crosstalk problems. Summary of the invention

[0004] In view of this, the present application provides a display panel and an electronic device, and the scheme is as follows:

[0005] A first aspect of the present application provides a display panel, the display panel comprising a light-emitting element and a pixel circuit connected to the light-emitting element;

[0006] The pixel circuit includes:

[0007] A driving transistor, wherein a gate of the driving transistor is connected to the first node, a first electrode is connected to the second node, and a second electrode is connected to the third node;

[0008] a first light emission control transistor, wherein a gate of the first light emission control transistor is connected to the light emission control signal line, a first electrode is connected to the first power supply signal line, and a second electrode is connected to the second node;

[0009] A bias transistor, wherein the gate of the bias transistor is connected to the first control signal line, the first electrode is connected to the second node through a connecting line, and the second electrode is connected to the bias signal line; the connecting line is insulated and crosses the light emitting control signal line;

[0010] The first shielding line is at the intersection of the connecting line and the light-emitting control signal line, and part of the first shielding line is located between the connecting line and the light-emitting control signal line; the first shielding line is connected to the target signal line, and shields the connecting line and the light-emitting control signal line based on the target signal connected to the target signal line.

[0011] A second aspect of the present application is a display panel, the display panel comprising a light emitting element and a pixel circuit connected to the light emitting element;

[0012] The pixel circuit includes:

[0013] A driving transistor, wherein a gate of the driving transistor is connected to the first node, a first electrode is connected to the second node, and a second electrode is connected to the third node;

[0014] a first light emission control transistor, wherein a gate of the first light emission control transistor is connected to the light emission control signal line, a first electrode is connected to the first power supply signal line, and a second electrode is connected to the second node;

[0015] A bias transistor, wherein the gate of the bias transistor is connected to the first control signal line, the first electrode is connected to the second node through a connecting line, and the second electrode is connected to the bias signal line; the connecting line is insulated and crosses the light emitting control signal line;

[0016] In the row direction of the array, the display panel has a first sub-display area and a second sub-display area arranged in sequence; a first pixel circuit in the first sub-display area is connected to a first data line, a second pixel circuit in the second sub-display area is connected to a second data line, and the first data line and the second data line are both located in the second sub-display area;

[0017] In a direction perpendicular to the plane where the display panel is located, the first data line and the connecting line in the second pixel circuit have an overlapping portion; in the overlapping portion, there is a second shielding line between the first data line and the connecting line, the second shielding line is connected to the target signal line, and the connecting line and the first data line are shielded based on the target signal.

[0018] A third aspect of the present application provides an electronic device, which includes the above-mentioned display panel.

[0019] It can be seen from the above description that in the display panel and the electronic device provided by the technical solution of the present application, a bias transistor is provided in the pixel circuit of the display panel, and the first electrode of the bias transistor is connected to the second node through a connecting line, so as to connect the driving transistor through the second node, so that the bias transistor can adjust the bias state of the driving transistor. In addition, on a plane perpendicular to the display panel, the connecting line and the light-emitting control signal line are insulated and crossed, that is, the two are located in different metal layers.

[0020] The technical solution of the present application sets a first shielding line between the connecting line and the light-emitting control signal line, and sets a target signal connected to the target signal line connected to the first shielding line, so that the connecting line and the light-emitting control signal line can be shielded at the intersection through the first connecting line connected to the target signal, thereby preventing the additional line crosstalk problem caused by adding bias transistors and improving the image display quality. The technical solution of the present application can also shield the connecting line and the first data line through the second shielding line connected to the target signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0022] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0023] Figure 1 A pixel circuit diagram in a display panel;

[0024] Figure 2 A cross-sectional view of a display panel provided in an embodiment of the present application;

[0025] Figure 3 A schematic diagram of a pixel circuit layout in a display panel;

[0026] Figure 4 for Figure 3 A cross-sectional view of the pixel circuit layout at the intersection of the connecting line and the light-emitting control signal line;

[0027] Figure 5 A schematic diagram of a pixel circuit layout in another display panel;

[0028] Figure 6 for Figure 5 A cross-sectional view of the pixel circuit layout at the intersection of the connecting line and the light-emitting control signal line;

[0029] Figure 7 A cross-sectional view of a pixel circuit layout at the intersection of a connecting line and a light-emitting control signal line;

[0030] Figure 8 is a schematic diagram of a pixel circuit layout in another display panel;

[0031] Fig. 9 is a schematic diagram of a pixel circuit layout in another display panel;

[0032] Fig.10 is a schematic diagram of a pixel circuit layout in another display panel;

[0033] Fig.11A schematic diagram of a layout of a pixel circuit in a display panel;

[0034] Fig.12 A schematic diagram of another layout of pixel circuits in a display panel;

[0035] Fig.13 for Fig.12 The layout of the first data line and the overlapped second pixel circuit in the display panel shown;

[0036] Fig.14 for Fig.13 A cross-sectional view of the layout shown at the intersection of the connection line and the light-emitting control signal line;

[0037] Fig.15 for Fig.12 Another layout of the first data line and the overlapping second pixel circuit in the display panel shown;

[0038] Fig.16 for Fig.12 Another cross-sectional view of the layout shown at the intersection of the connection line and the light-emitting control signal line;

[0039] Fig.17 A top view of an electronic device provided in an embodiment of the present application.

[0040] Reference numerals:

[0041] 10-substrate; 11-light-emitting control signal line; 12-first control signal line; 13-connecting line; 14-second scanning signal line; 15-second control signal line; 16-first scanning signal line; 17-first shielding line; 171-first part; 172-second part; 18-data line; 181-first data line; 182-second data line; 19-fan-out line; 20-driving chip; 21-second shielding line; 22-display panel; X-row direction; Y-column direction; T1-first light-emitting control transistor; T2-data writing transistor; T3-driving transistor T3; T4-threshold compensation transistor; T5-first reset transistor; T6-second light-emitting control transistor; T7-second reset transistor; T8-bias transistor; Cst-storage capacitor; C0-first capacitor; VDD-first power supply signal; VEE-first Two power supply signals; D-light-emitting element; N1-first node; N2-second node; N3-third node; N4-fourth node; DVH-bias signal; SC_P*-first control signal; SC_P-second control signal; SC_N1-first scan signal; SC_N2-second scan signal; VDATA-data signal; VREF1-first reset signal; VREF2-second reset signal; AL1-low-temperature polysilicon layer; MG1-first metal layer; MC-second metal layer; AL2-indium gallium zinc oxide layer; MG2-third metal layer; SD1-first data metal layer; SD2-second data metal layer; SD3-third data metal layer; M0-light-shielding metal layer; V0-target signal; Via1-conductive hole; Via0-target conductive hole; AA1-first sub-display area; AA2-second sub-display area. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0043] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0044] refer to Figure 1 , Figure 1The present invention is a pixel circuit diagram in a display panel, wherein the pixel circuit includes: a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4 and a bias transistor T8; the driving transistor T3 is used to provide a driving current for a light-emitting element D of the display panel; the data writing transistor T2 is connected to the first electrode (i.e., the second node N2) of the driving transistor T3, and is used to provide a data signal VDATA for the driving transistor T3; the bias transistor T8 is connected to the first electrode of the driving transistor T3, and is used to provide a bias signal DVH for the driving transistor T3; the threshold compensation transistor T4 is connected between the gate (i.e., the first node N1) and the second electrode (i.e., the third node N3) of the driving transistor, and is used to compensate for the threshold voltage of the driving transistor T3.

[0045] The pixel circuit may further include: a first reset transistor T5, used to provide a first reset signal VREF1 to the gate of the driving transistor T3; and a second reset transistor T7, used to provide a second reset signal VREF2 to the light emitting element D.

[0046] The pixel circuit may further include: a first light emission control transistor T1 and a second light emission control transistor T6, the two light emission control transistors are used to selectively allow the light emitting element D to enter the light emission stage. The gates of the two light emission control transistors are connected to the light emission control signal line to input the light emission control signal EM. The first electrode of the first light emission control transistor T1 is connected to the first power supply signal line to access the first power supply signal VDD, and the second electrode of the first light emission control transistor T1 is connected to the second node N2. The first electrode of the second light emission control transistor T6 is connected to the third node, and the second electrode of the second light emission control transistor T6 is connected to the fourth node N4, and the fourth node N4 is connected to the light emitting element D. The light emitting element D is connected between the fourth node N4 and the second power supply signal line, and the second power supply signal line is connected to the second power supply signal VEE.

[0047] Optionally, the gate of the bias transistor T8 is connected to the first control signal line to receive the first control signal line, and the first control signal line is used to input the first control signal SC_P* to control the on and off of the bias transistor T8; the gate of the data writing transistor T2 is connected to the second control signal line to receive the second control signal SC_P, and the second control signal SC_P controls the on and off of the data writing transistor T2; the gate of the first reset transistor T5 is connected to the first scan signal line to receive the first scan signal SC_N1, and the first scan signal SC_N1 controls the on and off of the first reset transistor T5; the threshold compensation transistor T 4 is connected to the second scan signal line to receive the second scan signal SC_N2, and the second scan signal SC_N2 controls the turning on and off of the threshold compensation transistor T4; the gate of the second reset transistor T7 is connected to the first control signal line to receive the first control signal SC_P*, and the first control signal SC_P* controls the turning on and off of the second reset transistor T7; the gates of the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are both connected to the light-emitting control signal line to receive the light-emitting control signal EM, and the light-emitting control signal EM controls the turning on and off of the first light-emitting control transistor T1 and the second light-emitting control transistor T6.

[0048] Optionally, the pixel circuit further includes a storage capacitor Cst, a first electrode of the storage capacitor Cst is connected to the first power signal line, a second electrode of the storage capacitor Cst is connected to the gate of the driving transistor T3, and is used to store a signal transmitted to the gate of the driving transistor T3.

[0049] Optionally, a first capacitor C0 is connected between the gate of the data writing transistor T2 and the gate of the driving transistor T3 to maintain a stable voltage at the first node N1.

[0050] A bias transistor T8 is provided in the pixel circuit, and the bias transistor T8 is used to provide a bias signal DVH for the driving transistor T3. Because the potential difference between the gate and the first pole or the second pole of the driving transistor T3 during the light emission process may cause a bias problem. The bias problem often causes a reverse electric field to be generated inside the driving transistor T3, resulting in carrier polarization, thereby causing the threshold voltage of the driving transistor T3 to shift. The threshold voltage shift of the driving transistor T3 causes the driving current generated by the driving transistor T3 to be unstable, especially when the grayscale changes, and a flicker problem may occur. In the embodiment of the present application, a bias signal DVH is provided to the first pole of the driving transistor T3, and the voltage difference between the gate of the driving transistor T3 and the first pole or the second pole is adjusted in time to offset the bias problem, avoid the threshold voltage of the driving transistor T3 from shifting, and thus help to reduce the flicker phenomenon.

[0051] In the pixel circuit, one of the first electrode and the second electrode of the transistor is a source electrode, and the other is a drain electrode. The transistor can be set to NMOS or PMOS according to the display requirements of the pixel circuit.

[0052] In one embodiment, the pixel circuit may be a low temperature polycrystalline oxide (LTPO) pixel circuit, in which the active regions of some transistors in the pixel circuit are made of indium gallium zinc oxide (IGZO), and the active regions of other transistors are made of low temperature polycrystalline silicon (LTPS). For example, the active regions of the threshold compensation transistor T4 and the first reset transistor T5 are made of metal oxide. The IGZO transistor is a dual-gate structure, and the IGZO transistor has a lower leakage current, so the use of the IGZO transistor in the pixel circuit can improve the image display quality of the display panel.

[0053] At least in other ways, each transistor in the pixel circuit can also be a LTPS transistor.

[0054] refer to Figure 2 , Figure 2 A cross-sectional view of a display panel provided in an embodiment of the present application, Figure 2 1 shows a cross-sectional view of a substrate 10 in a display panel and a portion of a pixel circuit on its surface. The display panel has a substrate 10 and a pixel circuit located on the substrate 10. The pixel circuit includes a low LTPS transistor and an IGZO transistor. The dashed box on the left is an LTPS transistor, and the dashed box on the right is an IGZO transistor.

[0055] A low temperature polysilicon layer AL1, a first metal layer MG1, a second metal layer MC, an indium gallium zinc oxide layer AL2, a third metal layer MG2, a first data metal layer SD1, a second data metal layer SD2 and a third data metal layer SD3 are sequentially disposed on a surface of one side of the substrate 10. An insulating layer is provided between adjacent metal layers and between a metal layer and an adjacent active layer.

[0056] The low temperature polysilicon layer AL1 is used at least to prepare the active region of the LTPS transistor. The first metal layer MG1 is used at least to prepare the gate of the transistor and the signal line connected to the same layer as the gate. The second metal layer MC is used at least to prepare the bottom gate of the IGZO transistor and a plate layer of the capacitor. The indium gallium zinc oxide layer AL2 is used at least to prepare the active region of the IGZO transistor. The third metal layer MG2 is used at least to prepare the top gate of the IGZO transistor.

[0057] The first data metal layer SD1 is at least used to prepare the source and drain of the pixel transistor and the signal line connected to the source and drain in the same layer. The second data metal layer SD2 and the third data metal layer SD3 are used to prepare the signal line on the source and drain of the transistor.

[0058] Optionally, a shading metal layer M0 may be provided between the low-temperature polysilicon layer AL1 and the substrate 10. The shading metal layer M0 has an overlapping portion with the active area of ​​the LTPS transistor and is used to shield the active area of ​​the LTPS transistor to prevent the active area of ​​the LTPS transistor from generating photocurrent and causing leakage.

[0059] refer to Figure 3 and Figure 4 As shown, Figure 3 is a schematic diagram of a pixel circuit layout in a display panel, Figure 4 for Figure 3 The cross-sectional view of the pixel circuit layout at the intersection of the connecting line and the light-emitting control signal line is shown.

[0060] Combination Figure 1-Figure 4 The display panel shown includes a light emitting element D and a pixel circuit connected to the light emitting element D. As mentioned above, the pixel circuit includes: a driving transistor T3, a first light emitting control transistor T1 and a bias transistor T8.

[0061] A gate electrode of the driving transistor T3 is connected to the first node N1 , a first electrode of the driving transistor T3 is connected to the second node N2 , and a second electrode of the driving transistor T3 is connected to the third node N3 .

[0062] The gate of the first light emission control transistor T1 is connected to the light emission control signal line 11, the first electrode of the first light emission control transistor T1 is connected to the first power signal line, and the second electrode of the first light emission control transistor T1 is connected to the second node N2. The light emission control signal line 11 is used to input the light emission control signal EM. The first power signal line is used to input the first power signal VDD. Figure 3 The first power signal line is not shown in the figure, and the first electrode of the first light emitting control transistor T1 is connected to the first power signal line through a corresponding conductive hole Via1 to input the first power signal VDD.

[0063] The gate of the bias transistor T8 is connected to the first control signal line 12, the first electrode of the bias transistor T8 is connected to the second node N2 through the connection line 13, and the second electrode of the bias transistor T8 is connected to the bias signal line; the connection line 13 is insulated and crosses the light emitting control signal line 11. The first control signal line 12 is used to transmit the first control signal SC_P*. The bias signal line is used to transmit the bias signal DVH. Figure 3 The bias signal line is not shown in the figure, and the second electrode of the bias transistor T8 is connected to the bias signal line through the corresponding conductive hole Via1 to input the bias signal DVH.

[0064] The active regions of the LTPS transistors in the pixel circuit are all located in the low-temperature polysilicon layer AL1. For example, the first light-emitting control transistor T1, the data writing transistor T2, the driving transistor T3, the second light-emitting control transistor T6, the second reset transistor T7 and the bias transistor T8 can be set to be LTPS transistors. The active regions of the LTPS transistors are all located in the low-temperature polysilicon layer AL1 and are prepared from the low-temperature polysilicon layer AL1. The active regions of the IGZO transistors in the pixel circuit are located in the indium gallium zinc oxide layer AL2. For example, the threshold compensation transistor T4 and the first reset transistor T5 can be set to be IGZO transistors. The active regions of the IGZO transistors are located in the indium gallium zinc oxide layer AL2 and are prepared from the indium gallium zinc oxide layer AL2.

[0065] Optionally, the pixel circuits connected to the light emitting elements D in the display panel are arranged in an array, and the row direction of the array is set to X, and the column direction of the array is set to Y. The XY plane is parallel to the plane where the display panel is located.

[0066] The signal lines connected to the gates of the transistors in the pixel circuit may all extend along the row direction X. For example, the light emitting control signal line 11 for providing the light emitting control signal EM, the first control signal line 12 for providing the first control signal SC_P*, the second control signal line 15 for providing the second control signal SC_P, the second scanning signal line 14 for providing the second scanning signal SC_N2, and the first scanning signal line 16 for providing the first scanning signal SC_N1 all extend along the row direction X.

[0067] The light emitting control signal line 11, the first control signal line 12, the second scanning signal line 14, the second control signal line 15 and the first scanning signal line 16 may be sequentially arranged along the column direction Y. The arrangement order of the light emitting control signal line 11, the first control signal line 12, the second scanning signal line 14, the second control signal line 15 and the first scanning signal line 16 in the column direction Y is related to the layout position of each transistor in the pixel circuit, and the arrangement order of each signal line extending along the row direction X in the column direction Y may be set according to the layout position of the transistor in the pixel circuit, which is not limited in the embodiment of the present application.

[0068] The connection line 13 and the light-emitting control signal line 11 are located in different metal layers in the display panel, and the two extend in different directions to achieve insulation crossing. Figure 3 As shown, in one embodiment, the light emitting control signal line 11 may be located in the first metal layer MG1 and is made of the first metal layer MG1 ; the connection line 13 may be located in the first data metal layer SD1 and is made of the first data metal layer SD1 .

[0069] In the embodiment of the present application, the connecting line 13 and the light-emitting control signal line 11 may also be arranged on two other different metal layers in the display panel, and the metal layers where the connecting line 13 and the light-emitting control signal line 11 are respectively located are not limited to Figure 4 In the manner shown, the embodiment of the present application does not limit the metal layer where the connecting line 13 and the light-emitting control signal line 11 are located.

[0070] Combination Figure 3 and Figure 4 As shown, since the connecting line 13 and the light-emitting control signal line 11 are insulated and crossed, in the direction perpendicular to the plane where the display panel is located, the connecting line 13 and the light-emitting control signal line 11 have an overlapping area at the insulated crossing position, and a parasitic capacitance is formed between the connecting line 13 and the light-emitting control signal line 11 in the overlapping area. In the high-frequency PWM stage of the light-emitting control signal EM, based on the parasitic capacitance, the light-emitting control signal EM input in the light-emitting control signal line 11 will continue to be coupled to the second node N2 through the connecting line 13, causing the potential of the second node N2 to increase, thereby affecting the potential of the third node N3 and the anode (fourth node N4) of the light-emitting element D. The changes in the potential of the third node N3 and the anode potential of the light-emitting element D will affect the image display quality. In particular, the changes in the potential of the third node N3 and the anode potential of the light-emitting element D will have a greater impact on the uniformity of low-brightness and low-grayscale display, and will cause grayscale color cast.

[0071] In order to reduce the coupling effect of the light emitting control signal EM on the second node N2, the following can be done: Figure 5 and Figure 6 As shown, a first shielding line 17 is provided between the connecting line 13 and the light emission control signal line 11 .

[0072] refer to Figure 5 and Figure 6 As shown, Figure 5 is a schematic diagram of a pixel circuit layout in another display panel, Figure 6 for Figure 5 The pixel circuit layout shown is a cross-sectional view at the intersection of the connecting line and the light-emitting control signal line. In this embodiment, the display panel is provided with a first shielding line 17, and at the intersection of the connecting line 13 and the light-emitting control signal line 11, a portion of the first shielding line 17 is located between the connecting line 13 and the light-emitting control signal line 11; the first shielding line 17 is connected to the target signal line, and shields the connecting line 13 and the light-emitting control signal line 11 based on the target signal V0 connected to the target signal line.

[0073] In one implementation, the first power signal line is used as the target signal line, and the first power signal VDD is used as the target signal V0 to shield the connection line 13 and the light-emitting control signal line 11, thereby shielding the coupling effect of the light-emitting control signal EM on the second node N2.

[0074] Since a conductive path needs to be formed between the first power signal VDD and the light emitting element D in the light emitting stage to control the light emitting element D to emit light, that is, the first power signal VDD needs to be used for light emitting display in the light emitting stage. Although this method can shield the coupling effect of the light emitting control signal EM on the second node N2 based on the first power signal VDD, it will cause the light emitting signal EM to couple with the first power signal VDD, resulting in fluctuations of the first power signal VDD in the light emitting stage, and causing other line crosstalk problems in the pixel circuit.

[0075] In order to avoid the new line crosstalk affecting the image display effect while reducing the coupling effect of the light-emitting control signal EM on the second node N2 during the light-emitting stage, the target signal line can be set to be connected to the pixel circuit in the non-light-emitting stage to control the working state of the pixel circuit in the non-light-emitting stage; and disconnected from the pixel circuit in the light-emitting stage. In this method, the target signal V0 is used to control the working state of the pixel circuit in the non-light-emitting stage, and the coupling effect of the light-emitting control signal EM on the second node N2 can be shielded based on the first shielding line 17 connected to the target signal V0. Moreover, since the target signal line is disconnected from the pixel circuit in the light-emitting stage, the target signal V0 is not the working signal of the pixel circuit in the light-emitting stage, so in the light-emitting stage, the crosstalk of the light-emitting control signal EM on the first shielding line 17 will not affect the display of the pixel circuit. Therefore, this method can not only reduce the coupling effect of the light-emitting control signal EM on the second node N2 in the light-emitting stage, but also avoid the line crosstalk affecting the image display effect.

[0076] The target signal line is also connected to the target signal V0 in the non-light-emitting stage, and can provide the target signal V0 for the first shielding line 17 and the second shielding line 21 described later in the light-emitting stage.

[0077] The target signal line is connected to the target transistor in the pixel circuit, and the conduction state of the target transistor can be controlled by the gate signal of the target transistor. In the non-light-emitting stage before the light-emitting stage, the target transistor is controlled to be turned on so that the target signal line and the pixel circuit are connected to input the target signal V0 to the pixel circuit. In the light-emitting stage, the target transistor is controlled to be turned off so that the target signal line and the pixel circuit are disconnected.

[0078] In one embodiment, the target signal line is a first reset signal line that provides a first reset signal VREF1, and the target signal V0 is the first reset signal VREF1. In this method, the first reset signal VREF1 is used as the target signal V0, and the coupling effect of the light-emitting control signal EM on the second node N2 is shielded based on the first reset signal VREF1. In the pixel circuit, the first reset signal VREF1 is used to reset the voltage of the first node N1 in the light-emitting stage. In the light-emitting stage, the first reset transistor T5 is controlled to be turned off by the first scanning signal SC_N1. At this time, the first reset signal line that provides the first reset signal VREF1 is disconnected from the pixel circuit. At this time, the light-emitting control signal EM is coupled to the first shielding line 17 connected to the first reset signal VREF1. Crosstalk will not generate additional line crosstalk to the pixel circuit, and will not affect the display effect, thereby being able to well improve the uniformity of low brightness and low grayscale and the grayscale color cast problem.

[0079] The first shielding line 17 can be located in the indium gallium zinc oxide layer AL2, and the first shielding line 17 is prepared by the indium gallium zinc oxide layer AL2, and no separate film layer is needed to prepare the first shielding line 17. Since the indium gallium zinc oxide layer AL2 is an IGZO material, it has a high transmittance to visible light. Therefore, preparing the first shielding line 17 by the indium gallium zinc oxide layer AL2 does not affect the transmittance of the area. For a display panel with a screen fingerprint recognition function, this method will not affect the fingerprint recognition effect.

[0080] In the embodiment of the present application, the target signal V0 is a DC constant voltage signal used to control the working state of the pixel circuit in the non-display stage, and the DC constant voltage signal is disconnected from the pixel circuit in the light-emitting stage. Figure 1 , Figure 3 and Figure 5 As shown, the gate and source and drain of each transistor in the pixel circuit need to be connected to a variety of signals, including the first reset signal VREF1, the second reset signal VREF2, the first power signal VDD, the second power signal VEE, the data signal VDATA, the first control signal SC_P*, the second control signal SC_P, the first scan signal SC_N1, the second scan signal SC_N2, the light control signal EM, and the bias signal DVH. Among them, the first reset signal VREF1, the second reset signal VREF2, and the bias signal DVH are DC constant voltage signals used to control the working state of the pixel circuit in the non-light-emitting stage, and the target signal V0 can be any one of the first reset signal VREF1, the second reset signal VREF2, and the bias signal DVH, and is not limited to using the first reset signal VREF1 as the target signal V0.

[0081] like Figure 2As shown, the display panel has multiple metal layers and two active layers. The connection line 13 and the light-emitting control signal line 11 can be prepared by selecting a metal layer in the display panel based on the wiring requirements, and the two are located in different metal layers. The first shielding line 17 can be prepared by at least one conductive layer between the two metal layers used to prepare the connection line 13 and the light-emitting control signal line 11.

[0082] As described above, the display panel has a substrate 10, on which a low temperature polysilicon layer AL1, a first metal layer MG1, a second metal layer MC, an indium gallium zinc oxide layer AL2, a third metal layer MG2 and a first data metal layer SD1 are sequentially arranged. Figure 6 As shown, the connection line 13 may be located in the first data metal layer SD1; the light emitting control signal line 11 may be located in the first metal layer MG1; and the first shielding line 17 may be located in at least one of the second metal layer MC, the indium gallium zinc oxide layer AL2 and the third metal layer MG2. Figure 6 The first shielding line 17 is located in the InGaZnO layer AL2 as an example for illustration.

[0083] If the connection line 13 is located in the first data metal layer SD1, the light emitting control signal line 11 is located in the first metal layer MG1, and the first shielding line 17 can be located in at least two of the second metal layer MC, the indium gallium zinc oxide layer AL2, and the third metal layer MG2; the wiring parts of the first shielding line 17 located in different layers are connected through the conductive hole Via1. In this way, the first shielding line 17 is prepared by multiple conductive layers, which can improve the shielding effect of the first shielding line 17.

[0084] refer to Figure 7 , Figure 7 It is a cross-sectional view of a pixel circuit layout at the intersection of a connection line and a light-emitting control signal line. In this method, the connection line 13 is located in the first data metal layer SD1, the light-emitting control signal line 11 is located in the first metal layer MG1, and the first shielding line 17 is a double-layer structure, one layer is located in the second metal layer MC, and the other layer is located in the indium gallium zinc oxide layer AL2. The two layers of the first shielding line 17 are connected through the conductive hole Via1. Figure 7 The conductive via Via1 between the two layers of first shielding wires 17 is not shown in the figure, and the conductive via Via1 is located outside the crossing position.

[0085] refer to Figure 8 , Figure 8 It is a schematic diagram of a pixel circuit layout in another display panel. In this embodiment, the pixel circuit is connected to the target signal line through the target conductive hole Via0; the first shielding line 17 reuses the target conductive hole Via0 to be connected to the target signal line.

[0086] exist Figure 8In the illustrated embodiment, the target conductive via Via0 is an existing conductive via Via1 in the pixel circuit for connecting the target signal line. Thus, the connection between the first shielding line 17 and the target signal line can be achieved without adding additional conductive vias or wiring, thereby simplifying the wiring in the pixel circuit.

[0087] The display panel has a plurality of pixel circuits arranged in an array, and different pixel circuits are connected to different light-emitting elements D. In one embodiment, the display panel can be Figure 8 As shown, in the row direction X of the array, in the same pixel circuit, the target conductive via Via0 and the first shielding line 17 are located on the same side of the driving transistor T3; the first shielding line connects the target conductive vias of the same pixel circuit.

[0088] In the row direction X of the array, when the target conductive hole Via0 and the first shielding line 17 are located on the same side of the driving transistor T3, the first shielding line 17 can be connected to the target conductive hole Via0 in the same pixel circuit to input the target signal V0, facilitating the connection between the first shielding line 17 and the target signal line.

[0089] You can Figure 8 As shown, the target conductive via Via0 is the conductive via Via1 used by the bias transistor T8 in the pixel circuit to connect the bias signal line. At this time, the target signal V0 is the bias signal DVH, and the first shielding line 17 can be connected to the conductive via Via1 used by the bias transistor T8 to connect the bias signal line, and the connection between the first shielding line 17 and the target signal line can be achieved without adding a conductive via separately.

[0090] exist Figure 8 In the illustrated method, the bias signal line is reused as the target signal line; the second electrode of the bias transistor T8 is connected to the bias signal line through the target conductive hole Via0; wherein the first shielding line 17 has a first portion 171 and a second portion 172 connected as one; the first portion 171 is located at a cross position; the second portion 172 extends from the light-emitting control signal line 11 connected to the pixel circuit to the target conductive hole Via0 to connect to the target conductive hole Via0. In this method, the first shielding line 17 in the pixel circuit directly reuses the target conductive hole Via0 connected to the bias transistor T8 to access the first reset signal VREF1, and the connection between the first shielding line 17 and the target signal line can be realized without separately preparing a conductive hole, which is convenient for the circuit layout in the display panel.

[0091] refer to Fig. 9 , Fig. 9 is a schematic diagram of a pixel circuit layout in another display panel. In this embodiment, Figure 8 The difference between the methods shown is that Fig. 9In the display panel shown, in the column direction Y of the array, in the same pixel circuit, the target conductive hole and the first shielding line 17 are located on different sides of the driving transistor T3, and the target conductive hole Via0 of the previous row of pixel circuits is set toward the next row of pixel circuits; the first shielding line 17 of the next row of pixel circuits is connected to the target conductive hole Via0 of the previous row of pixel circuits.

[0092] Fig. 9 Two target conductive holes Via0 are shown in the figure. The target conductive hole Via0 below Fig. 9 The first reset transistor T5 in the pixel circuit shown is used to connect to the conductive via Via1 of the first reset signal line, and the target conductive via Via0 above is the conductive via Via1 used to connect to the first reset signal line by the first reset transistor T5 in the pixel circuit of the previous row.

[0093] exist Fig. 9 The target conductive via Via0 is the conductive via Via1 used by the first reset transistor T5 in the pixel circuit to connect to the first reset signal line. At this time, the target signal V0 is the first reset signal VREF1, and the first shielding line 17 can be connected to the conductive via Via1 used by the first reset transistor T5 to connect to the first reset signal line. The connection between the first shielding line 17 and the target signal line can be achieved without adding a separate conductive via.

[0094] As described above, the pixel circuit has a second light-emitting control transistor T6, a first reset transistor T5 and a second reset transistor T7; the gate of the second light-emitting control transistor T6 is connected to the light-emitting control signal line 11, the first electrode is connected to the third node N3, the second electrode is connected to the fourth node N4, and the fourth node N4 is connected to the light-emitting element D; the gate of the first reset transistor T5 is connected to the first scanning signal line 16, the first electrode is connected to the first reset signal line, and the second electrode is connected to the first node N1; the gate of the second reset transistor T7 is connected to the first control signal line 12, the first electrode is connected to the second reset signal line, and the second electrode is connected to the fourth node N4.

[0095] The target signal line is one of the first reset signal line, the second reset signal line and the bias signal line.

[0096] As described above, the pixel circuit can be connected to the target signal line through the target conductive via Via0. The first shielding line 17 can be set to be connected to the target signal line through the target conductive via Via0, such as by using the existing conductive vias in the multiplexed pixel circuit to realize the connection between the first shielding line 17 and the target signal line.

[0097] If the target signal line is the first reset signal line, the target signal V0 is the first reset signal VREF1; if the target signal line is the second reset signal line, the target signal V0 is the second reset signal VREF2; if the target signal line is the bias signal line, the target signal V0 is the bias signal DVH.

[0098] The first reset signal VREF1, the second reset signal VREF2 and the bias signal DVH are all DC constant voltage signals for controlling the pixel circuit in the non-luminous stage. If the target signal line is one of the first reset signal line, the second reset signal line and the bias signal line, correspondingly, based on at least one of the first reset signal VREF1, the second reset signal VREF2 and the bias signal DVH, as the target signal V0, at this time, in the luminous stage, not only can the existing working signal of the pixel circuit be reused to shield the coupling of the luminous control signal EM to the second node N2, the interference of the luminous control signal EM to the target signal V0 will not affect the display effect, and the introduction of new line crosstalk that interferes with the luminous display can also be avoided.

[0099] like Fig. 9 As shown, if the first reset signal line is reused as the target signal line; the first electrode of the first reset transistor T5 is connected to the first reset signal line through the target conductive hole Via0; in the column direction Y of the array, the target conductive hole Via0 of the previous row of pixel circuits is arranged adjacent to the next row of pixel circuits; wherein the first shielding line 17 has a first part 171 and a second part 172 connected in an integral manner, the first part 171 is located at a cross position, and the second part 172 extends from the light emitting control signal line 11 connected to the pixel circuit where it is located to the previous row of pixel circuits to connect to the target conductive hole Via0 of the previous row of pixel circuits.

[0100] exist Fig. 9 In the manner shown, the first shielding line 17 in a pixel circuit reuses the target conductive via Via0 connected to the first reset transistor T5 of the previous pixel circuit adjacent in the column direction to access the first reset signal VREF1. The connection between the first shielding line 17 and the target signal line can be achieved without separately preparing a conductive via, which facilitates the circuit layout in the display panel.

[0101] refer to Fig.10 , Fig.10 is a schematic diagram of a pixel circuit layout in another display panel. In this embodiment, Fig.10 In the manner shown, the second reset signal line is reused as the target signal line, and the second reset signal VREF2 is used as the target signal V0; the first electrode of the second reset transistor T7 is connected to the second reset signal line through the target conductive hole Via0; wherein the first shielding line 17 has a first part 171 and a second part 172 that are integrally connected; the first part 171 is located at a cross position; the second part 172 extends from the light emitting control signal line 11 connected to the pixel circuit to the target conductive hole Via0 to connect to the target conductive hole Via0.

[0102] exist Fig.10In the manner shown, the first shielding line 17 in the pixel circuit directly reuses the target conductive via Via0 connected to its own second reset transistor T7 to access the second reset signal VREF2. The connection between the first shielding line 17 and the target signal line can be achieved without separately preparing a conductive via, which facilitates the circuit layout in the display panel.

[0103] refer to Fig.11 , Fig.11 The schematic diagram is a layout diagram of a pixel circuit in a display panel, wherein the display panel has a plurality of pixel circuits P arranged in an array, different pixel circuits P are connected to different light-emitting elements D, pixel circuits P in the same column are connected to the same data line 18, and pixel circuits P in different columns are connected to different data lines 18. The data line 18 extends along the column direction Y, and the plurality of data lines 18 are arranged in sequence along the row direction X. The data line 18 is connected to a driver chip 20 disposed in the lower end frame area through a fan-out line 19.

[0104] In order to reduce the border width, the array area fan-out (Fanout in Array Area, FIAA for short) can be used to move the data line 18 connected to the pixel circuit column at the edge of the display panel to the middle area of ​​the display panel, thereby reducing the influence of the fan-out line 19 connected to the edge pixel circuit column on the border area width.

[0105] refer to Figure 12-14 , Fig.12 FIG. 1 is a schematic diagram of another layout of pixel circuits in a display panel. Fig.13 for Fig.12 The layout of the first data line and the overlapping second pixel circuit in the display panel is shown, Fig.14 for Fig.13 The cross-sectional view of the layout shown is at the intersection of the connecting line and the light-emitting control signal line.

[0106] In the row direction X of the array, the display panel has a first sub-display area AA1 and a second sub-display area AA2 arranged in sequence; the first pixel circuit P1 in the first sub-display area AA1 is connected to the first data line 181, and the second pixel circuit P2 in the second sub-display area AA2 is connected to the second data line 182, and the first data line 181 and the second data line 182 are both located in the second sub-display area AA2. In the direction perpendicular to the plane where the display panel is located, the first data line 181 and the connecting line 13 in the second pixel circuit P2 have an overlapping portion (such as Fig.12 and Fig.13 In the overlapping part, there is a second shielding line 21 between the first data line 181 and the connecting line 13, and the second shielding line 21 is connected to the target signal line to shield the connecting line 13 and the first data line 181 based on the target signal V0.

[0107] exist Figure 12-13In the manner shown, based on the FIAA technology, the first data line 181 connected to the pixel circuit column at the edge of the display panel is moved to the second sub-display area AA2 close to the center area of ​​the display panel, relative to Fig.11 The method shown can reduce the influence of the fan-out line 19 connected to the edge pixel circuit column on the width of the lower frame. The first data line 181 and the second pixel circuit P2 are arranged to overlap in a direction perpendicular to the display panel, which facilitates the wiring of the first data line 181 in the second sub-display area AA2.

[0108] Since the first data line 181 and the connecting line 13 in the second pixel circuit P2 have an overlapping portion, such as Fig.14 As shown, at the intersection of the connecting line 13 and the light-emitting control signal line 11, the first data line 181 and the connecting line 13 have a cross-coupling position. When the data signal VDATA in the first data line 181 jumps, it will cause the voltage of the connecting line 13 to change, and then cause the voltage of the second node N2 to fluctuate, thereby affecting the display problem.

[0109] Since the target signal line is the working signal of the pixel circuit in the non-luminous stage, the second shielding line 21 connected to the target signal line can not only shield the coupling of the first data line 181 to the lower connection line 13, but also avoid introducing new line crosstalk to interfere with the display. Similar to the above, the target signal V0 can be any one of the first reset signal VREF1, the second reset signal VREF2 and the bias signal DVH.

[0110] exist Figure 12-14 In the shown manner, there is a second shielding line 21 between the first data line 181 and the connecting line 13. The second shielding line 21 is connected to the target signal line, which can avoid the interference of the data signal VDATA jump in the first data line 181 on the voltage of the second node N2, thereby preventing the display problem caused by the interference.

[0111] In the embodiment of the present application, the second shielding line 21 may be directly connected to the target signal line, or the second shielding line 21 may be connected to the target signal line through the first shielding line 17 .

[0112] exist Fig.13 In the illustrated embodiment, the second shielding line 21 passes through a conductive hole Via1 located above the first control signal line 12 and the first shielding line 17 to access the target signal V0 through the first shielding line 17 .

[0113] If the second shielding line 21 is directly connected to the target signal line, the pixel circuit is connected to the target signal line through the target conductive hole Via0 in the same way as the first shielding line 17 is connected to the target signal V0; the second shielding line 21 reuses the target conductive hole Via0 to be connected to the target signal line, which will not be described in detail in the embodiment of the present application.

[0114] In one embodiment, if Fig.14 As shown, the connection line 13 is located in the first data metal layer SD1; the light emitting control signal line 11 is located in the first metal layer MG1; the first shielding line 17 is located in at least one of the second metal layer MC, the indium gallium zinc oxide layer AL2 and the third metal layer MG2; the second shielding line 21 is located in the second data metal layer SD2; and the first data line 181 is located in the third data metal layer SD3. Fig.14 The first shielding line 17 is located in the InGaZnO layer AL2 as an example for illustration.

[0115] In the embodiment of the present application, different conductive layers already in the display panel may be used to prepare the first shielding line 17 , the second shielding line 21 and the first data line 181 , respectively, without increasing the thickness of the display panel.

[0116] refer to Fig.15 , Fig.15 for Fig.12 Another layout of the first data line and the overlapping second pixel circuit in the display panel shown, Fig.16 for Fig.12 Another cross-sectional view of the layout shown at the intersection of the connecting line and the light-emitting control signal line.

[0117] and Fig.13 and Fig.14 The same way is shown, Fig.15 and Fig.16 The FIAA scheme is also adopted. The display panel has a plurality of pixel circuits arranged in an array, and different pixel circuits are connected to different light-emitting elements D. In the row direction X of the array, the display panel has a first sub-display area AA1 and a second sub-display area AA2 arranged in sequence. The first pixel circuit P1 in the first sub-display area AA1 is connected to the first data line 181, and the second pixel circuit P2 in the second sub-display area AA2 is connected to the second data line 182. The first data line 181 and the second data line 182 are both located in the second sub-display area AA2. Fig.13 and Fig.14 The difference between the methods shown is that Fig.15 and Fig.16 In the manner shown, in a direction perpendicular to the plane where the display panel is located, the first data line 181 and the connecting line 13 in the second pixel circuit P2 have an overlapping portion; in the overlapping portion, there is a second shielding line 21 between the first data line 181 and the connecting line 13, and the second shielding line 21 is connected to the target signal line, and the connecting line 13 and the first data line 181 are shielded based on the target signal.

[0118] and Fig.13 and Fig.14 The difference between the methods shown is that Fig.15 and Fig.16In the illustrated embodiment, the first connecting line 13 may not be provided. Although this embodiment has coupling between the connecting line 13 and the light emitting control signal line 11 , the coupling problem between the connecting line 13 and the first data line 181 can be solved.

[0119] Based on the display provided in the above embodiment, an electronic device is structured as follows Fig.17 As shown, Fig.17 This is a top view of an electronic device provided in an embodiment of the present application. The electronic device includes a display panel 22. The display panel can adopt the structure provided in any implementation manner of the above embodiments.

[0120] In the embodiments of the present application, the electronic device may be a mobile phone, a tablet computer, a laptop computer, a smart wearable device, etc. The embodiments of the present application do not limit the implementation method of the electronic device.

[0121] The electronic device adopts the display panel 22 provided in the above embodiment, which can avoid the coupling influence of the light control signal EM in the light control signal line 11 on the potential of the second node N2 and / or can avoid the coupling influence of the data signal VDATA jump in the first data line 181 on the potential of the second node N2, thereby improving the image display quality.

[0122] In the specification of this application, each embodiment is described in a progressive, parallel, or progressive and parallel manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. The implementation methods provided in the embodiments of this application can be combined with each other if there is no contradiction.

[0123] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification identify the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region, or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially refer to positioning on the upper side of another element according to the direction of gravity.

[0124] The terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0125] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0126] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: The display panel includes a light emitting element and a pixel circuit connected to the light emitting element; The pixel circuit comprises: a driving transistor, wherein a gate of the driving transistor is connected to the first node, a first electrode is connected to the second node, and a second electrode is connected to the third node; a first light emission control transistor, wherein a gate of the first light emission control transistor is connected to a light emission control signal line, a first electrode is connected to a first power supply signal line, and a second electrode is connected to the second node; A bias transistor, wherein a gate of the bias transistor is connected to a first control signal line, a first electrode is connected to the second node via a connecting line, and a second electrode is connected to a bias signal line; the connecting line is insulated and crosses the light emitting control signal line; A first shielding line is located at the intersection of the connecting line and the light-emitting control signal line, and a portion of the first shielding line is located between the connecting line and the light-emitting control signal line; the first shielding line is connected to a target signal line, and shields the connecting line and the light-emitting control signal line based on a target signal connected to the target signal line.

2. The display panel according to claim 1, characterized in that: The target signal line is connected to the pixel circuit in the non-luminous phase to control the working state of the pixel circuit in the non-luminous phase; and is disconnected from the pixel circuit in the luminous phase.

3. The display panel according to claim 1, characterized in that: The pixel circuit is connected to the target signal line through a target conductive hole; The first shielding line reuses the target conductive via to be connected to the target signal line.

4. The display panel according to claim 3, characterized in that: The display panel has a plurality of pixel circuits arranged in an array, and different pixel circuits are connected to different light-emitting elements; In the column direction of the array, in the same pixel circuit, the target conductive via and the first shielding line are located on the same side of the driving transistor; and the first shielding line connects the target conductive via of the same pixel circuit.

5. The display panel according to claim 3, characterized in that: The display panel has a plurality of pixel circuits arranged in an array, and different pixel circuits are connected to different light-emitting elements; In the column direction of the array, in the same pixel circuit, the target conductive hole and the first shielding line are located on different sides of the driving transistor, and the target conductive hole of the pixel circuit in the previous row is set toward the pixel circuit in the next row; the first shielding line of the pixel circuit in the next row is connected to the target conductive hole of the pixel circuit in the previous row.

6. The display panel according to claim 1, characterized in that: The pixel circuit comprises a second light emission control transistor, a first reset transistor and a second reset transistor; The gate of the second light emitting control transistor is connected to the light emitting control signal line, the first electrode is connected to the third node, the second electrode is connected to the fourth node, and the fourth node is connected to the light emitting element; The gate of the first reset transistor is connected to the first scanning signal line, the first electrode is connected to the first reset signal line, and the second electrode is connected to the first node; The gate of the second reset transistor is connected to the first control signal line, the first electrode is connected to the second reset signal line, and the second electrode is connected to the fourth node; The target signal line is one of the first reset signal line, the second reset signal line and the bias signal line.

7. The display panel according to claim 6, characterized in that: The first reset signal line is reused as the target signal line; the first electrode of the first reset transistor is connected to the first reset signal line through a target conductive hole; the target conductive hole of the pixel circuit of the previous row is arranged adjacent to the pixel circuit of the next row; Among them, the first shielding line has a first part and a second part that are integrally connected, the first part is located at the intersection, and the second part is extended from the light-emitting control signal line connected to the pixel circuit where it is located to the previous row of pixel circuits to connect to the target conductive hole of the previous row of pixel circuits.

8. The display panel according to claim 6, characterized in that: The second reset signal line is reused as the target signal line; the first electrode of the second reset transistor is connected to the second reset signal line through the target conductive hole; Among them, the first shielding line has a first part and a second part that are integrally connected; the first part is located at the intersection; the second part extends from the light-emitting control signal line connected to the pixel circuit to the target conductive hole to connect to the target conductive hole.

9. The display panel according to claim 6, characterized in that: The bias signal line is reused as the target signal line; the second electrode of the bias transistor is connected to the bias signal line through a target conductive hole; Among them, the first shielding line has a first part and a second part that are integrally connected; the first part is located at the intersection; the second part extends from the light-emitting control signal line connected to the pixel circuit to the target conductive hole to connect to the target conductive hole.

10. The display panel according to claim 1, characterized in that: The display panel comprises a substrate, on which a low temperature polysilicon layer, a first metal layer, a second metal layer, an indium gallium zinc oxide layer, a third metal layer and a first data metal layer are sequentially arranged; The connection line is located in the first data metal layer; the light emitting control signal line is located in the first metal layer; and the first shielding line is located in at least one of the second metal layer, the indium gallium zinc oxide layer and the third metal layer.

11. The display panel according to claim 10, characterized in that: The first shielding line is located in at least two of the second metal layer, the indium gallium zinc oxide layer and the third metal layer; The routing parts of the first shielding wire located in different layers are connected through conductive holes.

12. The display panel according to claim 1, characterized in that: The display panel has a plurality of pixel circuits arranged in an array, and different pixel circuits are connected to different light-emitting elements; In the row direction of the array, the display panel has a first sub-display area and a second sub-display area arranged in sequence; a first pixel circuit in the first sub-display area is connected to a first data line, a second pixel circuit in the second sub-display area is connected to a second data line, and the first data line and the second data line are both located in the second sub-display area; In a direction perpendicular to the plane where the display panel is located, the first data line and the connecting line in the second pixel circuit have an overlapping portion; in the overlapping portion, a second shielding line is provided between the first data line and the connecting line, and the second shielding line is connected to the target signal line to shield the connecting line and the first data line based on the target signal.

13. The display panel according to claim 12, characterized in that: The second shielding line is directly connected to the target signal line, or the second shielding line is connected to the target signal line through the first shielding line.

14. The display panel according to claim 13, characterized in that: If the second shielding line is directly connected to the target signal line, the pixel circuit is connected to the target signal line through a target conductive hole; the second shielding line reuses the target conductive hole to be connected to the target signal line.

15. The display panel according to claim 13, characterized in that: The display panel comprises a substrate, on which a low temperature polysilicon layer, a first metal layer, a second metal layer, an indium gallium zinc oxide layer, a third metal layer, a first data metal layer, a second data metal layer and a third data metal layer are sequentially arranged; Among them, the connecting line is located in the first data metal layer; the light-emitting control signal line is located in the first metal layer; the first shielding line is located in at least one of the second metal layer, the indium gallium zinc oxide layer and the third metal layer; the second shielding line is located in the second data metal layer; and the first data line is located in the third data metal layer.

16. A display panel, characterized in that: The display panel includes a light emitting element and a pixel circuit connected to the light emitting element; The pixel circuit comprises: a driving transistor, wherein a gate of the driving transistor is connected to the first node, a first electrode is connected to the second node, and a second electrode is connected to the third node; a first light emission control transistor, wherein a gate of the first light emission control transistor is connected to a light emission control signal line, a first electrode is connected to a first power supply signal line, and a second electrode is connected to the second node; A bias transistor, wherein a gate of the bias transistor is connected to a first control signal line, a first electrode is connected to the second node via a connecting line, and a second electrode is connected to a bias signal line; the connecting line is insulated and crosses the light emitting control signal line; In the row direction of the array, the display panel has a first sub-display area and a second sub-display area arranged in sequence; a first pixel circuit in the first sub-display area is connected to a first data line, a second pixel circuit in the second sub-display area is connected to a second data line, and the first data line and the second data line are both located in the second sub-display area; In a direction perpendicular to the plane where the display panel is located, the first data line and the connecting line in the second pixel circuit have an overlapping portion; in the overlapping portion, a second shielding line is provided between the first data line and the connecting line, and the second shielding line is connected to the target signal line to shield the connecting line and the first data line based on the target signal.

17. An electronic device, characterized in that: Comprising a display panel as described in any one of claims 1-16.

Images