Low-cost configurable matrix backlight pipeline driving system and storage medium
By designing a matrix backlight pipeline driving system with a multi-stage pipeline structure inside the FPGA, the problem of high matrix backlight control in the prior art is solved, low-cost matrix backlight control is realized, and the dependence on external DDR is reduced.
Patent Information
- Application Number
- CN202411213653.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2024-12-13
AI Technical Summary
The existing matrix backlight control method is costly in the automotive electronics industry, mainly due to the need to use large RAM chips such as DDR for data cache, which leads to high costs.
A low-cost configurable matrix backlight pipeline driving system was designed to generate backlight data by using a multi-stage pipeline structure inside the FPGA, replacing the external DDR cache, including display data acquisition module, matrix backlight data generation module, and matrix backlight control module , clock module and data configuration module, use only FPGA common resources to realize the hardware driver of matrix backlighting.
This significantly reduces the cost. By using resources multiple times within the FPGA, the need for plug-in DDR is avoided, and efficient control of matrix backlight is achieved.
Smart Images
Figure CN119132242A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of display terminal matrix backlight control, and more specifically, to a low-cost configurable matrix backlight pipeline driving system and a storage medium. Background Art
[0002] At present, matrix backlight technology is being introduced into the automotive electronics industry. The main products currently introduced are car screen backlight and matrix backlight headlights. For car screens, the introduction of matrix backlight systems can significantly reduce screen energy consumption, improve screen contrast, and thus improve user experience and product quality. As a mature controllable programmable device, FPGA has incomparable advantages in parallel computing. The efficiency of many algorithms can be improved by several orders of magnitude after parallel processing by FPGA. It is currently the main chip solution for parallel computing. At present, the domestic FPGA industry is on the rise, and more and more domestic FPGAs have passed the automotive certification, which has greatly reduced the cost of using FPGAs. Domestic FPGAs have gradually penetrated into various fields. In the past, the use of FPGAs to control matrix backlights on car screens often required the use of large RAM chips such as DDR to cache display data in DDR, and then generate corresponding matrix backlight control data through FPGA operations to control the matrix backlight. However, the application cost of this method is relatively high.
[0003] The prior art discloses a matrix backlight control method, device, screen projector and storage medium of a display terminal, which belongs to the technical field of matrix backlight control of display terminals. The method is: after the display terminal is fully initialized, a preset startup picture of the current display terminal system is obtained; based on the matrix backlight algorithm, the matrix backlight data corresponding to the preset startup picture is determined; when the display terminal is powered on next time, the matrix backlight is controlled based on the matrix backlight data to realize the matrix backlight control when the preset startup picture is displayed. After the display terminal system is fully initialized, the matrix backlight data of the preset startup picture of the current system is calculated and stored. When the display terminal is powered on next time, before receiving a new matrix backlight control command, the matrix backlight controller calls the matrix backlight data for display. Therefore, the matrix backlight control can be performed as soon as the display terminal is powered on and initialized, and the function of preventing the display terminal from screen flashing can be realized without the user noticing. However, this method still needs to use large RAM chips such as DDR to cache the display data in DDR, and the cost is still high. Summary of the invention
[0004] The purpose of the present invention is to disclose a lower-cost configurable matrix backlight pipeline driving system and storage medium.
[0005] In order to achieve the above object, the present invention provides a low-cost configurable matrix backlight pipeline driving system, comprising: Display data acquisition module, matrix backlight data generation module, matrix backlight control module, clock module and data configuration module; wherein the display data acquisition module is data connected with the matrix backlight data generation module; the matrix backlight data generation module is data connected with the matrix backlight control module; the clock module is data connected with the display data acquisition module, the matrix backlight data generation module and the matrix backlight control module respectively; the data configuration module is data connected with the display data acquisition module, the matrix backlight data generation module and the matrix backlight control module respectively; Among them, the display data acquisition module is used to connect to various data interfaces, organize the data transmitted from the interface and send it to the matrix backlight data generation module Matrix backlight data generation module: used to generate backlight data, including a first-level data acquisition pipeline, a second-level row data processing pipeline, a third-level column data processing pipeline, and a fourth-level frame data processing pipeline; Matrix backlight control module: used to combine the data from the data configuration module and receive the data from the matrix backlight data generation module to drive the matrix backlight hardware; Clock module: used to provide the clock signal required for operation; Data configuration module: used to configure matrix backlight related parameters.
[0006] Furthermore, the data configuration module includes: Adapting the hardware interface and related drivers of the system according to the related counts, including at least one of the following: configuring the port for image data input, the format of image data, the frequency of image data input, the matrix backlight partition configuration, the matrix backlight output interface configuration, and the matrix backlight communication protocol configuration; Configuring relevant parameters in the matrix backlight data generation, including at least one of the following: demura data of the entire matrix backlight, overall light type parameters of the matrix backlight, and initialization parameters of the matrix backlight; Further, the matrix backlight data generation module: the four pipeline structures that do not interfere with each other are respectively a first-level data acquisition pipeline, a second-level row data processing pipeline, a third-level column data processing pipeline and a fourth-level frame data processing pipeline; The first-level data collection pipeline includes: at least three small data collection modules; The second-level row data processing pipeline includes: at least three row data processing small modules; The third-level column data processing pipeline: at least one small column data processing module; The fourth-level frame data processing pipeline: at least one small frame data processing module.
[0007] Further, including: Calculate the ratio of the clock required for data acquisition of the first-level data acquisition pipeline to the effective data of the data, and obtain the first-level data processing clock ratio; Calculate the ratio of the time required for the second-level row data processing pipeline to process the row data to the effective data of the data to obtain the second-level data processing clock ratio; If the first-stage data processing clock ratio is greater than 1.25, a small data acquisition module is added to the first-stage data acquisition pipeline; If the second-level data processing clock ratio is greater than 1.25, a small row data processing module is added to the second-level row data processing pipeline; Further, including: The display data acquisition module, matrix backlight data generation module, matrix backlight control module, clock module and data configuration module only use FPGA general resources Further, the display data acquisition module, the matrix backlight data generation module, the matrix backlight control module, the clock module and the data configuration module use a clock together, and the clock has the same frequency as the display data; Furthermore, the display data acquisition module is connected to the matrix backlight data generation module in a one-way communication manner; the matrix backlight data generation module is connected to the matrix backlight control module in a one-way communication manner; the clock module is connected to the display data acquisition module, the matrix backlight data generation module and the matrix backlight control module in a one-way communication manner; the data configuration module is connected to the display data acquisition module, the matrix backlight data generation module and the matrix backlight control module in a one-way communication manner; Further, adapting the hardware interface and related drivers of the system according to the related counts includes: Get the following information: communication rate of the interface, data rate of the interface, format of displayed data; Configure the interface of the display data acquisition module according to the interface type; Configure the clock module to display the data acquisition module clock according to the communication rate of the interface; Configure the matrix backlight data generation module clock in the clock module according to the rate of the interface data; Furthermore, the configuration of relevant parameters in the matrix backlight data generation also includes: the communication frequency of the interface, the initialization command, and the specific mapping rules of each partition; wherein the partition mapping rules are stored in a dedicated ROM area in the system.
[0008] In addition, the present invention also provides a low-cost configurable matrix backlight pipeline drive storage medium, characterized in that a computer program is stored thereon, and when the computer program is executed by a processor, the above-mentioned low-cost configurable matrix backlight pipeline drive system is implemented.
[0009] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The present invention can use the common resources inside the FPGA in small quantities and multiple times through the pipeline structure in the matrix backlight data generation module, and replace the external DDR to cache the entire frame of the picture without using the external DDR, thereby significantly reducing the cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1 A block diagram of the low-cost configurable matrix backlight pipeline driving system described in Example 1; Figure 2 This is a structural diagram of a three-module matrix backlight data generation module described in Example 3; Figure 3 This is a structural diagram of a four-module matrix backlight data generation module as described in Example 4; DETAILED DESCRIPTION The drawings are for illustrative purposes only and should not be construed as limiting the present patent; The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.
[0011] Embodiment 1: The present invention provides Figure 1 The low-cost configurable matrix backlight pipeline driving system shown includes: Display data acquisition module, matrix backlight data generation module, matrix backlight control module, clock module and data configuration module; wherein the display data acquisition module is data connected with the matrix backlight data generation module; the matrix backlight data generation module is data connected with the matrix backlight control module; the clock module is data connected with the display data acquisition module, the matrix backlight data generation module and the matrix backlight control module respectively; the data configuration module is data connected with the display data acquisition module, the matrix backlight data generation module and the matrix backlight control module respectively; Among them, the display data acquisition module is used to connect to various data interfaces, organize the data transmitted from the interface and send it to the matrix backlight data generation module Matrix backlight data generation module: used to generate backlight data, including a first-level data acquisition pipeline, a second-level row data processing pipeline, a third-level column data processing pipeline, and a fourth-level frame data processing pipeline; Matrix backlight control module: used to combine the data from the data configuration module and receive the data from the matrix backlight data generation module to drive the matrix backlight hardware; Clock module: used to provide the clock signal required for operation; Data configuration module: used to configure matrix backlight related parameters.
[0012] This embodiment can use the common resources inside the FPGA in small quantities and multiple times through the pipeline structure in the matrix backlight data generation module. In the case of no external DDR, it can replace the external DDR to cache the entire frame of the image, thereby significantly reducing costs.
[0013] Embodiment 2: The data configuration module includes: Adapting the hardware interface and related drivers of the system according to the related counts, including at least one of the following: configuring the port for image data input, the format of image data, the frequency of image data input, the matrix backlight partition configuration, the matrix backlight output interface configuration, and the matrix backlight communication protocol configuration; Configuring relevant parameters in the matrix backlight data generation, including at least one of the following: demura data of the entire matrix backlight, overall light type parameters of the matrix backlight, and initialization parameters of the matrix backlight; Matrix backlight data generation module: four non-interfering pipeline structures are the first-level data acquisition pipeline, the second-level row data processing pipeline, the third-level column data processing pipeline and the fourth-level frame data processing pipeline; The first-level data collection pipeline includes: at least three small data collection modules; The second-level row data processing pipeline includes: at least three row data processing small modules; The third-level column data processing pipeline: at least one small column data processing module; The fourth-level frame data processing pipeline: at least one small frame data processing module.
[0014] Calculate the ratio of the clock required for data acquisition of the first-level data acquisition pipeline to the effective data of the data, and obtain the first-level data processing clock ratio; Calculate the ratio of the time required for the second-level row data processing pipeline to process the row data to the effective data of the data to obtain the second-level data processing clock ratio; If the first-stage data processing clock ratio is greater than 1.25, a small data acquisition module is added to the first-stage data acquisition pipeline; If the second-level data processing clock ratio is greater than 1.25, a small row data processing module is added to the second-level row data processing pipeline; The display data acquisition module, matrix backlight data generation module, matrix backlight control module, clock module and data configuration module only use FPGA general resources The display data acquisition module, the matrix backlight data generation module, the matrix backlight control module, the clock module and the data configuration module all use a clock, which is the same as the frequency of the display data; The display data acquisition module is connected to the matrix backlight data generation module in a one-way communication manner; the matrix backlight data generation module is connected to the matrix backlight control module in a one-way communication manner; the clock module is connected to the display data acquisition module, the matrix backlight data generation module and the matrix backlight control module in a one-way communication manner; the data configuration module is connected to the display data acquisition module, the matrix backlight data generation module and the matrix backlight control module in a one-way communication manner; Adapting the system's hardware interfaces and related drivers based on the relevant counts includes: Get the following information: communication rate of the interface, data rate of the interface, format of displayed data; Configure the interface of the display data acquisition module according to the interface type; Configure the clock module to display the data acquisition module clock according to the communication rate of the interface; Configure the matrix backlight data generation module clock in the clock module according to the rate of the interface data; The configuration of relevant parameters in the matrix backlight data generation also includes: the communication frequency of the interface, the initialization command, and the specific mapping rules of each partition; wherein the partition mapping rules are stored in a dedicated ROM area in the system.
[0015] This embodiment can use the common resources inside the FPGA in small quantities and multiple times through the pipeline structure in the matrix backlight data generation module. In the case of no external DDR, it can replace the external DDR to cache the entire frame of the image, thereby significantly reducing costs.
[0016] Embodiment three: This embodiment further discloses on the basis of the first embodiment: The data configuration module includes: Adapting the hardware interface and related drivers of the system according to the related counts, including at least one of the following: configuring the port for image data input, the format of image data, the frequency of image data input, the matrix backlight partition configuration, the matrix backlight output interface configuration, and the matrix backlight communication protocol configuration; Configuring relevant parameters in the matrix backlight data generation, including at least one of the following: demura data of the entire matrix backlight, overall light type parameters of the matrix backlight, and initialization parameters of the matrix backlight; The matrix backlight data generation module is as follows Figure 2 The three-module matrix backlight data generation module shown: the four pipeline structures that do not interfere with each other are the first-level data acquisition pipeline, the second-level row data processing pipeline, the third-level column data processing pipeline and the fourth-level frame data processing pipeline; The first-level data collection pipeline includes: three small data collection modules; The second-level row data processing pipeline includes: three small row data processing modules; The third-level column data processing pipeline: a small column data processing module; The fourth-level frame data processing pipeline: a small frame data processing module; One of the small modules is in working state, the other two small modules focus on exchanging data with one small module, and the last small module enters the waiting state.
[0017] Calculate the ratio of the clock required for data acquisition of the first-level data acquisition pipeline to the effective data of the data, and obtain the first-level data processing clock ratio; Calculate the ratio of the time required for the second-level row data processing pipeline to process the row data to the effective data of the data to obtain the second-level data processing clock ratio; If the first-stage data processing clock ratio is greater than 1.25, a small data acquisition module is added to the first-stage data acquisition pipeline; If the second-level data processing clock ratio is greater than 1.25, a small row data processing module is added to the second-level row data processing pipeline; The display data acquisition module, matrix backlight data generation module, matrix backlight control module, clock module and data configuration module only use FPGA general resources The display data acquisition module, the matrix backlight data generation module, the matrix backlight control module, the clock module and the data configuration module all use a clock, which is the same as the frequency of the display data; The display data acquisition module is connected to the matrix backlight data generation module in a one-way communication manner; the matrix backlight data generation module is connected to the matrix backlight control module in a one-way communication manner; the clock module is connected to the display data acquisition module, the matrix backlight data generation module and the matrix backlight control module in a one-way communication manner; the data configuration module is connected to the display data acquisition module, the matrix backlight data generation module and the matrix backlight control module in a one-way communication manner; Adapting the system's hardware interfaces and related drivers based on the relevant counts includes: Get the following information: communication rate of the interface, data rate of the interface, format of displayed data; Configure the interface of the display data acquisition module according to the interface type; Configure the clock module to display the data acquisition module clock according to the communication rate of the interface; Configure the matrix backlight data generation module clock in the clock module according to the rate of the interface data; The configuration of relevant parameters in the matrix backlight data generation also includes: the communication frequency of the interface, the initialization command, and the specific mapping rules of each partition; wherein the partition mapping rules are stored in a dedicated ROM area in the system.
[0018] This embodiment can use the common resources inside the FPGA in small quantities and multiple times through the pipeline structure in the matrix backlight data generation module. In the case of no external DDR, it can replace the external DDR to cache the entire frame of the image, thereby significantly reducing costs.
[0019] Embodiment 4: This embodiment further discloses on the basis of the first embodiment: The data configuration module includes: Adapting the hardware interface and related drivers of the system according to the related counts, including at least one of the following: configuring the port for image data input, the format of image data, the frequency of image data input, the matrix backlight partition configuration, the matrix backlight output interface configuration, and the matrix backlight communication protocol configuration; Configuring relevant parameters in the matrix backlight data generation, including at least one of the following: demura data of the entire matrix backlight, overall light type parameters of the matrix backlight, and initialization parameters of the matrix backlight; The matrix backlight data generation module is as follows Figure 3 The four small module matrix backlight data generation module shown: the four pipeline structures that do not interfere with each other are the first-level data acquisition pipeline, the second-level row data processing pipeline, the third-level column data processing pipeline and the fourth-level frame data processing pipeline; The first-level data collection pipeline includes: four small data collection modules; The second-level row data processing pipeline includes: four small row data processing modules; The third-level column data processing pipeline: a small column data processing module; The fourth-level frame data processing pipeline: a small frame data processing module; One of the small modules is in working state; one of the remaining three small modules ends the working state and enters the waiting state, another small module performs data exchange, and the last small module enters the waiting state.
[0020] Calculate the ratio of the clock required for data acquisition of the first-level data acquisition pipeline to the effective data of the data, and obtain the first-level data processing clock ratio; Calculate the ratio of the time required for the second-level row data processing pipeline to process the row data to the effective data of the data to obtain the second-level data processing clock ratio; If the first-stage data processing clock ratio is greater than 1.25, a small data acquisition module is added to the first-stage data acquisition pipeline; If the second-level data processing clock ratio is greater than 1.25, a small row data processing module is added to the second-level row data processing pipeline; The display data acquisition module, matrix backlight data generation module, matrix backlight control module, clock module and data configuration module only use FPGA general resources The display data acquisition module, the matrix backlight data generation module, the matrix backlight control module, the clock module and the data configuration module all use a clock, which is the same as the frequency of the display data; The display data acquisition module is connected to the matrix backlight data generation module in a one-way communication manner; the matrix backlight data generation module is connected to the matrix backlight control module in a one-way communication manner; the clock module is connected to the display data acquisition module, the matrix backlight data generation module and the matrix backlight control module in a one-way communication manner; the data configuration module is connected to the display data acquisition module, the matrix backlight data generation module and the matrix backlight control module in a one-way communication manner; Adapting the system's hardware interfaces and related drivers based on the relevant counts includes: Get the following information: communication rate of the interface, data rate of the interface, format of displayed data; Configure the interface of the display data acquisition module according to the interface type; Configure the clock module to display the data acquisition module clock according to the communication rate of the interface; Configure the matrix backlight data generation module clock in the clock module according to the rate of the interface data; The configuration of relevant parameters in the matrix backlight data generation also includes: the communication frequency of the interface, the initialization command, and the specific mapping rules of each partition; wherein the partition mapping rules are stored in a dedicated ROM area in the system.
[0021] This embodiment can use the common resources inside the FPGA in small quantities and multiple times through the pipeline structure in the matrix backlight data generation module. In the case of no external DDR, it can replace the external DDR to cache the entire frame of the image, thereby significantly reducing costs.
[0022] Embodiment 4: This embodiment also provides a low-cost configurable matrix backlight pipeline drive storage medium, characterized in that a computer program is stored thereon, and when the computer program is executed by a processor, the above-mentioned low-cost configurable matrix backlight pipeline drive system is implemented.
[0023] This embodiment can use the common resources inside the FPGA in small quantities and multiple times through the pipeline structure in the matrix backlight data generation module. In the case of no external DDR, it can replace the external DDR to cache the entire frame of the image, thereby significantly reducing costs.
[0024] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.
Claims
1. Low-cost configurable matrix backlight pipeline drive system, It is characterized in that include: Display data acquisition module, matrix backlight data generation module, matrix backlight control module, clock module and data configuration module; The display data acquisition module is data connected with the matrix backlight data generation module; The matrix backlight data generation module is data-connected with the matrix backlight control module; the clock module is data-connected with the display data acquisition module, the matrix backlight data generation module and the matrix backlight control module respectively; the data configuration module is data-connected with the display data acquisition module, the matrix backlight data generation module and the matrix backlight control module respectively; Among them, the display data acquisition module is used to connect to various data interfaces, organize the data transmitted from the interface and send it to the matrix backlight data generation module Matrix backlight data generation module: used to generate backlight data, including a first-level data acquisition pipeline, a second-level row data processing pipeline, a third-level column data processing pipeline, and a fourth-level frame data processing pipeline; Matrix backlight control module: used to combine the data from the data configuration module and receive the data from the matrix backlight data generation module to drive the matrix backlight hardware; Clock module: used to provide the clock signal required for operation; Data configuration module: used to configure matrix backlight related parameters.
2. The low-cost configurable matrix backlight pipeline driving system according to claim 1, It is characterized in that The data configuration module includes: Adapting the hardware interface and related drivers of the system according to the related counts, including at least one of the following: configuring the port for image data input, the format of image data, the frequency of image data input, the matrix backlight partition configuration, the matrix backlight output interface configuration, and the matrix backlight communication protocol configuration; Relevant parameters are configured in the matrix backlight data generation, including at least one of the following: demura data of the entire matrix backlight, overall light type parameters of the matrix backlight, and initialization parameters of the matrix backlight.
3. The low-cost configurable matrix backlight pipeline driving system according to claim 1, It is characterized in that Matrix backlight data generation module: four non-interfering pipeline structures are the first-level data acquisition pipeline, the second-level row data processing pipeline, the third-level column data processing pipeline and the fourth-level frame data processing pipeline; The first-level data collection pipeline includes: at least three small data collection modules; The second-level row data processing pipeline includes: at least three row data processing small modules; The third-level column data processing pipeline: at least one small column data processing module; The fourth-level frame data processing pipeline: at least one small frame data processing module.
4. The low-cost configurable matrix backlight pipeline driving system according to claim 3, It is characterized in that include: Calculate the ratio of the clock required for data acquisition of the first-level data acquisition pipeline to the effective data of the data, and obtain the first-level data processing clock ratio; Calculate the ratio of the time required for the second-level row data processing pipeline to process the row data to the effective data of the data to obtain the second-level data processing clock ratio; If the first-stage data processing clock ratio is greater than 1.25, a small data acquisition module is added to the first-stage data acquisition pipeline; If the second-level data processing clock ratio is greater than 1.25, a small row data processing module is added to the second-level row data processing pipeline.
5. The low-cost configurable matrix backlight pipeline driving system according to claim 1, It is characterized in that include: The display data acquisition module, matrix backlight data generation module, matrix backlight control module, clock module and data configuration module all use only FPGA general resources.
6. The low-cost configurable matrix backlight pipeline driving system according to claim 1, It is characterized in that The display data acquisition module, the matrix backlight data generation module, the matrix backlight control module, the clock module and the data configuration module use a clock together, and the clock has the same frequency as the display data.
7. The low-cost configurable matrix backlight pipeline driving system according to claim 1, It is characterized in that The display data acquisition module is connected to the matrix backlight data generation module in a one-way communication manner; the matrix backlight data generation module is connected to the matrix backlight control module in a one-way communication manner; the clock module is connected to the display data acquisition module, the matrix backlight data generation module and the matrix backlight control module in a one-way communication manner respectively; the data configuration module is connected to the display data acquisition module, the matrix backlight data generation module and the matrix backlight control module in a one-way communication manner respectively.
8. The low-cost configurable matrix backlight pipeline driving system according to claim 2, It is characterized in that Adapting the system's hardware interfaces and related drivers based on the relevant counts includes: Get the following information: communication rate of the interface, data rate of the interface, format of displayed data; Configure the interface of the display data acquisition module according to the interface type; Configure the clock module to display the data acquisition module clock according to the communication rate of the interface; The matrix backlight data generation module clock in the clock module is configured according to the rate of the interface data.
9. The low-cost configurable matrix backlight pipeline driving system according to claim 2, It is characterized in that The configuration of relevant parameters in the matrix backlight data generation also includes: the communication frequency of the interface, the initialization command, and the specific mapping rules of each partition; wherein the partition mapping rules are stored in a dedicated ROM area in the system.
10. Low-cost configurable matrix backlight pipeline drive storage media, It is characterized in that A computer program is stored thereon, and when the computer program is executed by a processor, the low-cost configurable matrix backlight pipeline driving system described in any one of claims 1 to 9 is implemented.