Write noise margin measurement method and device, storage medium and equipment

Abstract

The invention discloses a write noise margin measurement method and device, a storage medium and equipment. The method comprises the following steps: acquiring a butterfly writing curve reflecting the characteristics of an inverter in a to-be-tested SRAM memory cell, wherein the butterfly writing curve comprises a first curve and a second curve; traversing the first curve and the second curve to obtain a side length set of all inscribed squares taking each point on the first curve and the second curve as a diagonal vertex; and taking the maximum side length in the side length set of all the inscribed squares as the write noise margin. By adopting the scheme of the invention, not only can the measurement efficiency be improved, but also the accuracy of the write noise margin can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of static random access memory, and in particular to a method, device, storage medium and equipment for measuring write noise margin. Background Art

[0002] Static Random-Access Memory (SRAM) is a commonly used storage device in computer systems. As long as the power is on, the data in it can be retained.

[0003] The static noise margin (SNM) is the maximum DC noise signal that the SRAM memory cell can withstand. If the noise fluctuation of the SRAM memory cell in the working state exceeds this value, the state of the storage node will be incorrectly flipped. Therefore, SNM is an important parameter to measure the anti-interference ability of the SRAM memory cell. The larger the static noise margin, the more stable the SRAM.

[0004] In practical applications, according to the state of the SRAM storage unit, the SNM static noise margin can be divided into hold noise margin, read noise margin, and write noise margin. Among them, the hold noise margin refers to the noise margin of the SRAM storage unit in the hold state. The read noise margin refers to the noise margin of the SRAM storage unit in the read state. The write noise margin refers to the noise margin of the SRAM storage unit in the write state.

[0005] However, the existing write noise margin measurement method has a large write noise margin error, which affects the evaluation of the anti-interference capability of the SRAM storage unit. Summary of the invention

[0006] The problem to be solved by the present invention is to improve the measurement efficiency and the accuracy of writing noise margin.

[0007] To solve the above problem, an embodiment of the present invention provides a method for measuring write noise margin, the method comprising:

[0008] Acquire a write butterfly curve reflecting the characteristics of an inverter in a SRAM storage unit to be tested, wherein the write butterfly curve includes a first curve and a second curve;

[0009] Traversing the first curve and the second curve, obtaining a set of side lengths of all inscribed squares with a point on the first curve and a point on the second curve as diagonal vertices;

[0010] The maximum side length in the set of side lengths of all the inscribed squares is used as the write noise tolerance.

[0011] In a possible embodiment, traversing the first curve and the second curve to obtain a set of side lengths of all inscribed squares with a point on each of the first curve and the second curve as a diagonal vertex includes:

[0012] Traversing the first curve and the second curve to obtain a set of squares with a point on the first curve and a point on the second curve as diagonal vertices;

[0013] Determine whether each square is an inscribed square;

[0014] Calculate the side lengths of all inscribed squares to form a set of side lengths of all inscribed squares.

[0015] In a possible embodiment, traversing the first curve and the second curve to obtain a set of squares with a point on each of the first curve and the second curve as diagonal vertices includes:

[0016] The coordinates of the remaining two points of the squares with one point on the first curve and one point on the second curve as diagonal vertices are calculated to obtain a set of all squares.

[0017] In a possible embodiment, the determining whether each square is an inscribed square includes:

[0018] Determine whether the square is completely located in the butterfly area of ​​the butterfly curve;

[0019] When the square is completely located in the butterfly region of the butterfly curve, the square is determined to be an inscribed square, otherwise it is not an inscribed square.

[0020] In a possible embodiment, the square with a point on each of the first curve and the second curve as diagonal vertices is obtained by randomly selecting points on the first curve and the second curve.

[0021] In a possible embodiment, the first curve is: a curve showing that, in a write state, the voltage at the output terminal of the second inverter in the SRAM storage unit to be tested changes with the voltage at the output terminal of the first inverter; the second curve is: a curve showing that, in a write state, the voltage at the output terminal of the first inverter in the SRAM storage unit to be tested changes with the voltage at the output terminal of the second inverter.

[0022] In a possible embodiment, the first curve is obtained by the following method: connecting the word line in the SRAM storage unit to be tested to the power supply voltage, initializing the output end of the first inverter to the power supply voltage, initializing the output end of the second inverter to 0, connecting the first bit line to the power supply voltage, and controlling the second bit line to scan from the power supply voltage to 0.

[0023] In a possible embodiment, the second curve is obtained by the following method: connecting the word line in the SRAM storage unit to be tested to the power supply voltage, initializing the output end of the first inverter to the power supply voltage, initializing the output end of the second inverter to 0, connecting the second bit line to the power supply voltage, and controlling the first bit line to be scanned from the power supply voltage to 0.

[0024] The embodiment of the present invention further provides a device for measuring write noise margin, the device comprising:

[0025] An acquisition unit, adapted to acquire a write butterfly curve reflecting the characteristics of an inverter in a SRAM storage unit to be tested, wherein the write butterfly curve includes a first curve and a second curve;

[0026] A traversal unit, adapted to traverse the first curve and the second curve to obtain a set of side lengths of all inscribed squares with a point on each of the first curve and the second curve as diagonal vertices;

[0027] The calculation unit is adapted to use the maximum side length in the set of side lengths of all the inscribed squares as the write noise tolerance.

[0028] In a possible embodiment, the traversal unit includes:

[0029] A traversal subunit, adapted to traverse the first curve and the second curve to obtain a set of squares with a point on the first curve and a point on the second curve as diagonal vertices;

[0030] A judging subunit, adapted to judge whether each square is an inscribed square;

[0031] The calculation subunit is adapted to calculate the side length of the inscribed square to form a side length set of the inscribed square.

[0032] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. The computer program is executed by a processor to implement the steps of any of the above methods.

[0033] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and the processor executes the steps of any of the above methods when running the computer program.

[0034] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0035] By applying the scheme of the present invention, after obtaining the write butterfly curve reflecting the characteristics of the inverter in the SRAM storage unit to be tested, the side length set of the inscribed square with each point on the first curve and the second curve as the diagonal vertex is obtained directly by traversing the first curve and the second curve, and finally the maximum side length in the side length set of the inscribed square is used as the write noise tolerance. Compared with the existing scheme, there is no need to convert the coordinate system of the butterfly curve, and there is no need to calculate the difference between the first curve and the second curve, so the measurement method is simplified, thereby improving the measurement efficiency. In addition, by using each point on the first curve and the second curve as the diagonal vertex to obtain the inscribed square of the write butterfly curve, all the inscribed squares of the write butterfly curve can be found more quickly, thereby further improving the measurement efficiency. In addition, in the scheme of the present invention, since there is no need to determine the inscribed square by calculating the difference between the first curve and the second curve, the symmetry of the first curve and the second curve has little effect on the calculation result, so that even when the symmetry of the first curve and the second curve is not high, the maximum side length of the inscribed square can still accurately reflect the write noise tolerance, so the accuracy of the write noise tolerance is higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a schematic diagram of the circuit structure of an SRAM storage unit;

[0037] Figure 2 It is a schematic diagram of the principle of calculating static noise tolerance based on the butterfly curve;

[0038] Figure 3 is a flow chart of a method for measuring write static noise margin in an embodiment of the present invention;

[0039] Figure 4 : is a schematic diagram of the principle of calculating the write static noise margin based on the butterfly curve in an embodiment of the present invention;;

[0040] Figure 5 is another flow chart of a method for measuring static noise margin in an embodiment of the present invention;

[0041] Figure 6 The figure is a schematic diagram of the structure of a device for measuring static noise margin in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] Figure 1 Schematic diagram of the circuit structure of a SRAM storage unit. Figure 1The SRAM storage unit includes 4 NMOS transistors and 2 PMOS transistors. The 4 NMOS transistors are respectively a first NMOS transistor T1, a second NMOS transistor T2, a third NMOS transistor T3 and a fourth NMOS transistor T4. The 2 PMOS transistors are respectively a first PMOS transistor T5 and a second PMOS transistor T6.

[0043] The first NMOS transistor T1 and the first PMOS transistor T5 form a first inverter; the second NMOS transistor N2 and the second PMOS transistor T6 form a second inverter, and the first inverter and the second inverter are cross-coupled to form a bistable trigger. The third NMOS transistor T3 and the fourth NMOS transistor T4 are both controlled by the word line WL as access transistors.

[0044] The output terminal Q1 of the first inverter is connected to the first bit line BL through the third NMOS transistor T3 , and the output terminal Q1 ′ of the second inverter is connected to the second bit line BL′ through the fourth NMOS transistor T4 .

[0045] When the control signal of the word line WL is at a high level, the third NMOS transistor T3 and the fourth NMOS transistor T4 are turned on, and the bistable trigger composed of the first NMOS transistor T1, the second NMOS transistor T2, the first PMOS transistor T5 and the second PMOS transistor T6 can read or write data.

[0046] Specifically, when a write operation is performed on the SRAM storage cell, since the control signal of the word line WL is at a high level, the third NMOS transistor T3 and the fourth NMOS transistor T4 are turned on, and the signals on the first bit line BL and the second bit line BL' are respectively sent to the output terminal Q1 of the first inverter and the output terminal Q1' of the second inverter. When a read operation is performed on the SRAM storage cell, the first bit line BL and the second bit line BL' are precharged first, and the information stored in the storage cell is read out through the first bit line BL and the second bit line BL' and the external sensitive differential amplifier.

[0047] When measuring the static noise margin, a butterfly curve reflecting the characteristics of two inverters in an SRAM storage unit is usually first tested and obtained, and the side length of the largest inscribed square of the butterfly curve is used as the static noise margin.

[0048] Figure 2 This is a schematic diagram of the principle of calculating static noise tolerance based on the butterfly curve. Figure 1 and Figure 2, a butterfly curve reflecting the characteristics of two inverters in an SRAM storage unit, including a first curve F1 in which the voltage of the second inverter output terminal Q1' changes with the voltage of the first inverter output terminal Q1 under the same state, and a second curve F2 in which the voltage of the first inverter output terminal Q1 changes with the voltage of the second inverter output terminal Q1'. The first curve F1 and the second curve F2 are located in an xy coordinate system and are symmetrical about y=x. The first curve F1 and the second curve F2 form a butterfly curve, also called a butterfly curve.

[0049] When calculating the static noise margin, the xy coordinate axis where the butterfly curve is located is first rotated 45° counterclockwise to obtain a new uv coordinate system, and the v values ​​corresponding to the same u value of the first curve F1 and the second curve F2 are subtracted in the uv coordinate system to obtain the third curve F3. The maximum value of the third curve F3 is the diagonal length of the inscribed square.

[0050] However, the above method is not only cumbersome, but also applicable to the butterfly curve in the holding state with a high degree of symmetry, that is, the first curve F1 and the second curve F2 have a high degree of symmetry. At this time, the x value variation range of the first curve F1 and the second curve F2 is the same. After conversion to the uv coordinate system, the maximum value of the third curve F3 is closer to the actual static noise tolerance. The butterfly curve in the write state is an asymmetric irregular curve. The x value variation range of the first curve F1 and the second curve F2 in the write state is quite different, and the write noise tolerance error obtained based on the third curve F3 is relatively large.

[0051] To solve this problem, the present invention provides a method for measuring write noise tolerance. According to the method, by obtaining the side length set of all inscribed squares with a point on each of the first curve and the second curve as the diagonal vertex in the butterfly curve, and selecting the maximum side length in the side length set of the inscribed squares as the write noise tolerance, not only the measurement efficiency can be improved, but also the measurement result of the write noise tolerance can be made more accurate.

[0052] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0053] Reference Figure 3 , an embodiment of the present invention provides a method for measuring write noise margin, the method may include the following steps:

[0054] Step 31, obtaining a write butterfly curve reflecting the characteristics of an inverter in a SRAM storage unit to be tested, wherein the write butterfly curve includes a first curve and a second curve.

[0055] In a specific implementation, the write butterfly curve is a butterfly curve obtained when the SRAM storage unit to be tested is in a write state. The write butterfly curve includes a first curve and a second curve.

[0056] Specifically, the first curve may be a curve showing that the voltage at the output terminal of the second inverter in the SRAM storage unit to be tested changes with the voltage at the output terminal of the first inverter in the write state. The second curve may be a curve showing that the voltage at the output terminal of the first inverter in the SRAM storage unit to be tested changes with the voltage at the output terminal of the second inverter in the write state.

[0057] by Figure 1 Taking the circuit structure of the SRAM storage unit in the example, when testing the first curve in the write butterfly curve, the word line WL in the SRAM storage unit to be tested can be connected to the power supply voltage VDD, the first inverter output terminal Q1 can be initialized to the power supply voltage VDD, the second inverter output terminal Q1' can be initialized to 0, the first bit line BL can be connected to the power supply voltage, and the second bit line BL' can be controlled to scan from the power supply voltage to 0. At this time, the voltage changes of the first inverter output terminal Q1 and the second inverter output terminal Q1' can be recorded, and the Figure 4 The first curve M1.

[0058] When testing the second curve in the write butterfly curve, the word line WL in the SRAM storage unit to be tested can be connected to the power supply voltage VDD, the first inverter output terminal Q1 can be initialized to the power supply voltage VDD, the second inverter output terminal Q1' can be initialized to the power supply voltage 0, the second bit line BL' can be connected to the power supply voltage VDD, and the first bit line BL can be controlled to scan from the power supply voltage VDD to 0, and the voltage changes of the first inverter output terminal Q1 and the second inverter output terminal Q1' can be recorded, so as to obtain Figure 4 The second curve M2.

[0059] The first curve M1 , the second curve M2 and the y-axis form a closed butterfly-shaped area.

[0060] In a specific implementation, simulation software may be used to obtain a write butterfly curve of the SRAM storage unit to be tested.

[0061] Step 32, traverse the first curve and the second curve to obtain a set of side lengths of all inscribed squares with a point on the first curve and a point on the second curve as diagonal vertices.

[0062] In specific implementation, various methods can be used, and the side length set of all inscribed squares is not limited here. For example, a point can be randomly selected on the first curve M1 and the second curve M2 as two adjacent vertices of the square, and the distance between the two adjacent vertices is the side length of the square. The other vertices of the square are determined by the side length, and finally the square is obtained. Finally, it is determined whether the square is an inscribed square. If it is an inscribed square, the side length of the square is used as an element in the side length set of all inscribed squares.

[0063] In an embodiment of the present invention, in order to quickly find all inscribed squares in a butterfly curve, a point on each of the first curve and the second curve is used as the diagonal vertex of the square, rather than as the adjacent vertex of the square. The squares with diagonal vertices on the first curve and the second curve are more likely to be inscribed squares, so that all inscribed squares can be found quickly, thereby improving measurement efficiency.

[0064] Specifically, the first curve and the second curve may be traversed to obtain a set of squares with a point on each of the first curve and the second curve as diagonal vertices, and then it may be determined whether each square is an inscribed square, and if so, the side length of the inscribed square is calculated. Thus, the side lengths of all inscribed squares form a set of side lengths of all inscribed squares.

[0065] In one embodiment, traversing the first curve and the second curve to obtain a set of squares with one point on the first curve and one point on the second curve as diagonal vertices may include: calculating the coordinates of the remaining two points of the squares with one point on the first curve and one point on the second curve as diagonal vertices to obtain a set of all squares.

[0066] In one embodiment, determining whether each square is an inscribed square may include: determining whether the square is completely located in the butterfly region of the butterfly curve. When the square is completely located in the butterfly region of the butterfly curve, the square is determined to be an inscribed square, otherwise it is not an inscribed square.

[0067] Step 33: taking the maximum side length in the side length set of the inscribed square as the write noise tolerance.

[0068] That is, the maximum value is selected from the set of side lengths of the inscribed square as the write noise tolerance.

[0069] It should be noted that the SRAM storage unit to be tested in the embodiment of the present invention includes but is not limited to Figure 1 The 6T circuit structure shown in the figure can also be an 8T, 12T or other circuit structure.

[0070] It should be noted that, in practical applications, the method may further include: outputting the write noise margin. For example, the write noise margin may be outputted by an electronic device.

[0071] Figure 5 A method for obtaining the set of side lengths of all inscribed squares in one embodiment of the present invention. Figure 5 , the method may include:

[0072] Step 51, obtaining a write butterfly curve reflecting the characteristics of the inverter in the SRAM storage unit to be tested.

[0073] The write butterfly curve includes a first curve and a second curve.

[0074] Regarding step 51, please refer to the above description about step 31 for details, which will not be repeated here.

[0075] Step 52, randomly select a point on the first curve and the second curve respectively, calculate the coordinates of the other two points of the square with the two points as diagonal vertices, and obtain the corresponding square.

[0076] For example, refer to Figure 4 , a point A can be randomly selected on the second curve M2, and its coordinates are (a, b), and a point B can be randomly selected on the first curve M1, and its coordinates are (c, d). Based on the distance between point A and point B, the side length of the corresponding square 41 can be obtained, and thus the coordinates of the other two points C and D of the square 41 can be obtained. Among them, the coordinates of point C are (x2, y2), and the coordinates of point D are (x1, y1).

[0077] For example, refer to Figure 4 , a point T can be randomly selected on the second curve M2, and a point R can be randomly selected on the first curve M1. Based on the distance between point T and point R, the side length of the corresponding square 42 can be obtained, thereby obtaining the coordinates of the other two points P and point Q of the square 42.

[0078] Step 53, determining whether the square is completely located in the butterfly region of the butterfly curve.

[0079] In a specific implementation, it is determined whether the square is completely located in the butterfly region of the butterfly curve, that is, whether the square is an inscribed square. A square completely located in the butterfly region of the butterfly curve is an inscribed square, otherwise it is not an inscribed square. For example, referring to Figure 4 , square 41 is partially located in the butterfly curve butterfly region, and the other part is located outside the butterfly curve butterfly region, then square 41 is not an inscribed square. Square 42 is completely located in the butterfly curve butterfly region, then square 42 is an inscribed square.

[0080] When the square is completely within the butterfly region of the butterfly curve, step 54 is executed; otherwise, step 55 is executed.

[0081] Step 54, calculate the side lengths of all inscribed squares.

[0082] In a specific implementation, the side length of the square can be calculated in the process of determining the coordinates of the other two points of the square, and when the square is determined to be an inscribed square, the side length of the inscribed square is recorded.

[0083] In a specific implementation, for any two points on the first curve and the second curve, there exists a square with the two points as diagonal vertices.

[0084] Step 55, determining whether to traverse the first curve and the second curve.

[0085] When the first curve and the second curve are traversed, step 56 is executed, otherwise step 52 is executed until the first curve and the second curve are traversed.

[0086] Step 56: taking the maximum side length in the set of side lengths of all inscribed squares as the write noise tolerance.

[0087] By adopting the solution of the present invention, all inscribed squares can be quickly obtained, thereby quickly determining the write noise margin, and improving the measurement efficiency of the write noise margin. In addition, due to the solution of the present invention, the write noise margin can also be accurately obtained.

[0088] In order to enable those skilled in the art to better understand and implement the present invention, the user terminal and computer-readable storage medium corresponding to the above method are described in detail below.

[0089] Reference Figure 6 The embodiment of the present invention provides a write noise margin measuring device 60, and the measuring device 60 may include: an acquisition unit 61, a traversal unit 62, and a calculation unit 63. Among them:

[0090] The acquisition unit 61 is adapted to acquire a write butterfly curve reflecting the characteristics of the inverter in the SRAM storage unit to be tested, wherein the write butterfly curve includes a first curve and a second curve;

[0091] The traversal unit 62 is adapted to traverse the first curve and the second curve to obtain a set of side lengths of all inscribed squares with a point on each of the first curve and the second curve as diagonal vertices;

[0092] The calculation unit 63 is adapted to use the maximum side length in the set of side lengths of all the inscribed squares as the write noise tolerance.

[0093] In one embodiment, referring to Figure 6 , the traversal unit 62 may include: a traversal subunit 621, a judgment subunit 622 and a calculation subunit 623. Wherein:

[0094] The traversal subunit 621 is adapted to traverse the first curve and the second curve to obtain a set of squares with a point on each of the first curve and the second curve as diagonal vertices;

[0095] The judging subunit 622 is adapted to judge whether each square is an inscribed square;

[0096] The calculation subunit 623 is adapted to calculate the side lengths of the inscribed square to form a side length set of the inscribed square.

[0097] Regarding the above-mentioned various functional units, they can be implemented by referring to the above-mentioned descriptions of the corresponding method steps, which will not be repeated here.

[0098] An embodiment of the present invention further provides another computer-readable storage medium on which computer instructions are stored. The computer instructions are executed by a processor to implement the steps of any one of the methods for measuring write noise margin in the above embodiments, which will not be described in detail.

[0099] In a specific implementation, the computer-readable storage medium may include: ROM, RAM, magnetic disk or optical disk, etc.

[0100] An embodiment of the present invention also provides an electronic device, wherein the terminal may include a memory and a processor, wherein the memory stores computer instructions that can be run on the processor, and when the processor runs the computer instructions, the steps of the write noise tolerance measurement method described in any one of the above embodiments are executed, which will not be repeated here.

[0101] Regarding the various modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, or hardware modules / units, or they can be partially software modules / units and partially hardware modules / units. For example, for various devices and products applied to or integrated in a chip, the various modules / units included therein can all be implemented in the form of hardware such as circuits, or at least some of the modules / units can be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in a chip module, the various modules / units included therein can all be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units can be implemented in the form of hardware such as circuits. The element can be implemented in the form of a software program, which runs on a processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal, the various modules / units contained therein can be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or in different components in the terminal, or, at least some modules / units can be implemented in the form of a software program, which runs on a processor integrated inside the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.

[0102] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for measuring write noise margin, characterized in that: include: Acquire a write butterfly curve reflecting the characteristics of an inverter in a SRAM storage unit to be tested, wherein the write butterfly curve includes a first curve and a second curve; Traversing the first curve and the second curve, obtaining a set of side lengths of all inscribed squares with a point on the first curve and a point on the second curve as diagonal vertices; The maximum side length in the set of side lengths of all the inscribed squares is used as the write noise tolerance.

2. The method for measuring write noise margin according to claim 1, characterized in that: The traversing of the first curve and the second curve to obtain a set of side lengths of all inscribed squares with each point on the first curve and the second curve as diagonal vertices includes: Traversing the first curve and the second curve to obtain a set of squares with a point on the first curve and a point on the second curve as diagonal vertices; Determine whether each square is an inscribed square; Calculate the side lengths of all inscribed squares to form a set of side lengths of all inscribed squares.

3. The method for measuring write noise margin according to claim 2, characterized in that: The traversing the first curve and the second curve to obtain a set of squares with each point on the first curve and the second curve as diagonal vertices includes: The coordinates of the remaining two points of the squares with one point on the first curve and one point on the second curve as diagonal vertices are calculated to obtain a set of all squares.

4. The method for measuring write noise margin according to claim 2, characterized in that: The step of judging whether each square is an inscribed square comprises: Determine whether the square is completely located in the butterfly area of ​​the butterfly curve; When the square is completely located in the butterfly region of the butterfly curve, the square is determined to be an inscribed square, otherwise it is not an inscribed square.

5. The method for measuring write noise margin according to claim 1, characterized in that: The square with a point on each of the first curve and the second curve as diagonal vertices is obtained by randomly selecting points on the first curve and the second curve.

6. The method for measuring write noise margin according to claim 1, characterized in that: The first curve is a curve showing that, in the write state, the voltage at the output terminal of the second inverter in the SRAM storage unit to be tested changes with the voltage at the output terminal of the first inverter; the second curve is a curve showing that, in the write state, the voltage at the output terminal of the first inverter in the SRAM storage unit to be tested changes with the voltage at the output terminal of the second inverter.

7. The method for measuring write noise margin according to claim 6, characterized in that: The first curve is obtained by the following method: connecting the word line in the SRAM storage unit to be tested to the power supply voltage, initializing the output end of the first inverter to the power supply voltage, initializing the output end of the second inverter to 0, connecting the first bit line to the power supply voltage, and controlling the second bit line to scan from the power supply voltage to 0.

8. The method for measuring write noise margin according to claim 6, characterized in that: The second curve is obtained by the following method: connecting the word line in the SRAM storage unit to be tested to the power supply voltage, initializing the output end of the first inverter to the power supply voltage, initializing the output end of the second inverter to 0, connecting the second bit line to the power supply voltage, and controlling the first bit line to scan from the power supply voltage to 0.

9. A device for measuring write noise margin, characterized in that: include: An acquisition unit, adapted to acquire a write butterfly curve reflecting the characteristics of an inverter in a SRAM storage unit to be tested, wherein the write butterfly curve includes a first curve and a second curve; A traversal unit, adapted to traverse the first curve and the second curve to obtain a set of side lengths of all inscribed squares with a point on each of the first curve and the second curve as diagonal vertices; The calculation unit is adapted to use the maximum side length in the set of side lengths of all the inscribed squares as the write noise tolerance.

10. The write noise margin measuring device according to claim 9, characterized in that: The traversal unit comprises: A traversal subunit, adapted to traverse the first curve and the second curve to obtain a set of squares with a point on the first curve and a point on the second curve as diagonal vertices; A judging subunit, adapted to judge whether each square is an inscribed square; The calculation subunit is adapted to calculate the side length of the inscribed square to form a side length set of the inscribed square.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: The computer program is executed by a processor to implement the steps of the method according to any one of claims 1 to 8.

12. An electronic device comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, wherein: When the processor runs the computer program, the steps of the method according to any one of claims 1 to 8 are performed.

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