SOI substrate-based LDMOS device and preparation method thereof
By introducing local buried doping regions with linearly increasing doping concentration in the LDMOS device, the electric field strength at the junction of the top silicon and the intermediate isolation layer is improved, the problem of insufficient longitudinal voltage withstand voltage of the device is solved, and the overall resistance of the device is significantly improved Pressure performance.
Patent Information
- Application Number
- CN202411151183.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-21
- Publication Date
- 2024-12-13
AI Technical Summary
The overall longitudinal withstand voltage of the LDMOS device based on SOI substrate is insufficient, mainly due to the insufficient electric field strength at the junction of the top silicon and the buried oxygen layer, which leads to the device being prone to breakdown.
Introduce local buried doping regions in LDMOS devices, define openings on the initial top layer of silicon through photolithography and perform ion implantation to form doping regions with linearly increasing doping concentration, and increase doping ions in local buried doping regions Concentration, thereby increasing the electric field intensity at the junction position of the initial top layer silicon and the intermediate spacer.
By increasing the electric field strength, the longitudinal voltage withstandability of the device is enhanced, the service life of the device is extended and the overall pressure bearing capacity is improved.
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Figure CN119132959A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to an LDMOS device based on an SOI substrate and a preparation method thereof. Background Art
[0002] The pressure-bearing mode of LDMOS devices based on SOI substrate (Si-O-Si, bottom silicon-buried oxide layer-top silicon) (hereinafter referred to as SOI-LDMOS devices) is different from that of LDMOS devices based on silicon substrate. The pressure-bearing mode of LDMOS devices based on SOI substrate consists of two parts:
[0003] (1) Lateral: The PN junction depletion region formed by N-drift (N-type drift region) and P-body (P-type body region) is under pressure;
[0004] (2) Vertically: Pressure is borne by the N-drift (N-type drift region) and the buried oxide layer in the SOI substrate;
[0005] Among them, the electric field strength in the middle oxide layer is three times the electric field strength of the initial top silicon at the interface with the buried oxide layer. For traditional LDMOS devices based on SOI substrates, the vertical breakdown of the device generally occurs on the initial top silicon side at the interface between the top silicon and the buried oxide layer below the drain, that is, when breakdown occurs, the electric field strength at this point reaches the critical field strength of the device. At present, the overall vertical withstand voltage of LDMOS devices based on SOI substrates is not enough. If the electric field strength on the top silicon side at the interface between the top silicon and the buried oxide layer can be improved, the overall vertical withstand voltage of the device can be increased. Summary of the invention
[0006] The present application provides an LDMOS device based on an SOI substrate and a preparation method thereof, which can solve the problem of insufficient overall longitudinal withstand voltage of existing SOI-LDMOS devices.
[0007] On the one hand, an embodiment of the present application provides an LDMOS device based on an SOI substrate, including:
[0008] A bottom silicon layer, a middle isolation layer, and an initial top silicon layer stacked in sequence;
[0009] a local buried doped region of a first conductivity type, the local buried doped region being located in the initial top silicon layer;
[0010] an epitaxial layer, the epitaxial layer covering the initial top silicon layer and the local buried doped region;
[0011] A body region of the second conductivity type and a drift region of the first conductivity type are maintained at a certain interval, the body region is located in the epitaxial layer, and the drift region is located in the epitaxial layer and the initial top silicon layer, wherein the local buried doped region is located at the bottom of the drift region close to the body region side, and the doping concentration of doped ions in the local buried doped region increases linearly from close to the body region to away from the body region;
[0012] A drain region, a base lead region and a source region maintained at a certain interval, wherein the drain region is located in the drift region, and the base lead region and the source region are respectively located in the body region;
[0013] a stepped oxide layer, wherein the stepped oxide layer covers a portion of a surface of the drift region; and
[0014] A stepped polysilicon layer covers a portion of the surface of the body region, a portion of the surface of the drift region, and a portion of the surface of the stepped oxide layer.
[0015] Optionally, in the LDMOS device based on the SOI substrate, the step of forming the local buried doped region includes:
[0016] Coating a photoresist layer on the initial top silicon surface;
[0017] A plurality of opening patterns are defined on the photoresist layer by using a special mask and a photolithography process, wherein the lateral dimensions of the openings in the photoresist layer increase gradually from the direction close to the body region to the direction away from the body region;
[0018] Using the patterned photoresist layer as a mask, ion implantation is performed on the initial top silicon layer to obtain the local buried doping region with linearly increasing doping concentration;
[0019] The patterned photoresist layer is removed.
[0020] Optionally, in the LDMOS device based on the SOI substrate, the lateral dimensions of the openings in the photoresist layer increase one by one from close to the body region to away from the body region according to the rule of an arithmetic progression.
[0021] Optionally, in the LDMOS device based on the SOI substrate, the spacings between any two adjacent openings in the photoresist layer are equal.
[0022] Optionally, in the LDMOS device based on the SOI substrate, the ion doping concentration in the local buried doping region is greater than the ion doping concentration in the drift region; the ion doping concentration in the local buried doping region is greater than the ion doping concentration in the epitaxial layer; the ion doping concentration in the local buried doping region is greater than the ion doping concentration in the body region.
[0023] Optionally, in the LDMOS device based on the SOI substrate, a lateral dimension of the local buried doped region does not exceed one half of a lateral dimension of the drift region.
[0024] Optionally, in the LDMOS device based on the SOI substrate, the conductivity type of the doped ions in the epitaxial layer is the same as the conductivity type of the doped ions in the body region.
[0025] On the other hand, an embodiment of the present application further provides a method for preparing an LDMOS device based on an SOI substrate, comprising:
[0026] providing a bottom silicon layer, a middle isolation layer, and an initial top silicon layer stacked in sequence;
[0027] forming a local buried doped region of the first conductivity type in the initial top silicon layer by an ion implantation process;
[0028] forming an epitaxial layer, the epitaxial layer covering the initial top silicon layer and the local buried doped region;
[0029] Through multiple ion implantations, a body region of the second conductivity type and a drift region of the first conductivity type are respectively formed with a certain interval, the body region is located in the epitaxial layer, and the drift region is located in the epitaxial layer and the initial top silicon layer, wherein the local buried doped region is located at the bottom of the drift region close to the body region side, and the doping concentration of the doped ions in the local buried doped region increases linearly from the body region to the direction away from the body region;
[0030] By multiple ion implantations, a base lead-out region and a source region are formed in the body region at a certain interval, and a drain region is formed in the drift region;
[0031] forming a stepped oxide layer, wherein the stepped oxide layer covers a portion of the surface of the drift region; and
[0032] A stepped polysilicon layer is formed, wherein the polysilicon layer covers a portion of the surface of the body region, a portion of the surface of the drift region, and a portion of the surface of the stepped oxide layer.
[0033] Optionally, in the method for preparing the LDMOS device based on the SOI substrate, the step of forming a local buried doped region of the first conductivity type in the initial top silicon by an ion implantation process includes:
[0034] Coating a photoresist layer on the initial top silicon surface;
[0035] A plurality of opening patterns are defined on the photoresist layer by using a special mask and a photolithography process, wherein the lateral dimensions of the openings in the photoresist layer increase gradually from the direction close to the body region to the direction away from the body region;
[0036] Using the patterned photoresist layer as a mask, ion implantation is performed on the initial top silicon layer to obtain the local buried doping region with linearly increasing doping concentration;
[0037] The patterned photoresist layer is removed.
[0038] Optionally, in the method for preparing the LDMOS device based on the SOI substrate, the lateral dimensions of the openings in the photoresist layer increase one by one from close to the body region to away from the body region according to the rule of an arithmetic progression.
[0039] The technical solution of this application has at least the following advantages:
[0040] The present application provides an LDMOS device based on an SOI substrate and a preparation method thereof, wherein in the LDMOS device structure, a local buried doped region of a first conductivity type is located in the top silicon, a drift region of the first conductivity type is located in the epitaxial layer and the initial top silicon, the local buried doped region is located at the bottom of the drift region near the body region side of the second conductivity type, and the doping concentration of the doped ions in the local buried doped region increases linearly from the body region to the direction away from the body region (from left to right). The present application sets the local buried doped region whose doping concentration increases linearly from left to right at the bottom left side of the drift region (lower left corner), so as to increase the electric field strength at the junction of the initial top silicon and the middle isolation layer, and then to increase the electric field strength in the middle isolation layer, thereby achieving the effect of improving the longitudinal withstand voltage of the device as a whole. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0042] Figure 1-Figure 8 It is a schematic diagram of a semiconductor structure in each process step of preparing an LDMOS device based on an SOI substrate according to an embodiment of the present invention;
[0043] FIG9( a ) is a schematic diagram of the longitudinal electric field distribution of a conventional LDMOS device based on an SOI substrate;
[0044] FIG9( b ) is a schematic diagram of the longitudinal electric field distribution of an LDMOS device based on an SOI substrate according to an embodiment of the present invention;
[0045] The reference numerals are described as follows:
[0046] 11-bottom silicon, 12-middle oxide layer, 13-initial top silicon, 14-photoresist layer, 15-opening one, 16-opening two, 17-opening three, 18-opening four, 20-local buried doping region, 30-epitaxial layer, 31-body region, 32-drift region, 33-base lead-out region, 34-shallow trench isolation structure, 35-source region, 36-drain region, 40-stepped oxide layer, 50-stepped polysilicon layer. DETAILED DESCRIPTION
[0047] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0048] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0049] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0050] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0051] The present application embodiment provides a method for preparing an LDMOS device based on an SOI substrate, referring to Figure 1-Figure 8 , Figure 1-Figure 8 1 is a schematic diagram of a semiconductor structure in each process step of preparing an LDMOS device based on an SOI substrate according to an embodiment of the present invention. The method for preparing an LDMOS device based on an SOI substrate includes:
[0052] First, refer to Figure 1 , Figure 1 It is a schematic structural diagram of an SOI substrate according to an embodiment of the present application, which provides a bottom silicon layer 11, an intermediate isolation layer 12 and an initial top silicon layer 13 stacked in sequence.
[0053] Preferably, the thickness of the initial top silicon layer 13 is The thickness of the intermediate isolation layer 12 is at least 2 μm; the thickness of the bottom silicon layer 11 is at least 760 μm.
[0054] In this embodiment, a 12-inch silicon wafer may be selected as the bottom silicon 11 .
[0055] In this embodiment, the middle isolation layer 12 is made of silicon dioxide.
[0056] Then, refer to Figure 2-Figure 5 , Figure 2 is a schematic diagram of the structure after forming a photoresist layer in an embodiment of the present application, Figure 3 is a schematic diagram of the structure after an opening is formed on the photoresist layer in an embodiment of the present application, Figure 4 is a schematic diagram of the structure of an embodiment of the present application after a local buried doping region is formed by ion implantation, Figure 5 1 is a schematic diagram of the structure after the patterned photoresist layer is removed according to an embodiment of the present application. A local buried doped region 20 of the first conductivity type is formed in the initial top silicon layer 13 through an ion implantation process.
[0057] Preferably, the step of forming the first conductivity type local buried doping region 20 in the initial top silicon layer 13 by ion implantation may specifically include:
[0058] 1)Reference Figure 2 , coating a photoresist layer 14 on the surface of the initial top silicon layer 13;
[0059] 2)Reference Figure 3 , using a special mask and a photolithography process to define a plurality of opening patterns on the photoresist layer 14, wherein, from left to right, that is, from a direction close to a subsequent body region to a direction away from the body region, the lateral dimensions of the openings in the photoresist layer 14 increase one by one;
[0060] 3)Reference Figure 4 , using the patterned photoresist layer 14 as a mask, ion implantation is performed on the initial top silicon layer 13 to obtain the local buried doping region 20 with a linearly increasing doping concentration;
[0061] 4)Reference Figure 5 , remove the patterned photoresist layer 14.
[0062] Preferably, from the direction close to the body region to the direction away from the body region, the lateral dimensions of the openings in the photoresist layer 14 increase one by one according to the rule of an arithmetic progression.
[0063] Preferably, the spacing between any two adjacent openings in the photoresist layer 14 (the lateral dimensions of the photoresist layer between any two adjacent openings) are equal.
[0064] In this embodiment, opening one 15, opening two 16, opening three 17 and opening four 18 are formed in the photoresist layer 14 by using a special mask and a photolithography process, and the lateral dimensions of opening one 15, opening two 16, opening three 17 and opening four 18 increase one by one according to the rule of arithmetic progression.
[0065] In this embodiment, the conductivity type of the doped ions in the local buried doped region 20 is N-type. In this embodiment, the local buried doped region 20 can be formed in the initial top silicon 13 by an N-type ion (eg, phosphorus ion or arsenic ion) implantation process.
[0066] In the ion implantation process for forming the local buried doping region 20, the ion implantation energy is 200Kev to 300Kev, and the ion implantation dose is 1E16atoms / cm 3 ~1E17atoms / cm 3 .
[0067] Next, refer to Figure 6 , Figure 6 It is a schematic diagram of the structure after forming an epitaxial layer according to an embodiment of the present application, wherein an epitaxial layer 30 is formed, and the epitaxial layer 30 covers the initial top silicon 13 and the local buried doped region 20 .
[0068] The epitaxial layer 30 and the initial top silicon 13 are combined to form the final top silicon of the device. In this embodiment, the thickness of the final top silicon formed by the epitaxial layer 30 and the initial top silicon 13 is about 2.5 μm.
[0069] In this embodiment, the conductivity type of the doped ions in the epitaxial layer 30 is P type.
[0070] For further reference, Figure 7 , Figure 7It is a schematic diagram of the structure after the base lead-out region, the source region and the drain region are formed in an embodiment of the present application. Through multiple ion implantations, a body region 31 of the second conductivity type and a drift region 32 of the first conductivity type maintained at a certain interval are formed respectively, the body region 31 is located in the epitaxial layer 30, and the drift region 32 is located in the epitaxial layer 30 and the initial top silicon 13, wherein the local buried doped region 20 is located at the bottom of the drift region 32 close to the body region 31 side, and the doping concentration of the doped ions in the local buried doped region 20 increases linearly from the body region 31 to the direction away from the body region 31.
[0071] Furthermore, after the body region 31 and the drift region 32 are formed respectively by the ion implantation process, the current semiconductor structure may be subjected to a thermal annealing process to diffuse the doping elements in the local buried doping region 20 , the body region 31 and the drift region 32 at high temperature.
[0072] It is worth noting that, from the direction close to the body region to the direction away from the body region (from left to right), the larger the lateral size of the opening, the more doping elements are injected by the ion implantation process, and therefore after subsequent high-temperature diffusion, the corresponding doping concentration is also higher. Therefore, from the direction close to the body region 31 to the direction away from the body region 31, the doping concentration of the doped ions in the local buried doping region 20 increases linearly.
[0073] Preferably, the conductivity type of the doped ions in the epitaxial layer 30 is the same as the conductivity type of the doped ions in the body region 31 .
[0074] In this embodiment, the conductivity type of the doped ions in the drift region 32 is N-type; the conductivity type of the doped ions in the body region 31 is P-type.
[0075] Further, the ion doping concentration in the local buried doping region 20 is greater than the ion doping concentration in the drift region 32; the ion doping concentration in the local buried doping region 20 is greater than the ion doping concentration in the epitaxial layer 30; the ion doping concentration in the local buried doping region 20 is greater than the ion doping concentration in the body region 31. That is, the lower limit of the ion doping concentration in the local buried doping region 20 is greater than the ion doping concentration in the drift region 32, the lower limit of the ion doping concentration in the local buried doping region 20 is also greater than the ion doping concentration in the epitaxial layer 30, and the lower limit of the ion doping concentration in the local buried doping region 20 is also greater than the ion doping concentration in the body region 31.
[0076] Preferably, the lateral dimension of the local buried doping region 20 does not exceed half of the lateral dimension of the drift region 32 .
[0077] In this embodiment, the lateral dimension of the local buried doping region 20 is half of the lateral dimension of the drift region 32 .
[0078] In this embodiment, reference Figure 7 After forming the epitaxial layer 30 and before forming the drift region 32 and the body region 31, the method for preparing the LDMOS device may further include: etching the epitaxial layer 30 to form a shallow trench in the epitaxial layer 30; filling an isolation material layer in the shallow trench to obtain a shallow trench isolation structure 34, wherein the shallow trench isolation structure 34 is located in the body region 31.
[0079] Next, continue to refer to Figure 7 Through multiple ion implantations, a base lead-out region 33 and a source region 35 are formed in the body region 31 at a certain interval, and a drain region 36 is formed in the drift region 32 .
[0080] In this embodiment, the shallow trench isolation structure 34 is located between the base lead-out region 33 and the source region 35 .
[0081] For further reference, Figure 8 , Figure 8 3 is a schematic diagram of the structure after forming a stepped polysilicon layer according to an embodiment of the present application, forming a stepped oxide layer 40 , and the stepped oxide layer 40 covers a portion of the surface of the drift region 32 .
[0082] Finally, continue to refer to Figure 8 , forming a stepped polysilicon layer 50 , wherein the polysilicon layer 50 covers a portion of the surface of the body region 31 , a portion of the surface of the drift region 32 , and a portion of the surface of the stepped oxide layer 40 .
[0083] Referring to Figures 9(a) and 9(b), Figure 9(a) is a schematic diagram of the longitudinal electric field distribution of a traditional LDMOS device based on an SOI substrate, and Figure 9(b) is a schematic diagram of the longitudinal electric field distribution of an LDMOS device based on an SOI substrate in an embodiment of the present application. The horizontal axes of Figures 9(a) and 9(b) are both the vertical distance from the upper surface of the epitaxial layer to the lower surface of the intermediate isolation layer, and the vertical axes of Figures 9(a) and 9(b) are both the electric field strength.
[0084] In Figure 9(a), 0-t si represents the vertical depth from the upper surface of the epitaxial layer to the lower surface of the initial top silicon layer; t si -t BOX It represents the vertical depth from the lower surface of the initial top silicon layer (that is, the upper surface of the middle isolation layer) to the lower surface of the middle isolation layer. si It represents the electric field strength at the bottom surface of the initial top silicon layer (that is, the top surface of the middle isolation layer); E BOXIndicates the electric field strength in the middle isolation layer. In traditional LDMOS devices based on SOI substrates, the closer to the lower surface of the epitaxial layer, the stronger the electric field strength. The electric field strength is linearly related to the depth of the epitaxial layer. When reaching the upper surface of the middle isolation layer, the device undergoes longitudinal breakdown, and the electric field strength at the lower surface of the initial top silicon layer (that is, the upper surface of the middle isolation layer) reaches the critical field strength of the device.
[0085] In FIG. 9( b ), the present application introduces a local buried doping region 20,0-t NBL represents the vertical depth from the upper surface of the epitaxial layer 30 to the upper surface of the local buried doped region 20; t NBL -t si represents the longitudinal depth from the upper surface of the local buried doping region 20 to the lower surface of the local buried doping region 20; t si -t BOX It represents the vertical depth from the lower surface of the local buried doping region 20 (that is, the upper surface of the intermediate isolation layer 12) to the lower surface of the intermediate isolation layer 12. EPI Represents the electric field strength at the lower surface of the epitaxial layer; E NBL represents the electric field strength at the lower surface of the local buried doping region 20 (that is, the upper surface of the intermediate isolation layer 12); E BOX Indicates the electric field strength within the intermediate isolation layer.
[0086] Among them, the doping concentration of the local buried doping area 20 increases linearly from left to right, and the corresponding electric field strength can gradually decrease from right to left, which can increase the electric field strength at the junction of the epitaxial layer and the initial top silicon and the electric field strength at the junction of the initial top silicon and the middle isolation layer, thereby improving the pressure-bearing capacity of the final top silicon (epitaxial layer + initial top silicon), and then increasing the electric field strength in the middle isolation layer, improving the pressure-bearing capacity of the middle isolation layer, and thus improving the voltage resistance performance of the device.
[0087] In the LDMOS device based on the SOI substrate provided in the present application, in the final top silicon (epitaxial layer + initial top silicon), the electric field strength undergoes a turn inside and is improved, which is mainly reflected in the upper surface position of the local buried doping region 20. The electric field strength undergoes a turn, and the electric field strength is improved compared with the electric field strength of the traditional LDMOS device based on the SOI substrate, that is, the electric field strength at the junction of the epitaxial layer and the initial top silicon and the electric field strength at the junction of the initial top silicon and the intermediate isolation layer are increased, the pressure bearing capacity of the final top silicon (epitaxial layer + initial top silicon) is improved, and then the electric field strength in the intermediate isolation layer is increased, and the pressure bearing capacity of the intermediate isolation layer is improved, thereby achieving the effect of improving the overall longitudinal withstand voltage of the device.
[0088] Based on the same inventive concept, the embodiment of the present application also provides an LDMOS device based on an SOI substrate, referring to Figure 8, the LDMOS device based on the SOI substrate comprises:
[0089] A bottom silicon layer 11, an intermediate isolation layer 12 and an initial top silicon layer 13 are stacked in sequence;
[0090] A local buried doped region 20 of a first conductivity type, wherein the local buried doped region 20 is located in the initial top silicon layer 13;
[0091] An epitaxial layer 30, the epitaxial layer 30 covers the initial top silicon layer 13 and the local buried doped region 20;
[0092] A body region 31 of the second conductivity type and a drift region 32 of the first conductivity type are maintained at a certain interval, wherein the body region 31 is located in the epitaxial layer 30, and the drift region 32 is located in the epitaxial layer 30 and the initial top silicon 13, wherein the local buried doped region 20 is located at the bottom of the drift region 32 close to the body region 31, and the doping concentration of the doped ions in the local buried doped region 20 increases linearly from the body region 31 to the direction away from the body region 31;
[0093] A drain region 36, a base lead region 33 and a source region 35 maintained at a certain interval, wherein the drain region 36 is located in the drift region 32, and the base lead region 33 and the source region 35 are respectively located in the body region 31;
[0094] a stepped oxide layer 40 , wherein the stepped oxide layer 40 covers a portion of the surface of the drift region 32 ; and
[0095] The stepped polysilicon layer 50 covers a portion of the surface of the body region 31 , a portion of the surface of the drift region 32 , and a portion of the surface of the stepped oxide layer 40 .
[0096] Preferably, the ion doping concentration in the local buried doping region 20 is greater than the ion doping concentration in the drift region 32; the ion doping concentration in the local buried doping region 20 is greater than the ion doping concentration in the epitaxial layer 30; and the ion doping concentration in the local buried doping region 20 is greater than the ion doping concentration in the body region 31.
[0097] Preferably, the lateral dimension of the local buried doping region 20 does not exceed half of the lateral dimension of the drift region 32 .
[0098] Furthermore, the conductivity type of the doped ions in the epitaxial layer 30 is the same as the conductivity type of the doped ions in the body region 31 .
[0099] In this embodiment, the conductivity type of the doped ions in the epitaxial layer 30 is P type; the conductivity type of the doped ions in the drift region 32 is N type; the conductivity type of the doped ions in the body region 31 is P type; and the conductivity type of the doped ions in the local buried doped region 20 is N type.
[0100] In the present application, by setting a local buried doping region with a doping concentration that increases linearly from left to right at the left bottom of the drift region (lower left corner), the electric field strength at the junction of the initial top silicon and the middle isolation layer can be increased, and then the electric field strength in the middle isolation layer can be increased, thereby achieving the effect of improving the overall longitudinal withstand voltage of the device.
[0101] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. An LDMOS device based on an SOI substrate, characterized in that: include: A bottom silicon layer, a middle isolation layer, and an initial top silicon layer stacked in sequence; a local buried doped region of a first conductivity type, the local buried doped region being located in the initial top silicon layer; an epitaxial layer, the epitaxial layer covering the initial top silicon layer and the local buried doped region; A body region of the second conductivity type and a drift region of the first conductivity type are maintained at a certain interval, the body region is located in the epitaxial layer, and the drift region is located in the epitaxial layer and the initial top silicon layer, wherein the local buried doped region is located at the bottom of the drift region close to the body region side, and the doping concentration of the doped ions in the local buried doped region increases linearly from close to the body region to away from the body region; A drain region, a base lead region and a source region maintained at a certain interval, wherein the drain region is located in the drift region, and the base lead region and the source region are respectively located in the body region; a stepped oxide layer, wherein the stepped oxide layer covers a portion of a surface of the drift region; and A stepped polysilicon layer covers a portion of the surface of the body region, a portion of the surface of the drift region, and a portion of the surface of the stepped oxide layer.
2. The LDMOS device based on SOI substrate according to claim 1, characterized in that: The step of forming the local buried doped region comprises: Coating a photoresist layer on the initial top silicon surface; A plurality of opening patterns are defined on the photoresist layer by using a special mask and a photolithography process, wherein the lateral dimensions of the openings in the photoresist layer increase gradually from the direction close to the body region to the direction away from the body region; Using the patterned photoresist layer as a mask, ion implantation is performed on the initial top silicon layer to obtain the local buried doping region with linearly increasing doping concentration; The patterned photoresist layer is removed.
3. The LDMOS device based on SOI substrate according to claim 2, characterized in that: From the direction close to the body region to the direction away from the body region, the lateral dimensions of the openings in the photoresist layer increase one by one according to the rule of an arithmetic progression.
4. The LDMOS device based on SOI substrate according to claim 2, characterized in that: The spacings between any two adjacent openings in the photoresist layer are equal.
5. The LDMOS device based on SOI substrate according to claim 1, characterized in that: The ion doping concentration in the local buried doping region is greater than the ion doping concentration in the drift region; the ion doping concentration in the local buried doping region is greater than the ion doping concentration in the epitaxial layer; the ion doping concentration in the local buried doping region is greater than the ion doping concentration in the body region.
6. The LDMOS device based on SOI substrate according to claim 1, characterized in that: The lateral dimension of the local buried doping region does not exceed one half of the lateral dimension of the drift region.
7. The LDMOS device based on SOI substrate according to claim 1, characterized in that: The conductivity type of the doped ions in the epitaxial layer is the same as the conductivity type of the doped ions in the body region.
8. A method for preparing an LDMOS device based on an SOI substrate, characterized in that: include: providing a bottom silicon layer, a middle isolation layer, and an initial top silicon layer stacked in sequence; forming a local buried doped region of the first conductivity type in the initial top silicon layer by an ion implantation process; forming an epitaxial layer, the epitaxial layer covering the initial top silicon layer and the local buried doped region; Through multiple ion implantations, a body region of the second conductivity type and a drift region of the first conductivity type are respectively formed with a certain interval, the body region is located in the epitaxial layer, and the drift region is located in the epitaxial layer and the initial top silicon layer, wherein the local buried doped region is located at the bottom of the drift region close to the body region side, and the doping concentration of the doped ions in the local buried doped region increases linearly from the body region to the direction away from the body region; By multiple ion implantations, a base lead-out region and a source region are formed in the body region at a certain interval, and a drain region is formed in the drift region; forming a stepped oxide layer, wherein the stepped oxide layer covers a portion of the surface of the drift region; and A stepped polysilicon layer is formed, wherein the polysilicon layer covers a portion of the surface of the body region, a portion of the surface of the drift region, and a portion of the surface of the stepped oxide layer.
9. The method for preparing an LDMOS device based on an SOI substrate according to claim 8, characterized in that: The step of forming a local buried doped region of the first conductivity type in the initial top silicon layer by an ion implantation process comprises: Coating a photoresist layer on the initial top silicon surface; A plurality of opening patterns are defined on the photoresist layer by using a special mask and a photolithography process, wherein the lateral dimensions of the openings in the photoresist layer increase gradually from the direction close to the body region to the direction away from the body region; Using the patterned photoresist layer as a mask, ion implantation is performed on the initial top silicon layer to obtain the local buried doping region with linearly increasing doping concentration; The patterned photoresist layer is removed.
10. The method for preparing an LDMOS device based on an SOI substrate according to claim 9, characterized in that: From the direction close to the body region to the direction away from the body region, the lateral dimensions of the openings in the photoresist layer increase one by one according to the rule of an arithmetic progression.