Chip packaging methods, semiconductor packaging components, and chip packaging components

Abstract

This application discloses a chip packaging method, a semiconductor packaging assembly, and a chip packaging assembly, including: obtaining a lead frame; the lead frame includes multiple chip islands and multiple island connecting ribs, the multiple chip islands being connected by the island connecting ribs; a dicing channel is provided between adjacent chip islands, the width of the dicing channel being less than or equal to 0.1 mm; mounting chips on each chip island; molding the multiple chips and the lead frame to form a molding compound; the molding compound covering the multiple chips, multiple chip islands, and multiple island connecting ribs; forming a first conductive post between the molding compound and the chip's surface away from the chip islands, and forming a first conductive line covering the first conductive post on the molding compound's surface near the chip, so that the chip is electrically connected to the first conductive line; cutting the lead frame based on the dicing channel to obtain multiple chip packaging assemblies. This application can improve the panel utilization rate of the lead frame and the yield of packaged products.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging, and in particular to chip packaging methods, semiconductor packaging components, and chip packaging components. Background Technology

[0002] Lead cutting is an important step in semiconductor packaging technology, which refers to separating the packaging units on the lead frame.

[0003] In existing technologies, leadframes typically include a chip base island, base island connecting ribs, chip pads, pin connecting ribs, a dam, and a dicing channel. The dam is a metal mesh surrounding the chip base island and located within the dicing channel. The base island connecting ribs connect the chip base island to the dam, and the pin connecting ribs connect the pads to the dam, enabling electrical connection between the chip base island and the pads. After packaging each chip, the dicing channel is cut using a dicing process to remove the dam simultaneously, resulting in a single chip package assembly.

[0004] However, dams usually have a preset width, and the cutting channel needs to cover the width of the dam while also setting a cutting allowance. On the one hand, this results in a larger cutting channel width, which reduces the utilization rate of the lead frame panel; on the other hand, it generates large burrs during the cutting process, resulting in a lower yield of the sealed product. Summary of the Invention

[0005] The main technical problem addressed by this application is to provide a chip packaging method, a semiconductor packaging component, and a chip packaging component that can solve the problems of low panel utilization and low yield of packaged products caused by existing packaging methods.

[0006] To solve the above-mentioned technical problems, the first technical solution adopted in this application is to provide a chip packaging method, including: obtaining a lead frame; wherein the lead frame includes multiple chip base islands and multiple base island connecting ribs, the multiple chip base islands are connected by the base island connecting ribs; a dicing channel is provided between adjacent chip base islands, the width of the dicing channel is less than or equal to 0.1 mm; mounting a chip on each chip base island; molding the multiple chips and the lead frame to form a molding compound; wherein the molding compound covers the multiple chips, the multiple chip base islands, and the multiple base island connecting ribs; forming a first conductive post between the molding compound and the chip on the side surface away from the chip base islands, and forming a first conductive line covering the first conductive post on the side surface of the molding compound close to the chip, so that the chip is electrically connected to the first conductive line; cutting the lead frame based on the dicing channel to obtain multiple chip packaging components.

[0007] The step of obtaining the lead frame includes: obtaining a metal substrate of a preset thickness, wherein the preset thickness is 100-210 μm; etching the metal substrate to form multiple chip islands and multiple island connecting ribs.

[0008] The step of etching the metal substrate to form multiple chip islands and multiple island connecting ribs includes: semi-etching the island connecting ribs to form a semi-etched structure; wherein the thickness of the semi-etched structure is 40% to 60% of the thickness of the chip islands.

[0009] The step of forming a first conductive post and a first conductive line on a molding compound, and connecting the first conductive post to the chip pins and the first conductive line respectively, so that the chip is electrically connected to the first conductive line, includes: drilling a hole in the molding compound until the chip is exposed to form a first blind via; forming a first conductive post in the first blind via; and forming a first conductive line covering the first conductive post on the side surface of the molding compound near the chip.

[0010] The step of forming a first conductive pillar in a first blind via and forming a first conductive line covering the first conductive pillar on the surface of the molding compound near the chip includes: forming a first conductive film on the bottom and wall of the first blind via and on the surface of the molding compound near the chip; performing whole-board electroplating on the board on which the first conductive film is formed to form the first conductive pillar in the first blind via and to form a first conductive layer on the surface of the molding compound near the chip; and performing pattern etching on the first conductive layer to form the first conductive line.

[0011] The method includes, after forming a first conductive post in a first blind via and forming a first conductive line covering the first conductive post on the surface of the molding compound near the chip, the method further includes: forming an insulating layer on the surface of the first conductive line away from the chip and on the surface of the molding compound near the chip; drilling through the insulating layer until the first conductive line is exposed to form a second blind via; forming a second conductive post in the second blind via and forming a second conductive line covering the second conductive post on the surface of the insulating layer away from the first conductive line, so that the chip is electrically connected to the second conductive line.

[0012] The step of forming a second conductive post in the second blind hole and forming a second conductive line on the side of the insulating layer away from the first conductive line includes: forming a protective layer on the second conductive line.

[0013] To address the aforementioned technical problems, the second technical solution adopted in this application is to provide a semiconductor packaging assembly, comprising: a lead frame including multiple chip islands and multiple island connecting ribs, the multiple chip islands being connected by the island connecting ribs; a dicing channel is provided between adjacent chip islands, the width of the dicing channel being less than or equal to 0.1 mm; multiple chips, respectively disposed on each chip island; a molding compound covering the multiple chips, multiple chip islands, and multiple island connecting ribs; a first blind via disposed on the molding compound, the bottom of the first blind via being the surface of the chip away from the chip island; a first conductive post disposed within the first blind via and connected to the pins of the chip; and a first conductive line disposed on the surface of the molding compound near the chip and covering the first conductive post. The chip and the first conductive line are electrically connected through the first conductive post.

[0014] To solve the above-mentioned technical problems, the third technical solution adopted in this application is to provide a chip packaging assembly, including: a chip base island; wherein, a base island connecting rib is provided on the periphery of the chip base island; a chip, disposed on the chip base island; a molding compound, covering the chip, the chip base island, and the base island connecting rib; a first blind via, disposed on the molding compound, and the bottom of the first blind via is the side surface of the chip away from the chip base island; a first conductive post, disposed in the first blind via and connected to the pin of the chip; a first conductive line, disposed on the side surface of the molding compound near the chip and covering the first conductive post; wherein, the chip and the first conductive line are electrically connected through the first conductive post.

[0015] The chip packaging assembly further includes: an insulating layer disposed on the surface of the first conductive line away from the chip and on the surface of the molding compound close to the chip; a second blind via disposed on the insulating layer, with the bottom of the second blind via being the first conductive line; a second conductive post disposed within the second blind via; a second conductive line disposed on the surface of the insulating layer away from the first conductive line and covering the second conductive post; wherein the chip and the second conductive line are electrically connected through the first conductive post, the first conductive line, and the second conductive post; and a protective layer covering the second conductive line.

[0016] The beneficial effects of this application are as follows: Unlike existing technologies, this application provides a chip packaging method, a semiconductor packaging assembly, and a chip packaging assembly. By including multiple chip base islands and multiple base island connecting ribs in the lead frame, and connecting the multiple chip base islands through the base island connecting ribs, a dam-free lead frame can be formed. This allows the width of the dicing track to be unrestricted by dams, effectively reducing the width of the dicing track and thus improving the panel utilization rate of the lead frame. Furthermore, since the width of the dicing track is less than or equal to 0.1 mm, the friction between the blade and the dicing track can be reduced during cutting, thereby reducing burr generation and improving the yield of packaged products. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating the first embodiment of the chip packaging method of this application;

[0019] Figure 2 This is a flowchart illustrating the second embodiment of the chip packaging method of this application;

[0020] Figure 3 This is a top view of one embodiment of the lead frame obtained in S203;

[0021] Figure 4 yes Figure 3 A schematic diagram of the cross-sectional structure of the middle lead frame along line AA;

[0022] Figure 5 This is a schematic diagram of one embodiment of the packaging structure obtained in S204;

[0023] Figure 6 This is a schematic diagram of one embodiment of the packaging structure obtained in S206;

[0024] Figure 7 This is a schematic diagram of one embodiment of the packaging structure obtained in S207;

[0025] Figure 8 This is a schematic diagram of one embodiment of the packaging structure obtained in S209;

[0026] Figure 9 This is a schematic diagram of one embodiment of the semiconductor packaging component of this application;

[0027] Figure 10 Based on the cutting track Figure 9 A schematic diagram illustrating the cutting process of semiconductor packaging components;

[0028] Figure 11 This is a schematic diagram of one embodiment of the chip packaging component of this application. Detailed Implementation

[0029] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0030] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “said,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless otherwise clearly indicated above. “Multiple” generally includes at least two, but does not exclude the inclusion of at least one.

[0031] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0032] It should be understood that the terms "comprising," "including," or any other variations used herein are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0033] In existing technologies, leadframes typically include a chip base island, base island connecting ribs, chip pads, pin connecting ribs, a dam, and a dicing channel. The dam is a metal mesh surrounding the chip base island and located within the dicing channel. The base island connecting ribs connect the chip base island to the dam, and the pin connecting ribs connect the pads to the dam, enabling electrical connection between the chip base island and the pads. After packaging each chip, the dicing channel is cut using a rib-cutting process to remove the dam simultaneously, resulting in a single chip package assembly. However, the dam typically has a preset width (0.16–0.18 mm), and the dicing channel needs to cover the dam width while also allowing for a cutting allowance (related to the cutting blade width and cutting machine precision). This results in a larger dicing channel width (greater than or equal to 0.3 mm), reducing the leadframe's panel utilization rate; furthermore, it generates larger burrs during the cutting process, leading to a lower yield of the packaged product.

[0034] Based on the above, this application provides a chip packaging method, a semiconductor packaging component, and a chip packaging component, which can solve the problems of low panel utilization and low yield of packaged products caused by existing packaging methods.

[0035] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0036] Please see Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the chip packaging method of this application. In this embodiment, the method includes:

[0037] S11: Obtain the lead frame; wherein the lead frame includes multiple chip base islands and multiple base island connecting ribs, the multiple chip base islands are connected by base island connecting ribs; a cutting channel is provided between adjacent chip base islands, the width of the cutting channel is less than or equal to 0.1mm.

[0038] In this embodiment, the lead frame is a frame obtained by etching a metal substrate.

[0039] In some embodiments, the metal substrate is a copper substrate.

[0040] In this embodiment, the chip base island is the area where the chip is mounted, and the base island connecting rib is the connecting part that connects adjacent chip base islands.

[0041] In this embodiment, the cutting channel is located between adjacent chip base islands. By cutting the lead frame along the cutting channel, a single chip base island can be obtained.

[0042] Understandably, since the lead frame in this embodiment is designed without a dam, the cutting channel is only affected by the width of the cutting blade and the precision of the cutting machine, and is not limited by the dam. Therefore, the width of the cutting channel can be reduced from 0.3mm in the prior art to 0.1mm, thereby effectively improving the panel utilization rate of the lead frame and reducing the manufacturing cost.

[0043] Understandably, if the width of the cutting blade and the precision of the cutting machine are further reduced, the width of the cutting track can be further reduced to below 0.1mm, thereby further improving the panel utilization rate of the lead frame.

[0044] Understandably, since no chip pads are provided in the lead frame without a dam, the size of the chip base island can be increased accordingly.

[0045] S12: Chips are mounted on each chip island.

[0046] In this embodiment, an adhesive is applied to a designated area of ​​each chip base island, and the chip is mounted on the adhesive.

[0047] In some implementations, the designated area is the middle region of the chip base island.

[0048] In some embodiments, the adhesive is a thermally conductive adhesive. In some specific embodiments, the adhesive is a substance such as solder paste or silver paste.

[0049] In some implementations, the pin region of the chip is located on the side surface of the chip away from the chip base island.

[0050] Understandably, since the lead frame does not include chip pads, it does not perform electrical interconnection; it only serves to fix the chip position and act as a heat sink for the chip.

[0051] In some embodiments, the chip includes a large-size chip or a high-power chip, such as a silicon carbide (SiC) chip or a gallium nitride (GaN) chip, which is not limited in this application.

[0052] Understandably, the larger size of the chip substrate allows for the mounting of larger chips. Furthermore, the larger chip substrate provides better heat dissipation, thus meeting the heat dissipation requirements of high-power chips.

[0053] S13: Molding multiple chips and lead frames to form a molding compound; wherein the molding compound covers multiple chips, multiple chip base islands and multiple base island connecting ribs.

[0054] In this embodiment, a molding compound is obtained and then pressed together with multiple chips and a lead frame to form a molding compound.

[0055] In some embodiments, the molding compound includes one or more of epoxy resins, phenolic resins, polyimides, BT resins, ABF resins, and ceramic-based resins, and this application does not limit the specific materials used.

[0056] S14: A first conductive post is formed between the molded package and the chip on the side away from the chip base island, and a first conductive line is formed on the side of the molded package close to the chip, covering the first conductive post, so that the chip is electrically connected to the first conductive line.

[0057] In this embodiment, the bottom end of the first conductive post is connected to the pin area of ​​the chip, and the top end of the first conductive post is covered by the first conductive line.

[0058] The first conductive post enables an electrical connection between the chip's I / O ports (input / output ports) and the first conductive line, thereby enabling the chip's signal to fan out.

[0059] Understandably, since the active surface of the chip is the side surface away from the chip base island and located on top, and the first conductive pillar is also located above the active surface of the chip, it is equivalent to achieving flip-chip packaging of the chip through the upright packaging process.

[0060] In the existing technology, in order to realize the flip-chip packaging, copper pillars are usually pre-processed on the active surface of the chip so that the copper pillars can be connected to the pads during packaging. This makes the chip manufacturing process more complicated and the processing cycle longer.

[0061] Unlike existing technologies, the first conductive pillar in this embodiment is formed after the chip is mounted, without the need to pre-process copper pillars, thus reducing the difficulty of chip fabrication, thereby reducing the chip processing cycle and consequently reducing the packaging difficulty of flip chips.

[0062] S15: Cut the lead frame based on the cutting path to obtain multiple chip packaging components.

[0063] In this embodiment, the lead frame is cut based on the cutting path to sever the base island connecting ribs that connect adjacent chip base islands, thereby obtaining multiple chip packaging components.

[0064] Understandably, since the width of the cutting channel is less than or equal to 0.1 mm, the friction between the cutting blade and the cutting channel can be reduced during cutting, thereby reducing the generation of burrs and improving the yield of packaged products.

[0065] Unlike existing technologies, this embodiment comprises multiple chip islands and connecting ribs within the leadframe, connecting the chip islands via these ribs to form a dam-free leadframe. This eliminates the dam limitation on the width of the dicing channel, effectively reducing its width and thus improving the panel utilization rate of the leadframe. Furthermore, since the dicing channel width is less than or equal to 0.1 mm, friction between the blade and the dicing channel is reduced during cutting, thereby minimizing burr generation and improving the yield of packaged products.

[0066] Please see Figure 2 , Figure 2 This is a flowchart illustrating a second embodiment of the chip packaging method of this application. In this embodiment, the method includes:

[0067] S201: Obtain a metal substrate of a preset thickness; wherein the preset thickness is 100~210μm.

[0068] In some embodiments, the metal substrate is a copper substrate. In other embodiments, the metal substrate is an iron substrate or a nickel substrate, and this application does not limit the specific substrate to copper.

[0069] Understandably, using a metal substrate to make the lead frame can not only effectively ensure the strength of the lead frame, but also improve the heat dissipation capacity of the chip.

[0070] S202: Etching the metal substrate to form multiple chip islands and multiple island connecting ribs.

[0071] In this embodiment, a cleaving channel is provided between adjacent chip base islands, and the width of the cleaving channel is less than or equal to 0.1 mm.

[0072] In some implementations, the chip base island and the connecting ribs of the base island are integrally formed during the etching process.

[0073] S203: Perform semi-etching on the base island interconnects to form a semi-etched structure; wherein the thickness of the semi-etched structure is 40% to 60% of the thickness of the chip base island.

[0074] In some embodiments, the thickness of the semi-etched structure is 50% of the thickness of the chip base island. In other embodiments, the thickness of the semi-etched structure is 45% of the thickness of the chip base island. In still other embodiments, the thickness of the semi-etched structure is 55% of the thickness of the chip base island, and this application does not limit this to any particular embodiment.

[0075] Understandably, by partially etching the base island connecting ribs to form a semi-etched structure, the thickness of the base island connecting ribs can be reduced. This can further reduce the friction between the blade and the metal during subsequent cutting, which can not only reduce the generation of burrs, but also effectively reduce the probability of blade wear. This can improve the yield of packaged products, extend the service life of the cutting tool, and reduce manufacturing costs.

[0076] Specifically, please refer to Figure 3 and Figure 4 , Figure 3 This is a top view of one embodiment of the lead frame obtained in S203. Figure 4 yes Figure 3 A schematic cross-sectional view of the lead frame along line AA. In this embodiment, the lead frame 100 includes multiple chip islands 10 and multiple island connecting ribs 11, with the multiple chip islands 10 connected by the island connecting ribs 11. A dicing channel 12 is provided between adjacent chip islands 10, and the width of the dicing channel 12 is less than or equal to 0.1 mm. The island connecting ribs 11 have a semi-etched structure, and the thickness of the island connecting ribs 11 is 50% of the thickness of the chip islands 10.

[0077] S204: Chips are mounted on each chip island.

[0078] Please refer to the description in S12 for the specific mounting process, which will not be repeated here.

[0079] S205: Multiple chips and lead frames are encapsulated to form a molded body; wherein the molded body covers multiple chips, multiple chip base islands and multiple base island connecting ribs.

[0080] Please refer to the description in S12 for the specific mounting process, which will not be repeated here.

[0081] Specifically, please refer to Figure 5 , Figure 5 This is a schematic diagram of one embodiment of the packaging structure obtained in S204. In this embodiment, the packaging structure 200 includes a lead frame 100, a plurality of chips 20, and a molding compound 30. The lead frame 100 includes a plurality of chip base islands 10 and a plurality of base island connecting ribs 11, and the plurality of chip base islands 10 are connected by the base island connecting ribs 11. The plurality of chips 20 are respectively disposed on each chip base island 10, and the chips 20 are attached to the chip base islands 10 by adhesive 21. The molding compound 30 covers the plurality of chips 20, the plurality of chip base islands 10, and the plurality of base island connecting ribs 11.

[0082] S206: Drill a hole through the molding compound until the chip is exposed to form the first blind via.

[0083] In this embodiment, the encapsulated body is drilled using a laser.

[0084] In this embodiment, the bottom of the first blind hole is the pin area of ​​the chip.

[0085] Specifically, please refer to Figure 6 , Figure 6 This is a schematic diagram of one embodiment of the packaging structure obtained in S206. In this embodiment, the packaging structure 300 includes a lead frame 100, multiple chips 20, a molding compound 30, and multiple first blind vias 40. The lead frame 100 includes multiple chip base islands 10 and multiple base island connecting ribs 11, and the multiple chip base islands 10 are connected by the base island connecting ribs 11. Multiple chips 20 are respectively disposed on each chip base island 10, and the chips 20 are attached to the chip base islands 10 by adhesive 21. The molding compound 30 covers the multiple chips 20, the multiple chip base islands 10, and the multiple base island connecting ribs 11. The first blind vias 40 are disposed on the molding compound 30, and the bottom of the first blind via 40 is the side surface of the chip 20 away from the chip base island 10. Wherein, the bottom of the first blind via 40 is the pin area of ​​the chip 20.

[0086] S207: A first conductive post is formed in the first blind via, and a first conductive line covering the first conductive post is formed on the side surface of the molding compound near the chip.

[0087] In this embodiment, a first conductive film is first formed on the bottom and wall of the first blind via and on the surface of the molding compound near the chip. The first conductive film is a conductive seed layer formed by sputtering or chemical deposition to facilitate subsequent copper electroplating.

[0088] Furthermore, the substrate on which the first conductive film is formed is subjected to whole-board electroplating to form a first conductive pillar in the first blind hole and a first conductive layer on the surface of the molding compound near the chip.

[0089] Further, the first conductive layer is patterned by etching to form the first conductive line.

[0090] In some implementations, the first conductive layer is patterned by photolithography, development, and etching.

[0091] Specifically, please refer to Figure 7 , Figure 7 This is a schematic diagram of one embodiment of the packaging structure obtained in S207. In this embodiment, the packaging structure 400 includes a lead frame 100, multiple chips 20, a molding compound 30, multiple first blind vias 40, multiple first conductive posts 41, and a first conductive line 50. The lead frame 100 includes multiple chip islands 10 and multiple island connecting ribs 11, and the multiple chip islands 10 are connected by the island connecting ribs 11. Multiple chips 20 are respectively disposed on each chip island 10, and the chips 20 are attached to the chip islands 10 by adhesive 21. The molding compound 30 covers the multiple chips 20, the multiple chip islands 10, and the multiple island connecting ribs 11. The first blind vias 40 are disposed on the molding compound 30, and the bottom of the first blind vias 40 is the side surface of the chip 20 away from the chip island 10. The bottom of the first blind vias 40 is the pin area of ​​the chip 20. The first conductive posts 41 are disposed in the first blind vias 40 and are connected to the pins of the chip 20. The first conductive line 50 is disposed on the surface of the molding compound 30 near the chip 20 and covers the first conductive post 41. The chip 20 and the first conductive line 50 are electrically connected through the first conductive post 41.

[0092] S208: An insulating layer is formed on the surface of the first conductive line away from the chip and on the surface of the molding compound close to the chip.

[0093] In this embodiment, an insulating material is obtained, and the insulating material is pressed together with the surface of the first conductive line away from the chip and the surface of the encapsulation close to the chip to form an insulating layer.

[0094] In some embodiments, the insulating material includes one or more of prepreg (PP), polyimide (PI), and FR-4 grade materials, which are not limited in this application.

[0095] Understandably, the insulation layer can increase the overall structural rigidity of the product and buffer welding stress.

[0096] S209: Drill holes in the insulating layer until the first conductive line is exposed, to form a second blind hole.

[0097] In this embodiment, the insulating layer is drilled using a laser.

[0098] Specifically, please refer to Figure 8 , Figure 8 This is a schematic diagram of one embodiment of the packaging structure obtained in S209. In this embodiment, the packaging structure 500 includes a lead frame 100, multiple chips 20, a molding compound 30, multiple first blind vias 40, multiple first conductive posts 41, a first conductive line 50, an insulating layer 60, and multiple second blind vias 70. The lead frame 100 includes multiple chip base islands 10 and multiple base island connecting ribs 11, and the multiple chip base islands 10 are connected by the base island connecting ribs 11. Multiple chips 20 are respectively disposed on each chip base island 10, and the chips 20 are attached to the chip base islands 10 by adhesive 21. The molding compound 30 covers the multiple chips 20, the multiple chip base islands 10, and the multiple base island connecting ribs 11. The first blind vias 40 are disposed on the molding compound 30, and the bottom of the first blind vias 40 is the side surface of the chip 20 away from the chip base island 10. Wherein, the bottom of the first blind vias 40 is the pin area of ​​the chip 20. A first conductive post 41 is disposed within a first blind via 40 and connected to a pin of the chip 20. A first conductive line 50 is disposed on the surface of the molding compound 30 near the chip 20 and covers the first conductive post 41. The chip 20 and the first conductive line 50 are electrically connected via the first conductive post 41. An insulating layer 60 is disposed on the surface of the first conductive line 50 away from the chip 20 and on the surface of the molding compound 30 near the chip 20. A second blind via 70 is disposed on the insulating layer 60, and the bottom of the second blind via 70 is the first conductive line 50.

[0099] S210: A second conductive post is formed in the second blind via, and a second conductive line covering the second conductive post is formed on the surface of the insulating layer away from the first conductive line, so that the chip is electrically connected to the second conductive line.

[0100] In this embodiment, a second conductive film is first formed on the bottom and wall of the second blind via, as well as on the surface of the insulating layer away from the first conductive line. The second conductive film is a conductive seed layer formed by sputtering or chemical deposition, facilitating subsequent copper electroplating.

[0101] Furthermore, the entire board of the substrate on which the second conductor film is formed is electroplated to form a second conductive pillar in the second blind hole and to form a second conductive layer on the side of the insulating layer away from the first conductive line.

[0102] Further, the second conductive layer is patterned by etching to form a second conductive line.

[0103] In some implementations, the second conductive layer is patterned by photolithography, development, and etching.

[0104] In this embodiment, the first conductive post, the first conductive line, and the second conductive post enable an electrical connection between the chip's I / O port and the second conductive line, thereby achieving chip signal fan-out.

[0105] Understandably, because an insulating layer is placed above the active surface of the chip, the stress conducted to the active surface of the chip during the soldering process can be greatly alleviated, thus meeting the stress release requirements of stress-sensitive analog chips. Furthermore, by setting the first and second conductive lines, the number of wiring layers can be increased, so that the fan-out of the chip is not limited by the number and diameter of wires, thereby increasing the flexibility of chip design and improving the current carrying capacity of the overall package assembly.

[0106] S211: A protective layer is formed on the second conductive line.

[0107] In this embodiment, a protective layer is formed on the second conductive line through surface treatment to prevent pad oxidation and provide solderability.

[0108] Specifically, please refer to Figure 9 , Figure 9This is a schematic diagram of one embodiment of the semiconductor packaging assembly of this application. In this embodiment, the semiconductor packaging assembly 600 includes a lead frame 100, a plurality of chips 20, a molding compound 30, a plurality of first blind vias 40, a plurality of first conductive pillars 41, a first conductive line 50, an insulating layer 60, a plurality of second blind vias 70, a plurality of second conductive pillars 71, a second conductive line 80, and a protective layer 90. The lead frame 100 includes a plurality of chip base islands 10 and a plurality of base island connecting ribs 11, and the plurality of chip base islands 10 are connected by the base island connecting ribs 11. A plurality of chips 20 are respectively disposed on each chip base island 10, and the chips 20 are attached to the chip base islands 10 by adhesive 21. The molding compound 30 covers the plurality of chips 20, the plurality of chip base islands 10, and the plurality of base island connecting ribs 11. The first blind vias 40 are disposed on the molding compound 30, and the bottom of the first blind via 40 is the side surface of the chip 20 away from the chip base island 10. Wherein, the bottom of the first blind via 40 is the pin area of ​​the chip 20. A first conductive post 41 is disposed within a first blind via 40 and connected to a pin of the chip 20. A first conductive line 50 is disposed on the surface of the molding compound 30 near the chip 20 and covers the first conductive post 41. The chip 20 and the first conductive line 50 are electrically connected via the first conductive post 41. An insulating layer 60 is disposed on the surface of the first conductive line 50 away from the chip 20 and on the surface of the molding compound 30 near the chip 20. A second blind via 70 is disposed on the insulating layer 60, with the bottom of the second blind via 70 being the first conductive line 50. A second conductive post 71 is disposed within the second blind via 70. A second conductive line 80 is disposed on the surface of the insulating layer 60 away from the first conductive line 50 and covers the second conductive post 71. The chip 20 is electrically connected to the second conductive line 80 via the first conductive post 41, the first conductive line 50, and the second conductive post 71. A protective layer 90 covers the second conductive line 80.

[0109] S212: Cut the lead frame based on the cutting path to obtain multiple chip packaging components.

[0110] In this embodiment, the lead frame is cut by a cutting machine based on the cutting track to obtain multiple chip packaging components.

[0111] Specifically, please refer to Figure 10 and Figure 11 , Figure 10 Based on the cutting track Figure 9 A schematic diagram of the cutting process for semiconductor packaging components. Figure 11 This is a schematic diagram of one embodiment of the chip packaging component of this application.

[0112] In this embodiment, the lead frame 100 is cut based on the cutting channel 12 to sever the base island connecting ribs 11 that connect adjacent chip base islands 10, thereby obtaining multiple chip packaging components 800.

[0113] In this embodiment, the chip packaging assembly 800 includes a chip base island 10, base island connecting ribs 11, a chip 20, a molding compound 30, a first blind via 40, a first conductive post 41, a first conductive line 50, an insulating layer 60, a second blind via 70, a second conductive post 71, a second conductive line 80, and a protective layer 90. The chip base island 10 has base island connecting ribs 11 arranged around its periphery. The chip 20 is disposed on the chip base island 10. The molding compound 30 covers the chip 20, the chip base island 10, and the base island connecting ribs 11. The first blind via 40 is disposed on the molding compound 30, and the bottom of the first blind via 40 is the surface of the chip 20 furthest from the chip base island 10. The first conductive post 41 is disposed within the first blind via 40 and connected to the pins of the chip 20. The first conductive line 50 is disposed on the surface of the molding compound 30 closest to the chip 20 and covers the first conductive post 41. The chip 20 and the first conductive line 50 are electrically connected through the first conductive post 41. An insulating layer 60 is disposed on the surface of the first conductive line 50 away from the chip 20 and on the surface of the molding compound 30 close to the chip 20. A second blind via 70 is disposed on the insulating layer 60, with the bottom of the second blind via 70 being the first conductive line 50. A second conductive post 71 is disposed within the second blind via 70. A second conductive line 80 is disposed on the surface of the insulating layer 60 away from the first conductive line 50 and covers the second conductive post 71. The chip 20 and the second conductive line 80 are electrically connected through the first conductive post 41, the first conductive line 50, and the second conductive post 71. A protective layer 90 covers the second conductive line 80.

[0114] Unlike existing technologies, this application, by including multiple chip islands and multiple island connecting ribs in the leadframe and connecting the chip islands through these ribs, forms a dam-free leadframe. This eliminates the limitation on the width of the dicing track, effectively reducing its width and thus improving the panel utilization rate of the leadframe. Furthermore, since the dicing track width is less than or equal to 0.1 mm, friction between the blade and the track is reduced during cutting, thereby reducing burr generation and improving the yield of packaged products. Simultaneously, by performing semi-etching on the island connecting ribs to form a semi-etched structure, the thickness of the connecting ribs can be reduced, further reducing friction between the blade and metal during subsequent cutting. This improves the yield of packaged products, extends the lifespan of the cutting tool, and reduces manufacturing costs. Furthermore, by setting a first conductive line, an insulating layer, and a second conductive line above the active surface of the chip, the stress transmitted to the active surface of the chip during the soldering process can be alleviated through the insulating layer, thereby meeting the stress release requirements of stress-sensitive analog chips; and by increasing the number of wiring layers, the fan-out of the chip is not restricted by the number and diameter of the wires, thereby increasing the flexibility of chip design and improving the current carrying capacity of the overall packaging assembly.

[0115] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A chip packaging method, characterized in that, include: A lead frame is obtained; wherein the lead frame includes multiple chip base islands and multiple base island connecting ribs, the multiple chip base islands are connected by the base island connecting ribs, and the lead frame has no dams; a cutting channel is provided between adjacent chip base islands, and the width of the cutting channel is less than or equal to 0.1mm; The chip is mounted on each of the chip islands; the pin area of ​​the chip is disposed on the surface of the chip away from the chip island. The plurality of chips and the lead frame are encapsulated to form a molded body; wherein the molded body covers the plurality of chips, the plurality of chip base islands, and the plurality of base island connecting ribs; A first conductive post is formed between the molding compound and the chip on the side away from the chip base island, and a first conductive line is formed on the side of the molding compound close to the chip, covering the first conductive post, so that the chip is electrically connected to the first conductive line; the bottom end of the first conductive post is connected to the pin area of ​​the chip, and the top end of the first conductive post is covered by the first conductive line. The lead frame is cut based on the cutting path to obtain multiple chip packaging components.

2. The chip packaging method according to claim 1, characterized in that, The step of obtaining the lead frame includes: Obtain a metal substrate with a preset thickness; wherein the preset thickness is 100–210 μm; The metal substrate is etched to form a plurality of chip islands and a plurality of island connecting ribs.

3. The chip packaging method according to claim 2, characterized in that, After etching the metal substrate to form multiple chip islands and multiple island interconnects, the process includes: The base island connecting ribs are partially etched to form a partially etched structure; wherein the thickness of the partially etched structure is 40% to 60% of the thickness of the chip base island.

4. The chip packaging method according to claim 1, characterized in that, The step of forming a first conductive post between the molding compound and the surface of the chip away from the chip base island, and forming a first conductive line covering the first conductive post on the surface of the molding compound near the chip, so as to electrically connect the chip to the first conductive line, includes: The molding compound is drilled through until the chip is exposed, forming a first blind via. The first conductive post is formed in the first blind via, and a first conductive line covering the first conductive post is formed on the surface of the molding compound near the chip.

5. The chip packaging method according to claim 4, characterized in that, The step of forming the first conductive post in the first blind via and forming a first conductive line covering the first conductive post on the surface of the molding compound near the chip includes: A first conductive film is formed on the bottom and wall of the first blind via and on the surface of the molding compound near the chip. The substrate on which the first conductor film is formed is subjected to whole-board electroplating to form the first conductive pillar in the first blind hole and to form a first conductive layer on the surface of the molding compound near the chip. The first conductive layer is patterned by etching to form the first conductive line.

6. The chip packaging method according to claim 4, characterized in that, After the step of forming the first conductive post in the first blind via and forming a first conductive line covering the first conductive post on the surface of the molding compound near the chip, the method includes: An insulating layer is formed on the surface of the first conductive line away from the chip and on the surface of the molding compound close to the chip; The insulating layer is drilled through until the first conductive line is exposed, in order to form a second blind hole; A second conductive post is formed in the second blind via, and a second conductive line is formed on the surface of the insulating layer away from the first conductive line, covering the second conductive post, so that the chip is electrically connected to the second conductive line.

7. The chip packaging method according to claim 6, characterized in that, After the steps of forming a second conductive post in the second blind hole and forming a second conductive line on the surface of the insulating layer away from the first conductive line, the method includes: A protective layer is formed on the second conductive line.

8. A semiconductor packaging component, characterized in that, include: A lead frame includes multiple chip islands and multiple island connecting ribs, wherein the multiple chip islands are connected by the island connecting ribs, and the lead frame has no dams. A dicing channel is provided between adjacent chip base islands, and the width of the dicing channel is less than or equal to 0.1 mm; Multiple chips are respectively disposed on each of the chip base islands; the pin area of ​​each chip is disposed on the surface of the chip away from the chip base island; A molding compound covering multiple chips, multiple chip base islands, and multiple base island connecting ribs; A first blind via is disposed on the molding compound, and the bottom of the first blind via is the side surface of the chip away from the chip base island; A first conductive post is disposed within the first blind via and connected to the pin area of ​​the chip; A first conductive line is disposed on the surface of the molding compound near the chip and covers the first conductive post; wherein the chip and the first conductive line are electrically connected through the first conductive post.

9. A chip packaging component, characterized in that, The chip packaging assembly is obtained by cutting the semiconductor packaging assembly of claim 8 based on a dicing channel, and the chip packaging assembly includes: Chip base island; wherein, the chip base island is provided with base island connecting ribs on its periphery; A chip is disposed on the chip base island; the pin area of ​​the chip is disposed on the surface of the chip away from the chip base island. A molding compound covering the chip, the chip base island, and the base island connecting ribs; A first blind via is disposed on the molding compound, and the bottom of the first blind via is the side surface of the chip away from the chip base island; A first conductive post is disposed within the first blind via and connected to the pin area of ​​the chip; A first conductive line is disposed on the surface of the molding compound near the chip and covers the first conductive post; wherein the chip and the first conductive line are electrically connected through the first conductive post.

10. The chip packaging assembly according to claim 9, characterized in that, The chip packaging assembly also includes: An insulating layer is disposed on the surface of the first conductive line away from the chip and on the surface of the molding compound close to the chip; A second blind hole is disposed on the insulating layer, and the bottom of the second blind hole is the first conductive line; The second conductive post is disposed within the second blind hole; The second conductive line is disposed on the surface of the insulating layer away from the first conductive line and covers the second conductive post; wherein, the chip and the second conductive line are electrically connected through the first conductive post, the first conductive line and the second conductive post; A protective layer covers the second conductive line.

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