Method for improving defect of junction of NMOS metal gate and PMOS metal gate
By forming SiN or SiCN separation at the junction of NMOS and PMOS metal gates, increasing the width of the junction and using metal replacement, the defect problem caused by wet etching is solved, the product yield is improved, and the performance at the junction is improved.
Patent Information
- Application Number
- CN202411215437.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2024-12-13
AI Technical Summary
In the HKMG process at the 28nm process node, defects are prone to occur at the junction of NMOS metal gates and PMOS metal gates, resulting in timing problems and product yield losses, mainly due to Si residual or hollow defects and AL damage defects caused by wet etching.
By forming a certain width of SiN or SiCN separation at the junction of NMOS and PMOS metal gates, the width at the junction is increased, and the SiN or SiCN is replaced by metal to improve defect problems and improve product yield.
It effectively solves the defect problem at the boundary, improves product yield, and improves the performance at the junction of NMOS and PMOS metal gates.
Smart Images
Figure CN119133104A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of semiconductor manufacturing, and in particular to a method for improving defects at the junction of an NMOS metal gate and a PMOS metal gate. Background Art
[0002] HKMG has a gate dielectric layer with a high dielectric constant (HK) and a metal gate (MG), so it is usually abbreviated as HKMG in the art. In the HKMG process of the 28nm process node, metal aluminum is used as a filling layer, that is, a metal conductive material layer of the metal gate that fills the gate trench, which has the following advantages: compared with precious metals such as gold and silver, it has a lower cost and lower resistivity, and the deposition process is simple, and can be completed through traditional PVD processes.
[0003] At present, in the NP separation HKMG process, the NMOS metal gate (NMG) and the PMOS metal gate (PMG) are made separately (and the PMOS metal gate is made first and then the NMOS metal gate). NDPR (N Dummy Poly Remove) requires that the N Dummy poly (NMOS pseudo polysilicon gate) be removed cleanly without damaging the metal aluminum of PMG. However, since NDPR uses wet etching, the wet etching solution has a high etching rate for metal aluminum, which makes this process have higher requirements for PRG / DRG CD&OVL. If the NRG (N Replacing Gate) PR line is larger than the PRG (P Replacing Gate) PR space (i.e., when the NMOS pseudo-polysilicon gate is removed, the photoresist protection layer formed above the PMOS metal gate extends to the top of the NMOS pseudo-gate), Si residue or void defects are likely to occur. If the NRG PR line is smaller than the PRG PR space (i.e., when the NMOS pseudo-polysilicon gate is removed, the photoresist protection layer formed above the PMOS metal gate is smaller than the width of the PMOS metal gate), AL damage defects are likely to occur, resulting in poor defect performance at the MG NP junction, causing timing problems and resulting in product yield loss. Summary of the invention
[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for improving defects at the junction of NMOS metal gate and PMOS metal gate, so as to solve the problem that defects are easily generated at the junction of NMOS metal gate and PMOS metal gate.
[0005] To achieve the above objectives and other related objectives, the present invention provides a method for improving defects at the junction of an NMOS metal gate and a PMOS metal gate, the method comprising:
[0006] A substrate is provided, which has an NMOS region and a PMOS region, wherein a high-K dielectric layer, a first isolation layer, a dummy gate layer and a groove are formed on the surface of the substrate, wherein the groove is formed by etching the high-K dielectric layer, the first isolation layer and the dummy gate layer at the junction of the NMOS region and the PMOS region;
[0007] Forming a sidewall on the substrate and forming a filling layer in the groove, wherein the sidewall is located on a side of the NMOS region and the PMOS region away from the groove, and is used to define the NMOS region and the PMOS region;
[0008] Removing the dummy gate layer and the first isolation layer in the PMOS region, and forming a PMOS metal gate structure, wherein the PMOS metal gate structure includes a first bottom barrier layer, a U-shaped PMOS work function metal layer, a U-shaped first top barrier layer, a U-shaped first adhesion layer and a PMOS metal gate layer;
[0009] Removing the dummy gate layer and the first isolation layer in the NMOS region, and forming an NMOS metal gate structure, wherein the NMOS metal gate structure includes a second bottom barrier layer, a U-shaped NMOS work function metal layer, a U-shaped second adhesion layer and an NMOS metal gate layer;
[0010] The filling layer in the groove is removed, and the groove is filled with a metal layer.
[0011] Optionally, the first bottom barrier layer includes a TiN layer and a U-shaped TaN layer formed on the surface of the high-K dielectric layer, wherein the bottom of the U-shaped TaN layer is located on the surface of the TiN layer, and its sides are respectively located on the sidewalls of the sidewalls and the filling layer.
[0012] Optionally, the PMOS work function metal layer is formed on a surface of the TaN layer; the first top barrier layer is formed on a surface of the PMOS work function metal layer; and the first adhesion layer is formed on a surface of the first top barrier layer.
[0013] Optionally, the material of the PMOS work function metal layer includes TiN; the material of the first top barrier layer includes TaN; the material of the first adhesion layer includes Ti and TiN; and the material of the PMOS metal gate layer includes metal aluminum.
[0014] Optionally, the second bottom barrier layer includes a TiN layer and a U-shaped TaN layer formed on the surface of the high-K dielectric layer, wherein the bottom of the U-shaped TaN layer is located on the surface of the TiN layer, and its sides are respectively located on the sidewalls and the sidewalls of the filling layer.
[0015] Optionally, the NMOS work function metal layer is formed on a surface of the TaN layer; and the second adhesion layer is formed on a surface of the NMOS work function metal layer.
[0016] Optionally, the material of the NMOS work function metal layer includes TiAL; the material of the second adhesion layer includes Ti and TiN; and the material of the NMOS metal gate layer includes metal aluminum.
[0017] Optionally, the metal layer filling the groove includes Ti / TiN / W or Co / Ru / Cu.
[0018] Optionally, the material of the first isolation layer includes TiN.
[0019] Optionally, the material of the dummy gate layer includes polysilicon.
[0020] Optionally, the filling layer includes a SiN layer or a SiCN layer.
[0021] Optionally, when removing the filling layer in the groove, a hard mask layer and a cap layer are used to protect the PMOS metal gate structure and the NMOS metal gate structure, wherein the cap layer is formed on a surface of the hard mask layer.
[0022] Optionally, the material of the hard mask layer includes TiN; and the material of the cap layer includes silicon oxide.
[0023] As described above, the method of improving defects at the junction of an NMOS metal gate and a PMOS metal gate of the present invention is to increase the width of the junction by separating the two with SiN or SiCN of a certain width at the junction when forming the NMOS metal gate and the PMOS metal gate, so that the defect window at the boundary is increased, and then metal is used to replace SiN or SiCN, thereby effectively improving the defect problem at the boundary and improving the product yield. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 to Figure 5 It is a cross-sectional structural schematic diagram of the process of forming a PMOS metal gate and an NMOS metal gate according to the present invention.
[0025] Figure 6 The flowchart is a method for improving the defects at the interface between NMOS metal gate and PMOS metal gate according to the present invention.
[0026] Description of Figure Numbers
[0027] 10: substrate; 20: high-K dielectric layer; 30: first isolation layer; 40: pseudo gate layer; 50: groove; 51: filling layer; 52: metal layer; 52a: Ti / TiN layer; 52b: W layer; 60: sidewall; 70: PMOS metal gate structure; 71: first bottom barrier layer; 71a, 81a: TiN layer; 71b, 81b: TaN layer; 72: PMOS work function metal layer; 73: first top barrier layer; 74: first adhesion layer; 75: PMOS metal gate layer; 80: NMOS metal gate structure; 81: second bottom barrier layer; 82: NMOS work function metal layer; 83: second adhesion layer; 84: NMOS metal gate layer; 91: hard mask layer; 92: cap layer DETAILED DESCRIPTION
[0028] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0029] See also Figures 1 to 6 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.
[0030] like Figure 6 As shown, this embodiment provides a method for improving defects at the junction of an NMOS metal gate and a PMOS metal gate, the method comprising:
[0031] Step 1) providing a substrate 10 having an NMOS region and a PMOS region, wherein a high-K dielectric layer 20, a first isolation layer 30, a dummy gate layer 40 and a groove 50 are formed on the surface of the substrate 10, wherein the groove 50 is formed by etching the high-K dielectric layer 20, the first isolation layer 30 and the dummy gate layer 40 at the junction of the NMOS region and the PMOS region;
[0032] Step 2) forming a sidewall 60 on the substrate and forming a filling layer 51 in the groove 50, wherein the sidewall 60 is located on a side of the NMOS region and the PMOS region away from the groove 50, and is used to define the NMOS region and the PMOS region;
[0033] Step 3) removing the dummy gate layer 40 and the first isolation layer 30 in the PMOS region, and forming a PMOS metal gate structure 70, wherein the PMOS metal gate structure 70 includes a first bottom barrier layer 71, a U-shaped PMOS work function metal layer 72, a U-shaped first top barrier layer 73, a U-shaped first adhesion layer 74 and a PMOS metal gate layer 75;
[0034] Step 4) removing the dummy gate layer 40 and the first isolation layer 30 in the NMOS region, and forming an NMOS metal gate structure 80, wherein the NMOS metal gate structure 80 includes a second bottom barrier layer 81, a U-shaped NMOS work function metal layer 82, a U-shaped second adhesion layer 83 and an NMOS metal gate layer 84;
[0035] Step 5) removing the filling layer 51 in the groove 50 and filling the groove with a metal layer 52 .
[0036] The following is combined with Figure 1 ~Attached Figure 5 The method for improving the defects at the junction of the NMOS metal gate and the PMOS metal gate provided in this embodiment is described in detail.
[0037] like Figure 1 As shown, in step 1), a substrate 10 is provided, which has an NMOS region and a PMOS region, and a high-K dielectric layer 20, a first isolation layer 30, a dummy gate layer 40 and a groove 50 are formed on the surface of the substrate 10, wherein the groove 50 is formed by etching the high-K dielectric layer 20, the first isolation layer 30 and the dummy gate layer 40 at the junction of the NMOS region and the PMOS region.
[0038] Specifically, the material of the first isolation layer 30 includes TiN.
[0039] Specifically, the material of the dummy gate layer 40 includes polysilicon.
[0040] like Figure 2 As shown, in step 2), a sidewall 60 is formed on the substrate, and a filling layer 51 is formed in the groove 50, wherein the sidewall 60 is located on a side of the NMOS region and the PMOS region away from the groove 50, and is used to define the NMOS region and the PMOS region.
[0041] Specifically, the filling layer 51 includes a SiN layer or a SiCN layer.
[0042] like Figure 2As shown, in step 3), the pseudo gate layer 40 and the first isolation layer 30 of the PMOS region are removed, and a PMOS metal gate structure 70 is formed, wherein the PMOS metal gate structure 70 includes a first bottom barrier layer 71, a U-shaped PMOS work function metal layer 72, a U-shaped first top barrier layer 73, a U-shaped first adhesion layer 74 and a PMOS metal gate layer 75.
[0043] Specifically, the first bottom barrier layer 71 includes a TiN layer 71a and a U-shaped TaN layer 71b formed on the surface of the high-K dielectric layer, wherein the bottom of the U-shaped TaN layer 71b is located on the surface of the TiN layer 71a, and its sides are respectively located on the side walls of the sidewalls 60 and the filling layer 51.
[0044] Specifically, the PMOS work function metal layer 72 is formed on the surface of the TaN layer 71 b ; the first top barrier layer 73 is formed on the surface of the PMOS work function metal layer 72 ; and the first adhesion layer 74 is formed on the surface of the first top barrier layer 73 .
[0045] More specifically, the material of the PMOS work function metal layer 72 includes TiN; the material of the first top barrier layer 73 includes TaN; the material of the first adhesion layer 74 includes Ti and TiN; and the material of the PMOS metal gate layer 75 includes metal aluminum.
[0046] like Figure 3 As shown, in step 4), the pseudo gate layer 40 and the first isolation layer 30 of the NMOS region are removed, and an NMOS metal gate structure 80 is formed, wherein the NMOS metal gate structure 80 includes a second bottom barrier layer 81, a U-shaped NMOS work function metal layer 82, a U-shaped second adhesion layer 83 and an NMOS metal gate layer 84.
[0047] Specifically, the second bottom barrier layer 81 includes a TiN layer 81a and a U-shaped TaN layer 81b formed on the surface of the high-K dielectric layer, wherein the bottom of the U-shaped TaN layer 81b is located on the surface of the TiN layer 81a, and its sides are respectively located on the side walls of the side wall 60 and the filling layer 51.
[0048] Specifically, the NMOS work function metal layer 82 is formed on the surface of the TaN layer 81 b ; and the second adhesion layer 83 is formed on the surface of the NMOS work function metal layer 84 .
[0049] More specifically, the material of the NMOS work function metal layer 82 includes TiAL; the material of the second adhesion layer 83 includes Ti and TiN; and the material of the NMOS metal gate layer 84 includes metal aluminum.
[0050] like Figure 4 and Figure 5 As shown, in step 5), the filling layer 51 in the groove 50 is removed, and the groove is filled with a metal layer 52.
[0051] Specifically, when removing the filling layer 51 in the groove 50 , the PMOS metal gate structure 70 and the NMOS metal gate structure 80 are protected by a hard mask layer 91 and a cap layer 92 , wherein the cap layer 92 is formed on the surface of the hard mask layer 91 .
[0052] More specifically, the material of the hard mask layer 91 includes TiN; the material of the cap layer 102 includes silicon oxide.
[0053] Specifically, the metal layer 52 filling the groove 50 includes Ti / TiN / W or Co / Ru / Cu.
[0054] In this embodiment, the metal selected for the metal layer 52 is Ti / TiN / W, and the Ti / TiN layer 52a is U-shaped, and the W layer 52b is filled in the groove formed by the U-shaped Ti / TiN layer.
[0055] In summary, the method of improving the defect at the junction of the NMOS metal gate and the PMOS metal gate of the present invention is to separate the NMOS metal gate and the PMOS metal gate at the junction by SiN or SiCN of a certain width when forming the NMOS metal gate and the PMOS metal gate, increase the width of the junction, so that the defect window at the boundary is increased, and then use metal to replace SiN or SiCN, thereby effectively solving the defect problem at the boundary and improving the product yield. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0056] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for improving defects at the junction of NMOS metal gate and PMOS metal gate, characterized in that: The method comprises: providing a substrate having an NMOS region and a PMOS region, wherein a high-K dielectric layer, a first isolation layer, a dummy gate layer and a groove are formed on the surface of the substrate, wherein the groove is formed by etching the high-K dielectric layer, the first isolation layer and the dummy gate layer at the junction of the NMOS region and the PMOS region; Forming a sidewall on the substrate and forming a filling layer in the groove, wherein the sidewall is located on a side of the NMOS region and the PMOS region away from the groove, and is used to define the NMOS region and the PMOS region; Removing the dummy gate layer and the first isolation layer in the PMOS region, and forming a PMOS metal gate structure, wherein the PMOS metal gate structure includes a first bottom barrier layer, a U-shaped PMOS work function metal layer, a U-shaped first top barrier layer, a U-shaped first adhesion layer and a PMOS metal gate layer; Removing the dummy gate layer and the first isolation layer in the NMOS region, and forming an NMOS metal gate structure, wherein the NMOS metal gate structure includes a second bottom barrier layer, a U-shaped NMOS work function metal layer, a U-shaped second adhesion layer and an NMOS metal gate layer; The filling layer in the groove is removed, and the groove is filled with a metal layer.
2. The method for improving the defect at the junction of NMOS metal gate and PMOS metal gate according to claim 1, characterized in that: The first bottom barrier layer includes a TiN layer and a U-shaped TaN layer formed on the surface of the high-K dielectric layer, wherein the bottom of the U-shaped TaN layer is located on the surface of the TiN layer, and its sides are respectively located on the sidewalls of the spacer and the sidewalls of the filling layer.
3. The method for improving the defect at the junction of NMOS metal gate and PMOS metal gate according to claim 2, characterized in that: The PMOS work function metal layer is formed on the surface of the TaN layer; the first top barrier layer is formed on the surface of the PMOS work function metal layer; and the first adhesion layer is formed on the surface of the first top barrier layer.
4. The method for improving the defect at the junction between the NMOS metal gate and the PMOS metal gate according to claim 3, characterized in that: The material of the PMOS work function metal layer includes TiN; the material of the first top barrier layer includes TaN; the material of the first adhesion layer includes Ti and TiN; and the material of the PMOS metal gate layer includes metal aluminum.
5. The method for improving the defect at the junction between the NMOS metal gate and the PMOS metal gate according to claim 1, characterized in that: The second bottom barrier layer includes a TiN layer and a U-shaped TaN layer formed on the surface of the high-K dielectric layer, wherein the bottom of the U-shaped TaN layer is located on the surface of the TiN layer, and its sides are respectively located on the sidewalls and the sidewalls of the filling layer.
6. The method for improving the defect at the junction between the NMOS metal gate and the PMOS metal gate according to claim 5, characterized in that: The NMOS work function metal layer is formed on the surface of the TaN layer; and the second adhesion layer is formed on the surface of the NMOS work function metal layer.
7. The method for improving the defect at the junction between the NMOS metal gate and the PMOS metal gate according to claim 6, characterized in that: The material of the NMOS work function metal layer includes TiAL; the material of the second adhesion layer includes Ti and TiN; The material of the NMOS metal gate layer includes metal aluminum.
8. The method for improving the defect at the junction between NMOS metal gate and PMOS metal gate according to claim 1, characterized in that: The metal layer filling the groove includes Ti / TiN / W or Co / Ru / Cu.
9. The method for improving the defect at the junction between the NMOS metal gate and the PMOS metal gate according to claim 1, characterized in that: The material of the first isolation layer includes TiN.
10. The method for improving the defect at the junction between NMOS metal gate and PMOS metal gate according to claim 1, characterized in that: The material of the dummy gate layer includes polysilicon.
11. The method for improving the defect at the junction between NMOS metal gate and PMOS metal gate according to claim 1, characterized in that: The filling layer includes a SiN layer or a SiCN layer.
12. The method for improving the defect at the junction between NMOS metal gate and PMOS metal gate according to claim 1, characterized in that: When removing the filling layer in the groove, the PMOS metal gate structure and the NMOS metal gate structure are protected by a hard mask layer and a cap layer, wherein the cap layer is formed on the surface of the hard mask layer.
13. The method for improving the defect at the junction between the NMOS metal gate and the PMOS metal gate according to claim 12, characterized in that: The material of the hard mask layer includes TiN; the material of the cap layer includes silicon oxide.