Monitoring graph and monitoring method in CMP (chemical mechanical polishing) process

Abstract

The invention discloses a monitoring graph and a monitoring method in a CMP (Chemical Mechanical Polishing) process, and belongs to the technical field of CMP processes, the monitoring graph in the CMP process comprises a substrate, an opening is formed in the substrate and used for arranging a bonding pad, the monitoring graph is arranged on the bonding pad, and the monitoring graph comprises a monitoring area which is provided with a base layer, the at least one lamination layer is laminated on the base layer; the influence areas are distributed on the two sides of the monitoring area, and active areas and polycrystalline silicon which are stacked in a specific structure are arranged in the influence areas. By providing the new monitoring graph and the corresponding monitoring method, as the monitoring area and the influence area are both of a double-layer structure, different dish-shaped defect conditions in the chip can be accurately judged, the dish-shaped defect problems in the chip can be monitored, and guidance is provided for CMP process optimization.

Description

Technical Field

[0001] The invention relates to the technical field of chemical mechanical polishing process, and in particular to a monitoring pattern and a monitoring method in a CMP process. Background Art

[0002] CMP stands for Chemical Mechanical Polishing, which is one of the key technologies for surface processing of semiconductor wafers. The industry uses chemical mechanical polishing models to predict post-CMP process hotspots so that hotspots can be processed before the mask is published. For the design side, the CMP model can find graphics that are unfriendly to process manufacturing in the layout design, and then propose solutions; for the manufacturing side, the CMP model can find weak locations in the process window, helping the process department to improve early warning or optimize the process.

[0003] like Figure 1 As shown in Figure 1, there are many cases in which the difference in thickness of different dielectric layers in the front layer (Dishing or step height) leads to defects in subsequent layers in the CMP process, such as the dish-shaped defects (dishing) generated when STI, ILD0 and MG are planarized using CMP. Figure 2-Figure 4 As shown, the current CMP process monitors the CMP process based on a single pad film thickness, lacks monitoring graphics that characterize the different structures of dishing in the chip, and is difficult to obtain data on the different structures of dishing in the chip, making it impossible to discover problems in a timely manner.

[0004] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide a monitoring pattern and a monitoring method in a CMP process to solve the problem of lack of monitoring patterns representing different structure dishing in a chip and difficulty in obtaining data of different structure dishing in a chip.

[0006] In order to solve the above technical problems, the present invention provides a monitoring pattern in a CMP process, comprising a substrate, the substrate having an opening for arranging a pad, the pad having a monitoring pattern arranged thereon, the monitoring pattern comprising:

[0007] A monitoring area having a base layer and at least one stacked layer stacked on the base layer;

[0008] The influence area is distributed on both sides of the monitoring area, and the active area and polysilicon stacked in a specific structure are arranged in the influence area.

[0009] Preferably, one stack is provided, and both the base layer and the stack are made of silicon oxide.

[0010] Preferably, one stack is provided, and both the base layer and the stack are made of silicon.

[0011] Preferably, the stack is provided with one, the base layer is made of silicon oxide material, and the stack is made of silicon material.

[0012] Preferably, the stack is provided with one, the base layer is made of silicon material, and the stack is made of silicon oxide material.

[0013] Preferably, the silicon material is polycrystalline silicon, or is an active region.

[0014] Preferably, a plurality of active regions and a plurality of polysilicon are arranged in the affected area, the plurality of active regions are arranged vertically in a first specific pattern, the plurality of polysilicon are arranged horizontally in a second specific pattern, and the plurality of polysilicon are stacked on top of the plurality of active regions.

[0015] Based on the same technical concept, the present disclosure also provides a monitoring method in a CMP process, which uses the monitoring graph in the CMP process as described above for monitoring.

[0016] Preferably, the method comprises the following steps:

[0017] Measure whether the pad thickness reaches the required range;

[0018] If the pad thickness reaches the required range, the monitoring pattern is measured to obtain dishing defect data;

[0019] DFM provides a layout structure distribution diagram within the chip;

[0020] Determine whether the parameter factor in the on-chip monitoring graphic reaches a specific range, and set the parameter factor according to the structure of the monitoring graphic, wherein the parameter factor includes an environmental factor, a previous layer factor, and a current layer factor, wherein the environmental factor is used to characterize the graphic structure of the impact area, the previous layer factor is used to characterize the lower layer graphic structure in the monitoring graphic, and the current layer factor is used to characterize the upper layer graphic structure in the monitoring graphic.

[0021] Preferably, the front layer factor includes the line width and spacing of the active region, and the current layer factor includes the line width and spacing of polysilicon.

[0022] In the monitoring pattern in the CMP process provided by the present invention, a single monitoring pattern is composed of an influence area and a monitoring area. The influence area is located on both sides of the monitoring area. The influence area can be designed differently according to actual conditions. The monitoring area can also be designed differently according to the characteristics of the front and back layers. The dishing conditions between different structures in the chip can be accurately judged, and the stacking effect between layers and the environmental impact effect can be characterized. A stacked structure is set in the monitoring area and the influence area. The dishing conditions between different structures in the chip can be accurately judged, and the stacking effect between layers and the environmental impact effect can be characterized. The defect problem of the later layer caused by the dishing of the previous layer can be reduced through monitoring, and data guidance can also be provided for the process optimization of CMP.

[0023] The monitoring method in the CMP process provided by the present invention and the monitoring pattern in the CMP process provided by the present invention belong to the same inventive concept. Therefore, the monitoring method in the CMP process provided by the present invention has at least all the advantages of the monitoring pattern in the CMP process provided by the present invention, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0025] Figure 1 It is a schematic diagram of the dish-shaped defect structure produced by CMP in the prior art;

[0026] Figure 2 It is the layout of the prior art and its electron microscope image;

[0027] Figure 3 It is the pad distribution layout in the FRAM measurement area in the prior art;

[0028] Figure 4 It is a CMP pad distribution layout in the prior art;

[0029] Figure 5 It is a flow chart of using CMP pad in the prior art;

[0030] Figure 6 It is a schematic diagram of the distribution of monitoring patterns within the measurement area of ​​the present invention;

[0031] Figure 7 is a monitoring diagram schematic diagram of the first embodiment of the present invention;

[0032] Figure 8 is a monitoring graphical diagram of the second embodiment of the present invention;

[0033] Fig. 9 is a monitoring graphical diagram of Embodiment 3 of the present invention;

[0034] Fig.10 is a monitoring graphical diagram of the fourth embodiment of the present invention;

[0035] Fig.11 is a flow chart of a monitoring method in a CMP provided by an embodiment of the present invention;

[0036] Fig.12 It is a distribution diagram of the proportion of monitoring graphics and in-chip cutting graphics provided by an embodiment of the present invention.

[0037] In the attached figure:

[0038] 100, monitoring area; 200, impact area; 300, active area; 400, polysilicon. DETAILED DESCRIPTION

[0039] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0040] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in a sense including "and / or", the term "several" is generally used in a sense including "at least one", and the term "at least two" is generally used in a sense including "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features. The term "proximal end" is usually the end close to the operator, and the term "distal end" is usually the end close to the patient. "One end" and "the other end" as well as "proximal end" and "distal end" usually refer to two corresponding parts, which include not only the endpoints. The terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of the two elements or the interaction relationship between the two elements. In addition, as used in the present invention, an element is arranged on another element, which usually only means that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and it cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, one element can be in any position such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0041] The inventors have found that in CMP, there are many problems that the thickness difference of different dielectric layers in the front layer leads to defects in the subsequent layers, such as Figure 2 The scanning electron microscope (SEM) image and the original design layout in the figure show that there are many defects in the SEM image. Generally, the detection of CMP process defects is done by opening the measurement area of ​​the substrate and depositing metal there to form a pad. The design layout is roughly as follows: Figure 3 As shown, the actual example Figure 4 As shown in FIG. 1 , the CMP process is often monitored by measuring the film thickness of the pad, such as Figure 5As shown, after measuring the film thickness of the pad, it is determined whether the value is within a specific range. If so, it is released for subsequent processes. Otherwise, it is reworked (RWK) or scrapped. This method of CMP monitoring based on the pad as a monitoring pattern has fewer characterization parameters for the pad and is difficult to provide data for dishing of different structures. In addition, the method of CMP process monitoring based on the pad has a single standard for measuring defects and cannot reflect problems in the process in a timely manner.

[0042] Based on this, the core idea of ​​the present invention is to provide a new monitoring graph and a corresponding monitoring method. Since both the monitoring area and the impact area have a double-layer structure, different dishing conditions within the chip can be accurately judged to monitor the dishing problem within the chip, provide analysis for related inline cases, and provide guidance for CMP process optimization.

[0043] For details, please refer to Figure 6-Figure 10 , which is a schematic diagram of an embodiment of the present invention. A monitoring pattern in a CMP process comprises a substrate, the substrate having an opening for arranging a pad, the pad having a monitoring pattern arranged thereon, the monitoring pattern comprising:

[0044] A monitoring area 100, which has a base layer and at least one stacked layer stacked on the base layer;

[0045] The influence area 200 is distributed on both sides of the monitoring area 100 , and an active area 300 and polysilicon 400 stacked in a specific structure are arranged in the influence area 200 .

[0046] like Figure 6-Figure 7 As shown, taking into account the multi-layer structure, environmental impact and structural changes in the CMP process, in order to reflect the influence of various factors, a single monitoring pattern (Testkey) is composed of an impact area 200 and a monitoring area 100. The impact area 200 is located on both sides of the monitoring area 100, a double-layer structure is arranged in the monitoring area 100, and a stacked active area 300 (AA, active area) and polysilicon 400 are arranged in the impact area 200. Different structural designs can be made for the impact area 200 according to actual conditions, and the monitoring area 100 can also be designed differently according to the characteristics of the front and back layers, for example, according to the layout design and arrangement around the area to be monitored. In the present disclosure, two layers are used as an example for explanation, and the actual situation can be expanded to multiple layers. The design between adjacent layers can refer to the following embodiments.

[0047] By setting up a stacked structure in the monitoring area 100 and the impact area 200, the dishing conditions between different structures in the chip can be accurately judged, and the stacking effect between layers and the environmental impact effect can be characterized. Through monitoring, the defect problem of the subsequent layer caused by the dishing of the previous layer can be reduced, and data guidance can also be provided for the process optimization of CMP.

[0048] Among them, Figure 6 The monitoring pattern (Tsk, Testkey) shown in the figure retains the pads of the prior art. A plurality of pads are arranged in a measurement area on the substrate, such as a Frame measurement area. The pads can be arranged in a rectangular array. A monitoring pattern is added to each pad. The outer dimensions of the newly designed monitoring pattern can generally be controlled within 15 μm, for example Figure 7-Figure 10 The width w can be within 15 μm, and the size of the pad is greatly reduced compared to the existing pad. The arrangement and size of the monitoring pattern can be adjusted according to actual conditions.

[0049] Exemplarily, a plurality of active areas 300 and a plurality of polysilicon 400 are arranged in the affected area 200 , the plurality of active areas 300 (AA, active area) are arranged vertically in a first specific pattern, the plurality of polysilicon 400 are arranged in a horizontal array in a second specific pattern, and the plurality of polysilicon 400 are stacked on top of the plurality of active areas 300 .

[0050] like Figure 7 As shown, two active areas 300 are arranged in the lower layer, the shape of the active area 300 is a rectangle with the X direction larger than the Y direction, and the active area 300 is arrayed along the Y direction; six polysilicon 400 are arranged in the upper layer, the shape of the polysilicon 400 is a rectangle with the Y direction larger than the X direction, and the polysilicon 400 is arrayed along the X direction, and the polysilicon 400 is stacked on the active area 300. The shape, array method and overlapping method of the polysilicon 400 and the active area 300 are not limited to this.

[0051] It can be understood that the polysilicon 400 is a type of silicon material, and the active region 300 can be regarded as a carrier layer having a region doped with N-type ions or P-type ions, and the carrier is made of silicon material.

[0052] The monitoring area 100 is, for example, a double-layer structure, which has a base layer and a stacked layer of the same or different materials. Please refer to the following different embodiments of the monitoring diagram.

[0053] [Example 1]

[0054] Please refer to Figure 7The base layer and the stacked layer are both made of silicon oxide. A stacked structure is arranged in the monitoring area 100. The base layer (not shown) and the stacked layer (not shown) may have the same or different shapes, but at least partially overlap. For example, the base layer and the stacked layer have the same shape, and the stacked layer completely covers the base layer.

[0055] The design principle of each monitoring graphic Testkey is Figure 7 The three parameter factors shown in the middle environment factor α, the front layer factor β and the current layer factor γ are interactively batched, the environment factor is used to characterize the graphic structure of the influence area, the front layer factor is used to characterize the lower graphic structure in the monitoring graphic, and the current layer factor is used to characterize the upper graphic structure in the monitoring graphic. In this embodiment, when the monitoring graphic is used for monitoring, the environment factor α is the graphic structure of the influence area 200 on both sides of the monitoring area 100; the front layer factor β is the spacing between the active areas 300 in the lower layer of the influence area 200; the current layer factor γ is the spacing between the polysilicon 400 in the upper layer of the influence area 200, and the spacing here is, for example, the maximum spacing.

[0056] [Example 2]

[0057] Please refer to Figure 8 , the base layer and the stacked layer are both made of silicon. A stacked structure is arranged in the monitoring area 100, and the silicon material is polysilicon 400, or an active area 300. In this embodiment, the base layer is the active area 300, and the stacked layer is polysilicon 400, and the shapes of the upper polysilicon 400 and the lower active area 300 can be different, but there is at least a partial overlap.

[0058] In this embodiment, when monitoring is performed using a monitoring pattern, the environmental factor α is the graphic structure of the influencing area 200 on both sides of the monitoring area 100; the front layer factor β is the line width of the active area 300 in the monitoring area 100; and the layer factor γ is the line width of the polysilicon 400 in the monitoring area 100, where the line width is, for example, the maximum line width.

[0059] [Example 3]

[0060] Please refer to Fig. 9 , the base layer is made of silicon oxide, and the stacked layer is made of silicon. The silicon material is polysilicon 400, or is the active region 300. In this embodiment, the base layer is made of silicon oxide (not shown), and the top stacked layer is polysilicon 400. The shapes of the upper polysilicon 400 and the lower silicon oxide can be different, but at least partially overlap.

[0061] In this embodiment, when monitoring is performed using a monitoring pattern, the environmental factor α is the graphic structure of the impact area 200 on both sides of the monitoring area 100; the front layer factor β is the spacing between the active areas 300 in the impact area 200; the layer factor γ is the line width of the polysilicon 400 in the monitoring area 100, where the line width is, for example, the maximum line width, and the spacing is, for example, the maximum spacing.

[0062] [Example 4]

[0063] Please refer to Fig.10 , the base layer is made of silicon, and the stacked layer is made of silicon oxide. The silicon material is polysilicon 400, or is an active area 300. In this embodiment, the base layer is made of silicon oxide (not shown), and the top stacked layer is the active area 300. The shapes of the upper active area 300 and the lower silicon oxide can be different, but at least there is a partial overlap.

[0064] In this embodiment, when monitoring is performed using a monitoring pattern, the environmental factor α is the graphic structure of the impact area 200 on both sides of the monitoring area 100; the front layer factor β is the line width of the active area 300 in the monitoring area 100; the layer factor γ is the spacing of the polysilicon 400 in the impact area 200, where the line width is, for example, the maximum line width, and the spacing is, for example, the maximum spacing.

[0065] Based on the same technical concept, such as Fig.11 As shown, the present disclosure provides a monitoring method in a CMP process, which uses the monitoring graph in the CMP process described above for monitoring. The method includes the following steps:

[0066] S1, measure whether the pad thickness reaches the required range.

[0067] S2, if the pad thickness reaches the required range, the monitoring pattern is measured to obtain dishing defect data. The monitoring pattern is measured by AFM (Atomic Force Microscope). If the pad thickness does not reach the required range, RWK or scrap.

[0068] S3, DFM (Design for Manufacturing) provides a distribution diagram of the on-chip layout structure.

[0069] S4, judging whether the parameter factor in the on-chip monitoring pattern reaches a specific range, setting the parameter factor according to the structure of the monitoring pattern, wherein the parameter factor includes an environmental factor α, a front layer factor β and a current layer factor γ, wherein the environmental factor α is used to characterize the pattern structure of the affected area, the front layer factor β is used to characterize the lower layer pattern structure in the monitoring pattern, and the current layer factor γ is used to characterize the upper layer pattern structure in the monitoring pattern. If the parameter factor reaches a specific range, it is released; if not, the process is optimized.

[0070] Exemplarily, the environmental factor α, the previous layer factor β and the current layer factor γ may be introduced into a specific calculation formula so that the output result meets a certain numerical range and the vehicle can be released.

[0071] like Figure 6-Figure 7 As shown, taking into account the multi-layer structure, environmental impact and structural changes in the CMP process, in order to reflect the influence of various factors, a single monitoring pattern (Testkey) is composed of an impact area 200 and a monitoring area 100. The impact area 200 is located on both sides of the monitoring area 100. A double-layer structure is arranged in the monitoring area 100, and a stacked active area 300 (AA) and polysilicon 400 are arranged in the impact area 200. Different structural designs can be made for the impact area 200 according to actual conditions, and the monitoring area 100 can also be designed differently according to the characteristics of the front and back layers.

[0072] The dimensions of the newly designed monitoring graphics can generally be controlled within 15μm, for example Figure 7-Figure 10 The width w can be within 15 μm, and the size of the pad is greatly reduced compared to the existing pad. The arrangement and size of the monitoring pattern can be adjusted according to actual conditions.

[0073] By setting up a stacked structure in the monitoring area 100 and the impact area 200, combined with the parameter factors of the design monitoring graphics, the dishing conditions between different structures in the chip can be accurately judged, and the stacking effects between layers and the environmental impact effects can be characterized. Through monitoring, the defect problem of the subsequent layers caused by the dishing of the previous layer can be reduced, and data guidance can also be provided for the process optimization of CMP.

[0074] In one embodiment, the front layer factor includes the line width and spacing of the active area 300, and the current layer factor includes the line width and spacing of the polysilicon 400. For details, please refer to the application of the parameter factors in the above embodiments 1 to 4, but the various parameter factors are not limited to the above description.

[0075] like Fig.12 As shown in the figure, the distribution diagram of the monitoring pattern and the cutting pattern within the chip shows that when the distribution of the monitoring pattern is consistent, there are differences in the layout distribution within the chip, so there are also different dishing defect distributions. Therefore, the monitoring pattern can effectively reflect the impact of the CMP process on different device designs, and the CMP process can be optimized for devices with different designs through the monitoring pattern.

[0076] The present invention proposes a monitoring pattern and a monitoring method in a CMP process, which are used to monitor the dishing problem in a chip. The monitoring pattern is designed according to factors such as the multi-layer structure of a chip layout, environmental impact and layout structure. The design principle of each monitoring pattern is the interactive batching of key geometric factors. A single monitoring pattern is composed of an influence area and a monitoring area. The influence area is located on both sides of the monitoring area. The influence area can be designed differently according to actual conditions. The monitoring area can also be designed differently according to the characteristics of the front and back layers. The dishing situation between different structures in the chip can be accurately judged, and the stacking effect between layers and the environmental impact effect can be characterized. In implementation, the monitoring method is designed based on the parameter factors of the image structure in the monitoring area and the influence area. When the parameter factors meet the required range, the method is released. When they do not meet the range, the CMP process flow is re-optimized. Monitoring can reduce the defect problem of the back layer caused by the dishing of the front layer, and can also provide data guidance for the process optimization of CMP.

[0077] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A monitoring pattern in a CMP process, comprising a substrate having an opening for arranging a pad, characterized in that: A monitoring pattern is arranged on the pad, and the monitoring pattern includes: A monitoring area having a base layer and at least one stacked layer stacked on the base layer; The influence area is distributed on both sides of the monitoring area, and the active area and polysilicon stacked in a specific structure are arranged in the influence area.

2. The monitoring pattern in the CMP process according to claim 1, characterized in that: The stack is provided with one, and the base layer and the stack are both made of silicon oxide.

3. The monitoring pattern in the CMP process according to claim 1, characterized in that: The stack is provided with one, and the base layer and the stack are both made of silicon.

4. The monitoring pattern in the CMP process according to claim 1, characterized in that: The stack is provided with one, the base layer is made of silicon oxide, and the stack is made of silicon.

5. The monitoring pattern in the CMP process according to claim 1, characterized in that: The stack is provided with one, the base layer is made of silicon material, and the stack is made of silicon oxide material.

6. The monitoring pattern in the CMP process according to any one of claims 3 to 5, characterized in that: The silicon material is polysilicon, or is an active region.

7. The monitoring pattern in the CMP process according to claim 1, characterized in that: A plurality of active regions and a plurality of polysilicones are arranged in the affected area. The plurality of active regions are arranged vertically in a first specific pattern, the plurality of polysilicones are arranged horizontally in a second specific pattern, and the plurality of polysilicones are stacked on top of the plurality of active regions.

8. A monitoring method in a CMP process, characterized in that: The monitoring is performed using the monitoring pattern in the CMP process as described in any one of claims 1 to 7.

9. The monitoring method in the CMP process according to claim 8, characterized in that: The following steps are involved: Measure whether the pad thickness reaches the required range; If the pad thickness reaches the required range, the monitoring pattern is measured to obtain dishing defect data; DFM provides a distribution diagram of the on-chip layout structure; Determine whether the parameter factor in the on-chip monitoring graphic reaches a specific range, and set the parameter factor according to the structure of the monitoring graphic, wherein the parameter factor includes an environmental factor, a previous layer factor, and a current layer factor, wherein the environmental factor is used to characterize the graphic structure of the impact area, the previous layer factor is used to characterize the lower layer graphic structure in the monitoring graphic, and the current layer factor is used to characterize the upper layer graphic structure in the monitoring graphic.

10. The monitoring method in the CMP process according to claim 9, characterized in that: The front layer factors include the line width and spacing of the active region, and the current layer factors include the line width and spacing of polysilicon.

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