Heterojunction bipolar transistor

Abstract

The invention discloses a heterojunction bipolar transistor, and belongs to the technical field of semiconductors. The heterojunction bipolar transistor comprises a collector electrode; the base electrode is positioned on one side of the collector electrode; the emitting electrode is positioned on one side, deviating from the collecting electrode, of the base electrode; wherein the base electrode comprises a superlattice structure, the band gap of the base electrode is smaller than the band gap of the emitter electrode, the conduction band offset between the base electrode and the emitter electrode is smaller than the target conduction band offset, and the valence band offset between the base electrode and the emitter electrode is larger than the first target valence band offset. The valence band offset between the base and the collector is greater than a second target valence band offset. The electron injection efficiency of the emitter can be improved, the overall power consumption of the device is reduced, injection of holes from the base to the collector is effectively prevented, and the performance of the device is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a heterojunction bipolar transistor. Background Art

[0002] At present, the base and collector of heterojunction bipolar transistors are mainly GaAs, and the emitter is mainly InGaP. Since the emitter InGaP has a higher bandgap energy than the base GaAs, a potential barrier peak appears at the interface between the emitter and the base, which hinders the injection of electrons from the emitter to the base, resulting in high device power consumption. In addition, the base and the collector form a homojunction, which cannot effectively prevent the injection of holes from the base to the collector, further affecting the performance of the device. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a heterojunction bipolar transistor, which can improve the electron injection efficiency of the emitter, reduce the overall power consumption of the device, and effectively prevent the injection of holes from the base to the collector, thereby improving the performance of the device.

[0004] In a first aspect, the present application provides a heterojunction bipolar transistor, comprising:

[0005] collector;

[0006] A base electrode, located at one side of the collector electrode;

[0007] an emitter, located at a side of the base away from the collector;

[0008] Wherein, the base includes a superlattice structure, the band gap of the base is smaller than the band gap of the emitter, the conduction band offset between the base and the emitter is smaller than the target conduction band offset, the valence band offset between the base and the emitter is greater than the first target valence band offset, and the valence band offset between the base and the collector is greater than the second target valence band offset.

[0009] According to the heterojunction bipolar transistor of the present application, a superlattice structure is set in the base so that the conduction band offset between the base and the emitter is smaller than the target conduction band offset, so as to reduce the conduction band discontinuity at the interface between the base and the emitter, and effectively reduce the overall power consumption of the device. The valence band offset between the base and the emitter is greater than the first target valence band offset, so as to increase the valence band discontinuity at the interface between the base and the emitter, and improve the electron injection efficiency of the emitter. The valence band offset between the base and the collector is greater than the second target valence band offset, so as to increase the valence band discontinuity at the interface between the base and the collector, effectively prevent the injection of holes from the base to the collector, and further improve the device performance.

[0010] According to one embodiment of the present application, the superlattice structure includes first semiconductor layers and second semiconductor layers that are alternately arranged.

[0011] According to one embodiment of the present application, the superlattice structure is a type I superlattice, and the band gap of the second semiconductor layer is smaller than the band gap of the first semiconductor layer.

[0012] According to one embodiment of the present application, in the direction toward the collector, the thickness of the second semiconductor layer gradually decreases, and / or the material composition in the second semiconductor layer gradually decreases or increases, and the conduction band of the base gradually decreases.

[0013] According to an embodiment of the present application, the film layer on the side of the superlattice structure close to the collector is the first semiconductor layer, and the collector is made of the same material as the first semiconductor layer.

[0014] According to one embodiment of the present application, the superlattice structure is a type II superlattice, the first semiconductor layer is an electron potential well layer, and the second semiconductor layer is a hole potential well layer.

[0015] According to one embodiment of the present application, in the direction toward the collector, the thickness of the first semiconductor layer gradually increases, and / or the material composition in the first semiconductor layer gradually decreases or increases, and the conduction band of the base gradually decreases.

[0016] According to an embodiment of the present application, the thickness of the adjacent first semiconductor layer and the second semiconductor layer is 10 to 70 angstroms, and the number of alternations is 5 to 25 times.

[0017] According to one embodiment of the present application, the first semiconductor layer and the second semiconductor layer respectively include any one of GaAs, AlSb, InGaAs, GaAsSb, InGaAsSb and AlGaAsSb, and the materials of the first semiconductor layer and the second semiconductor layer are different, or the materials of the first semiconductor layer and the second semiconductor layer are the same but have different material compositions.

[0018] According to an embodiment of the present application, the emitter includes any one of InGaP, AlGaAs, AlPSb, InGaAsP, InAlGaP and AlGaPSb, and the collector includes GaAs.

[0019] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0020] By setting a super crystal structure in the base, the conduction band offset between the base and the emitter is smaller than the target conduction band offset, so as to reduce the conduction band discontinuity at the interface between the base and the emitter, and effectively reduce the overall power consumption of the device; the valence band offset between the base and the emitter is larger than the first target valence band offset, so as to increase the valence band discontinuity at the interface between the base and the emitter, and improve the electron injection efficiency of the emitter; the valence band offset between the base and the collector is larger than the second target valence band offset, so as to increase the valence band discontinuity at the interface between the base and the collector, effectively prevent the injection of holes from the base to the collector, and further improve the device performance;

[0021] Furthermore, the superlattice structure in the base can significantly improve the mobility of holes in the base, reduce the resistance of the base, thereby increasing the maximum oscillation frequency, and the increased potential barrier between the base and the collector helps to reduce charge storage and further increase the maximum oscillation frequency; the superlattice structure in the base can not only promote the diffusion transmission of minority carriers, but also allow electrons to enter through the quantum tunneling mechanism, thereby increasing the storage concentration of minority carriers in the base, and the high-density minority carrier storage can rapidly increase the collector current, thereby effectively reducing the on-state voltage of the base and emitter.

[0022] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0024] Figure 1 This is one of the structural schematic diagrams of the heterojunction bipolar transistor provided in the embodiments of the present application;

[0025] Figure 2 This is the second structural schematic diagram of the heterojunction bipolar transistor provided in the embodiment of the present application;

[0026] Figure 3 This is one of the energy band structure schematic diagrams of the heterojunction bipolar transistor provided in the embodiments of the present application;

[0027] Figure 4 This is the second schematic diagram of the energy band structure of the heterojunction bipolar transistor provided in the embodiment of the present application;

[0028] Figure 5 This is the third structural schematic diagram of the heterojunction bipolar transistor provided in the embodiment of the present application. DETAILED DESCRIPTION

[0029] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0030] Heterojunction Bipolar Transistor (HBT) uses at least two different semiconductor materials to construct the emitter and base, forming a unique heterostructure. The key advantage of HBT is that its emitter efficiency is mainly affected by the difference in the bandgap width of the materials, rather than the traditional doping ratio constraints. This feature greatly improves the flexibility and performance of transistor design. For example, in the InGaP / GaAs HBT structure (the emitter is InGaP / GaAs), the emitter efficiency is mainly affected by the difference in the bandgap width of the materials, rather than the traditional doping ratio constraints. 0.48 Ga 0.52 P, base is GaAs), In 0.48 Ga 0.52 The lattice constants between P and GaAs are highly matched, and the difference in the bandgap width is about 0.5eV, which makes wide-bandgap emitter heterojunction transistors possible. This structural design makes the barrier encountered by the diffusion of holes in the base to the emitter higher than the diffusion of electrons from the emitter to the base, thereby significantly increasing the injection ratio of electrons to holes, and further greatly improving the current gain of the transistor. By precisely controlling the heavy doping and thickness of the base, the time for carriers to transit the base can be effectively reduced, which helps to increase the cutoff frequency of the device, enabling it to operate at a higher frequency to meet the needs of high-performance applications.

[0031] Heterojunction bipolar transistors can be divided into single heterojunction bipolar transistors (SHBT) and double heterojunction bipolar transistors (DHBT) according to their structural characteristics. If there is a heterojunction structure between the emitter and the base, and the base and collector are made of the same material, the transistor is a single heterojunction bipolar transistor. If the materials of the emitter, base, and collector are all different, so that both the emitter-base and base-collector form heterojunction structures, the transistor is a double heterojunction bipolar transistor. A significant advantage of the double heterojunction bipolar transistor is that the heterojunction between the base and the collector can effectively prevent the injection of holes from the base region to the collector region. This mechanism helps to reduce the saturated storage charge density and accelerate the shutdown speed of the device under the saturation region bias, which is crucial to improving the response speed of the device and reducing power consumption. In addition, the design of this structure also helps to increase the breakdown voltage of the device and enhance the voltage tolerance of the device.

[0032] In the related art, the base and collector in a single heterojunction bipolar transistor are mainly GaAs, and the emitter is mainly InGaP. The emitter (InGaP) has a higher bandgap energy than the base (GaAs), resulting in a peak discontinuity (ΔEc) at the bottom of the conduction band at the interface between the base and the emitter, which affects the performance of the device.

[0033] The heterojunction bipolar transistor provided by the embodiments of the present application is described below with reference to the accompanying drawings.

[0034] Figure 1 and Figure 2 A schematic diagram of the structure of a heterojunction bipolar transistor provided in an embodiment of the present application.

[0035] like Figure 1 and Figure 2 As shown, the heterojunction bipolar transistor includes a collector 1, a base 2 and an emitter 3. The base 2 is located on one side of the collector 1, and the emitter 3 is located on the side of the base 2 away from the collector 1, and the band gap of the base 2 is smaller than the band gap of the emitter 3. Among them, the collector 1 is used to collect electrons injected by the base 2, which has a decisive influence on the efficiency of the device. The emitter 3 is used to inject electrons into the base 2. The base 2 has a first doping type, and the collector 1 and the emitter 3 may have a second doping type, and the first doping type is different from the second doping type. For example, the first doping type is p-type doping, and the second doping type is n-type doping.

[0036] The base 2 includes a superlattice structure. The superlattice structure can be obtained by lattice matching growth, superlattice growth or component gradient growth technology. The superlattice structure is an artificial periodic structure formed by alternating stacking of extremely thin material layers, and its unique physical properties (such as effective bandwidth, band gap and effective mass, etc.) can be precisely controlled by adjusting the thickness of the constituent material layers.

[0037] By adjusting the superlattice structure in the base 2, the conduction band and valence band of the base 2 can be adjusted, and the band gap of the base 2 can be reduced, so that the conduction band offset between the base 2 and the emitter 3 is smaller than the target conduction band offset, the valence band offset between the base 2 and the emitter 3 is larger than the first target valence band offset, and the valence band offset between the base 2 and the collector 3 is larger than the second target valence band offset.

[0038] The target conduction band offset can be less than or equal to the conduction band offset between the emitter (GaInP) and the base (GaAs) in the related art (e.g., 0.2 eV). By adjusting the superlattice structure in the base 2, the conduction band of the base 2 can be adjusted so that the conduction band of the base 2 is close to the conduction band of the emitter 3, or even the conduction band of the base 2 is completely aligned with the conduction band of the emitter 3, that is, the conduction band offset between the base 2 and the emitter 3 is less than the target conduction band offset, and compared with the related art, the conduction band offset between the base 2 and the emitter 3 is reduced, that is, the conduction band discontinuity at the interface between the base 2 and the emitter 3 is reduced, thereby reducing or even eliminating the potential barrier spike, and effectively reducing the overall power consumption of the device.

[0039] The first target valence band offset can be greater than or equal to the valence band offset between the emitter (GaInP) and the base (GaAs) in the related art (e.g., 0.3 eV). By adjusting the superlattice structure in the base 2, the valence band of the base 2 can be adjusted so that the valence band offset between the base 2 and the emitter 3 is greater than the first target valence band offset, which increases the valence band offset between the base 2 and the emitter 3 compared to the related art, that is, increases the valence band discontinuity at the interface between the base 2 and the emitter 3, and improves the electron injection efficiency of the emitter 3.

[0040] The second target valence band offset can be greater than or equal to the valence band offset between the base (GaAs) and the collector (GaAs) in the related art (such as 0eV). By adjusting the superlattice structure in the base 2, the valence band of the base 2 can be adjusted so that the valence band offset between the base 2 and the collector 1 is greater than the second target valence band offset. Compared with the related art, the valence band offset between the base 2 and the collector 1 is increased, that is, the valence band offset at the interface between the base 2 and the collector 1 is increased, which effectively prevents the injection of holes from the base 2 to the collector 1, and further improves the device performance.

[0041] In addition, the superlattice structure in the base 2 can significantly improve the mobility of holes in the base 2, reduce the resistance of the base 2, and thus increase the maximum oscillation frequency (fmax). At the same time, the potential barrier between the base 2 and the collector 1 increases, which helps to reduce charge storage and further increase the maximum oscillation frequency. Moreover, the superlattice structure in the base 2 can not only promote the diffusion transmission of minority carriers, but also allow electrons to enter through the quantum tunneling mechanism, thereby increasing the storage concentration of minority carriers in the base 2, and the high-density minority carrier storage can quickly increase the collector 1 current, thereby effectively reducing the on-state voltage of the base 2 and the emitter 3.

[0042] In some embodiments, Figure 1 and Figure 2As shown, the heterojunction bipolar transistor may further include a substrate 4, which is located on the side of the collector 1 away from the base 2. The substrate 4 provides a stable physical support and electrical connection for the entire device. The selection of the substrate 4 is conducive to achieving high stability and excellent electrical performance of the device. Among them, the substrate 4 may include GaAs and the like.

[0043] In some embodiments, Figure 1 and Figure 2 As shown, the heterojunction bipolar transistor may further include a sub-collector contact layer 5, which is located between the substrate 4 and the collector 1. The sub-collector contact layer 5 is used to optimize the electrical contact performance of the device and is a key factor in improving the overall electrical performance of the device. The sub-collector contact layer 5 may include GaAs or the like.

[0044] In some embodiments, Figure 1 and Figure 2 As shown, the heterojunction bipolar transistor may further include a first emitter capping layer 6 and a second emitter capping layer 7, wherein the first emitter capping layer 6 is located on the side of the emitter 3 away from the base 2, and the second emitter capping layer 7 is located on the side of the first emitter capping layer 6 away from the emitter 3. The first emitter capping layer 6 and the second emitter capping layer 7 are used to optimize the electrical contact performance of the device, and play an important role in reducing the contact resistance and improving the stability and performance of the device. Among them, the first emitter capping layer 6 and the second emitter capping layer 7 respectively include at least one of GaAs and InGaAs.

[0045] In some embodiments, the superlattice structure in the base 2 includes alternatingly arranged first semiconductor layers 21 and second semiconductor layers 22 , that is, there is a second semiconductor layer 22 between any two adjacent first semiconductor layers 21 , and there is a first semiconductor layer 21 between any two adjacent second semiconductor layers 22 .

[0046] In some embodiments, the first semiconductor layer 21 and the second semiconductor layer 22 include any one of GaAs, AlSb, InGaAs, GaAsSb, InGaAsSb and AlGaAsSb, respectively. The materials of the first semiconductor layer 21 and the second semiconductor layer 22 may be the same or different. In the case where the materials of the first semiconductor layer 21 and the second semiconductor layer 22 are the same, the material components in the first semiconductor layer 21 and the second semiconductor layer 22 are different. For example, both the first semiconductor layer 21 and the second semiconductor layer 22 may be GaAsSb, but the As component and the Sb component in the first semiconductor layer 21 and the second semiconductor layer 22 are different.

[0047] In some embodiments, the superlattice structure in the base 2 can be a type I superlattice or a type II superlattice. Superlattices can be divided into multiple types of superlattices according to the type of heterojunction formed. Among them, the conduction band and valence band of the type I superlattice are formed by the semiconductor material of the same layer, so that electrons and holes are confined in the same semiconductor layer. The conduction band and valence band of the type II superlattice are formed in different layers, so that electrons and holes are confined in different semiconductor layers.

[0048] In the case where the superlattice structure in the base 2 is an I-type superlattice, the band gap of the second semiconductor layer 22 is smaller than the band gap of the first semiconductor layer 21. The first semiconductor layer 21 can be the same material as the base in the related art. The band gap of the second semiconductor layer 22 is smaller than the band gap of the first semiconductor layer 21, that is, the band gap of the second semiconductor layer 22 is smaller than the band gap of the base in the related art. The energy band structure 21a formed by the first semiconductor layer 21 in the base 2 and the energy band structure 22a formed by the second semiconductor layer 22 are as shown in FIG. Figure 3 As shown, it can be seen that the base 2 includes a superlattice structure formed by alternating first semiconductor layers 21 and second semiconductor layers 22, which reduces the band gap of the base 2 compared to the related art.

[0049] The first semiconductor layer 21 may include GaAs, and the second semiconductor layer 22 may include In x Ga 1-x As and In z Ga 1-z As m Sb 1-m Any one of the above, wherein x is 0 to 0.7, z is 0 to 1, and m is 0.35 to 1.

[0050] When the superlattice structure in the base 2 is a type I superlattice, by adjusting the film thickness and / or material composition of the second semiconductor layer 22 in the superlattice structure, the conduction band of the base 2 can be gradually reduced in the direction from the emitter 3 toward the collector 1, thereby generating a built-in electric field to assist electron transport and improve device performance.

[0051] In the direction toward the collector electrode 1, the thickness of the second semiconductor layer 22 gradually decreases, and the conduction band of the base electrode 2 gradually decreases. The thickness of the first semiconductor layer 21 may remain unchanged.

[0052] In the direction toward the collector 1, the material composition in the second semiconductor layer 22 gradually decreases or increases, and the conduction band of the base 2 gradually decreases. The material composition in the second semiconductor layer 22 is different, and the change trend of the material composition is different. For example, the second semiconductor layer 22 includes InGaAs. In the direction toward the collector 1, the In component in the second semiconductor layer 22 gradually decreases or the Ga component gradually increases, so that the conduction band of the base 2 gradually decreases.

[0053] In the direction toward the collector electrode 1 , the thickness of the second semiconductor layer 22 gradually decreases, and the material composition in the second semiconductor layer 22 gradually decreases or increases, and the conduction band of the base electrode 2 gradually decreases.

[0054] In this embodiment, the base 2 includes an I-type superlattice, and a narrow bandgap material (i.e., the second semiconductor layer 22) is used to reduce the bandgap of the base 2 by appropriately adjusting the thickness and / or material composition of the second semiconductor layer 22 while maintaining no lattice relaxation with the substrate 4, so as to optimize device performance.

[0055] In the case where the superlattice structure in the base 2 is a type I superlattice, such as Figure 1 As shown, the film layer on the side of the superlattice structure close to the collector 1 in the base 2 is the first semiconductor layer 21, that is, the bottom layer of the superlattice structure is the first semiconductor layer 21. The collector 1 and the first semiconductor layer 21 are made of the same material. For example, the collector 1 and the first semiconductor layer 21 both include GaAs. The thickness of the first semiconductor layer 21 can be relatively thin, such as the first semiconductor layer 21 is less than 10nm. The film layer on the side of the superlattice structure close to the emitter 1 can also be the first semiconductor layer 21, that is, the top layer of the superlattice structure is also the first semiconductor layer 21.

[0056] In this embodiment, while increasing the valence band discontinuity at the interface between the base 2 and the collector 1 and effectively preventing holes from being injected from the base 2 to the collector 1, the first semiconductor layer 21 is made of the same material as the collector 1, so that the base 2 and the collector 1 exhibit homojunction characteristics, avoiding the conduction band discontinuity at the interface between the base 2 and the collector 1, effectively reducing the potential current blocking effect between the base 2 and the collector 1, and thereby significantly reducing the residual voltage (Voffset) of the transistor.

[0057] When the superlattice structure in the base 2 is a type II superlattice, the first semiconductor layer 21 is an electron potential well layer, and the second semiconductor layer 22 is a hole potential well layer, that is, the electron potential well layer and the hole potential well layer are alternately arranged between the collector 1 and the emitter 3. In the type II superlattice, electrons and holes are respectively confined in different quantum wells on both sides of the heterointerface, and this structure allows the effective band gap to be flexibly adjusted by adjusting the period thickness.

[0058] The first semiconductor layer 21 (i.e., the electron potential well layer) may include any one of GaAs and InGaAsSb, and the second semiconductor layer 22 (i.e., the hole potential well layer) may include any one of AlSb, GaAsSb, and AlGaAsSb, etc. For example, the type II superlattice in the base 2 may be a combination of GaAs / AlSb, GaAs / GaAsSb, or InGaAsSb / AlGaAsSb.

[0059] The energy band structure 21a formed by the first semiconductor layer 21 in the base 2 and the energy band structure 22a formed by the second semiconductor layer 22 are as shown in FIG. Figure 4 As shown. It can be seen that the base 2 includes a superlattice structure composed of the first semiconductor layer 21 and the second semiconductor layer 22 arranged alternately, which reduces the band gap of the base 2 compared with the related art. By adjusting the thickness of the first semiconductor layer 21 and the second semiconductor layer 22, the conduction band of the base 2 can be completely aligned with the conduction band of the emitter 3, thereby optimizing the electron transport performance.

[0060] In the case where the superlattice structure in the base 2 is a type II superlattice, by adjusting the film thickness and / or material composition of the first semiconductor layer 21 (i.e., the electron potential well layer) in the superlattice structure, the conduction band of the base 2 can be adjusted, thereby generating a built-in electric field to assist electron transport and improve device performance. By adjusting the film thickness and / or material composition of the second semiconductor layer 22 (i.e., the hole potential well layer) in the superlattice structure, the valence band of the base 2 can be adjusted to generate a higher valence band offset at the interface between the emitter 3 and the base 2 and at the interface between the base 2 and the collector 1, further optimizing the performance of the device.

[0061] In the direction toward the collector electrode 1, the thickness of the first semiconductor layer 21 gradually increases, and the conduction band of the base electrode 2 gradually decreases. The thickness of the second semiconductor layer 22 may remain unchanged.

[0062] In the direction toward the collector 1, the material composition in the first semiconductor layer 21 gradually decreases or increases, and the conduction band of the base 2 gradually decreases. The material composition in the first semiconductor layer 21 is different, and the change trend of the material composition is different.

[0063] In the direction toward the collector electrode 1 , the thickness of the first semiconductor layer 21 gradually increases, and the material composition in the first semiconductor layer 21 gradually decreases or increases, and the conduction band of the base electrode 2 gradually decreases.

[0064] In this embodiment, the base 2 includes a type II superlattice, and the band gap adjustment of the base 2 is more flexible. By adjusting the film thickness and / or material composition in the superlattice structure, the band gap of the base 2 can be reduced while the conduction band of the base 2 is completely aligned with the conduction band of the emitter 3 to effectively solve the electron transport problem and significantly improve the device performance.

[0065] When the superlattice structure in the base 2 is a type II superlattice, the film layer on the side of the superlattice structure close to the collector 1 may be the second semiconductor layer 22, and the materials of the second semiconductor layer 22 and the collector 1 may be different. The formation of a type II energy band arrangement at the interface between the base 2 and the collector 1 does not require a GaAs thin layer.

[0066] In some embodiments, the thickness of the adjacent first semiconductor layer 21 and the second semiconductor layer 22 is 10 to 70 angstroms, and the number of alternations is 5 to 25. In the superlattice structure in the base 2, every two film layers (a first semiconductor layer 21 and a second semiconductor layer 22) constitute a superlattice layer, the thickness of the superlattice layer is 10 to 70 angstroms, and the number of layers of the superlattice layer is 5 to 25.

[0067] In some embodiments, the emitter 3 may include any one of InGaP, AlGaAs, AlPSb, InGaAsP, InAlGaP and AlGaPSb.

[0068] In some embodiments, the emitter 3 may include a superlattice structure. By adjusting the superlattice parameters of the superlattice structure in the emitter 3, the conduction band and the valence band of the emitter 3 may be adjusted, the band gap of the emitter 3 may be increased, the conduction band offset between the base 2 and the emitter 3 may be further reduced, that is, the conduction band discontinuity at the interface between the base 2 and the emitter 3 may be further reduced, and the valence band offset between the base 2 and the emitter 3 may be further increased, that is, the valence band discontinuity at the interface between the base 2 and the emitter 3 may be further increased.

[0069] In some embodiments, Figure 5 As shown, the superlattice structure in the emitter 3 includes third semiconductor layers 31 and fourth semiconductor layers 32 arranged alternately, that is, there is a fourth semiconductor layer 32 between any two adjacent third semiconductor layers 31, and there is a third semiconductor layer 31 between any two adjacent fourth semiconductor layers 32.

[0070] In some embodiments, the third semiconductor layer 31 and the fourth semiconductor layer 32 include any one of GaAs, InGaP, AlGaAs, AlPSb, InGaAsP, InAlGaP and AlGaPSb respectively. The materials of the third semiconductor layer 31 and the fourth semiconductor layer 32 may be the same or different. In the case where the materials of the third semiconductor layer 31 and the fourth semiconductor layer 32 are the same, the material components in the third semiconductor layer 31 and the fourth semiconductor layer 32 are different. For example, the third semiconductor layer 31 and the fourth semiconductor layer 32 may both be InGaP, but the In component and the Ga component in the third semiconductor layer 31 and the fourth semiconductor layer 32 are different.

[0071] In some embodiments, the superlattice structure in the emitter 3 may be a type I superlattice or a type II superlattice.

[0072] In the case where the superlattice structure in the emitter 3 is an I-type superlattice, the band gap of the fourth semiconductor layer 32 is greater than the band gap of the third semiconductor layer 31. The third semiconductor layer 31 may be made of the same material as the first semiconductor layer 21. The band gap of the fourth semiconductor layer 32 is greater than the band gap of the third semiconductor layer 31, that is, the band gap of the fourth semiconductor layer 32 is greater than the band gap of the first semiconductor layer 21.

[0073] The third semiconductor layer 31 may include GaAs, and the fourth semiconductor layer 32 may include any one of InGaP, AlGaAs, AlPSb, InGaAsP, InAlGaP, AlGaPSb and the like.

[0074] Under the premise of maintaining good material matching, this embodiment increases the band gap of the emitter 3 , improves the electron injection efficiency, and enhances the performance of the emitter 3 .

[0075] When the superlattice structure in the emitter 3 is a type I superlattice, by adjusting the film thickness and / or material composition of the fourth semiconductor layer 32 in the superlattice structure in the emitter 3, the valence band of the emitter 3 can be gradually increased in the direction toward the base 2, so as to produce a higher valence band offset at the interface between the emitter 3 and the base 2, thereby optimizing the device performance.

[0076] In the direction toward the base electrode 2, the thickness of the fourth semiconductor layer 32 gradually increases, and the valence band of the emitter electrode 3 gradually increases. The thickness of the third semiconductor layer 31 may remain unchanged.

[0077] In the direction toward the base 2, the material composition in the fourth semiconductor layer 32 gradually decreases or increases, and the valence band of the emitter 3 gradually increases. Among them, the material composition in the fourth semiconductor layer 32 is different, and the change trend of the material composition is different. For example, the fourth semiconductor layer 32 includes InGaP. In the direction toward the base 2, the In component in the fourth semiconductor layer 32 gradually decreases or the Ga component gradually increases, so that the valence band of the emitter 3 gradually increases.

[0078] In the direction toward the base 2 , the thickness of the fourth semiconductor layer 32 gradually increases, and the material composition in the fourth semiconductor layer 32 gradually decreases or increases, and the valence band of the emitter 3 gradually increases.

[0079] In the case where the superlattice structure in the emitter 3 is a type I superlattice, as Figure 5As shown, the film layer of the superlattice structure in the emitter 3 close to the base 2 is the third semiconductor layer 31, that is, the bottom layer of the superlattice structure in the emitter 3 is the third semiconductor layer 31. The film layer of the superlattice structure in the base 2 close to the emitter 3 is the first semiconductor layer 21, and the material of the first semiconductor layer 21 and the third semiconductor layer 31 are the same. For example, the first semiconductor layer 21 and the third semiconductor layer 31 both include GaAs. The thickness of the first semiconductor layer 21 and the third semiconductor layer 31 can be relatively thin, such as the thickness of the first semiconductor layer 21 and the third semiconductor layer 31 are less than 100 angstroms respectively. In addition, the film layer of the superlattice structure in the emitter 3 facing away from the base 2 can also be the third semiconductor layer 31, that is, the topmost layer of the superlattice structure in the emitter 3 is also the third semiconductor layer 31.

[0080] In this embodiment, the third semiconductor layer 31 is made of the same material as the first semiconductor layer 21, so that the emitter 3 and the base 2 present homojunction characteristics, effectively eliminating the potential spike at the interface between the emitter 3 and the base 2, thereby meeting the requirements of high current gain at low offset voltage and low current levels. In addition, since the first semiconductor layer 21 and the third semiconductor layer 31 are very thin (such as GaAs thin layers), the emitter 3 will be completely depleted at low base-emitter voltage levels, and the confinement effect of holes is maintained by the large valence band discontinuity of the emitter heterojunction. Electrons are transmitted in the emitter part by resonant tunnel injection, and tunnel electrons from the emitter 3 will pass through the third semiconductor layer 31 and easily enter the base 2.

[0081] When the superlattice structure in the emitter 3 is a type II superlattice, the third semiconductor layer 31 is an electron potential well layer, and the fourth semiconductor layer 32 is a hole potential well layer, that is, the electron potential well layer and the hole potential well layer are alternately arranged on the side of the base 2 away from the collector 1. In the type II superlattice, electrons and holes are respectively confined in different quantum wells on both sides of the heterogeneous interface, and this structure allows the effective band gap to be flexibly adjusted by adjusting the period thickness.

[0082] The third semiconductor layer 31 (i.e., the electron potential well layer) may include any one of GaAs, InGaP, AlGaAs, AlPSb, InGaAsP, InAlGaP, and AlGaPSb, etc., and the fourth semiconductor layer 32 (i.e., the hole potential well layer) may include any one of GaAs, InGaP, AlGaAs, AlPSb, InGaAsP, InAlGaP, and AlGaPSb, etc. The third semiconductor layer 31 and the fourth semiconductor layer 32 satisfy the strain with a net effect of zero and can be grown very thick.

[0083] By adjusting the thickness of any material film layer constituting the superlattice structure in the emitter 3, the band gap of the emitter 3 can be changed between the lowest valence band and the highest conduction band of the third semiconductor layer 31 and the fourth semiconductor layer 32, that is, the II-type superlattice can adjust the band gap of the emitter 3 more flexibly.

[0084] In the case where the superlattice structure in the emitter 3 is a type II superlattice, by adjusting the film thickness and / or material composition of the third semiconductor layer 31 (i.e., the electron potential well layer) in the superlattice structure in the emitter 3, the conduction band of the emitter 3 can be adjusted in the direction toward the base 2 to optimize the device performance. By adjusting the film thickness and / or material composition of the fourth semiconductor layer 32 (i.e., the hole potential well layer) in the superlattice structure in the emitter 3, the valence band of the emitter 3 can be adjusted to generate a higher valence band offset at the interface between the emitter 3 and the base 2, further optimizing the device performance.

[0085] In the direction toward the base electrode 2, the thickness of the fourth semiconductor layer 32 gradually increases, and the valence band of the emitter electrode 3 gradually increases. The thickness of the third semiconductor layer 31 may remain unchanged.

[0086] In the direction toward the base 2, the material composition of the fourth semiconductor layer 32 gradually decreases or increases, and the valence band of the emitter 3 gradually increases. The material composition in the fourth semiconductor layer 32 is different, and the variation trend of the material composition is different.

[0087] In the direction toward the base 2 , the thickness of the fourth semiconductor layer 32 gradually increases, and the material composition of the fourth semiconductor layer 32 gradually decreases or increases, and the valence band of the emitter 3 gradually increases.

[0088] In the case where the superlattice structure in the emitter 3 is a type II superlattice, the film layer of the superlattice structure in the emitter 3 close to the base 2 is the third semiconductor layer 31, and the film layer of the superlattice structure in the base 2 close to the emitter 3 is the first semiconductor layer 21, and the first semiconductor layer 21 and the third semiconductor layer 31 are made of the same material. For example, the first semiconductor layer 21 and the third semiconductor layer 31 both include GaAs. The thickness of the first semiconductor layer 21 and the third semiconductor layer 31 can be relatively thin, such as the thickness of the first semiconductor layer 21 and the third semiconductor layer 31 are less than 100 angstroms respectively.

[0089] In this embodiment, the third semiconductor layer 31 is made of the same material as the first semiconductor layer 21, so that the emitter 3 and the base 2 present homojunction characteristics, effectively eliminating the potential spike at the interface between the emitter 3 and the base 2, thereby meeting the requirements of high current gain at low offset voltage and low current levels. In addition, since the first semiconductor layer 31 and the third semiconductor layer 21 are very thin (such as GaAs thin layers), the emitter 3 will be completely depleted at low base-emitter voltage levels, and the confinement effect of holes is maintained by the large valence band discontinuity of the emitter heterojunction. Electrons are transmitted in the emitter part by resonant tunnel injection, and tunnel electrons from the emitter 3 will pass through the first semiconductor layer 31 and easily enter the base 2.

[0090] In some embodiments, the thickness of the adjacent third semiconductor layer 31 and the fourth semiconductor layer 32 is 10 to 100 angstroms, and the number of alternations is 4 to 40. In the superlattice structure in the emitter 3, every two film layers (a third semiconductor layer 31 and a fourth semiconductor layer 32) constitute a superlattice layer, the thickness of the superlattice layer is 10 to 70 angstroms, and the number of layers of the superlattice layer is 5 to 25.

[0091] According to the heterojunction bipolar transistor provided by the embodiment of the present application, by setting a superlattice structure in the base 2, and using a narrow bandgap semiconductor material in the superlattice structure, the electron injection efficiency is effectively improved, the overall power consumption of the device is reduced, and the hole mobility is improved to reduce the base resistance and increase the maximum oscillation frequency. The superlattice structure is set in the base 2, which also promotes the diffusion transmission of minority carriers, increases the minority carrier storage concentration in the base 2 through the quantum tunneling mechanism, thereby rapidly increasing the collector 1 current and effectively reducing the base-emitter conduction voltage.

[0092] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0093] In the description of the present application, “plurality” means two or more.

[0094] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0095] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A heterojunction bipolar transistor, characterized in that: include: collector; A base electrode, located at one side of the collector electrode; an emitter, located at a side of the base away from the collector; Wherein, the base includes a superlattice structure, the band gap of the base is smaller than the band gap of the emitter, the conduction band offset between the base and the emitter is smaller than the target conduction band offset, the valence band offset between the base and the emitter is greater than the first target valence band offset, and the valence band offset between the base and the collector is greater than the second target valence band offset.

2. The heterojunction bipolar transistor according to claim 1, characterized in that: The superlattice structure includes first semiconductor layers and second semiconductor layers that are alternately arranged.

3. The heterojunction bipolar transistor according to claim 2, characterized in that: The superlattice structure is an I-type superlattice, and the band gap of the second semiconductor layer is smaller than the band gap of the first semiconductor layer.

4. The heterojunction bipolar transistor according to claim 3, characterized in that: In the direction toward the collector, the thickness of the second semiconductor layer gradually decreases, and / or the material composition in the second semiconductor layer gradually decreases or increases, and the conduction band of the base gradually decreases.

5. The heterojunction bipolar transistor according to claim 3, characterized in that: The film layer on the side of the superlattice structure close to the collector is the first semiconductor layer, and the collector is made of the same material as the first semiconductor layer.

6. The heterojunction bipolar transistor according to claim 2, characterized in that: The superlattice structure is a type II superlattice, the first semiconductor layer is an electron potential well layer, and the second semiconductor layer is a hole potential well layer.

7. The heterojunction bipolar transistor according to claim 6, characterized in that: In the direction toward the collector, the thickness of the first semiconductor layer gradually increases, and / or the material composition in the first semiconductor layer gradually decreases or increases, and the conduction band of the base gradually decreases.

8. The heterojunction bipolar transistor according to any one of claims 2 to 7, characterized in that: The thickness of the adjacent first semiconductor layer and the second semiconductor layer is 10 to 70 angstroms, and the number of alternations is 5 to 25.

9. The heterojunction bipolar transistor according to any one of claims 2 to 7, characterized in that: The first semiconductor layer and the second semiconductor layer respectively include any one of GaAs, AlSb, InGaAs, GaAsSb, InGaAsSb and AlGaAsSb, and the first semiconductor layer and the second semiconductor layer are made of different materials, or the first semiconductor layer and the second semiconductor layer are made of the same material but have different material compositions.

10. The heterojunction bipolar transistor according to claim 9, characterized in that: The emitter includes any one of InGaP, AlGaAs, AlPSb, InGaAsP, InAlGaP and AlGaPSb, and the collector includes GaAs.

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