Double-groove SiC MOSFET device capable of improving reverse freewheeling and preparation method of double-groove SiC MOSFET device
By integrating the Schottky metal contact layer with high and low barriers and introducing trench structure in SiC MOSFET, the problems of bipolar degradation effect and high freewheeling loss in reverse freewheeling of traditional SiC MOSFET devices are solved, and the device is improved Reverse free flow capability and gate oxide reliability.
Patent Information
- Application Number
- CN202411176603.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-26
- Publication Date
- 2024-12-13
AI Technical Summary
Traditional SiC MOSFET devices have bipolar degradation effects and high turn-on voltages in reverse freewheeling applications, resulting in high freewheeling losses and lack of effective reverse recovery characteristics.
By integrating the Schottky metal contact layer with high and low barriers in the SiC MOSFET and introducing a trench structure into the source region, a multi-layer structure is formed to improve the reverse free flow capability and improve the reliability of the gate oxide layer.
It improves the reverse freewheeling capability of the device, reduces the freewheeling loss, and enhances the voltage withstand performance of the gate oxide layer, reduces the forward conduction voltage drop of the device, and improves the performance in circuit applications.
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Figure CN119133234A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a double-trench SiC MOSFET device for improving reverse freewheeling and a preparation method thereof. Background Art
[0002] Compared with Si materials, SiC materials have better development prospects in the fields of high voltage, high power, high temperature and high frequency due to their outstanding characteristics such as wide bandgap, high critical breakdown electric field strength, high thermal conductivity and high saturated electron drift velocity. Compared with planar gate structures, grooved gate SiC MOSFET has a larger on-current and is more popular in power applications.
[0003] Since SiC MOSFET devices are often used in power management systems such as bridge circuits and inverter applications, there is a demand for reverse freewheeling function, so its reverse recovery characteristics are an important indicator for evaluating its performance. However, in the application of traditional SiC MOSFET, there is a bipolar degradation effect when using parasitic PN junction diodes for freewheeling, and its higher turn-on voltage also leads to higher freewheeling losses. Therefore, developing a dual-trench SiC MOSFET device that can obtain better reverse recovery characteristics and avoid bipolar degradation effects is a technical problem that needs to be solved urgently in the industry. Summary of the invention
[0004] In view of the above problems, the present invention provides a dual-trench SiC MOSFET device and a preparation method thereof, which can obtain better reverse recovery characteristics and avoid bipolar degradation effects.
[0005] A method for preparing a double-trench SiC MOSFET device for improving reverse freewheeling comprises the following steps: S100, epitaxially growing an N-epitaxial layer on the N+ substrate layer, and forming a PW region on the top of the N-epitaxial layer by ion implantation; S200, etching the top surface of the PW region to form a plurality of gate trench regions; S300, forming a first P+ region, a second P+ region, a first N+ region and a second N+ region by secondary implantation in the PW region; S400, etching a source trench region on the first P+ region, and forming an ohmic contact alloy on the sidewall of the source trench region to form an ohmic contact with the P+ regions on both sides of the source trench; S500, depositing a gate oxide layer on the sidewall and bottom of the gate trench region, and filling it with a Poly layer to be led out as a gate electrode; S600, forming an isolation dielectric layer, an ohmic contact alloy layer, a Schottky metal layer and a front electrode metal layer in sequence on the N-epitaxial layer.
[0006] Specifically, in step S100, the concentration range of the PW region is 1E 17 cm -2 -1E 18 cm -2 , the injection depth is 0.8-1.5um.
[0007] Specifically, in step S200, the etching depth of the gate trench region is 1-1.8 um.
[0008] Specifically, in step S300, the concentration ranges of the first P+ region and the second P+ region are 1E 18 cm -2 -1E 19 cm -2 , the injection depth is 0.8-1.5um.
[0009] Specifically, in step S400, the etching depth of the source trench region is 0.4-0.9 um.
[0010] Specifically, in step S600, high-barrier Schottky metal particles with a thickness of 1-2 layers are deposited on the N-epitaxial layer, and the particles are relatively evenly dispersed on the SiC surface; then a layer of low-barrier Schottky metal layer is deposited, and then rapidly annealed under high temperature conditions to form high- and low-barrier Schottky metal layers, forming Schottky contacts with the second P+ region and the top of the second N+ region.
[0011] Specifically, the high temperature value in step S600 is 950°C-1050°C.
[0012] Specifically, in step S600 , the thickness of the Schottky metal layer of the high and low potential barriers is 60 nm.
[0013] Specifically, in step S600, a front electrode metal layer is formed on the isolation dielectric layer, the ohmic contact alloy layer, the Schottky metal layer and in the source trench region by Al metal sputtering to serve as a source electrode lead.
[0014] Specifically, in step S600, the front electrode metal layer fills the entire source trench region, and the ohmic contact alloy on both side walls of the source trench region contacts the front electrode metal layer Al.
[0015] A double-trench SiC MOSFET device for improving reverse freewheeling current comprises an N+ substrate layer, an N-epitaxial layer and a front electrode metal layer arranged in sequence from bottom to top; The N-epitaxial layer is provided with: A PW region extends downward from the top surface of the N-epitaxial layer and is spaced apart from the bottom surface of the N-epitaxial layer; the PW region is divided into a middle PW region and a plurality of side PW regions by a plurality of gate trench regions; the bottom of the gate trench region is lower than the bottom surface of the PW region; A P+ region, including a first P+ region and a second P+ region; Wherein, the first P+ region extends downward from the middle of the top surface of the middle PW region, and a side portion is spaced apart from a side portion of the middle PW region; Wherein, the second P+ region extends downward from the top side of the side PW region; N+ region, including a first N+ region and a second N+ region; The first N+ region extends downward from the top surface of the middle PW region and is connected to the side of the first P+ region; a gap is provided between the bottom surface of the first N+ region and the bottom surface of the middle PW region; Wherein, the second N+ region extends downward from the middle of the top surface of the side PW region; Ohmic contact alloy, arranged on the sidewall of the source trench region in the middle of the first P+ region; A gate oxide layer formed on the sidewalls and bottom of the gate trench region; A Poly layer, filled in the gate trench region and connected to the gate oxide layer; An isolation dielectric layer, an ohmic contact alloy layer, a Schottky metal layer and a front electrode metal layer are arranged on the N-epitaxial layer.
[0016] Beneficial effects of the present invention: 1. Improve the reverse freewheeling capability of the device: By integrating a diode inside the SiC MOSFET, the reverse freewheeling capability of the device is improved. Two metals with different potential barriers form a Schottky metal contact layer. The high doping of the contact surface can increase the maximum electric field on the semiconductor surface, thereby enhancing the mirror force and further lowering the metal potential barrier, reducing the forward conduction voltage drop of the diode, making it easier to achieve forward conduction in circuit applications, and reducing the freewheeling loss of the device.
[0017] 2. Improve the gate oxide reliability of the device: When manufacturing a trench MOSFET structure, a stronger breakdown field strength will reduce the gate oxide withstand voltage performance at the bottom of the trench. The present invention introduces a trench structure in the source region to suppress the peak electric field at the gate oxide layer, thereby improving the reliability problem of the gate oxide layer of the trench MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 is a structural diagram of step S100 of the present invention; Figure 2 is a structural diagram of step S200 of the present invention; Figure 3 is a structural diagram of step S300 of the present invention; Figure 4 is a structural diagram of step S400 of the present invention; Figure 5 is a structural diagram of step S500 of the present invention; Figure 6 is a structural diagram of step S600 of the present invention; Figure 7 is a structural diagram of step S700 of the present invention; Figure 8 is a structural diagram of step S800 of the present invention; Fig. 9 is a structural diagram of step S900 of the present invention; Fig.10 is a structural diagram of step S1000 of the present invention; Fig.11 is a structural diagram of step S1100 of the present invention; Fig.12 is a structural diagram of step S1200 of the present invention; Fig.13 is a structural diagram of step S1300 of the present invention; In the figure, 1 is the N+ substrate layer, 2 is the N- epitaxial layer, 3 is the PW region, 4 is the gate trench region, 5 and 5' are the P+ regions, 6 and 6' are the N+ regions, 7 is the source trench region, 8 is the ohmic contact alloy, 9 is the gate oxide layer, 10 is the Poly layer, 11 is the isolation dielectric layer, 12 is the ohmic contact alloy layer, 13 is the Schottky metal layer, and 14 is the front electrode metal layer. DETAILED DESCRIPTION
[0019] The present invention is described in detail below in conjunction with specific implementation cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.
[0020] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. indicate positions or positional relationships based on the positions and positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "multiple" means two or more.
[0021] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0022] A method for preparing a double-trench SiC MOSFET device for improving reverse freewheeling comprises the following steps: S100, refer to Figure 1 As shown, an N- epitaxial layer 2 is formed by epitaxial growth on an N+ substrate layer 1, and then cleaned and dried; S200, refer to Figure 2 As shown, SiO2 is used as a mask for ion implantation, and Al ions are implanted to form a PW region 3 in the N-epitaxial layer 2; the concentration range of the PW region 3 is 1E 17 cm -2 -1E 18 cm -2 , the injection depth is 0.8-1.5um.
[0023] S300, refer to Figure 3 As shown, the N-epitaxial layer 2 is etched by plasma etching technology to form a plurality of gate trench regions 4, and the etching depth is 1-1.8 um; S400, such as Figure 4 As shown, SiO2 is used as a mask, and Al ions are injected into the PW region 3 multiple times to form a first P+ region 5 and a second P+ region 5'; they can simultaneously serve as a reverse voltage-resistant shielding layer and a source contact P+ region. The concentration range of the first P+ region 5 and the second P+ region 5' is 1E 18 cm -2 -1E 19 cm -2 The implantation depth is 0.8-1.5 um, and the mask is removed after the implantation is completed; the implantation depth of the first P+ region 5 and the second P+ region 5 ′ is the same as the implantation depth of the PW region 3 .
[0024] S500, such as Figure 5 As shown, SiO2 is used as a mask, and N ions are injected into the PW region 3 multiple times to form a first N+ region 6 and a second N+ region 6', which serve as the source contact N+ region and the Schottky contact N+ region during reverse flow, respectively. The concentration range is 1E 18 cm -2 -1E 19 cm -2After the implantation is completed, the mask is removed; then a thin layer of graphite is deposited on the surface of the device as protection, and annealed at a high temperature of 1650℃-1690℃ for 15min to activate the implanted ions; The implantation depth of the first N+ region 6 is 0.4-0.8um, and the implantation depth of the second N+ region 6' is 0.8-1.5um. The PW region 3, the P+ region 5 and the first N+ region 6 have the same potential, which can enhance the withstand voltage and short circuit tolerance of the device.
[0025] The N+ region in step S500 is divided into two parts: one part is the first N+ region 6 above the inversion layer, which is in contact with the source and is used for forward conduction of current. The injection depth of the N+ region in this part is only half of that of the PW region 3; the other part is the second N+ region 6' below the Schottky metal layer 13, which is used for reverse flow. The injection depth of the N+ region in this part is the same as that of the PW region 3.
[0026] S600, such as Figure 6 As shown, a source trench region 7 is etched on the first P+ region 5, and the etching depth is 0.4-0.9 um; In step S600 , the depth of the source trench region 7 is 0.5-0.6 times the implantation depth of the PW region 3 , which reduces the on-resistance while enhancing the withstand voltage performance of the device.
[0027] S700, such as Figure 7 As shown, an ohmic metal is formed on the side wall of the source trench region 7 by sputtering Ni metal, and then annealed at a high temperature of 1000° C. for 5 minutes to form an ohmic contact alloy 8, which forms an ohmic contact with the P+ region on both sides of the source trench; S800, such as Figure 8 As shown, a gate oxide layer 9 is deposited on the sidewall and bottom of the gate trench region 4 by using the LPCVD method; The thickness of the gate oxide layer 9 in step S800 is 60 nm-70 nm, which further improves the robustness of the gate oxide layer.
[0028] S900, refer to Fig. 9 As shown, polysilicon is deposited in the gate trench region 4 by LPCVD to form a Poly layer 10, which is used as a gate electrode lead; S1000, refer to Fig.10 As shown, an isolation dielectric layer 11 is formed on the N-epitaxial layer 2 by depositing oxide; In step S1000 , both ends of the isolation dielectric layer 11 overlap the upper ends of the second P+ region 5 ′ and the first N+ region 6 , respectively. The overlapping distance is not set and is adjusted according to actual process conditions.
[0029] S1100, reference Fig.11As shown, an ohmic metal layer is formed on the N-epitaxial layer 2 by Ni metal sputtering deposition, and then annealed at a high temperature of 1000° C. for 5 minutes to form an ohmic contact alloy layer 12, which forms an ohmic contact with the first P+ region 5 and the first N+ region 6; S1200, refer to Fig.12 As shown, high barrier Schottky metal particles with a thickness of 1-2 layers are deposited on the N-epitaxial layer 2, and the particles are relatively evenly dispersed on the SiC surface; then a layer of low barrier Schottky metal layer is deposited, and then rapidly annealed at a high temperature of 950°C-1050°C for 5 minutes to form a high and low barrier Schottky metal layer 13 with a thickness of 60nm, forming Schottky contacts with the second P+ region 5' and the upper part of the second N+ region 6'; In step S1200, the metal material of the high barrier Schottky metal particle layer includes any one or several of Au, Ni, Pt, and Pd, with a nanometer particle diameter, and the metal particles can be deposited by aerosol or sputtering. The metal of the low barrier Schottky metal layer includes any one or several of Ti, Mo, and W, and then a rapid annealing treatment is performed, which can not only improve the uniformity of the Schottky contact, but also make the high barrier metal particles better embedded in the low barrier Schottky metal layer.
[0030] S1300, refer to Fig.13 As shown, a front electrode metal layer 14 is formed on the isolation dielectric layer 11, the ohmic contact alloy layer 12, the Schottky metal layer 13 and in the source trench region 7 by Al metal sputtering to serve as a source electrode lead.
[0031] In step S1300 , the front electrode metal layer 14 needs to fill the entire source trench region 7 , and the ohmic contact alloy 8 on both side walls of the source trench region 7 is in contact with the front electrode metal layer 14A1.
[0032] A double-trench SiC MOSFET device for improving reverse freewheeling current comprises an N+ substrate layer 1, an N- epitaxial layer 2 and a front electrode metal layer 14 arranged in sequence from bottom to top; The N-epitaxial layer 2 is provided with: The PW region 3 extends downward from the top surface of the N-epitaxial layer 2 and is spaced apart from the bottom surface of the N-epitaxial layer 2; the PW region 3 is divided into a middle PW region and a plurality of side PW regions by a plurality of gate trench regions 4; the bottom of the gate trench region 4 is lower than the bottom surface of the PW region 3; P+ region, including a first P+ region 5 and a second P+ region 5'; Wherein, the first P+ region 5 extends downward from the middle of the top surface of the middle PW region, and a gap is provided between the side and the side of the middle PW region; Wherein, the second P+ region 5' extends downward from the top side of the side PW region; N+ region, including a first N+ region 6 and a second N+ region 6'; The first N+ region 6 extends downward from the top surface of the middle PW region and is connected to the side of the first P+ region 5; a gap is provided between the bottom surface of the first N+ region 6 and the bottom surface of the middle PW region; Wherein, the second N+ region 6' extends downward from the middle of the top surface of the side PW region; An ohmic contact alloy 8 is arranged on the side wall of the source trench region 7 in the middle of the first P+ region 5; A gate oxide layer 9 is formed on the sidewalls and bottom of the gate trench region 4; A Poly layer 10, filled in the gate trench region 4 and connected to the gate oxide layer 9; An isolation dielectric layer 11 , an ohmic contact alloy layer 12 , a Schottky metal layer 13 and a front electrode metal layer 14 are disposed on the N-epitaxial layer 2 .
[0033] The isolation dielectric layer 11 is formed on the N-epitaxial layer 2; the bottom surface of the isolation dielectric layer 11 in the middle area is respectively connected to the Poly layer 10, the gate oxide layer 9, the first N+ region 6 and the second P+ region 5'; the bottom surface of the isolation dielectric layer 11 near the edge area is respectively connected to the Poly layer 10, the gate oxide layer 9 and the second P+ region 5'.
[0034] The ohmic contact alloy layer 12 is formed on the top surfaces of the first P+ region 5 and the first N+ region 6 , and the side portions thereof are connected to the isolation dielectric layer 11 .
[0035] The Schottky metal layer 13 is formed on the top surfaces of the second P+ region 5 ′ and the second N+ region 6 ′, and the side portions thereof are connected to the isolation dielectric layer 11 .
[0036] The bottom of the front electrode metal layer 14 is respectively connected to the isolation dielectric layer 11, the Schottky metal layer 13, the ohmic contact alloy layer 12, the first P+ region 5 and the ohmic contact alloy 8.
[0037] The present invention uses two metals with different potential barriers to form a Schottky metal contact layer. The high doping of the contact surface increases the maximum electric field on the semiconductor surface, thereby enhancing the mirror force to further reduce the metal barrier, reduce the forward conduction voltage drop of the diode, make it easier to achieve forward conduction in circuit applications, and reduce the device's freewheeling loss. In addition, the groove structure of the source region can alleviate the electric field gathered at the gate oxide layer, and improve the gate oxide reliability. Compared with connecting a fast recovery diode in parallel externally, the number of devices is reduced, and the packaging space in the module application is saved.
[0038] Regarding the contents disclosed in this case, there are a few points that need to be explained: (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. For other structures, please refer to the general reference; (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments; (3) The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case shall be subject to the protection scope of the claims.
Claims
1. A method for preparing a double trench SiC MOSFET device for improving reverse freewheeling, characterized in that: The steps include: S100, epitaxially growing an N-epitaxial layer (2) on an N+ substrate layer (1), and forming a PW region (3) on top of the N-epitaxial layer (2) by ion implantation; S200, etching the top surface of the PW region (3) to form a plurality of gate trench regions (4); S300, forming a first P+ region (5), a second P+ region (5'), a first N+ region (6) and a second N+ region (6') by secondary implantation in the PW region (3); S400, etching a source trench region (7) on the first P+ region (5), and forming an ohmic contact alloy (8) on the sidewalls of the source trench region (7) to form an ohmic contact with the P+ regions on both sides of the source trench; S500, depositing a gate oxide layer (9) on the sidewalls and bottom of the gate trench region (4), and filling it with a Poly layer (10) to serve as a gate electrode lead; S600, forming an isolation dielectric layer (11), an ohmic contact alloy layer (12), a Schottky metal layer (13) and a front electrode metal layer (14) in sequence on the N-epitaxial layer (2).
2. The method for preparing a dual trench SiC MOSFET device for improving reverse freewheeling according to claim 1, characterized in that: The concentration range of the PW region (3) in step S100 is 1E 17 cm -2 -1E 18 cm -2 , the injection depth is 0.8-1.5um.
3. The method for preparing a dual trench SiC MOSFET device for improving reverse freewheeling according to claim 1, characterized in that: In step S300, the concentration ranges of the first P+ region (5) and the second P+ region (5') are 1E 18 cm -2 -1E 19 cm -2 , the injection depth is 0.8-1.5um.
4. The method for preparing a double trench SiC MOSFET device for improving reverse freewheeling according to claim 1, characterized in that: In step S400, the etching depth of the source trench region (7) is 0.4-0.9 um.
5. The method for preparing a double trench SiC MOSFET device for improving reverse freewheeling according to claim 1, characterized in that: In step S600, high-barrier Schottky metal particles with a thickness of 1-2 layers are deposited on the N-epitaxial layer (2), and the particles are relatively evenly dispersed on the SiC surface; then a layer of low-barrier Schottky metal layer is deposited, and then rapidly annealed under high temperature conditions to form a high-low barrier Schottky metal layer (13), which forms Schottky contacts with the second P+ region (5') and the second N+ region (6').
6. The method for preparing a double trench SiC MOSFET device for improving reverse freewheeling according to claim 5, characterized in that: The high temperature value in step S600 is 950°C-1050°C.
7. The method for preparing a double trench SiC MOSFET device for improving reverse freewheeling according to claim 5, characterized in that: In step S600, the thickness of the Schottky metal layer (13) with high and low potential barriers is 60 nm.
8. The method for preparing a double trench SiC MOSFET device for improving reverse freewheeling according to claim 1, characterized in that: In step S600, a front electrode metal layer (14) is formed on the isolation dielectric layer (11), the ohmic contact alloy layer (12), the Schottky metal layer (13) and in the source trench region (7) by means of Al metal sputtering to serve as a source electrode lead.
9. The method for preparing a dual trench SiC MOSFET device for improving reverse freewheeling according to claim 1, characterized in that: In step S600, the front electrode metal layer (14) fills the entire source trench region (7), and the ohmic contact alloy (8) on both side walls of the source trench region (7) is in contact with Al of the front electrode metal layer (14).
10. A double trench SiC MOSFET device with improved reverse freewheeling current, prepared by the method for preparing a double trench SiC MOSFET device with improved reverse freewheeling current according to any one of claims 1 to 9, characterized in that: It comprises an N+ substrate layer (1), an N- epitaxial layer (2) and a front electrode metal layer (14) which are arranged in sequence from bottom to top; The N-epitaxial layer (2) is provided with: A PW region (3) extends downward from the top surface of the N-epitaxial layer (2) and is spaced apart from the bottom surface of the N-epitaxial layer (2); the PW region (3) is divided into a middle PW region and a plurality of side PW regions by a plurality of gate trench regions (4); the bottom of the gate trench region (4) is lower than the bottom surface of the PW region (3); P+ region, including a first P+ region (5) and a second P+ region (5'); The first P+ region (5) extends downward from the middle of the top surface of the middle PW region, and a gap is provided between the side and the side of the middle PW region; Wherein, the second P+ region (5') extends downward from the top side of the side PW region; N+ region, including a first N+ region (6) and a second N+ region (6'); The first N+ region (6) extends downward from the top surface of the middle PW region and is connected to the side of the first P+ region (5); a gap is provided between the bottom surface of the first N+ region (6) and the bottom surface of the middle PW region; Wherein, the second N+ region (6') extends downward from the middle of the top surface of the side PW region; An ohmic contact alloy (8) is arranged on the side wall of the source trench region (7) in the middle of the first P+ region (5); A gate oxide layer (9) formed on the sidewalls and bottom of the gate trench region (4); A Poly layer (10) filled in the gate trench region (4) and connected to the gate oxide layer (9); An isolation dielectric layer (11), an ohmic contact alloy layer (12), a Schottky metal layer (13) and a front electrode metal layer (14) are provided on the N-epitaxial layer (2).