Semiconductor device and preparation method

Abstract

The invention discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, a cellular region and an emitter which are sequentially stacked, the first region and the second region are alternately arranged in the first direction, the gate medium region is located in the first region, the gate is located in the gate medium region, the source region is located in the second region, the first region and the source region are of a first conduction type, the second region is of a second conduction type, the first region is connected with the emitter through the metal conduction region, and the second region is connected with the emitter through the metal conduction region. The metal conduction region and the first region form Schottky contact; along the first direction, gate medium regions are arranged on two sides of each second region, and the second regions are connected with the emitter; the gate is positioned on one side close to the second region in the gate dielectric region; along the first direction, two sides of the source region are respectively connected with the gate medium region and the emitter; in the second direction, the metal conduction region is arranged between the emitting electrode and the first region.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a semiconductor device and a preparation method thereof. Background Art

[0002] SuperJunction Metal-oxide-semiconductor Field Effect Transistor (SJ MOSFET) is a power device that alternately arranges N-type column regions and P-type column regions in an N-type drift region in a traditional power semiconductor device. It can reduce on-resistance while improving breakdown resistance and is widely used in control circuits and other fields.

[0003] However, super junction MOSFET still has the problem of poor reverse recovery characteristics which needs to be improved. Summary of the invention

[0004] An embodiment of the present application provides a semiconductor device and a preparation method thereof. The semiconductor device improves the reverse recovery characteristics of the device by integrating a Schottky barrier diode structure in a super junction MOSFET, so that the device can be used in the field of high-frequency switching.

[0005] In a first aspect, an embodiment of the present application provides a semiconductor device, including a substrate, a cell region, and an emitter that are stacked in sequence; the cell region includes:

[0006] A first region and a second region alternately arranged along a first direction, wherein the second region is interconnected with the emitter;

[0007] A gate dielectric region located in the first region, wherein the gate dielectric region is disposed on both sides of each of the second regions along the first direction;

[0008] A gate located in the gate dielectric region, the gate located on a side of the gate dielectric region close to the second region;

[0009] A source region located in the second region, with two sides of the source region connected to the gate dielectric region and the emitter electrode respectively along the first direction;

[0010] A metal conduction region, arranged between the emitter and the first region along a second direction;

[0011] The first region and the source region are of the first conductivity type, the second region is of the second conductivity type, the first region is interconnected with the emitter through the metal conduction region, and the metal conduction region forms a Schottky contact with the first region.

[0012] In some embodiments, the semiconductor device also includes a source located in the gate dielectric region, the source is located on a side of the gate dielectric region away from the second region, the source and the gate are arranged spaced apart along a first direction, and the length of the gate in the first direction is less than the length of the gate in the second direction.

[0013] In some embodiments, the semiconductor device also includes a first connection portion, and the first connection portions are respectively arranged on both sides of the metal conduction region along the third direction, and the two sources located on both sides of the metal conduction region are interconnected through two first connection portions, and the first connection portion is interconnected with the emitter.

[0014] In some embodiments, the semiconductor device also includes a second connection portion and a gate bus bar, the second connection portions are respectively arranged on both sides of the metal conduction area along the third direction, the two gates located on both sides of the metal conduction area are interconnected through the second connection portions, and the second connection portions arranged at intervals along the first direction are interconnected through the gate bus bar.

[0015] In some embodiments, the metal conduction region is made of the same material as the emitter, and the metal conduction region and the emitter are integrally formed, or the metal conduction region and the emitter are made of different materials, and the work function of the metal conduction region is greater than the work function of the emitter.

[0016] In some embodiments, the semiconductor device further includes an interlayer dielectric layer, which is disposed between the metal conduction region and the emitter along a first direction and between the emitter and the cell region along a second direction.

[0017] In some embodiments, the semiconductor device further includes a terminal region, which is disposed on one side of the substrate and connected to the cell region, a work function tuning layer is disposed between the terminal region and the cell region, and the emitter and the first region are interconnected through the work function tuning layer.

[0018] In some embodiments, the emitter includes a terminal contact, the work function of the terminal contact is smaller than the work function of the work function tuning layer, and the orthographic projection of the terminal contact on the plane where the work function tuning layer is located falls within the range of the work function tuning layer.

[0019] In a second aspect, an embodiment of the present application provides a method for preparing a semiconductor device, the method comprising:

[0020] Providing a substrate, and forming first regions and second regions which are alternately arranged and have opposite conductivity types on the substrate;

[0021] Etching and depositing oxide on a side of the second region away from the substrate to form a gate dielectric region;

[0022] A gate and a source region are formed on a side of the gate dielectric region away from the substrate, and an interlayer dielectric layer is formed above the gate and the source region;

[0023] The interlayer dielectric layer is etched to form a metal conduction region groove, and a metal conduction region is deposited in the metal conduction region groove, so that the metal conduction region forms a Schottky contact with the first region.

[0024] In some embodiments, forming a gate and a source region on a side of the gate dielectric region away from the substrate comprises:

[0025] Depositing a gate material layer on a side of the gate dielectric region away from the substrate and etching the gate material layer;

[0026] Depositing a source material layer in the gate dielectric region, polishing the source material layer and the gate material layer to expose the second region, and obtaining a source and a gate spaced apart in the gate dielectric region along a first direction;

[0027] The second region is etched to form a source region groove, and ions are implanted into the source region groove to form a source region having a conductivity type opposite to that of the second region.

[0028] The semiconductor device of the embodiment of the present application sets a metal conduction region in the super junction MOSFET, so that the emitter can form a Schottky contact with the first region through the metal conduction region, and the Schottky barrier diode is integrated in the super junction MOSFET, which significantly improves the problem of poor reverse recovery characteristics caused by the large proportion of the PN junction area in the super junction structure. When the super junction MOSFET is in a forward bias, the emitter can be connected to the first region through the metal conduction region to reduce the reverse recovery charge of the super junction MOSFET, speed up the reverse recovery speed, and adapt to the application of high-frequency switching and other scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Moreover, the same reference numerals are used throughout the drawings to represent the same components. In the drawings:

[0030] Figure 1 A schematic diagram of a cross-sectional structure of a semiconductor device according to an embodiment of the present application;

[0031] Figure 2 A schematic diagram of a top view of a semiconductor device according to an embodiment of the present application;

[0032] Figure 3 It is another schematic top view of the structure of the semiconductor device according to an embodiment of the present application;

[0033] Figure 4 for Figure 3 A schematic diagram of a cross-sectional structure of a semiconductor device shown;

[0034] Figure 5a to Figure 5h Schematic diagram of the process of manufacturing a semiconductor device according to an embodiment of the present application.

[0035] The reference numerals in the specific implementation manner are as follows:

[0036] 100, cell region; 110, substrate; 121, first region; 122, second region; 123, third region; 130, gate dielectric region; 140, gate; 141, second connecting portion; 150, source region; 160, interlayer dielectric layer;

[0037] 210, metal conduction region; 220, source; 221, first connection portion;

[0038] 300, emitter;

[0039] 400, terminal region; 410, terminal contact; 420, work function tuning layer;

[0040] The first direction is X; the second direction is Z; the third direction is Y. DETAILED DESCRIPTION

[0041] The following embodiments of the technical solution of the present application are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0043] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0044] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0045] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0046] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0047] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0048] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0049] As a direct indicator of the reverse recovery performance of power devices, when the MOSFET body diode changes from the on state to the withstand voltage state, a reverse current will be generated in the MOSFET due to the reverse voltage. This reverse current is called the reverse recovery current. It is easy to understand that the magnitude of the reverse recovery current has a great influence on the switching frequency characteristics of the power device.

[0050] SuperJunction Metal-oxide-semiconductor Field Effect Transistor (SJ MOSFET) is a structure in which N-type column regions and P-type column regions are alternately arranged in the N-type drift region in the traditional power MOSFET, which can reduce the on-resistance while improving the breakdown resistance. However, the body diode of the superjunction MOSFET stores more charge during forward conduction, resulting in a higher reverse recovery current peak. Therefore, the reverse recovery characteristics of the superjunction MOSFET still need to be improved to expand its application in scenarios such as high-frequency switching and improve work efficiency.

[0051] In order to solve the problems in the prior art, the present invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device provided by the present invention is first introduced below.

[0052] First, see Figure 1 to Figure 2 The embodiment of the present application provides a semiconductor device, which includes a substrate 110, a cell region 100 and an emitter 300 which are stacked in sequence. The cell region 100 includes a first region 121 and a second region 122 which are alternately arranged along a first direction (e.g., the X direction in the figure), a gate dielectric region 130 located in the first region 121, a gate 140 located in the gate dielectric region 130, a source region 150 located in the second region 122, and a metal conduction region 210, wherein the first region 121 and the source region 150 are of the first conductivity type, the second region 122 is of the second conductivity type, the first region 121 is interconnected with the emitter 300 through the metal conduction region 210, and the metal conduction region 210 is connected to the emitter 300. The through region 210 forms a Schottky contact with the first region 121; along the first direction, gate dielectric regions 130 are provided on both sides of each second region 122, and the second region 122 is interconnected with the emitter 300; the gate 140 is located on one side of the gate dielectric region 130 close to the second region 122; along the first direction, both sides of the source region 150 are respectively connected to the gate dielectric region 130 and the emitter 300; along the second direction (for example, the Z direction in the figure), the metal conduction region 210 is provided between the emitter 300 and the first region 121.

[0053] Optionally, the first conductivity type is one of N type or P type, and the second conductivity type is the other of N type or P type. Exemplarily, the first conductivity type is N type doping, and the second conductivity type is P type doping. When the gate 140 voltage is greater than the threshold voltage, the second region 122 located between the source region 150 and the first region 121 along the second direction can form a channel on the side close to the gate 140 to achieve current conduction.

[0054] Optionally, the cell region 100 further includes a third region 123 of the first conductivity type, the third region 123 is sandwiched between the second region 122 and the substrate 110 , and along the first direction, the second regions 122 are interconnected through the third region 123 .

[0055] As a result, a Schottky barrier diode is formed between the metal conduction region 210 and the first region 121, and a body diode of the super junction MOSFET is formed between the first region 121 and the second region 122. When the super junction MOSFET is in a forward bias state, since the Schottky barrier diode has a lower voltage drop, the current of the MOSFET mainly flows through the Schottky barrier diode, thereby reducing the amount of charge stored in the body diode during the forward conduction process. On the one hand, the excellent reverse recovery characteristics of the Schottky barrier diode itself are utilized, and on the other hand, the reverse recovery current of the body diode is reduced by reducing the charge stored in the body diode, thereby improving the reverse recovery performance of the super junction MOSFET.

[0056] According to some embodiments of the present application, the semiconductor device further includes a source 220 located in the gate dielectric region 130 . The source 220 is located in a side of the gate dielectric region 130 away from the second region 122 .

[0057] As a result, a trench MOS Schottky barrier diode is formed between the source 220, the metal conduction region 210 and the first region 121. When the super junction MOSFET is in a reverse bias state, the MOS structure laterally depletes the epitaxial layer between the trenches, reducing the surface electric field of the Schottky contact, thereby reducing the leakage current, increasing the reverse breakdown voltage of the device, and reducing the impact of the integrated Schottky barrier diode on the voltage resistance performance of the super junction MOSFET.

[0058] Optionally, the source electrode 220 is made of the same material as the emitter electrode 300 .

[0059] For further information, see Figure 1 According to some embodiments of the present application, in the gate dielectric region 130 , the source 220 and the gate 140 are arranged spaced apart along a first direction.

[0060] Optionally, the length of the gate 140 in the first direction is smaller than the length of the gate 140 in the second direction.

[0061] Therefore, by adjusting the arrangement of the source 220 and the gate 140, the proportion of the gate 140 in the gate dielectric region 130 is reduced, thereby reducing the surface area of ​​the gate 140 relative to the first region 121, reducing the parasitic gate-drain capacitance of the super junction MOSFET, and thus reducing switching losses.

[0062] According to certain embodiments of the present application, the semiconductor device further includes an interlayer dielectric layer 160 , which is disposed between the metal conduction region 210 and the emitter 300 along a first direction and between the emitter 300 and the cell region 100 along a second direction.

[0063] Optionally, the interlayer dielectric layer 160 includes silicon dioxide.

[0064] Thus, partial insulation between the metal conduction region 210 and the emitter 300 is achieved through the interlayer dielectric layer 160 to prevent unexpected conduction from occurring in the semiconductor device.

[0065] According to some embodiments of the present application, the semiconductor device further includes a first connection portion 221 , and the sources 220 in the two gate dielectric regions 130 disposed on both sides of the metal conduction region 210 along the first direction are interconnected through the first connection portion 221 .

[0066] Optionally, along the first direction, the first connection portion 221 is disposed between two source electrodes 220 to simplify the connection.

[0067] Optionally, along a third direction (eg, the Y direction in the figure), first connecting portions 221 are provided on both sides of the metal conductive region 210 .

[0068] Optionally, the semiconductor device includes a plurality of cell regions 100 , and two first connection portions 221 distributed along the third direction on both sides of the metal conductive region 210 are shared by two adjacent cell regions 100 .

[0069] Optionally, each first connection portion 221 passes through the interlayer dielectric layer 160 and is interconnected with the emitter 300 .

[0070] Thus, a plurality of source electrodes 220 can be interconnected through the first connection portion 221 , and each cell region 100 can be interconnected through the first connection portion 221 .

[0071] According to some embodiments of the present application, the semiconductor device further includes a second connection portion 141 , and the gates 140 in the two gate dielectric regions 130 disposed on both sides of the metal conduction region 210 along the first direction are interconnected through the second connection portion 141 .

[0072] Optionally, along the first direction, the second connection portion 141 is disposed between two gates 140 to simplify the connection.

[0073] Optionally, along the third direction, second connecting portions 141 are provided on both sides of the metal conductive region 210 .

[0074] Optionally, along the third direction, the two second connection portions 141 are disposed on the outer sides of the two first connection portions 221 .

[0075] Optionally, the semiconductor device includes a plurality of cell regions 100 , and two second connection portions 141 distributed along the third direction on both sides of the metal conductive region 210 are shared by two adjacent cell regions 100 .

[0076] Thus, the plurality of gates 140 can be interconnected through the second connection portion 141 , and the cell regions 100 can be interconnected through the second connection portion 141 .

[0077] Optionally, the semiconductor device further includes a gate bus bar, wherein two gate bus bars are provided, and the two gate bus bars are arranged on both sides of the source pad along the third direction, and the two gate bus bars are respectively connected to two second connection portions 141 located in the same cell area 100 .

[0078] Optionally, the second connection portion 141 passes through the interlayer dielectric layer 160 and connects to the gate bus bar.

[0079] According to some embodiments of the present application, the metal conduction region 210 and the emitter 300 are made of the same material, and the metal conduction region 210 and the emitter 300 are integrally formed.

[0080] Optionally, the metal conduction region 210 and the emitter 300 are integrally formed after the first connection portion 221 and the second connection portion 141 are prepared.

[0081] Optionally, the metal conduction region 210 and the emitter 300 are formed by a deposition process.

[0082] Therefore, the preparation process of the metal conductive region 210 is simplified, making the metal conductive region 210 easier to obtain in terms of process.

[0083] According to some embodiments of the present application, the metal conduction region 210 is made of a material different from that of the emitter 300 . The metal conduction region 210 is made of a material having a work function greater than that of the emitter 300 .

[0084] Optionally, the metal conducting region 210 is formed by a deposition process.

[0085] Optionally, the work function of the metal conduction region 210 is greater than 4.85 eV.

[0086] Therefore, the height of the Schottky barrier can be adjusted by selecting the material of the metal conduction region 210 , thereby adjusting the leakage current of the Schottky barrier diode and changing the withstand voltage performance of the Schottky barrier diode.

[0087] See also Figure 3 to Figure 4According to certain embodiments of the present application, the semiconductor device further includes a terminal region 400 , which is disposed on one side of the substrate 110 and connected to the cell region 100 , a work function tuning layer 420 is disposed between the terminal region 400 and the cell region 100 , and the emitter 300 is interconnected with the first region 121 through the work function tuning layer 420 .

[0088] Optionally, the orthographic projection of the work function tuning layer 420 along the second direction is a continuous closed figure.

[0089] Therefore, when the super junction MOSFET is in a forward bias state, the MOSFET can be forward-conducted through the metal conduction region 210 and the work function tuning layer 420 at the same time, so as to further reduce the number of carriers flowing through the body diode and further improve the reverse recovery performance of the super junction MOSFET.

[0090] According to some embodiments of the present application, the emitter 300 includes a terminal contact 410 , which is in electrical contact with the work function tuning layer 420 .

[0091] Optionally, the work function of the work function tuning layer 420 is greater than the work function of the terminal contact 410 .

[0092] Optionally, the work function of the work function tuning layer 420 is greater than 4.85 eV.

[0093] Thus, the barrier height of the Schottky barrier diode formed at the work function tuning layer 420 is adjusted, and the withstand voltage performance of the semiconductor device is improved.

[0094] Optionally, an orthographic projection of the terminal contact 410 on the plane where the work function tuning layer 420 is located falls within the range of the work function tuning layer 420 .

[0095] Optionally, the terminal contact 410 and the emitter 300 are manufactured in an integral manner.

[0096] Second, see Figure 5a to Figure 5h , an embodiment of the present application provides a method for preparing a semiconductor device, the method comprising:

[0097] Provide a substrate 110, and form first regions 121 and second regions 122 which are alternately arranged and have opposite conductivity types on the substrate 110;

[0098] Etching and depositing oxide on a side of the second region 122 away from the substrate 110 to form a gate dielectric region 130;

[0099] A gate 140 and a source region 150 are formed on a side of the gate dielectric region 130 away from the substrate 110 , and an interlayer dielectric layer 160 is formed above the gate 140 and the source region 150 ;

[0100] The interlayer dielectric layer 160 is etched to form a metal conduction region groove, and a metal conduction region 210 is deposited in the metal conduction region groove, so that the metal conduction region 210 forms a Schottky contact with the first region 121 .

[0101] According to some embodiments of the present application, forming the gate 140 and the source region 150 on a side of the gate dielectric region 130 away from the substrate 110 includes:

[0102] Depositing a gate material layer on a side of the gate dielectric region 130 away from the substrate 110 and etching the gate material layer;

[0103] Depositing a source material layer in the gate dielectric region 130, polishing the source material layer and the gate material layer to expose the second region 122, and obtaining a source 220 and a gate 140 spaced apart in the gate dielectric region 130 along the first direction;

[0104] The second region 122 is etched to form a source region groove, and ions are implanted into the source region groove to form a source region 150 having a conductivity type opposite to that of the second region 122 .

[0105] According to some embodiments of the present application, the preparation method further includes etching the interlayer dielectric layer 160 to form a first connection portion groove, and depositing to form the first connection portion 221 in the first connection portion groove.

[0106] Furthermore, the preparation method further includes performing a thermal annealing treatment on the first connecting portion 221 .

[0107] Optionally, the thermal annealing process is a RTP process.

[0108] According to some embodiments of the present application, the preparation method further includes etching the interlayer dielectric layer 160 to form a second connection portion groove, and depositing to form the second connection portion 141 in the second connection portion groove.

[0109] Furthermore, the preparation method further includes performing a thermal annealing treatment on the second connecting portion 141 .

[0110] Optionally, the thermal annealing process is a RTP process.

[0111] According to some embodiments of the present application, the preparation method further includes: etching the interlayer dielectric layer 160 to form an emitter 300 groove, and depositing the emitter 300 in the emitter 300 groove.

[0112] Furthermore, the preparation method further includes preparing a passivation layer after the emitter 300 is formed.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A semiconductor device, It is characterized in that It comprises a substrate, a cell region and an emitter which are stacked in sequence; the cell region comprises: A first region and a second region alternately arranged along a first direction, wherein the second region is interconnected with the emitter; A gate dielectric region located in the first region, wherein the gate dielectric region is disposed on both sides of each of the second regions along the first direction; A gate located in the gate dielectric region, the gate located on a side of the gate dielectric region close to the second region; A source region located in the second region, with two sides of the source region connected to the gate dielectric region and the emitter electrode respectively along the first direction; A metal conduction region, arranged between the emitter and the first region along a second direction; The first region and the source region are of the first conductivity type, the second region is of the second conductivity type, the first region is interconnected with the emitter through the metal conduction region, and the metal conduction region forms a Schottky contact with the first region.

2. The semiconductor device according to claim 1, It is characterized in that The semiconductor device also includes a source located in the gate dielectric region, the source is located on a side of the gate dielectric region away from the second region, the source and the gate are spaced apart along a first direction, and the length of the gate in the first direction is less than the length of the gate in the second direction.

3. The semiconductor device according to claim 2, It is characterized in that The semiconductor device further includes a first connection portion, which is respectively provided on both sides of the metal conduction region along the third direction, and the two sources located on both sides of the metal conduction region are interconnected through the two first connection portions, and the first connection portion is interconnected with the emitter.

4. The semiconductor device according to claim 3, It is characterized in that The semiconductor device also includes a second connection portion and a gate bus bar. The second connection portions are respectively arranged on both sides of the metal conduction area along the third direction. The two gates located on both sides of the metal conduction area are interconnected through the second connection portions. The second connection portions arranged at intervals along the first direction are interconnected through the gate bus bar.

5. The semiconductor device according to claim 1, It is characterized in that The metal conduction region and the emitter are made of the same material, and the metal conduction region and the emitter are integrally formed, or the metal conduction region and the emitter are made of different materials, and the work function of the metal conduction region is greater than the work function of the emitter.

6. The semiconductor device according to claim 1, It is characterized in that The semiconductor device further comprises an interlayer dielectric layer, wherein the interlayer dielectric layer is arranged between the metal conduction region and the emitter along a first direction, and between the emitter and the cell region along a second direction.

7. The semiconductor device according to any one of claims 1 to 6, It is characterized in that The semiconductor device further comprises a terminal region, which is arranged at one side of the substrate and connected to the cell region, a work function tuning layer is arranged between the terminal region and the cell region, and the emitter and the first region are interconnected through the work function tuning layer.

8. The semiconductor device according to claim 7, It is characterized in that The emitter includes a terminal contact, a work function of the terminal contact is smaller than a work function of the work function tuning layer, and an orthographic projection of the terminal contact on a plane where the work function tuning layer is located falls within the range of the work function tuning layer.

9. A method for preparing a semiconductor device, It is characterized in that include: Providing a substrate, and forming first regions and second regions which are alternately arranged and have opposite conductivity types on the substrate; Etching and depositing oxide on a side of the second region away from the substrate to form a gate dielectric region; A gate and a source region are formed on a side of the gate dielectric region away from the substrate, and an interlayer dielectric layer is formed above the gate and the source region; The interlayer dielectric layer is etched to form a metal conduction region groove, and a metal conduction region is deposited in the metal conduction region groove, so that the metal conduction region forms a Schottky contact with the first region.

10. The method for preparing a semiconductor device according to claim 9, It is characterized in that The forming of the gate and the source region on the side of the gate dielectric region away from the substrate comprises: Depositing a gate material layer on a side of the gate dielectric region away from the substrate and etching the gate material layer; Depositing a source material layer in the gate dielectric region, polishing the source material layer and the gate material layer to expose the second region, and obtaining a source and a gate spaced apart in the gate dielectric region along a first direction; The second region is etched to form a source region groove, and ions are implanted into the source region groove to form a source region having a conductivity type opposite to that of the second region.

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