Silicon carbide MOSFET integrated with heterojunction diode and manufacturing method thereof

Abstract

The invention discloses a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with a heterojunction diode, which comprises a drain metal layer, a silicon carbide N-type doped substrate, a silicon carbide N-type epitaxial region and a silicon carbide N-type current expansion layer which are sequentially arranged from bottom to top, and is characterized in that a silicon carbide P-type buried layer is embedded in the middle of the silicon carbide N-type current expansion layer; groove gate oxide layers are arranged at the two ends of the silicon carbide N-type current expansion layer respectively, a silicon carbide P-type shielding layer is arranged at the bottom of each groove gate oxide layer, silicon carbide P-type base regions are arranged at the two ends of the upper side of the silicon carbide N-type current expansion layer respectively, and a silicon carbide N-type source region and a silicon carbide P-type source region are arranged above each silicon carbide P-type base region at the same time. And a heterojunction polycrystalline silicon region is arranged in the center of the top of the silicon carbide N-type current expansion layer. The invention further discloses a manufacturing method of the silicon carbide MOSFET integrated with the heterojunction diode, the device has low reverse turn-on voltage, and the static quality factor and the short circuit reliability of the device are improved.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductor devices and relates to a silicon carbide MOSFET integrated with a heterojunction diode; the invention also relates to a method for manufacturing a silicon carbide MOSFET integrated with a heterojunction diode. Background Art

[0002] Silicon carbide MOSFETs are widely used in high-voltage and high-power fields, such as photovoltaic inverters, wind inverters, industrial high-power power supplies, high-voltage direct current transmission (HVDC), and electric vehicles. Trench MOSFETs introduce additional electric fields at the bottom and corners of the trench, which may have a negative impact on the performance and reliability of the device. To address this issue, the current main commercial device structure is C-TMOS, which introduces a p+ shielding layer at the bottom of the trench. In order to protect the bottom of the gate oxide layer and reduce the electric field of the gate oxide layer, this structure introduces a P+ shielding layer. Although the gate oxide layer electric field is reduced to a certain extent, the on-resistance of the device is greatly increased.

[0003] On the other hand, when SiC MOSFET works in power electronic systems, it usually requires an anti-parallel diode for freewheeling. However, on the circuit side, the external anti-parallel diode increases the cost and overall volume of the system. On the other hand, it will also introduce stray inductance, leading to electromagnetic interference (EMI) problems and voltage spikes, which will affect the high-frequency switching performance of the device and system reliability. In theory, SiC MOSFET can use its own body diode for freewheeling, but due to the wide bandgap characteristics of SiC material, the turn-on voltage of the SiC MOSFET body diode is as high as 3V, which reduces the switching frequency of the device and increases the reverse conduction loss. And due to the defects of the material, the device has the risk of bipolar degradation in the bipolar conduction mode, which will increase the conduction loss of the device and reduce the blocking characteristics, affecting the stability and reliability of the entire system, and easily causing the risk of "out of control". Summary of the invention

[0004] The object of the present invention is to provide a silicon carbide MOSFET with an integrated heterojunction diode, which has a lower turn-on voltage, improves the forward blocking voltage and switching frequency of the device, reduces switching losses and characteristic on-resistance, significantly improves the reverse recovery characteristics of the device, and effectively avoids bipolar degradation of the device.

[0005] Another object of the present invention is to provide a method for manufacturing a silicon carbide MOSFET with an integrated heterojunction diode.

[0006] The first technical solution adopted by the present invention is a silicon carbide MOSFET with an integrated heterojunction diode, comprising a drain metal layer, a silicon carbide N-type doped substrate, a silicon carbide N-type epitaxial region, and a silicon carbide N-type current expansion layer arranged in sequence from bottom to top, a silicon carbide P-type buried layer embedded in the middle of the silicon carbide N-type current expansion layer, trench gate oxide layers are respectively provided at both ends of the silicon carbide N-type current expansion layer, a silicon carbide P-type shielding layer is provided at the bottom of each trench gate oxide layer, silicon carbide P-type base regions are respectively provided at both ends of the upper side of the silicon carbide N-type current expansion layer, a silicon carbide N-type source region and a silicon carbide P-type source region are simultaneously provided above each silicon carbide P-type base region, and a heterojunction polysilicon region is provided at the top center of the silicon carbide N-type current expansion layer.

[0007] The first technical solution of the present invention is also characterized in that:

[0008] A trench gate oxide layer is arranged outside each silicon carbide P-type base region, and each trench gate oxide layer is filled with trench gate N-type polysilicon.

[0009] A gate metal layer is provided above each of the trench gate N-type polysilicon.

[0010] A source metal layer is arranged above the silicon carbide N-type source region, the silicon carbide P-type source region, the gate metal layer and the heterojunction polysilicon region.

[0011] The thickness of the trench gate oxide layer is 30-50nm.

[0012] The polysilicon in the heterojunction polysilicon region is P-type polysilicon or N-type polysilicon.

[0013] The second technical solution adopted by the present invention is a method for manufacturing a silicon carbide MOSFET with an integrated heterojunction diode, which specifically comprises the following steps:

[0014] Step 1, selecting an N-type doped 4H-SiC substrate as a silicon carbide N-type doped substrate, growing a silicon carbide N-type epitaxial region on the silicon carbide N-type doped substrate by epitaxial growth, continuing to epitaxially grow a silicon carbide N-type current spreading layer, and forming a drain metal layer on the lower surface of the silicon carbide N-type doped substrate;

[0015] Step 2, forming a window on the silicon carbide N-type current spreading layer by photolithography, and performing ion implantation to form a silicon carbide P-type buried layer and a silicon carbide P-type shielding layer;

[0016] Step 3, based on step 2, continue to epitaxially grow the silicon carbide N-type current spreading layer, and perform ion implantation through a photolithography process to sequentially form a silicon carbide P-type base region, a silicon carbide N-type source region, and a silicon carbide P-type source region;

[0017] Step 4, using inductively coupled plasma reactive ion etching to perform trench etching on the silicon carbide N-type current spreading layer, and sequentially performing trench gate oxide layer growth and trench gate N-type polysilicon manufacturing in the trench;

[0018] Step 5, forming a source metal layer on the upper surfaces of the silicon carbide N-type source region, the silicon carbide P-type source region and the heterojunction polysilicon region in sequence, and forming a gate metal layer on the upper surface of the trench gate N-type polysilicon.

[0019] The second technical solution of the present invention is also characterized in that:

[0020] In step 1, the doping concentration of the SiC N-type epitaxial region is 5×10 15 ~2×10 16 cm -3 , with a thickness of 8 to 15 μm, and a doping concentration of 1×10 16 ~2×10 17 cm -3 , thickness is 0.1~0.4μm.

[0021] In step 2, the width of the silicon carbide P-type buried layer is 0.4-1.6 μm; the width of the silicon carbide P-type shielding layer is 0.5-1.0 μm.

[0022] In step 3, the doping concentration of the SiC N-type source region is 1×10 19 cm -3 , with a thickness of 0.2 to 0.4 μm; the doping concentration of the SiC P-type source region is 1×10 19 cm -3 , thickness is 0.2~0.4μm.

[0023] The beneficial effects of the present invention are as follows:

[0024] 1. Compared with the conventional structure C-TMOS used in the prior art, the device of the present invention achieves an increase in forward blocking voltage and an improvement in gate oxide layer reliability while ensuring low on-resistance, and has a high static quality factor (FOM).

[0025] 2. Compared with the traditional structure C-TMOS that uses a body diode for freewheeling, the device in the present invention has a lower reverse turn-on voltage and a higher switching frequency. It also utilizes the advantages of a heterojunction diode as a unipolar device to shorten the reverse recovery time, reduce the reverse recovery charge, and improve the reverse recovery characteristics of the device.

[0026] 3. Compared with the traditional structure C-TMOS, the device in the present invention can reduce the coupling area between the gate and the drain by adding an embedded P buried layer, effectively reduce the gate-drain capacitance and reduce the gate-drain charge, thereby increasing the switching speed; reducing the switching loss; and improving the switching characteristics of the device.

[0027] 4. The manufacturing process of the device in the present invention adopts a combination of the traditional trench MOS manufacturing process and the polysilicon manufacturing process, and the manufacturing process is simple and the manufacturing cost is low. In addition, the present invention improves the tolerance of the device in extreme conditions (short circuit state, dynamic avalanche) by embedding the P buried layer, and has high reliability. In addition, the present invention adopts the relatively mature silicon carbide process, and there is no special process requirement. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of the structure of a silicon carbide MOSFET with an integrated heterojunction diode according to the present invention;

[0029] Figure 2 It is a process flow chart of a silicon carbide MOSFET with an integrated heterojunction diode according to the present invention;

[0030] Figure 3 It is a schematic structural diagram of a silicon carbide MOSFET with an integrated heterojunction diode according to the present invention, in which a silicon carbide N-type epitaxial region and a silicon carbide N-type current spreading layer are formed on a silicon carbide substrate;

[0031] Figure 4 It is a schematic structural diagram of the silicon carbide P-type shielding layer and the P buried layer formed by the silicon carbide MOSFET with integrated heterojunction diode of the present invention;

[0032] Figure 5 It is a schematic structural diagram of the silicon carbide N-type current spreading layer formed by epitaxy of the silicon carbide MOSFET with integrated heterojunction diode of the present invention;

[0033] Figure 6 It is a schematic structural diagram of the silicon carbide MOSFET integrated heterojunction diode of the present invention, in which ion implantation forms a silicon carbide P-type base region, an N+ source region and a P+ source region respectively;

[0034] Figure 7 It is a schematic diagram of the structure of etching grooves of a silicon carbide MOSFET with an integrated heterojunction diode of the present invention;

[0035] Figure 8 It is a schematic structural diagram of a trench gate dielectric formed by a silicon carbide MOSFET with an integrated heterojunction diode according to the present invention;

[0036] Fig. 9 It is a comparison curve of gate charge characteristics of the traditional structure (C-TMOS) and the silicon carbide MOSFET with integrated heterojunction diode of the present invention;

[0037] Fig.10 The capacitance characteristic comparison curve of the silicon carbide MOSFET with the traditional structure and the integrated heterojunction diode of the present invention;

[0038] Fig.11 It is a comparison curve of the switch-off phase of the conventional structure (C-TMOS) and the silicon carbide MOSFET with integrated heterojunction diode of the present invention;

[0039] Fig.12 It is a comparison curve of the switch characteristics of the conventional structure (C-TMOS) and the silicon carbide MOSFET with integrated heterojunction diode of the present invention during the turn-on phase;

[0040] Fig.13 It is a comparison curve of reverse IV characteristics of the traditional structure (C-TMOS) and the silicon carbide MOSFET with integrated heterojunction diode of the present invention;

[0041] Fig.14 It is a comparison curve of reverse recovery characteristics of the traditional structure (C-TMOS) and the silicon carbide MOSFET with integrated heterojunction diode of the present invention;

[0042] Fig.15 It is a comparison curve of forward IV characteristics of the traditional structure (C-TMOS) and the silicon carbide MOSFET with integrated heterojunction diode of the present invention;

[0043] Fig.16 It is a short-circuit reliability comparison curve of the traditional structure (C-TMOS) and the silicon carbide MOSFET with integrated heterojunction diode of the present invention.

[0044] In the figure, 1. Silicon carbide N-type doped substrate, 2. Silicon carbide N-type epitaxial region, 3. Silicon carbide N-type current spreading layer, 4. Silicon carbide P-type buried layer, 5. Silicon carbide P-type shielding layer, 6. Silicon carbide P-type base region, 7. Silicon carbide N-type source region, 8. Silicon carbide P-type source region, 9. Trench gate oxide layer, 10. Heterojunction polysilicon region, 11. Trench gate N-type polysilicon, 12. Gate metal layer, 13. Source metal layer, 14. Drain metal layer. DETAILED DESCRIPTION

[0045] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0046] Example 1

[0047] The silicon carbide MOSFET with integrated heterojunction diode of the present invention connects the integrated heterojunction diode in reverse parallel between two adjacent cells of the trench silicon carbide MOSFET. The polycrystalline silicon / silicon carbide heterojunction diode utilizes energy band engineering to achieve a small electron barrier height on the basis of ensuring a high valence band barrier and a low conduction band barrier, thereby greatly reducing the diode turn-on voltage. Therefore, the heterojunction diode is integrated on the silicon carbide MOSFET so that the reverse turn-on voltage of the device is much smaller than that of the body pin diode. During the switching process of the silicon carbide MOSFET, the integrated heterojunction diode will be turned on with a smaller voltage, thereby increasing the switching frequency and reducing the switching loss. In addition, since the integrated heterojunction diode only injects electrons, only a few holes are injected into the body region, and compared with the body pin diode, the reverse recovery characteristics of the device are significantly improved.

[0048] like Figure 1 As shown, the silicon carbide MOSFET with integrated heterojunction diode of the present invention includes, from bottom to top, a drain metal layer 14, a silicon carbide N-type doped substrate 1, a silicon carbide N-type epitaxial region 2, and a silicon carbide N-type current spreading layer 3, wherein a P buried layer 4 and two silicon carbide P-type shielding layers 5 located at the bottom of the trench are embedded in the middle of the silicon carbide N-type current spreading layer 3, silicon carbide P-type base regions 6 are respectively arranged at the upper ends of the silicon carbide N-type current spreading layer, and a silicon carbide N-type source region 7 and a silicon carbide P-type source region 8 are simultaneously arranged above each silicon carbide P-type base region, and the middle part between the two ends of each silicon carbide P-type base region 6 is the silicon carbide N-type current spreading layer 3, and the heterojunction polysilicon region 10 is located above the region.

[0049] Example 2

[0050] A trench gate oxide layer 9 is provided on both sides of the silicon carbide P-type base region 6, each trench gate oxide layer 9 is filled with a trench gate N-type polysilicon 11, a silicon carbide P-type shielding layer 5 is provided at the bottom of each trench gate oxide layer 9, a gate metal layer 12 is provided at both ends above the trench gate N-type polysilicon 11, a source metal layer 13 is provided above the silicon carbide N-type source region 7, the silicon carbide P-type source region 8 and the heterojunction polysilicon region 10; the thickness of the trench gate oxide layer 9 is between 30-50nm. The heterojunction polysilicon region 10 includes but is not limited to P-type polysilicon and N-type polysilicon, preferably taking P-type polysilicon as an example.

[0051] Example 3

[0052] The method for manufacturing a silicon carbide MOSFET with an integrated heterojunction diode of the present invention has the following process steps: Figure 2 As shown, the specific steps include:

[0053] S1, select an N-type doped 4H-SiC substrate as a silicon carbide N-type doped substrate 1, grow a silicon carbide N-type epitaxial region 2 on the silicon carbide N-type doped substrate 1 by epitaxial growth, continue to epitaxially grow a silicon carbide N-type current spreading layer 3, and form a drain metal layer 14 on the lower surface of the silicon carbide N-type doped substrate 1, as shown in FIG. Figure 3 As shown;

[0054] Specifically, the doping element of the 4H-SiC substrate is N, and the doping concentration is 1×10 19 cm -3 , with a thickness of 350μm or 500μm, the silicon carbide N-type epitaxial region 2 is epitaxially grown by chemical vapor deposition (LPCVD), the doping element is N, and the doping concentration is 5×10 15 ~2×10 16 cm -3 , with a thickness of 8 to 15 μm, and a doping concentration of 1×10 16 ~2×10 17 cm -3 , thickness is 0.1~0.4μm;

[0055] Specifically, a drain metal is deposited on the lower surface of the silicon carbide N-type doped substrate 1, and a Ti / Ni / Al alloy is used as an ohmic contact material, and annealing is performed at an ambient temperature of 900 to 1100° C. to achieve ohmic contact;

[0056] In this implementation case, the thickness of the 4H-SiC substrate is 350 μm, and the doping concentration of the SiC N-type epitaxial region 2 is 8×10 15 cm -3 , with a thickness of 10 μm, and a doping concentration of 1×10 16 cm -3 , thickness is 0.2μm;

[0057] The 4H-SiC substrate is divided into an upper surface and a lower surface, wherein the upper surface is covered with a silicon carbide N-type epitaxial region 2, and the lower surface is used for drain metal connection;

[0058] In step S1, the doping concentration of the silicon carbide N-type epitaxial region is 5×10 15 ~2×10 16 cm -3 , with a thickness of 8 to 15 μm, and a doping concentration of 1×10 16 ~2×10 17 cm -3 , thickness is 0.1~0.4μm;

[0059] S2, forming a window on the silicon carbide N-type current spreading layer 3 by photolithography, and performing high-temperature and high-energy ion implantation to form a silicon carbide P-type buried layer 4 and a silicon carbide P-type shielding layer 5, such as Figure 4 As shown;

[0060] Specifically, photolithography is first performed to form SiO2 as an ion implantation mask layer on the surface of the SiC N-type current spreading layer 3, and photoresist is deposited on the surface of the SiO2. After photolithography processes such as exposure, development, and hardening, an ion implantation window is formed. A high-energy ion implanter is used to form a SiC P-type buried layer 4 doped with Al, with a doping concentration of 5×10 17 ~3×10 18 cm -3 The thickness is 0.1-0.4 μm, the doping element is Al, and the doping concentration is 5×10 17 ~3×10 18 cm -3 , thickness is 0.2~0.4μm;

[0061] The width of the silicon carbide P-type buried layer 4 is determined by the window of the photolithography plate, and the width is 0.4-1.6 μm. The width of the silicon carbide P-type shielding layer 5 is determined by the window of the photolithography plate, and the width is 0.5-1.0 μm.

[0062] S3, based on S2, further epitaxially grow a silicon carbide N-type current spreading layer 3; then, through a photolithography process, selective ion implantation is performed to sequentially form a silicon carbide P-type base region 6, a silicon carbide N-type source region 7 and a silicon carbide P-type source region 8, such as Figure 5-6 As shown;

[0063] Specifically, on the basis of S2, a silicon carbide N-type current spreading layer 3 is further epitaxially grown by chemical vapor deposition (LPCVD), and then photolithography is performed to form SiO2 on the surface of the silicon carbide N-type current spreading layer 3 as an ion implantation mask layer, and photoresist is deposited on the surface of SiO2. After photolithography processes such as exposure, development and hardening, an ion implantation window is formed, and a high-energy ion implanter is used to form a silicon carbide P-type base region 6 doped with Al as an element, and the doping concentration is 1×10 17 ~8×10 17 cm -3 , with a thickness of 0.5 to 1.0 μm, and then a window is formed on the silicon carbide P-type base region 6, and selective ion implantation is performed to form a silicon carbide N-type source region 7 with a doping element of N, and its doping concentration is 1×10 19 cm -3 , with a thickness of 0.2 to 0.4 μm, forming a silicon carbide P-type source region 8 doped with Al, with a doping concentration of 1×10 19 cm -3, thickness is 0.2~0.4μm;

[0064] After all the selective ion implantation is completed, activation annealing is required at above 1500℃. Argon is used as a protective gas during the annealing process to activate the ions in the lattice gap to release electrical properties and repair the lattice damaged after ion implantation.

[0065] S4, using inductively coupled plasma reactive ion etching (ICP-RIE) to perform trench etching on the silicon carbide N-type current spreading layer 3, such as Figure 7 As shown, the trench gate oxide layer 9 is grown and the trench gate N-type polysilicon 11 is fabricated in sequence in the trench. Figure 8 As shown;

[0066] Specifically, the etching is performed by nested etching using a photomask, so that the window of the etched groove is aligned with the window of the ion implanted silicon carbide P-type shielding layer 5, the etching depth reaches above the silicon carbide P-type shielding layer 5, and the groove depth is about 1.0-1.5 μm;

[0067] Specifically, firstly, wet oxidation is performed for 1 hour, and after BOE etching (HF / NH4F) treatment, dry oxygen oxidation is performed to grow a trench gate oxide layer 9, and polysilicon gate is manufactured. A photomask is used to deposit P-type polysilicon on the silicon carbide N-type current spreading layer 3 to generate a heterojunction polysilicon region 10, and N-type polysilicon is deposited in the trench gate oxide layer 9 to generate a trench gate N-type polysilicon 11;

[0068] Specifically, polysilicon is grown by LPCVD, ion implantation is performed on the polysilicon, annealing is performed at 900°C, and then planarization is performed, and then polysilicon etching is performed. Fig. 9 After the gate oxide layer is grown, annealing is performed. The purpose of annealing is to reduce the interface state and improve the quality of the gate oxide layer.

[0069] After the groove etching, passivation treatment is required to eliminate the micro-grooves. Argon is used as the main gas and SiH4 is used as the auxiliary gas for passivation treatment;

[0070] After the gate oxide layer is grown, it needs to be annealed to reduce the interface state and improve the quality of the gate oxide layer;

[0071] The width of the etched groove is consistent with the silicon carbide P-type shielding layer 5, and the etching depth reaches the top of the silicon carbide P-type shielding layer 5;

[0072] S5, forming a source metal layer 13 on the carbon upper surfaces of the silicon carbide N-type source region 8, the silicon carbide P-type source region 7 and the heterojunction polysilicon region 10, and forming a gate metal layer 12 on the upper surface of the trench gate N-type polysilicon 11, such as Figure 1 As shown;

[0073] Specifically, on the basis of S4, an isolation layer is deposited on the surface, and a gate window is formed on the upper surface of the trench gate by reactive ion etching (RIE etching) or plasma etching (ICP etching), and a gate metal layer 12 is formed in the gate window, and the gate metal layer 12 is an Al metal layer; a source window is formed on the upper surface of the silicon carbide N-type source region 7, the silicon carbide P-type source region 8 and the heterojunction polysilicon region 10, and a source metal layer 13 is formed in the source window.

[0074] Example 4

[0075] In order to verify the performance of the silicon carbide MOSFET with integrated heterojunction diode of the present invention, the C-TMOS with a P-type shielding layer used in the prior art and the high-performance silicon carbide MOSFET with integrated heterojunction diode of the present invention were compared. Fig. 9 is a comparison curve of gate charge characteristics of C-TMOS and high-performance silicon carbide MOSFET with integrated heterojunction diode of the present invention, wherein the gate-drain charge (Q GD ) is 46.91nC, and the gate-drain charge of the high-performance silicon carbide MOSFET with integrated heterojunction diode of the present invention is 28.71nC, with a decrease of about 38.8%. Fig.10 : is a comparison curve of capacitance characteristics between C-TMOS and the high-performance silicon carbide MOSFET with integrated heterojunction diode of the present invention, wherein the gate-drain capacitance (C GD ) is 39.6pF / cm 2 , and the structure C proposed in the present invention GD 12.1pF / cm 2 , the decrease is about 69.4%; the gate-source capacitance of C-TMOS (C GS ) is 15.8nF / cm 2 , and the structure C proposed in the present invention GS 16.4nF / cm 2 ;

[0076] The drain-source capacitance (C DS ) is 215.2pF / cm 2 , and the structure C proposed in the present invention DS 243.9pF / cm 2 However, the gate-drain capacitance and gate-drain charge are key factors that determine the switching characteristics of SiC MOSFET, because the gate-drain capacitance charging and discharging phase accounts for the main part of the overall switching loss and switching time. Therefore, the structure proposed in the present invention has superior dynamic characteristics and can greatly improve the switching performance of the device.

[0077] Fig.11The turn-off characteristics comparison curve of the C-TMOS with a P-type shielding layer used in the prior art and the high-performance silicon carbide MOSFET with an integrated heterojunction diode of the present invention, wherein the turn-off loss of the C-TMOS is 0.163 mJ / cm 2 The turn-on loss of the high-performance silicon carbide MOSFET with integrated heterojunction diode is 0.150 mJ / cm 2 , a decrease of about 8%. Fig.12 It is a comparison curve of the turn-on characteristics of C-TMOS and the high-performance silicon carbide MOSFET with integrated heterojunction diode of the present invention, wherein the turn-on loss of C-TMOS is 0.880, and the turn-on loss of the high-performance silicon carbide MOSFET with integrated heterojunction diode of the present invention is 0.754, which is reduced by about 15%. Therefore, the structure proposed by the present invention can reduce switching loss, increase switching frequency, and improve the switching characteristics of the device.

[0078] Fig.13 It is a reverse IV characteristic comparison curve of the C-TMOS with a P-type shielding layer used in the prior art and the high-performance silicon carbide MOSFET with an integrated heterojunction diode of the present invention, wherein the reverse conduction voltage Von of the C-TMOS is 2.6V, and the reverse conduction voltage Von of the high-performance silicon carbide MOSFET with an integrated heterojunction diode of the present invention is 1.6V, and the on-voltage is reduced by 1.0V. Fig.15 : This is a comparison curve of reverse recovery characteristics of C-TMOS and the high-performance silicon carbide MOSFET with integrated heterojunction diode of the present invention. Fig.14 The reverse recovery charge (Q rr ) is 3.51μC / cm 2 , the structure Q proposed by the present invention rr 1.08μC / cm 2 Therefore, the structure proposed in the present invention can reduce the reverse conduction voltage, shorten the reverse recovery time, reduce the reverse recovery charge, and improve the reverse recovery characteristics of the device.

[0079] Fig.15 The forward IV characteristic comparison curves of the C-TMOS with a P-type shielding layer used in the prior art and the high-performance silicon carbide MOSFET with an integrated heterojunction diode of the present invention are shown in FIG. on,sp 2.8 mΩ·cm 2 The specific on-resistance R of the high-performance silicon carbide MOSFET with integrated heterojunction diode of the present invention is on,sp 2.2 mΩ·cm 2The on-resistance is reduced by 21.4%, the breakdown voltage of C-TMOS is 1697V, and the breakdown voltage of the high-performance silicon carbide MOSFET with integrated heterojunction diode of the present invention is 1922V, and the breakdown voltage is increased by 14%. Therefore, the structure proposed by the present invention can greatly reduce the static power consumption of the device, and improve the breakdown voltage of the device, reduce the electric field strength of the gate oxide layer, and improve the reliability of the device.

[0080] Fig.16 The short-circuit reliability comparison curve of the C-TMOS with a P-type shielding layer used in the prior art and the high-performance silicon carbide MOSFET with an integrated heterojunction diode of the present invention when the bus voltage is 800V is shown in FIG. SC = 26us, the failure point is reached, and the short-circuit withstand time of the high-performance silicon carbide MOSFET with integrated heterojunction diode of the present invention is T SC =27us, the failure point is reached, which proves that the present invention has better short-circuit tolerance than the traditional structure.

Claims

1. A silicon carbide MOSFET with an integrated heterojunction diode, characterized in that: The invention comprises a drain metal layer (14), a silicon carbide N-type doped substrate (1), a silicon carbide N-type epitaxial region (2), and a silicon carbide N-type current spreading layer (3) which are arranged in sequence from bottom to top; a silicon carbide P-type buried layer (4) is embedded in the middle of the silicon carbide N-type current spreading layer (3); trench gate oxide layers (9) are respectively arranged at both ends of the silicon carbide N-type current spreading layer (3); a silicon carbide P-type shielding layer (5) is arranged at the bottom of each trench gate oxide layer (9); silicon carbide P-type base regions (6) are respectively arranged at both ends of the upper side of the silicon carbide N-type current spreading layer (3); a silicon carbide N-type source region (8) and a silicon carbide P-type source region (7) are simultaneously arranged above each silicon carbide P-type base region (6); and a heterojunction polysilicon region (10) is arranged at the top center of the silicon carbide N-type current spreading layer (3).

2. The silicon carbide MOSFET with integrated heterojunction diode according to claim 1, characterized in that: A trench gate oxide layer (9) is provided on the outer side of each silicon carbide P-type base region (6), and each trench gate oxide layer (9) is filled with trench gate N-type polysilicon (11).

3. The silicon carbide MOSFET with integrated heterojunction diode according to claim 2, characterized in that: A gate metal layer (12) is provided above each of the trench gate N-type polysilicon (11).

4. The silicon carbide MOSFET with integrated heterojunction diode according to claim 3, characterized in that: A source metal layer (13) is provided above the silicon carbide N-type source region (8), the silicon carbide P-type source region (7), the gate metal layer (12) and the heterojunction polysilicon region (10).

5. The silicon carbide MOSFET with integrated heterojunction diode according to claim 4, characterized in that: The thickness of the trench gate oxide layer (9) is 30-50 nm.

6. The silicon carbide MOSFET with integrated heterojunction diode according to claim 5, characterized in that: The polysilicon in the heterojunction polysilicon region (10) is P-type polysilicon or N-type polysilicon.

7. The method for manufacturing a silicon carbide MOSFET with an integrated heterojunction diode according to any one of claims 1 to 6, characterized in that: The specific steps include: Step 1, selecting an N-type doped 4H-SiC substrate as a silicon carbide N-type doped substrate (1), growing a silicon carbide N-type epitaxial region (2) on the silicon carbide N-type doped substrate (1) by epitaxial growth, continuing to epitaxially grow a silicon carbide N-type current spreading layer (3), and forming a drain metal layer (14) on the lower surface of the silicon carbide N-type doped substrate (1); Step 2, forming a window on the silicon carbide N-type current spreading layer (3) by photolithography, and performing ion implantation to form a silicon carbide P-type buried layer (4) and a silicon carbide P-type shielding layer (5); Step 3, based on step 2, continue to epitaxially grow the silicon carbide N-type current spreading layer (3), and perform ion implantation through a photolithography process to sequentially form a silicon carbide P-type base region (6), a silicon carbide N-type source region (7), and a silicon carbide P-type source region (8); Step 4, using inductively coupled plasma reactive ion etching to perform trench etching on the silicon carbide N-type current spreading layer (3), and sequentially growing a trench gate oxide layer (9) and manufacturing a trench gate N-type polysilicon (11) in the trench; Step 5, forming a source metal layer (13) on the carbon upper surfaces of the silicon carbide N-type source region (8), the silicon carbide P-type source region (7) and the heterojunction polysilicon region (10) in sequence, and forming a gate metal layer on the upper surface of the trench gate N-type polysilicon (11).

8. The method for manufacturing a silicon carbide MOSFET with an integrated heterojunction diode according to claim 7, characterized in that: In step 1, the doping concentration of the silicon carbide N-type epitaxial region (2) is 5×10 15 ~2×10 16 cm -3 , with a thickness of 8 to 15 μm, and a doping concentration of the silicon carbide N-type current spreading layer (3) of 1×10 16 ~2×10 17 cm -3 , thickness is 0.1~0.4μm.

9. The method for manufacturing a silicon carbide MOSFET with an integrated heterojunction diode according to claim 7, characterized in that: In the step 2, the width of the silicon carbide P-type buried layer (4) is 0.4-1.6 μm; the width of the silicon carbide P-type shielding layer (5) is 0.5-1.0 μm.

10. The method for manufacturing a silicon carbide MOSFET with an integrated heterojunction diode according to claim 7, characterized in that: In step 3, the doping concentration of the silicon carbide N-type source region (7) is 1×10 19 cm -3 , with a thickness of 0.2 to 0.4 μm; the doping concentration of the silicon carbide P-type source region (8) is 1×10 19 cm -3 , thickness is 0.2~0.4μm.

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