RC-IGBT structure with low reverse recovery loss and preparation method thereof

Abstract

The invention discloses an RC-IGBT structure with low reverse recovery loss and a preparation method thereof, and belongs to the technical field of power devices.When the RC-IGBT structure is reversely conducted, electrons injected into an n + short circuit region can directly flow to an n + ohmic contact region in an n-type carrier storage region after sequentially passing through an n field stop layer, an n-drift region and a P well region, so that the electrons can be directly injected into the n + ohmic contact region in the n-type carrier storage region; therefore, the electron density below the anode region of the integrated diode in the RC-IGBT structure is reduced, the hole injection efficiency of the anode region is further reduced, the reverse recovery speed of the integrated diode is improved, reverse recovery charges are reduced, and the preparation process is simple.

Description

Technical Field

[0001] The invention belongs to the technical field of power devices, and in particular relates to an RC-IGBT structure with low reverse recovery loss and a preparation method thereof. Background Art

[0002] Reverse Conducting IGBT (RC-IGBT) integrates IGBT (Insulated Gate Bipolar Transistor) and FRD (Fast Recovery Diode) on a single chip, which helps reduce the overall chip size. To improve the performance of RC-IGBT, the performance of both IGBT and FRD needs to be optimized to obtain optimal parameters. However, the methods for optimizing the performance of IGBT and FRD are always incompatible.

[0003] Usually, in order to obtain a sufficient threshold voltage for IGBT, the doping concentration of the P body region is 1e 17 cm -3 Order of magnitude, and in order to make ohmic contact between silicon and metal, the silicon in the emitter region is mostly heavily doped. This results in more holes being injected from the anode region (p+ ohmic contact region) to the P body region when the integrated diode in the RC-IGBT is turned on, resulting in a slower reverse recovery speed and worse reverse recovery performance. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a RC-IGBT structure with low reverse recovery loss and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions: In a first aspect, the present invention provides a RC-IGBT structure with low reverse recovery loss, which comprises, from bottom to top, an n+ short-circuit region, an n-field stop layer located on the surface of the n+ short-circuit region, and an n-drift region located on the surface of the n-field stop layer; The RC-IGBT further comprises: a first trench gate, a second trench gate, a P-well region, an n-type carrier storage region, an n+ ohmic contact region, a first P-body region, a second P-body region, a first n+ emitter region, a second n+ emitter region, a first p+ ohmic contact region, and a second p+ ohmic contact region; wherein the first trench gate and the second trench gate are arranged above the n-drift region relatively, the first P-body region is located on a side of the first trench gate close to the second trench gate, the second P-body region is located on a side of the second trench gate close to the first trench gate, the n-type carrier storage region is located in the middle and below the first P-body region and the second P-body region, the P-well region is located between the n-type carrier storage region and the n-drift region, and the n+ ohmic contact region is located in the n-type carrier storage region between the first P-body region and the second P-body region, and the n+ ohmic contact region is located near the upper surface. The first p+ ohmic contact region is located in the first P body region near the upper surface, the first n+ emitter region is located between the first trench gate and the first p+ ohmic contact region, the second p+ ohmic contact region is located in the second P body region near the upper surface, and the second n+ emitter region is located between the second trench gate and the second p+ ohmic contact region.

[0005] In a second aspect, the present invention further provides a method for preparing a RC-IGBT structure with low reverse recovery loss, comprising: Providing a silicon wafer; Performing P-well region injection and n-type carrier storage region injection in sequence on the surface of the silicon wafer to form an n-drift region, a P-well region and an n-type carrier storage region from bottom to top; Digging a first trench and a second trench on both sides of the wafer respectively, filling heavily doped polysilicon after forming a gate oxide layer on the inner surface of the first trench, and filling heavily doped polysilicon after forming a gate oxide layer on the inner surface of the second trench, to form a first trench gate and a second trench gate; Performing P-body region implantation on the upper surface of the wafer to form a first P-body region on a side of the first trench gate close to the second trench gate, and forming a second P-body region on a side of the second trench gate close to the first trench gate; Performing implantation of a first n+ emitter region and a second n+ emitter region on the surface of the first P body region and the second P body region, respectively, and performing implantation of an n+ ohmic contact region on the surface of the n-type carrier storage region; After depositing an insulating layer on the upper surface of the wafer, hole etching is performed, and further a first p+ ohmic contact region is implanted and a second p+ ohmic contact region is implanted at the opening; wherein the first n+ emitter region is located between the first trench gate and the first p+ ohmic contact region, the second n+ emitter region is located between the second trench gate and the second p+ ohmic contact region, and the orthographic projections of the first n+ emitter region and the first p+ ohmic contact region are located in the first opening of the insulating layer, the orthographic projections of the n+ ohmic contact region are located in the second opening of the insulating layer, and the orthographic projections of the second n+ emitter region and the second p+ ohmic contact region are located in the third opening of the insulating layer; Depositing a metal layer on the upper surface of the wafer to short-circuit the first n+ emitter region, the first p+ ohmic contact region, the second n+ emitter region, the second p+ ohmic contact region and the n+ ohmic contact region to form an emitter; Performing n field stop layer implantation on the lower surface of the wafer, and performing p+ collector region implantation and n+ short circuit region implantation on both sides of the lower surface of the n field stop layer respectively; Metal is deposited on the lower surface of the wafer and reversely etched to short-circuit the p+ collector region and the n+ short-circuit region to form a collector.

[0006] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides an RC-IGBT structure with low reverse recovery loss and a preparation method thereof. When the RC-IGBT structure is reversely conducted, electrons injected into an n+ short-circuit region can directly flow to an n+ ohmic contact region in an n-type carrier storage region after sequentially passing through an n-field stop layer, an n-drift region, and a P-well region, thereby reducing the electron density below an anode region of an integrated diode, thereby reducing the hole injection efficiency of the anode region, improving the reverse recovery speed of the integrated diode, and reducing the reverse recovery charge. The preparation process is simple.

[0007] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is the traditional RC-IGBT structure in the related art; Figure 2 It is a structural schematic diagram of a RC-IGBT structure with low reverse recovery loss provided by an embodiment of the present invention; Figure 3 It is a flow chart of a method for preparing a RC-IGBT structure with low reverse recovery loss provided by an embodiment of the present invention; Figures 4 to 14 It is a schematic diagram of the preparation process of the RC-IGBT structure with low reverse recovery loss provided by an embodiment of the present invention; Fig.15is a reverse conduction characteristic curve diagram of different RC-IGBT structures at room temperature provided by an embodiment of the present invention; Fig.16 4 is a reverse recovery characteristic curve diagram of different RC-IGBT structures at room temperature provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0009] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0010] Figure 1 It is the traditional RC-IGBT structure in the related technology. Figure 1 As shown, the conventional RC-IGBT structure includes: a collector 1'; a p+ collector region 2' and an n+ short-circuit region 3' located on the surface of the collector 1'; an n-field stop region 4' located on the surface of the p+ collector region 2' and the n+ short-circuit region 3'; an n-drift region 5' located on the surface of the n-field stop region 4'; a P-well region 6', a carrier storage region 7' ​​and a P-body region 8' located on the surface of the n-drift region 5' from bottom to top; two n+ emitter regions 9' located on the surface of the P-body region 8', and a p+ ohmic contact region 10' located between the two n+ emitter regions 9'; The conventional RC-IGBT structure further includes: two trench gates 11' arranged on both sides above the n-drift region 5'; an insulating layer 12' located on the surfaces of the two trench gates 11'; and an emitter 13' located on the surfaces of the insulating layer 12', the p+ ohmic contact region 10' and the two n+ emitter regions 9'.

[0011] The traditional RC-IGBT structure introduces an n+ short-circuit region 3' above the collector 1'. The n+ short-circuit region 3' and the p+ ohmic contact region 10' below the emitter 13' form a fast recovery diode integrated in the traditional RC-IGBT structure, which is referred to as an integrated diode below. The p+ ohmic contact region 10' serves as the anode region of the integrated diode, and the n+ short-circuit region 3' serves as the cathode region of the integrated diode. When reverse conduction occurs, a reverse voltage V is applied between the collector 1' and the emitter 13'. CE <0, the above integrated diode is forward biased, the p+ ohmic contact region 10' injects holes into the n-drift region 5', and the n+ short-circuit region 3' injects electrons into the n-drift region 5', thereby realizing the conduction of the integrated diode. However, since the p+ ohmic contact region 10' is heavily doped, the concentration on the anode side of the integrated diode is very high when it is turned on, which causes a high reverse recovery current peak to be generated when the integrated diode is turned off, thereby slowing down the reverse recovery speed and increasing the reverse recovery charge value.

[0012] Figure 2 Schematic diagram of the structure of the RC-IGBT structure with low reverse recovery loss provided by an embodiment of the present invention. Figure 2, an embodiment of the present invention provides a RC-IGBT structure with low reverse recovery loss, which includes, from bottom to top: an n+ short-circuit region 1, an n-field stop layer 2 located on the surface of the n+ short-circuit region 1, and an n-drift region 3 located on the surface of the n-field stop layer 2; The RC-IGBT further includes: a first trench gate 4, a second trench gate 5, a P-well region 6, an n-type carrier storage region 7, an n+ ohmic contact region 8, a first P-body region 9, a second P-body region 10, a first n+ emitter region 11, a second n+ emitter region 12, a first p+ ohmic contact region 13 and a second p+ ohmic contact region 14; wherein the first trench gate 4 and the second trench gate 5 are arranged above the n-drift region 3 relatively, the first P-body region 9 is located on a side of the first trench gate 4 close to the second trench gate 5, the second P-body region 10 is located on a side of the second trench gate 5 close to the first trench gate 4, the n-type carrier storage region 7 is located in the middle and below the first P-body region 9 and the second P-body region 10, the P-well region 6 is located between the n-type carrier storage region 7 and the n-drift region 3, and the n+ ohmic contact region 8 is located in the n-type carrier storage region 7 between the first P-body region 9 and the second P-body region 10, close to the upper surface position; The first p+ ohmic contact region 13 is located in the first P body region 9 near the upper surface, the first n+ emitter region 11 is located between the first trench gate 4 and the first p+ ohmic contact region 13 , the second p+ ohmic contact region 14 is located in the second P body region 10 near the upper surface, and the second n+ emitter region 12 is located between the second trench gate 5 and the second p+ ohmic contact region 14 .

[0013] Specifically, in this embodiment, n-type single crystal silicon is used as the n-drift region 3. Figure 2 From the perspective shown, the upper left and upper right of the n-drift region 3 are respectively the first trench gate 4 and the second trench gate 5, and between the two are a P-well region 6 (Pwell), an n-type carrier storage region 7, a first P-body region 9 and a second P-body region 10, wherein the P-well region 6 is located on the upper surface of the n-drift region 3, the first P-body region 9 is located on the side of the first trench gate 4 close to the second trench gate 5, that is, the right side of the first trench gate 4, the second P-body region 10 is located on the side of the second trench gate 5 close to the first trench gate 4, that is, the left side of the second trench gate 5, the n-type carrier storage region 7 is located in the middle and below the first P-body region 9 and the second P-body region 10, that is, the n-type carrier storage region 7 can be regarded as two parts, one part is between the two P-body regions, and the other part is on the upper surface of the P-well region 6. In addition, the bottoms of the first trench gate 4 and the second trench gate 5 are both lower than the bottom of the P-well region 6, that is, in a direction perpendicular to the plane where the RC-IGBT structure is located, the first trench gate 4 extends from the first P-body region 9 to the inside of the n-drift region 3, and the second trench gate 5 extends from the second P-body region 10 to the inside of the n-drift region 3.

[0014] For example, the depth of the P-well region 6 is 4 μm to 9 μm, and the doping concentration is 1×10 16 cm -3 ~ 3×10 17 cm -3 The depth of the n-type carrier storage region 7 is 3µm~7µm, and the doping concentration is 1×10 15 cm -3 ~ 1×10 17 cm -3 The depth of the first P body region 9 and the second P body region 10 is 1.5µm~4µm, and the doping concentration is 1×10 17 cm -3 ~ 5×10 17 cm -3 , the distance between the two is 1µm~3µm.

[0015] Furthermore, the above-mentioned RC-IGBT structure also includes a first n+ emitter region 11, a first p+ ohmic contact region 13, an n+ ohmic contact region 8, a second n+ emitter region 12 and a second p+ ohmic contact region 14. Specifically, the n+ ohmic contact region 8 is located in the n-type carrier storage region 7 and close to its upper surface. In the horizontal direction, the distance between the n+ ohmic contact region 8 and the first P body region 9 is equal to the distance between the n+ ohmic contact region 8 and the second P body region 10. The first n+ emitter region 11 and the first p+ ohmic contact region 13 are located in the first P body region 9 and close to the upper surface of the first P body region 9. The first n+ emitter region 11 is between the first trench gate 4 and the first p+ ohmic contact region 13. The second n+ emitter region 12 and the second p+ ohmic contact region 14 are located in the second P body region 10 and close to the upper surface of the second P body region 10. The second n+ emitter region 12 is between the second trench gate 5 and the second p+ ohmic contact region 14.

[0016] In addition, the RC-RGBT structure provided by the embodiment of the present invention also includes an n field stop layer 2 located on the lower surface of the n-drift region 3, and an n+ short-circuit region 1 located on the surface of the n field stop layer 2 (nFS layer) away from the n-drift region 3, wherein the n+ short-circuit region 1 and the first p+ ohmic contact region 13 and the second p+ ohmic contact region 14 form a fast recovery diode integrated in the RC-RGBT structure, hereinafter referred to as an integrated diode, the n+ short-circuit region 1 serves as the cathode region of the integrated diode, and the first p+ ohmic contact region 13 and the second p+ ohmic contact region 14 serve as the first anode region and the second anode region of the integrated diode, respectively. When the RC-IGBT structure is reversely conducted, the electrons injected into the n+ short-circuit region 1 can flow directly to the n+ ohmic contact region 8 in the n-type carrier storage region 7 after passing through the n field stop layer 2, the n- drift region 3, and the P-well region 6 in sequence, thereby reducing the electron density under the anode region of the integrated diode, thereby reducing the hole injection efficiency of the two anode regions, improving the reverse recovery speed of the integrated diode, reducing the reverse recovery charge, and having a simple preparation process.

[0017] Optionally, the RC-IGBT structure with low reverse recovery loss further includes a collector 15 and a p+ collector region 16, such as Figure 2 As shown, the p+ collector region 16 and the n+ short-circuit region 1 are disposed adjacent to the upper surface of the collector 15, that is, the lower surface of the n field stop layer 2, respectively on the left and right sides. The collector 15 can be an aluminum metallized collector.

[0018] Furthermore, the RC-IGBT structure with low reverse recovery loss also includes an emitter 17 and an insulating layer 18; The insulating layer 18 includes a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer, wherein the first insulating layer is located on the surface of the first trench gate 4, the fourth insulating layer is located on the surface of the second trench gate 5, and in a direction perpendicular to the plane where the n-drift region 3 is located, the orthographic projection of the second insulating layer is located between the orthographic projection of the first p+ ohmic contact region 13 and the orthographic projection of the n+ ohmic contact region 8, and the orthographic projection of the third insulating layer is located between the orthographic projection of the second p+ ohmic contact region 14 and the orthographic projection of the n+ ohmic contact region 8; the emitter 17 is located on the surfaces of the insulating layer 18, the first n+ emitter region 11, the first p+ ohmic contact region 13, the n+ ohmic contact region 8, the second p+ ohmic contact region 14 and the second n+ emitter region 12.

[0019] Specifically, an aluminum metallized emitter 17 is provided on the upper surfaces of the first n+ emitter region 11, the second n+ emitter region 12, the first p+ ohmic contact region 13, the second p+ ohmic contact region 14 and the n+ ohmic contact region 8, and the insulating layer 18 includes a first insulating layer to a fourth insulating layer, the first insulating layer is located on the upper surface of the first trench gate 4, the second insulating layer is located on the upper surface of part of the first P body region 9 and part of the n-type carrier storage region 7, and its orthographic projection is located between the first p+ ohmic contact region 13 and the n+ ohmic contact region 8, the third insulating layer is located on the upper surface of part of the second P body region 10 and part of the n-type carrier storage region 7, and its orthographic projection is located between the second p+ ohmic contact region 14 and the n+ ohmic contact region 8, and the fourth insulating layer is located on the upper surface of the second gate trench.

[0020] In this embodiment, the first trench gate 4 and the second trench gate 5 have a depth of 5µm to 10µm and a width of 1µm to 4µm, and both have the same structure, including: Groove 19; A gate oxide layer 20 located on the inner surface of the trench 19; A heavily doped polysilicon layer 21 is located on the surface of the gate oxide layer 20 .

[0021] The following describes the various working stages of the RC-IGBT structure with low reverse recovery loss provided by the present invention: (1) When the RC-IGBT structure is blocked, the two trench gate-emitter electrodes are both connected to zero potential (i.e. ), a forward voltage is applied between the collector and emitter (i.e. ), the Pwell / n-drift region junction is reverse biased, and the n-drift region 3 is completely depleted and bears the applied forward voltage.

[0022] (2) When the RC-IGBT structure is forward conducting (IGBT is turned on), a forward voltage is applied between the collector and emitter ( ) and a positive voltage is applied between the two trench gate-emitter Greater than the threshold voltage When the electron current is in the p state, the electrons in the first n+ emitter region 11 and the second n+ emitter region 12 will flow through the longitudinal channels on the side walls of the first trench gate 4 and the second trench gate 5, directly enter the n- drift region 3, and then flow to the n+ short-circuit region 1. At this time, the RC-IGBT structure is turned on in the unipolar mode of the power MOSFET. + When the voltage drop generated above the collector region 16 is greater than the turn-on voltage of the p+ collector region / nFS junction, the p+ collector region 16 injects holes into the n-drift region 3. At this time, the RC-IGBT structure is turned on in the bipolar mode of the IGBT and has a lower saturation voltage.

[0023] (3) When the RC-IGBT structure is turned off, a reverse voltage is applied between the two trench gate-emitter electrodes ( ), a forward voltage is applied between the collector and emitter ( ), both the lateral channel and the longitudinal channel will disappear, making it impossible for the electrons of the emitter 17 to be injected into the n-drift region 3, and the IGBT starts the shutdown process; when shutting down, the n+ short-circuit region 1 can quickly extract electrons, so that the RC-IGBT structure obtains a much faster shutdown speed than the IGBT.

[0024] (4) When the RC-IGBT structure is reverse-conducting (the integrated diode is turned on), a reverse voltage is applied between the collector (cathode of the integrated diode) and the emitter (anode of the integrated diode). ), that is, a forward voltage is applied between the anode and cathode of the integrated diode ( ), and a reverse voltage is applied between the two trench gate-emitters ( ). The first p+ ohmic contact region 13 and the second p+ ohmic contact region 14 inject holes into the n-drift region 3, and the n+ short-circuit region 1 injects electrons into the n-drift region 3, which directly flow to the n+ ohmic contact region 8 in the n-type carrier storage region 7 through the n-drift region 3 and the P-well region 6, so that the electron density below the first p+ ohmic contact region 13 and the second p+ ohmic contact region 14 is reduced, thereby reducing the hole injection efficiency of the anode of the integrated diode, so that the carrier concentration gradient on the anode side is reduced when it is turned on, so as to improve the reverse recovery characteristics of the integrated diode.

[0025] (5) A forward voltage is applied between the collector 15 (cathode of the integrated diode) and the emitter (anode of the integrated diode) of the RC-IGBT structure ( ), that is, a reverse voltage is applied between the anode and cathode of the integrated diode ( ), and a reverse voltage is applied between the two trench gate-emitters ( ), the integrated diode enters the reverse recovery stage. During the conduction period, a large number of unbalanced carriers stored in the n-drift region 3 continuously recombine, and the external voltage can accelerate the extraction of unbalanced carriers and shorten the reverse recovery time of the integrated diode.

[0026] Figure 3 is a flow chart of a method for preparing a RC-IGBT structure with low reverse recovery loss provided by an embodiment of the present invention, Figures 4 to 14 Schematic diagram of the preparation process of the RC-IGBT structure with low reverse recovery loss provided by the embodiment of the present invention. Figures 2~14 The embodiment of the present invention further provides a method for preparing a RC-IGBT structure with low reverse recovery loss, comprising: S1. Provide a silicon wafer; S2, sequentially injecting the P-well region 6 and the n-type carrier storage region 7 on the surface of the silicon wafer to form the n-drift region 3, the P-well region 6 and the n-type carrier storage region 7 from bottom to top; S3, digging a first trench and a second trench on both sides of the wafer respectively, forming a gate oxide layer 20 on the inner surface of the first trench and then filling it with heavily doped polysilicon, and forming a gate oxide layer 20 on the inner surface of the second trench and then filling it with heavily doped polysilicon, to form a first trench gate 4 and a second trench gate 5; S4, implanting a P body region into the upper surface of the wafer, forming a first P body region 9 on a side of the first trench gate 4 close to the second trench gate 5, and forming a second P body region 10 on a side of the second trench gate 5 close to the first trench gate 4; S5, implanting the first n+ emitter region 11 and the second n+ emitter region 12 on the surface of the first P body region 9 and the second P body region 10 respectively, and implanting the n+ ohmic contact region 8 on the surface of the n-type carrier storage region 7; S6. After depositing an insulating layer 18 on the upper surface of the wafer, hole etching is performed, and further the first p+ ohmic contact region 13 and the second p+ ohmic contact region 14 are injected into the opening; wherein the first n+ emitter region 11 is located between the first trench gate 4 and the first p+ ohmic contact region 13, the second n+ emitter region 12 is located between the second trench gate 5 and the second p+ ohmic contact region 14, and the orthographic projections of the first n+ emitter region 11 and the first p+ ohmic contact region 13 are located in the first opening of the insulating layer 18, the orthographic projection of the n+ ohmic contact region 8 is located in the second opening of the insulating layer 18, and the orthographic projections of the second n+ emitter region 12 and the second p+ ohmic contact region 14 are located in the third opening of the insulating layer 18; S7, depositing a metal layer on the upper surface of the wafer to short-circuit the first n+ emitter region 11, the first p+ ohmic contact region 13, the second n+ emitter region 12, the second p+ ohmic contact region 14 and the n+ ohmic contact region 8 to form an emitter 17; S8, performing an n field stop layer 2 injection on the lower surface of the wafer, and performing a p+ collector region 16 injection and an n+ short circuit region 1 injection on both sides of the lower surface of the n field stop layer 2 respectively; S9. Deposit metal on the lower surface of the chip and reverse etch it to short-circuit the p+ collector region 16 and the n+ short-circuit region 1 to form a collector electrode 15.

[0027] Next, the reverse conduction performance and reverse recovery performance of the RC-IGBT structure with low reverse recovery loss provided by the present invention are further described through simulation experiments.

[0028] Fig.15: is a reverse conduction characteristic curve diagram of different RC-IGBT structures provided by the embodiment of the present invention at room temperature, wherein the horizontal axis represents the voltage drop of the integrated diode, and the vertical axis represents the current density of the integrated diode. Specifically, the reverse conduction performance curves of the RC-LIGBT structure with improved reverse recovery performance of the integrated diode provided by the present invention and the traditional RC-IGBT structure at room temperature (300K) are as follows: Fig.15 As shown, at room temperature (300K), the anode current density is 100A / cm 2 When the reverse conduction voltage drop of the conventional RC-IGBT structure is about 1.02V, the reverse conduction voltage drop of the RC-IGBT structure provided by the present invention is about 1.45V.

[0029] Fig.16 : is a reverse recovery characteristic curve diagram of different RC-IGBT structures provided by the embodiment of the present invention at room temperature, wherein the horizontal axis represents time and the vertical axis represents the current density of the integrated diode. Specifically, the reverse recovery performance curves of the RC-LIGBT structure with improved integrated diode reverse recovery performance provided by the present invention and the traditional RC-IGBT structure at room temperature (300K) are as follows: Fig.16 As shown in the figure, in the traditional RC-IGBT structure, the peak reverse recovery current density of the integrated diode is 366.6A / cm 2 , the reverse recovery charge is about 270µC / cm 2 In the RC-IGBT structure provided by the present invention, the peak reverse recovery current density of the integrated diode is 258.7A / cm 2 , the reverse recovery charge is about 170µC / cm 2 , compared with the traditional RC-IGBT structure, they are reduced by 29.4% and 37% respectively. Obviously, under the same test conditions, compared with the traditional RC-IGBT structure, the reverse recovery time of the integrated diode in the RC-IGBT structure provided by the present invention is greatly reduced.

[0030] It can be seen from the above embodiments that the beneficial effects of the present invention are: The present invention provides an RC-IGBT structure with low reverse recovery loss and a preparation method thereof. When the RC-IGBT structure is reversely conducted, electrons injected into an n+ short-circuit region can directly flow to an n+ ohmic contact region in an n-type carrier storage region after sequentially passing through an n-field stop layer, an n-drift region, and a P-well region, thereby reducing the electron density below an anode region of an integrated diode, thereby reducing the hole injection efficiency of the anode region, improving the reverse recovery speed of the integrated diode, and reducing the reverse recovery charge. The preparation process is simple.

[0031] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0032] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0033] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the present application for which protection is sought, a person skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims.

[0034] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A RC-IGBT structure with low reverse recovery loss, characterized in that: The invention comprises, from bottom to top, an n+ short-circuit region, an n-field stop layer located on the surface of the n+ short-circuit region, and an n-drift region located on the surface of the n-field stop layer; The RC-IGBT further comprises: a first trench gate, a second trench gate, a P-well region, an n-type carrier storage region, an n+ ohmic contact region, a first P-body region, a second P-body region, a first n+ emitter region, a second n+ emitter region, a first p+ ohmic contact region, and a second p+ ohmic contact region; wherein the first trench gate and the second trench gate are arranged above the n-drift region relatively, the first P-body region is located on a side of the first trench gate close to the second trench gate, the second P-body region is located on a side of the second trench gate close to the first trench gate, the n-type carrier storage region is located in the middle and below the first P-body region and the second P-body region, the P-well region is located between the n-type carrier storage region and the n-drift region, and the n+ ohmic contact region is located in the n-type carrier storage region between the first P-body region and the second P-body region, and the n+ ohmic contact region is located near the upper surface. The first p+ ohmic contact region is located in the first P body region near the upper surface, the first n+ emitter region is located between the first trench gate and the first p+ ohmic contact region, the second p+ ohmic contact region is located in the second P body region near the upper surface, and the second n+ emitter region is located between the second trench gate and the second p+ ohmic contact region.

2. The RC-IGBT structure with low reverse recovery loss according to claim 1, characterized in that: It also includes a collector and a p+ collector region; The p+ collector region and the n+ short-circuit region are disposed adjacent to the upper surface of the collector electrode.

3. The RC-IGBT structure with low reverse recovery loss according to claim 2, characterized in that: Also includes an emitter and an insulating layer; The insulating layer includes a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer, wherein the first insulating layer is located on the surface of the first trench gate, the fourth insulating layer is located on the surface of the second trench gate, and in a direction perpendicular to the plane where the n-drift region is located, the orthographic projection of the second insulating layer is located between the orthographic projection of the first p+ ohmic contact region and the orthographic projection of the n+ ohmic contact region, and the orthographic projection of the third insulating layer is located between the orthographic projection of the second p+ ohmic contact region and the orthographic projection of the n+ ohmic contact region; the emitter is located on the surfaces of the insulating layer, the first n+ emitter region, the first p+ ohmic contact region, the n+ ohmic contact region, the second p+ ohmic contact region and the second n+ emitter region.

4. The RC-IGBT structure with low reverse recovery loss according to claim 1, characterized in that: The first trench gate and the second trench gate have the same structure, and both include: Grooves; a gate oxide layer located on the inner surface of the trench; A heavily doped polysilicon layer is located on the surface of the gate oxide layer.

5. The RC-IGBT structure with low reverse recovery loss according to claim 1, characterized in that: The first trench gate and the second trench gate have a depth of 5µm-10µm and a width of 1µm-4µm.

6. The RC-IGBT structure with low reverse recovery loss according to claim 5, characterized in that: The depth of the P-well region is 4µm~9µm, and the doping concentration is 1×10 16 cm -3 ~ 3×10 17 cm -3 .

7. The RC-IGBT structure with low reverse recovery loss according to claim 6, characterized in that: The depth of the n-type carrier storage region is 3µm~7µm, and the doping concentration is 1×10 15 cm -3 ~ 1×10 17 cm -3 .

8. The RC-IGBT structure with low reverse recovery loss according to claim 7, characterized in that: The depth of the first P body region and the second P body region is 1.5µm~4µm, and the doping concentration is 1×10 17 cm -3 ~ 5×10 17 cm -3 .

9. The RC-IGBT structure with low reverse recovery loss according to claim 8, characterized in that: The distance between the first P body region and the second P body region is 1µm~3µm.

10. A method for preparing a RC-IGBT structure with low reverse recovery loss, characterized in that: include: Providing a silicon wafer; Performing P-well region injection and n-type carrier storage region injection in sequence on the surface of the silicon wafer to form an n-drift region, a P-well region and an n-type carrier storage region from bottom to top; Digging a first trench and a second trench on both sides of the wafer respectively, filling heavily doped polysilicon after forming a gate oxide layer on the inner surface of the first trench, and filling heavily doped polysilicon after forming a gate oxide layer on the inner surface of the second trench, to form a first trench gate and a second trench gate; Performing P-body region implantation on the upper surface of the wafer to form a first P-body region on a side of the first trench gate close to the second trench gate, and forming a second P-body region on a side of the second trench gate close to the first trench gate; Performing implantation of a first n+ emitter region and a second n+ emitter region on the surface of the first P body region and the second P body region, respectively, and performing implantation of an n+ ohmic contact region on the surface of the n-type carrier storage region; After depositing an insulating layer on the upper surface of the wafer, hole etching is performed, and further a first p+ ohmic contact region is implanted and a second p+ ohmic contact region is implanted at the opening; wherein the first n+ emitter region is located between the first trench gate and the first p+ ohmic contact region, the second n+ emitter region is located between the second trench gate and the second p+ ohmic contact region, and the orthographic projections of the first n+ emitter region and the first p+ ohmic contact region are located in the first opening of the insulating layer, the orthographic projections of the n+ ohmic contact region are located in the second opening of the insulating layer, and the orthographic projections of the second n+ emitter region and the second p+ ohmic contact region are located in the third opening of the insulating layer; Depositing a metal layer on the upper surface of the wafer to short-circuit the first n+ emitter region, the first p+ ohmic contact region, the second n+ emitter region, the second p+ ohmic contact region and the n+ ohmic contact region to form an emitter; Performing n field stop layer implantation on the lower surface of the wafer, and performing p+ collector region implantation and n+ short circuit region implantation on both sides of the lower surface of the n field stop layer respectively; Metal is deposited on the lower surface of the wafer and reversely etched to short-circuit the p+ collector region and the n+ short-circuit region to form a collector.

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