Super junction MOSFET device

Abstract

A first contact hole at the top of a source region is directly composed of a material layer of a front metal layer filled in an opening of the first contact hole, the front metal layer is made of AlSiCu, and the content of Si in the AlSiCu reaches a saturation value; the AiSiCu of the first contact hole directly forms ohmic contact with the source region and the semiconductor material of the first epitaxial layer of the second conductive type well, and by utilizing the characteristic that the content of Si in the AlSiCu reaches a saturation value, the sharp convex defect is prevented from being formed when the A1Cu directly contacts with the semiconductor material of the first epitaxial layer; by utilizing the characteristic that the resistivity of AlSiCu is greater than that of AlCu, the forward conduction voltage drop of the body diode is increased, and the reverse recovery characteristic of the device is improved. The reverse recovery charge can be reduced, and the reverse recovery characteristic of the device can be improved.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit, and in particular to a super junction MOSFET device. Background Art

[0002] Compared with traditional VDMOS, super junction MOSFET has been widely used in various electronic power fields due to its excellent device characteristics. Due to the special N column and P column in the super junction MOSFET structure, the area of ​​the PN built-in electric field is expanded, so that it can achieve a high breakdown voltage on a denser NEPI epitaxial substrate. Therefore, super junction MOSFET has a low on-resistance and high breakdown voltage that exceeds the limit of Si.

[0003] There are two major challenges in superjunction MOSFET devices. One is that the device process is relatively complex, and the other is that the reverse recovery characteristics of the device are poor. Since the superjunction MOSFET itself has a large PN junction area, the parasitic body diode will inject more minority carrier charges when it is turned on; the lateral depletion rate of the N column and the P column is fast, which can easily cause current overshoot. Therefore, the reverse recovery characteristics of the superjunction MOSFET are manifested as a larger reverse recovery charge (larger reverse recovery current and longer reverse recovery time) and a harder reverse recovery curve, which ultimately increases the power consumption of the device and reduces the application reliability.

[0004] The main solution to improve the reverse recovery characteristics is to add a buffer layer at the bottom of the P column or N column to slow down the depletion rate of the N column and the P column and obtain softer reverse recovery characteristics. However, this method often increases the reverse recovery charge. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a super junction MOSFET device which can reduce the reverse recovery charge and improve the reverse recovery characteristics of the device.

[0006] In order to solve the above technical problems, the super junction MOSFET device provided by the present invention comprises:

[0007] A super junction structure is formed in a first epitaxial layer doped with a first conductivity type, wherein the super junction structure includes first conductivity type columns and second conductivity type columns that are alternately arranged.

[0008] The first epitaxial layer at the bottom of the super junction structure serves as a buffer layer.

[0009] In the active region, a plurality of parallel device unit structures are formed in the top region of the super junction structure.

[0010] The device unit structure includes a gate structure, a second conductivity type well and a first conductivity type heavily doped source region.

[0011] The second conductivity type well is formed in a top region of the second conductivity type column and extends into the first conductivity type column, and the drift region includes the first conductivity type column and the buffer layer located outside or at the bottom of the second conductivity type well.

[0012] The surface of the second conductive type well covered by the gate structure is used to form a conductive channel connecting the source region and the drift region.

[0013] The body diode is a parasitic diode formed by the second conductivity type well and the drift region.

[0014] The source region and the top of the second conductive type well are connected to the source metal composed of the front metal layer through a first contact hole; the first contact hole passes through the source region and contacts the second conductive type well.

[0015] The first contact hole is directly composed of a material layer of the front metal layer filling the opening of the first contact hole, and the material of the front metal layer is AlSiCu, and the Si content in AlSiCu reaches above the saturation value; the AlSiCu of the first contact hole directly forms an ohmic contact with the semiconductor material of the first epitaxial layer of the source region and the second conductive type well, and utilizes the characteristic that the Si content in AlSiCu reaches above the saturation value to prevent the formation of sharp convex defects when AlCu directly contacts the semiconductor material of the first epitaxial layer; utilizes the characteristic that the resistivity of AlSiCu is greater than the resistivity of AlCu to increase the forward conduction voltage drop of the body diode and improve the reverse recovery characteristics of the device.

[0016] A further improvement is that the gate structure includes a gate dielectric layer and a gate conductive material layer; the top of the gate conductive material layer is connected to the gate metal composed of the front metal layer through a second contact hole; and the second contact hole is directly composed of a material layer of the front metal layer filling the second contact hole opening.

[0017] A further improvement is that the gate structure is a planar gate or a trench gate.

[0018] A further improvement is that the second conductivity type column includes a second conductivity type doped second epitaxial layer filled in the super junction trench, and the first conductivity type column includes the first epitaxial layer located between the super junction trenches.

[0019] A further improvement is that a transition region surrounds the active region, and a termination region surrounds the transition region.

[0020] The second conductivity type well also extends into the transition region.

[0021] A further improvement is that the first epitaxial layer is formed on the top surface of the semiconductor substrate.

[0022] A drain region heavily doped with the first conductivity type is formed on the back side of the drift region, and the drain region is composed of the thinned semiconductor substrate heavily doped with the first conductivity type or a back ion implantation region heavily doped with the first conductivity type formed in the thinned semiconductor substrate.

[0023] A further improvement is that the material of the semiconductor substrate includes silicon.

[0024] The material of the first epitaxial layer includes silicon.

[0025] A further improvement is that the Si content in the AlSiCu of the front metal layer is greater than or equal to 1%.

[0026] A further improvement is that the thickness of the front metal layer is 4 μm to 5 μm.

[0027] A further improvement is that increasing the Si content in the AlSiCu of the front metal layer will increase the threshold voltage of the device.

[0028] An initial design value of the implantation dose of the second conductive type well is determined by the AlCu material, and an actual value of the implantation dose of the second conductive type well is reduced based on the initial design value and is determined according to the increase in the threshold voltage caused by the Si content in the AlSiCu of the front metal layer.

[0029] A further improvement is that the actual value of the implantation dose of the second conductive type well is in the range of 5E12cm -2 ~5E13cm -2 .

[0030] A further improvement is that the active region is defined by a protective epoxy film, and the protective epoxy film covers the top surface of the first epitaxial layer in the transition region and the termination region.

[0031] A further improvement is that a third contact hole is formed in the transition region and the terminal region, and the third contact hole is composed of the front metal layer filling the third contact hole opening.

[0032] The first contact hole passes through the interlayer film and a portion of the thickness of the first epitaxial layer; the first contact hole passes through the thickness of the first epitaxial layer to ensure passing through the source region.

[0033] The third contact hole passes through the interlayer film and the protective epoxy film and contacts the first epitaxial layer, and the thickness of the first epitaxial layer through which the third contact hole passes is smaller than the thickness of the first epitaxial layer through which the first contact hole passes.

[0034] A further improvement is that the thickness of the first contact hole through the first epitaxial layer is The thickness of the third contact hole passing through the first epitaxial layer is less than

[0035] A further improvement is that the super junction MOSFET device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the super junction MOSFET device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0036] In view of the adverse effects on the reverse recovery characteristics of the device caused by the large PN junction area and the fast lateral depletion speed brought about by the super junction structure in the super junction MOSFET device, the present invention makes special arrangements for the metal materials of the contact hole and the front metal layer. The filling metal of the contact hole is directly filled with the front metal layer, and the material of the front metal layer is set to AlSiCu, that is, Si is added to AlCu and the content of Si is specially set. The Si content in AlSiCu reaches above the saturation value, so that AlSiCu can be directly contacted with the material of the first epitaxial layer without using a barrier layer such as a superimposed layer of Ti and TiN. The material of the first epitaxial layer usually includes Si. Since the Si in AlSiCu is saturated, the Si in the first epitaxial layer will no longer diffuse into AlSiCu, so the resulting convex defects can be avoided.

[0037] When both the contact hole and the front metal layer are made of AlSiCu, compared with the prior art in which the metal material of the contact hole is W and the material of the front metal layer is AlCu, the resistivity of AlSiCu is slightly larger than that of AlCu, which increases the forward conduction resistance of the body diode of the present invention and reduces the forward conduction current. The reduction in the forward conduction current will reduce the stored charge generated by the body diode during the conduction process, and the corresponding reverse recovery charge will also be reduced, thereby reducing the reverse recovery time and the reverse recovery current, thereby improving the reverse recovery characteristics of the device and making the reverse recovery curve softer. Therefore, the present invention can obtain a softer reverse recovery characteristic while reducing the reverse recovery charge.

[0038] At the same time, compared with the direct use of AlCu material for the front metal layer, after the incorporation of Si, the AlSiCu material will increase the threshold voltage of the device, such as the threshold voltage of the NMOS device. In order to compensate for the increase in the threshold voltage of the device, the doping concentration of the second conductive type well can be further reduced. After the doping concentration of the second conductive type well is reduced, the amount of second conductive type charge injection into the body diode can be reduced, thereby further improving the reverse recovery characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0040] Figure 1 is a schematic structural diagram of a super junction MOSFET device according to an embodiment of the present invention;

[0041] Figure 2A-2E Schematic diagram of the device structure in each step of the method for manufacturing a super junction MOSFET device according to an embodiment of the present invention;

[0042] Figure 3 It is the reverse recovery characteristic curve of the body diode of the super junction MOSFET device according to the embodiment of the present invention and the existing super junction MOSFET device. DETAILED DESCRIPTION

[0043] In order to overcome the deficiencies in the existing technology, the applicant has further analyzed the existing super junction MOSFET devices:

[0044] In existing super junction MOSFET devices, the metal electrode is formed by patterning the front metal layer, and the bottom of the metal electrode is connected to the corresponding contact hole. The material of the front metal layer is usually AlCu, and the filling metal of the contact hole is tungsten. Usually, before tungsten fills the contact hole opening, a barrier layer formed by Ti and TiN, that is, a Ti layer and a TiN layer, is formed, and then metal tungsten is filled and the tungsten on the outer surface of the contact hole opening is removed, and then the AlCu layer is formed. Ti and TiN are to prevent Si in the bottom epitaxial layer from dissolving in AlCu and thus prevent the formation of sharp protrusions caused by the dissolution of Si. The metal electrode in the prior art has the advantage of low on-resistance. In order to improve the reverse recovery characteristics of the super junction device, the applicant has set his sights on how to improve the materials of the metal electrodes such as the contact holes and the front metal layer to improve the reverse recovery characteristics of the super junction device. Finally, the embodiment of the present invention increases the forward conduction voltage drop of the body diode, reduces the reverse recovery charge, and increases the softness of the reverse recovery characteristic curve by adopting AlSiCu as the metal electrode material of the super junction MOSFET device. The following is combined with Figure 1 The super junction MOSFET device according to the embodiment of the present invention is further described in detail:

[0045] like Figure 1 , which is a schematic diagram of the structure of a super junction MOSFET device according to an embodiment of the present invention; the super junction MOSFET device according to an embodiment of the present invention comprises:

[0046] The super junction structure is formed in the first epitaxial layer 2 doped with the first conductivity type, and the super junction structure includes first conductivity type columns and second conductivity type columns 4 which are alternately arranged.

[0047] In the embodiment of the present invention, the second conductivity type column 4 includes a second conductivity type doped second epitaxial layer filled in the super junction trench 3 , and the first conductivity type column includes a first epitaxial layer 2 located between the super junction trenches 3 .

[0048] The first epitaxial layer 2 at the bottom of the super junction structure serves as a buffer layer.

[0049] In the active region, a plurality of parallel device unit structures are formed in the top region of the super junction structure. Figure 1 Only the structure in the active region is shown in the figure, and the active region is surrounded by a transition region (not shown) and a termination region (not shown) on the periphery of the transition region.

[0050] The device unit structure includes a gate structure, a second conductivity type well 8 and a first conductivity type heavily doped source region 9 .

[0051] In the embodiment of the present invention, the second conductivity type well 8 also extends into the transition region.

[0052] In the embodiment of the present invention, the gate structure includes a gate dielectric layer 6 and a gate conductive material layer 7. In some embodiments, the gate dielectric layer 6 is made of silicon dioxide, and the gate conductive material layer 7 is made of polysilicon.

[0053] In the embodiment of the present invention, the gate structure is a trench gate. The gate dielectric layer 6 is formed on the inner surface of the gate trench 5, and the gate conductive material layer 7 is filled in the gate trench 5. The gate trench 5 vertically passes through the second conductive type well 8. In other embodiments, the gate structure can also be a planar gate.

[0054] The second conductive type well 8 is formed in the top region of the second conductive type column 4 and extends into the first conductive type column, and the drift region includes the first conductive type column and the buffer layer located outside or at the bottom of the second conductive type well 8. When the gate structure is a trench gate, generally, the second conductive type well 8 is located in the top region of the first conductive type column and the second conductive type column 4 between each gate trench 5. In other embodiments, when the gate structure is a planar gate, the second conductive type well 8 on both sides of the first conductive type column has a gap.

[0055] The surface of the second conductivity type well 8 covered by the gate structure is used to form a conductive channel connecting the source region 9 and the drift region.

[0056] The body diode is a parasitic diode formed by the second conductivity type well 8 and the drift region.

[0057] The source region 9 and the top of the second conductive type well 8 are connected to the source metal composed of the front metal layer 12 through the first contact hole 11; the first contact hole 11 passes through the source region 9 and contacts the second conductive type well 8.

[0058] The first contact hole 11 is directly composed of a material layer of the front metal layer 12 filling the opening of the first contact hole 11, and the material of the front metal layer 12 is AlSiCu, and the Si content in AlSiCu reaches above the saturation value; the AlSiCu of the first contact hole 11 directly forms an ohmic contact with the semiconductor material of the first epitaxial layer 2 of the source region 9 and the second conductive type well 8, and utilizes the characteristic that the Si content in AlSiCu reaches above the saturation value to prevent the formation of sharp convex defects when AlCu directly contacts the semiconductor material of the first epitaxial layer 2; utilizes the characteristic that the resistivity of AlSiCu is greater than the resistivity of AlCu to increase the forward conduction voltage drop of the body diode and improve the reverse recovery characteristics of the device.

[0059] In some embodiments, the Si content in the AlSiCu of the front metal layer 12 is greater than or equal to 1%.

[0060] The thickness of the front metal layer 12 is 4 μm to 5 μm.

[0061] In the embodiment of the present invention, the top of the gate conductive material layer 7 is connected to the gate metal composed of the front metal layer 12 through the second contact hole, and the second contact hole and the gate metal are not located at Figure 1 On the corresponding cross section, Figure 1 The second contact hole and the gate metal are not shown; the second contact hole is directly composed of a material layer of the front metal layer 12 filling the second contact hole opening.

[0062] In the embodiment of the present invention, the first epitaxial layer 2 is formed on the top surface of the semiconductor substrate 1 .

[0063] A drain region heavily doped with the first conductivity type is formed on the back side of the drift region. The drain region is composed of a thinned semiconductor substrate 1 heavily doped with the first conductivity type or a back ion implantation region heavily doped with the first conductivity type formed in the thinned semiconductor substrate 1 .

[0064] The material of the semiconductor substrate 1 includes silicon.

[0065] The material of the first epitaxial layer 2 includes silicon.

[0066] In the embodiment of the present invention, an increase in the Si content in the AlSiCu of the front metal layer 12 will increase the threshold voltage of the device.

[0067] The initial design value of the implantation dose of the second conductive type well 8 is determined by the AlCu material, and the actual value of the implantation dose of the second conductive type well 8 is reduced on the basis of the initial design value and determined according to the increase in the threshold voltage caused by the Si content in the AlSiCu of the front metal layer 12. In some embodiments, the actual value of the implantation dose of the second conductive type well 8 is in the range of 5E12cm -2 ~5E13cm-2 .

[0068] In the embodiment of the present invention, the active region is defined by a protective epoxy film (not shown) covering the top surface of the first epitaxial layer 2 in the transition region and the termination region.

[0069] A third contact hole is formed in the transition region and the terminal region, and the third contact hole is composed of a front metal layer 12 filling the third contact hole opening. The third contact hole can connect the doped region formed in the transition region or the terminal region and the field plate composed of the front metal layer 12.

[0070] The first contact hole 11 passes through the interlayer film 10 and a portion of the thickness of the first epitaxial layer 2 ; the first contact hole 11 passes through the thickness of the first epitaxial layer 2 to ensure passing through the source region 9 .

[0071] The third contact hole passes through the interlayer film 10 and the protective epoxy film and contacts the first epitaxial layer 2 , and the thickness of the first epitaxial layer 2 passed through the third contact hole is smaller than the thickness of the first epitaxial layer 2 passed through the first contact hole 11 .

[0072] In some embodiments, the first contact hole 11 passes through the first epitaxial layer 2 to a thickness of The thickness of the third contact hole through the first epitaxial layer 2 is less than

[0073] In the embodiment of the present invention, the super junction MOSFET device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the super junction MOSFET device can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0074] In view of the adverse effects on the reverse recovery characteristics of the device caused by the large PN junction area and the fast lateral depletion speed brought about by the super junction structure in the super junction MOSFET device, the embodiment of the present invention makes special arrangements for the metal materials of the contact hole and the front metal layer 12. The filling metal of the contact hole is directly filled with the front metal layer 12, and the material of the front metal layer 12 is set to AlSiCu, that is, Si is added to AlCu and the Si content is specially set. The Si content in AlSiCu reaches above the saturation value. In this way, it is possible to directly make AlSiCu and the material of the first epitaxial layer 2 contact without using a barrier layer such as a stacking layer of Ti and TiN. The material of the first epitaxial layer 2 usually includes Si. Since the Si in AlSiCu is saturated, the Si in the first epitaxial layer 2 will no longer diffuse into AlSiCu, so the resulting sharp convex defects can be avoided.

[0075] When both the contact hole and the front metal layer 12 are made of AlSiCu, compared with the prior art in which the metal material of the contact hole is W and the material of the front metal layer 12 is AlCu, the resistivity of AlSiCu is slightly larger than that of AlCu, which will increase the forward conduction resistance of the body diode of the embodiment of the present invention and reduce the forward conduction current. The reduction in the forward conduction current will reduce the stored charge generated by the body diode during the conduction process, and the corresponding reverse recovery charge will also be reduced, which will reduce the reverse recovery time and reverse recovery current, thereby improving the reverse recovery characteristics of the device and making the reverse recovery curve softer. Therefore, the embodiment of the present invention can obtain a softer reverse recovery characteristic while reducing the reverse recovery charge.

[0076] At the same time, compared with the front metal layer 12 directly using AlCu material, after being doped with Si, the AlSiCu material will increase the threshold voltage of the device, such as the threshold voltage of the NMOS device. In order to compensate for the increase in the threshold voltage of the device, the doping concentration of the second conductive type well 8 can be further reduced. After the doping concentration of the second conductive type well 8 is reduced, the second conductive type charge injection amount of the body diode can be reduced, thereby further improving the reverse recovery characteristics of the device.

[0077] The embodiment of the present invention adopts AlSiCu metal process, that is, deposits AlSiCu as the electrode material of the source and gate of the super junction MOSFET, and improves the reverse recovery characteristics of the body diode by optimizing the metal electrode composition. In order to further illustrate the super junction MOSFET of the embodiment of the present invention, the following is a further explanation in combination with the manufacturing method and the corresponding parameters:

[0078] like FIG. 2A to FIG. 2E FIG. 1 is a schematic diagram of the device structure in each step of the manufacturing method of the super junction MOSFET device according to an embodiment of the present invention; taking a 600V trench gate N-type super junction MOSFET as an example, the corresponding wafer manufacturing process includes the following steps:

[0079] 1. As Figure 2A As shown, firstly, a first N-type epitaxial layer 2 is grown on a low resistivity N-type semiconductor substrate 1, i.e., a silicon substrate. The first epitaxial layer 2 has a thickness of 50 μm and adopts double-layer epitaxy. The top resistivity is 0.85 ohm.cm and the bottom resistivity is 1.05 ohm.cm. In actual production, single-layer, double-layer, and multi-layer N-type epitaxy with different resistivities are common.

[0080] 2. If Figure 2B As shown, a super junction trench 3 is formed.

[0081] The sub-steps of forming the super junction trench 3 include:

[0082] Then, a dielectric film is deposited on the first epitaxial layer 2, and several super junction trenches 3 with a certain aspect ratio are formed by etching in the first epitaxial layer 2 by photolithography. Generally, the width of the super junction trench 3 of a 600V super junction product is 3.2μm, and the distance between the super junction trenches 3 is 3.8μm. The depth of the super junction trench 3 is 40-45μm. According to the characteristics of different products and the selection of epitaxial substrates, the trench width, spacing and width can be adjusted accordingly. Generally, for the above-mentioned type of super junction products (N-type epitaxial thickness 50μm), the trench depth will not exceed 47μm, and a buffer layer of a certain thickness needs to be left at the bottom of the trench, which is beneficial to the device's ability to resist current shock. After the super junction trench 3 morphology etching is completed, a dielectric film needs to be left at the bottom of the super junction trench 3, which can be an oxide film or a SiN film with a thickness of about 0.1-0.2 microns. Some processes also inject P-type ions at the bottom of the superjunction trench 3 to increase BVdss. The commonly used P-type ions are boron, with an injection energy of 90-180kev and an injection dose of 1.0E12cm -2 ~2.0E12cm -2 Then, P-type silicon, namely, the second epitaxial layer, is epitaxially filled in the super junction trench 3 , and then chemical mechanical polishing is used for planarization to form a P-type column, namely, the second conductive type column 4 composed of the second epitaxial layer filled in the super junction trench 3 .

[0083] 3. Such as Figure 2C As shown, a plurality of gate trenches 5 are then formed on the first epitaxial layer 2 by photolithography and etching. The gate trenches 5 are shallower than the super junction trenches 3. The depth of the gate trenches 5 is generally 2 to 4 μm. A gate oxide film, i.e., a gate dielectric layer 6, is then deposited. The thickness of the gate oxide film is about Then, a gate conductive material layer 7 of the device is formed by depositing and etching polysilicon.

[0084] 4. Such as Figure 2D As shown, after CVD deposition, a layer of thickness is formed on the surface of the silicon wafer, i.e., the silicon substrate. The oxide film is the protective epoxy film, which can prevent the device from being broken down by high voltage. Generally, the higher the BVdss of the device, the thicker the oxide film is required. This oxide film only covers the transition zone and the terminal area, and the oxide film in the charge flow area needs to be etched away.

[0085] 5. Then, a P-type well, i.e., a second conductive type well 8, is formed in the device cell region, i.e., the active region and the transition region by photolithography and ion implantation. The implanted impurity is generally boron, the implantation energy is 60-120 KeV, and the implantation dose is 1e13 cm -2 ~1e14cm -2 In daily production, the threshold voltage of the device will be affected by product characteristics, such as irradiated or non-irradiated products, and other process adjustments, which can be achieved by changing the implantation dose or energy of the P-type well.

[0086] 6. Such as Figure 2E As shown, a source region 9 is then formed by photolithography and ion implantation of N-type impurities. Common N-type impurities include phosphorus and arsenic.

[0087] Compared with the prior art, the embodiment of the present invention mainly changes the materials of the contact hole and the front metal layer. The corresponding forming processes of the contact hole and the front metal layer are described as follows:

[0088] For the existing method, the subsequent process steps for forming the metal electrode include:

[0089] 7. Go back Figure 1 As shown, the current metal electrode process mainly includes the deposition of the interlayer film 10, the etching and filling of the contact hole 11, and the deposition of the front metal layer 12 to form a semiconductor-metal ohmic contact. In the conventional metal electrode process, in the device current flow area, the contact hole, i.e., the first contact hole 11, will etch away the silicon in the N-type high-concentration area of ​​the contact hole area, and the etching amount is 2000-4000 angstroms; while in the transition area, the contact hole, i.e., the third contact hole, only needs to pass through the interlayer film 10 and the protective epoxy film, and the etching amount of silicon in this area does not exceed 500 angstroms. Subsequently, Ti-TiN, i.e., Ti and TiN blocking layers are deposited to prevent Si from dissolving in AlCu to form a sharp convexity, and annealing is performed. After that, metal tungsten (W) is deposited to fill the contact hole, and the thickness of W is 4000 angstroms. After that, the surface metal is removed, and 4-5μm AlCu is deposited, in which the Cu content accounts for 0.5%, to form a metal electrode.

[0090] For the embodiment of the present invention, the subsequent process of forming the metal electrode is slightly different, that is, the AlSiCu process is adopted, and step 7 corresponding to the above-mentioned existing method is replaced by the AlSiCu process. The specific process steps of the AlSiCu process include:

[0091] After etching to obtain the contact hole, a Ti-TiN blocking layer is not deposited, and 4-5 μm AlSiCu is directly deposited. AlSiCu directly forms a metal semiconductor ohmic contact with Si to form a device metal electrode. The AlSiCu metal is AlCu metal, and about 1% Si is added to the AlCu metal, so that Si can be saturated in AlCu. When the AlSiCu metal is deposited on the device surface, it can prevent the Si on the upper surface of the device from dissolving in the AlCu metal, and can also effectively prevent the occurrence of the convex phenomenon.

[0092] The subsequent steps are the same as those of the present invention and the prior art, including:

[0093] 8. The next step is the preparation of the passivation layer and the protective layer. Generally, a high-density silicon oxide layer, i.e., the passivation layer, is deposited under the action of plasma, and then a thicker polyimide film is deposited as a protective layer. After that, a protective pattern is formed by photolithography and development, covering the terminal area, transition area, gate area, and source area opening. The thickness of the polyimide layer after baking is 4 to 10 μm.

[0094] 9. Some devices need electron irradiation. Electron irradiation can be performed after the passivation layer process, and then the polyimide process can be performed. In this way, processes such as polyimide baking may affect the effect of electron irradiation. Electron irradiation can also be introduced after the polyimide process, and then a suitable dose and annealing conditions are set. In some embodiments, the general dose of electron irradiation is 60-300KGY, and the annealing conditions include a temperature of 300-380°C and a time of 30-300min, which can further improve the body diode reverse recovery characteristics of the device.

[0095] Compared with AlCu, AlSiCu has a slightly larger resistivity, which makes it difficult to turn on the body diode of the superjunction MOSFET, reduces the forward conduction current of the body diode, and reduces the stored charge. According to the test results, the forward conduction voltage drop of the body diode of the AlCu electrode device, i.e., the existing superjunction MOSFET device, is 0.9V, while the forward conduction voltage drop of the body diode of the AlSiCu electrode device, i.e., the superjunction MOSFET device of the embodiment of the present invention, is increased to 0.95V. Correspondingly, the reverse recovery charge of the body diode of the AlCu electrode device is 0.85uc, while the reverse recovery charge of the body diode of the AlSiCu electrode device is reduced to 0.67uc, a reduction of 20%. The reverse recovery time of the AlSiCu electrode device is shorter and the reverse recovery current is smaller. See Table 1 for specific comparison values. Moreover, the reverse recovery curve of the AlSiCu electrode device is softer, with a softness factor of 0.63, while the reverse recovery softness factor of the existing AlCu electrode device is 0.53. The reverse recovery characteristic comparison curve of the AlSiCu electrode device and the AlCu electrode device is shown in Figure 3 , Figure 3 The middle curve 101 represents the reverse recovery characteristic curve of the body diode of the existing super junction MOSFET device, namely the reverse recovery characteristic curve of the AlCu electrode device, and the curve 102 represents the reverse recovery characteristic curve of the body diode of the super junction MOSFET device of the embodiment of the present invention, namely the reverse recovery characteristic curve of the AlSiCu electrode device.

[0096] Table 1

[0097]

[0098]

[0099] In Table 1, Irrm represents the reverse recovery peak current, trr represents the reverse recovery time, and Qrr represents the reverse recovery charge.

[0100] The AlSiCu metal electrode process will affect the threshold voltage (VTH) of the device. The interface between the polysilicon and silicon dioxide of the device will change, causing the threshold voltage to drift. According to experimental data, the VTH of the AlSiCu electrode process device increases by 0.5V. In order to achieve the VTH value required by the application, the embodiment of the present invention will reduce the boron dose injected into the P-type well. The boron dose injected into the P-type well of the initial process corresponding to the existing method is as high as 1e13cm -2 ~1e14cm -2 In the process of the embodiment of the present invention, the dose can be reduced to 5e12cm -2 ~5e13cm -2 This will also lead to a reduction in the number of holes injected into the body diode and improve the reverse recovery characteristics.

[0101] Compared with the prior art, the embodiment of the present invention can improve the reverse recovery characteristics of the superjunction MOSFET by using a metal electrode process compatible with the existing superjunction process without increasing the process complexity and cost. Specifically, the use of AlSiCu metal electrodes instead of traditional AlCu metal electrodes reduces the forward conduction current of the superjunction MOSFET body diode, that is, reduces the number of injected minority carriers, thereby reducing the reverse recovery charge and softening the reverse recovery curve, ultimately reducing the power consumption of the device and improving the application reliability of the device.

[0102] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A super junction MOSFET device, characterized in that: include: A super junction structure formed in a first epitaxial layer doped with a first conductivity type, the super junction structure comprising first conductivity type columns and second conductivity type columns arranged alternately; The first epitaxial layer at the bottom of the super junction structure serves as a buffer layer; In the active region, a plurality of parallel device unit structures are formed in the top region of the super junction structure; The device unit structure includes a gate structure, a second conductivity type well and a first conductivity type heavily doped source region; The second conductive type well is formed in a top region of the second conductive type column and extends into the first conductive type column, and the drift region includes the first conductive type column and the buffer layer located outside or at the bottom of the second conductive type well; The surface of the second conductive type well covered by the gate structure is used to form a conductive channel connecting the source region and the drift region; The body diode is a parasitic diode formed by the second conductive type well and the drift region; The source region and the top of the second conductive type well are connected to the source metal composed of the front metal layer through a first contact hole; the first contact hole passes through the source region and contacts the second conductive type well; The first contact hole is directly composed of a material layer of the front metal layer filling the opening of the first contact hole, and the material of the front metal layer is AlSiCu, and the Si content in AlSiCu reaches above the saturation value; the AlSiCu of the first contact hole directly forms an ohmic contact with the semiconductor material of the first epitaxial layer of the source region and the second conductive type well, and utilizes the characteristic that the Si content in AlSiCu reaches above the saturation value to prevent the formation of sharp convex defects when AlCu directly contacts the semiconductor material of the first epitaxial layer; utilizes the characteristic that the resistivity of AlSiCu is greater than the resistivity of AlCu to increase the forward conduction voltage drop of the body diode and improve the reverse recovery characteristics of the device.

2. The super junction MOSFET device according to claim 1, characterized in that: The gate structure includes a gate dielectric layer and a gate conductive material layer; the top of the gate conductive material layer is connected to the gate metal composed of the front metal layer through a second contact hole; the second contact hole is directly composed of the material layer of the front metal layer filling the second contact hole opening.

3. The super junction MOSFET device according to claim 1, characterized in that: The gate structure is a planar gate or a trench gate.

4. The super junction MOSFET device according to claim 1, wherein: The second conductive type column includes a second conductive type doped second epitaxial layer filled in the super junction trench, and the first conductive type column includes the first epitaxial layer located between the super junction trenches.

5. The super junction MOSFET device according to claim 1, characterized in that: A transition region surrounds the active region, and a terminal region surrounds the transition region; The second conductivity type well also extends into the transition region.

6. The super junction MOSFET device according to claim 1, wherein: The first epitaxial layer is formed on a top surface of a semiconductor substrate; A drain region heavily doped with the first conductivity type is formed on the back side of the drift region, and the drain region is composed of the thinned semiconductor substrate heavily doped with the first conductivity type or a back ion implantation region heavily doped with the first conductivity type formed in the thinned semiconductor substrate.

7. The super junction MOSFET device according to claim 6, characterized in that: The material of the semiconductor substrate includes silicon; The material of the first epitaxial layer includes silicon.

8. The super junction MOSFET device according to claim 2, characterized in that: The Si content in the AlSiCu of the front metal layer is greater than or equal to 1%.

9. The super junction MOSFET device according to claim 2, characterized in that: The thickness of the front metal layer is 4 μm to 5 μm.

10. The super junction MOSFET device according to claim 2, characterized in that: An increase in the Si content in the AlSiCu of the front metal layer will increase the threshold voltage of the device; An initial design value of the implantation dose of the second conductive type well is determined by the AlCu material, and an actual value of the implantation dose of the second conductive type well is reduced based on the initial design value and is determined according to the increase in the threshold voltage caused by the Si content in the AlSiCu of the front metal layer.

11. The super junction MOSFET device according to claim 10, characterized in that: The actual value range of the implantation dose of the second conductivity type well is 5E12cm -2 ~5E13cm -2 .

12. The super junction MOSFET device according to claim 5, characterized in that: The active region is defined by a protective epoxy film covering a top surface of the first epitaxial layer in the transition region and the termination region.

13. The super junction MOSFET device according to claim 12, characterized in that: A third contact hole is formed in the transition region and the terminal region, and the third contact hole is composed of the front metal layer filling the third contact hole opening; The first contact hole passes through the interlayer film and a portion of the thickness of the first epitaxial layer; the first contact hole passes through the thickness of the first epitaxial layer to ensure passing through the source region; The third contact hole passes through the interlayer film and the protective epoxy film and contacts the first epitaxial layer, and the thickness of the first epitaxial layer through which the third contact hole passes is smaller than the thickness of the first epitaxial layer through which the first contact hole passes.

14. The super junction MOSFET device according to claim 13, characterized in that: The thickness of the first contact hole through the first epitaxial layer is The thickness of the third contact hole passing through the first epitaxial layer is less than 15. The super junction MOSFET device according to any one of claims 1 to 14, characterized in that: The super junction MOSFET device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the super junction MOSFET device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

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