Silicon carbide transistor structure and preparation method thereof

Abstract

The invention provides a silicon carbide transistor structure and a preparation method thereof. The method comprises the steps that a silicon carbide substrate is formed, a well region is formed in the silicon carbide substrate, and a first doped region is formed in the well region; forming a groove in the first doped region and executing ion implantation to form a second doped region extending into the well region; forming a gate structure and a gate dielectric layer completely wrapping the gate structure on the top surface of the silicon carbide substrate; and forming a contact hole which penetrates through the gate dielectric layer and at least partially exposes the second doped region, and forming a metal silicide layer in contact with the second doped region in the contact hole. According to the invention, the first doped region formed in the well region is etched to form the groove, and then the second doped region extending into the well region is formed at the groove, so that the region voltage drop of the first doped region can be reduced, and the purpose of effectively reducing the VFSD of the device is achieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a silicon carbide transistor structure and a method for preparing the same. Background Art

[0002] As the manufacturing technology of semiconductor integrated circuits continues to advance, the performance of semiconductor devices continues to improve. As a new type of power device, silicon carbide (SiC) metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, referred to as MOSFET or MOS) devices have the characteristics of high breakdown voltage, low on-resistance, high temperature resistance, and low loss compared to traditional silicon (Si)-based power devices. Thanks to its above advantages, silicon carbide transistors are generally used in high-voltage fields of 650V and above, and can replace silicon-based super-junction MOSFET devices and high-voltage IGBT devices.

[0003] VFSD is an important parameter of planar silicon carbide MOS tube, which means "vertical FET source-drain diode". The VFSD parameter refers to the forward DC resistance between the drain and source of the MOS tube under specific conditions. This parameter reflects the performance of the MOS tube under forward bias. When the MOS tube is in a forward biased state, the smaller the VFSD parameter is, the smaller the resistance between the drain and the source is, and the stronger the current flow capacity is. Therefore, the size of the VFSD parameter directly affects the performance indicators of the MOS tube, such as efficiency, power consumption and temperature rise. Summary of the invention

[0004] The technical problem to be solved by the present application is to provide a silicon carbide transistor structure and a preparation method thereof, so as to solve the problem of large VFSD of planar silicon carbide MOSFET and achieve the purpose of reducing the device VFSD by reducing the voltage drop in the NPS region.

[0005] In order to solve the above problems, the present application provides a method for preparing a silicon carbide transistor structure, comprising the following steps: forming a silicon carbide substrate, a well region formed in the silicon carbide substrate, and a first doped region formed in the well region; forming a groove in the first doped region and performing ion implantation to form a second doped region extending into the well region, wherein in a first direction, the second doped region separates the first doped region into two independent parts, and in a second direction, the top surface of the second doped region is lower than the top surface of the first doped region, wherein the first direction is parallel to the top surface of the silicon carbide substrate, and the second direction is perpendicular to the top surface of the silicon carbide substrate; forming a gate structure and a gate dielectric layer that completely covers the gate structure on the top surface of the silicon carbide substrate; and forming a contact hole that penetrates the gate dielectric layer and at least partially exposes the second doped region, and forming a metal silicide layer in contact with the second doped region in the contact hole.

[0006] In order to solve the above problems, the present application also provides a silicon carbide transistor structure, including: a silicon carbide substrate, a well region is formed in the silicon carbide substrate, and a first doped region is formed in the well region; a second doped region extends from the first doped region to the well region, in a first direction, the second doped region separates the first doped region into two independent parts, in a second direction, the top surface of the second doped region is lower than the top surface of the first doped region, wherein the first direction is parallel to the top surface of the silicon carbide substrate, and the second direction is perpendicular to the top surface of the silicon carbide substrate; a gate structure is formed on the top surface of the silicon carbide substrate; a gate dielectric layer completely covers the gate structure; and a metal silicide layer is formed in a contact hole that penetrates the gate dielectric layer and at least partially exposes the second doped region, and the metal silicide layer is in contact with the second doped region.

[0007] The above technical solution, by etching the first doped region formed in the well region to form a groove, and then forming a second doped region extending into the well region at the groove, can reduce the regional voltage drop of the first doped region, thereby achieving the purpose of effectively reducing the device VFSD. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the specific implementation of the present application, the following is a brief introduction to the drawings required for the description of the specific implementation. Obviously, the drawings described below are only some specific implementations of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 A flowchart of the steps of a method for preparing a silicon carbide transistor structure according to an embodiment of the present application;

[0010] Figure 2A to Figure 2D A schematic diagram of the local morphology of forming a silicon carbide substrate according to an embodiment of the present application;

[0011] Figure 3A to Figure 3C A schematic diagram of the local morphology of forming a second doping region according to an embodiment of the present application;

[0012] Figure 4 A schematic diagram of the local morphology of forming a gate structure and a gate dielectric layer according to an embodiment of the present application;

[0013] Figure 5A to Figure 5B It is a schematic diagram of the local morphology of forming a metal silicide layer according to an embodiment of the present application. DETAILED DESCRIPTION

[0014] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0015] Research has found that in practical applications, the size of the VFSD parameter is related to factors such as the manufacturing process, material and structure of the MOS tube. In order to obtain better performance, it is crucial to select a MOS tube with a smaller VFSD parameter. In addition, reasonable design and control of circuit parameters are also important means to reduce MOS tube losses and improve system efficiency.

[0016] Please also read Figure 1 to Figure 5B ,in, Figure 1 A flowchart of the steps of a method for preparing a silicon carbide transistor structure according to an embodiment of the present application; Figure 2A to Figure 2D A schematic diagram of the local morphology of forming a silicon carbide substrate according to an embodiment of the present application; Figure 3A to Figure 3C A schematic diagram of the local morphology of forming a second doping region according to an embodiment of the present application; Figure 4 A schematic diagram of the local morphology of forming a gate structure and a gate dielectric layer according to an embodiment of the present application; Figure 5A to Figure 5B It is a schematic diagram of the local morphology of forming a metal silicide layer according to an embodiment of the present application.

[0017] For convenience of explanation, in the following embodiments, the first direction D1 is parallel to the top surface of the silicon carbide substrate, the second direction D2 is perpendicular to the top surface of the silicon carbide substrate (the second direction D2 is the device stacking direction), and the first direction D1 intersects with the second direction D2. Specifically, the first direction D1 may be the X-axis direction in a Cartesian coordinate system, and the second direction D2 may be the Z-axis direction in a Cartesian coordinate system.

[0018] like Figure 1 As shown, the preparation method of the silicon carbide transistor structure described in this embodiment includes the following steps: S1, forming a silicon carbide substrate, a well region formed in the silicon carbide substrate, and a first doped region formed in the well region; S2, forming a groove in the first doped region and performing ion implantation to form a second doped region extending into the well region; S3, forming a gate structure and a gate dielectric layer completely covering the gate structure on the top surface of the silicon carbide substrate; and S4, forming a contact hole that penetrates the gate dielectric layer and at least partially exposes the second doped region, and forming a metal silicide layer in contact with the second doped region in the contact hole.

[0019] See also Figure 2DAnd step S1, forming a silicon carbide substrate, a well region 22 is formed in the silicon carbide substrate, and a first doping region 23 is formed in the well region 22. Specifically, a plurality of well regions 22 are formed in the silicon carbide substrate, and a JFET region is formed between two adjacent well regions 22 in a first direction D1. The first direction D1 is parallel to the top surface of the silicon carbide substrate. The figure also illustrates a second direction D2, which is a direction perpendicular to the top surface of the silicon carbide substrate.

[0020] like Figure 2A to Figure 2D As shown, in this embodiment, the step of forming a silicon carbide substrate further includes: (1) providing a silicon carbide substrate, the silicon carbide substrate is covered with a first mask layer 291 having a first opening 292, as shown in FIG. Figure 2A (2) using the first mask layer 291 as a shield for ion implantation, forming the well region 22 in the silicon carbide substrate corresponding to the first opening 292, as shown in FIG. Figure 2B (3) forming a barrier layer 28 on the sidewall of the first opening 292 of the first mask layer 291, and performing ion implantation under the self-alignment of the barrier layer 28 to form the first doped region 23 in the well region 22, as shown Figure 2C As shown; wherein the first doping region 23 and the well region 22 are implanted with ions of different conductivity types; and (4) removing the first mask layer 291 and the barrier layer 28 to form the silicon carbide substrate, wherein the well region 22 is formed in the silicon carbide substrate, and the first doping region 23 is formed in the well region 22, as shown in FIG. Figure 2D shown.

[0021] The well region 22 is formed by ion implantation of a first conductivity type, and the first doped region 23 is formed by ion implantation of a second conductivity type, and the first conductivity type is different from the second conductivity type. The first conductivity type is, for example, a P type, and the second conductivity type is, for example, an N type. Parameters of ion implantation can be adjusted according to transistor parameters and process conditions, and are not specifically limited here. The first doped region 23 can be a heavily doped region.

[0022] In this embodiment, the silicon carbide substrate (SiC) includes a support substrate 20 and a silicon carbide epitaxial layer 21 formed on the support substrate 20. The support substrate 20 can be any one of a silicon (Si) substrate and a silicon carbide (SiC). The support substrate 20 can also be a stacked structure, such as a silicon / germanium / silicon stack. The silicon carbide epitaxial layer 21 is a thin film layer epitaxially grown (EPI) on the support substrate 20 and having substantially the same crystal structure and electrical properties as the support substrate 20. The silicon carbide epitaxial layer 21 can be grown by chemical vapor deposition (CVD). CVD technology is mainly a method of generating a thin film by chemically reacting one or more gas phase compounds or single substances containing thin film elements on the surface of the substrate. The well region 22 and the first doping region 23 are formed in the silicon carbide epitaxial layer 21. The support substrate 20 , the silicon carbide epitaxial layer 21 , and the well region 22 may all have a first conductivity type, and the first doped region 23 may have a second conductivity type.

[0023] In this embodiment, in the first direction D1 , the first doped region 23 is formed in the top middle region of the well region 22 and has a first distance W1 from the sidewall of the well region 22 .

[0024] In this embodiment, in the second direction D2, the top surface of the silicon carbide substrate, the top surface of the well region 22 and the top surface of the first doping region 23 are substantially flush.

[0025] See also Figure 3C In step S2, a groove 239 is formed in the first doping region 23 and ion implantation is performed to form a second doping region 24 extending into the well region 22. Specifically, in the first direction D1, the second doping region 24 separates the first doping region 23 into two independent parts (such as Figure 3C In the second direction D2, the top surface of the second doping region 24 is lower than the top surface of the first doping region 23. The first direction D1 is parallel to the top surface of the silicon carbide substrate, and the second direction D2 is perpendicular to the top surface of the silicon carbide substrate.

[0026] like Figure 3A to Figure 3C As shown, in this embodiment, the steps of forming the groove 239 in the first doping region 23 and performing ion implantation to form the second doping region 24 extending into the well region 22 specifically include: (1) forming a second mask layer 391 having a second opening 392 on the silicon carbide substrate, wherein the second opening 392 partially exposes the first doping region 23, such as Figure 3A(2) etching the first doped region 23 with the second mask layer 391 as a shield, forming the groove 239 in the first doped region 23 corresponding to the second opening 392, as shown in FIG. Figure 3B (3) ion implantation is performed with the second mask layer 391 as a shield to form the second doping region 24 corresponding to the second opening 392 and extending to the well region 22, as shown in FIG. Figure 3C shown.

[0027] In this embodiment, the second doping region 24 and the well region 22 are implanted with ions of the same conductivity type, and the ion implantation concentration of the second doping region 24 is greater than the ion implantation concentration of the well region 22. That is, the well region 22 and the second doping region 24 have a first conductivity type, the first doping region 23 has a second conductivity type, and the first conductivity type is different from the second conductivity type.

[0028] In this embodiment, in the first direction D1 , the second doping region 24 is formed in the middle of the first doping region 23 and divides the first doping region 23 into two parts 231 and 232 that are independent of each other and substantially the same.

[0029] In this embodiment, in the second direction D2, the top surface of the silicon carbide substrate, the top surface of the well region 22 and the top surface of the first doping region 23 are basically flush; the top surface of the second doping region 24 is lower than the top surface of the first doping region 23, and there is a second distance W2 between the bottom surface of the second doping region 24 and the bottom surface of the well region 22.

[0030] Taking the first conductivity type as P type and the second conductivity type as N type as an example, a P well (well region 22) is formed on the silicon carbide epitaxial layer 21 by ion implantation; in the first direction D1, the middle region at the top of the P well forms a first doping region 23 (NPS, full name NPLUS, N-type heavy doping) by extremely high concentration ion implantation, and the NPS and the sidewall of the P well have a first spacing W1; a groove 239 is formed in the middle of the NPS by etching and a second doping region 24 (PPS, full name PPLUS, P-type heavy doping) is formed by extremely high concentration ion implantation. In this embodiment, the ions implanted into the P well may be Al ions or B ions, the ions implanted into the NPS may be extremely high concentration P ions or N ions, and the PPS implants may be extremely high concentration Al ions or B ions. Specifically, the VFSD of the flat silicon carbide MOS tube includes the voltage drop in the NPS region; therefore, by reducing the voltage drop in the NPS region, the purpose of effectively reducing the VFSD of the device can be achieved.

[0031] In this embodiment, the bottom wall of the groove 239 is located in the first doping region 23. That is, when the first doping region 23 is etched with the second mask layer 391 as a shield, the first doping region 23 is not etched through. By partially etching the first doping region 23, the voltage drop in the region can be reduced, thereby achieving the purpose of effectively reducing the VFSD of the device. In other embodiments, the bottom wall of the groove 239 is located in the well region 22. That is, when the first doping region 23 is etched with the second mask layer 391 as a shield, the first doping region 23 is etched through, thereby further reducing the voltage drop in the region.

[0032] See also Figure 4 And step S3, forming a gate structure 25 and a gate dielectric layer 26 completely covering the gate structure 25 on the top surface of the silicon carbide substrate.

[0033] In some embodiments, the steps of forming a gate structure 25 on the top surface of the silicon carbide substrate and a gate dielectric layer 26 completely covering the gate structure 25 specifically include: (1) forming a patterned gate oxide layer 251 on the top surface of the silicon carbide substrate, the gate oxide layer 251 covering the top surface of the silicon carbide substrate, the top surface of the well region and a portion of the top surface of the first doped region; (2) forming a gate electrode 252 on the top surface of the gate oxide layer 251, the gate electrode 252 and the gate oxide layer 251 constituting the gate structure 25; and (3) forming the gate dielectric layer 26 completely covering the gate structure 25. The gate electrode may be a polysilicon gate electrode.

[0034] In some embodiments, the step of forming a patterned gate oxide layer on the top surface of the silicon carbide substrate specifically includes: (11) using a thermal oxidation process to form an oxide layer covering the top surface of the silicon carbide substrate, the top surface of the well region, and the top surface of the first doped region; (12) forming a third mask layer on the oxide layer, the third mask layer having a third opening corresponding to a portion of the first doped region; (13) etching the oxide layer using the third mask layer as a shield to remove the oxide layer in the third opening area, and removing the third mask layer, and the remaining oxide layer serves as the gate oxide layer.

[0035] In this embodiment, the gate structure 25 is located in a region between two adjacent well regions 22 on the top surface of the silicon carbide substrate and extends to above the first doping region 23 .

[0036] See also Figure 5A to Figure 5B In step S4, a contact hole 50 is formed which penetrates the gate dielectric layer 26 and at least partially exposes the second doped region 24. Figure 5A and forming a metal silicide layer 27 in contact with the second doped region 24 in the contact hole 50, as shown Figure 5B shown.

[0037] In this embodiment, in the second direction D2 , a top surface of the metal silicide layer 27 is lower than a top surface of the first doping region 23 .

[0038] In some embodiments, the method for preparing the silicon carbide transistor structure described in this embodiment further includes: forming a lead-out structure (not shown) that fills the contact hole 50 and contacts the metal silicide layer 27 .

[0039] In some embodiments, the silicon carbide transistor structure prepared by the method for preparing the silicon carbide transistor structure described in this embodiment is a flat silicon carbide MOS transistor. Specifically, VFSD of the flat silicon carbide MOS transistor is VF CNT +VF NPS +VF PPS +VF EPI+Sub +VF Backmetal Therefore, by reducing the voltage drop in the NPS region, the purpose of effectively reducing the device VFSD can be achieved. CNT is the voltage drop of the lead structure formed in the contact hole 50, VF NPS is the NPS area pressure drop, VF PPLUS is the PPS area pressure drop, VF EPI+Sub is the voltage drop of the silicon carbide substrate (including the support substrate 20 (sub) and the silicon carbide epitaxial layer 21 (EPI)), VF Backmetal The present embodiment etches the NPS region to form a groove in the NPS region, thereby reducing the voltage drop in the NPS region and achieving the purpose of effectively reducing the VFSD of the device.

[0040] Based on the same inventive concept, an embodiment of the present application further provides a silicon carbide transistor structure, which can be prepared using the above-mentioned preparation method of the present application.

[0041] See also Figure 5B The silicon carbide transistor structure described in this embodiment includes: a silicon carbide substrate, a well region 22 , a first doping region 23 , a second doping region 24 , a gate structure 25 , a gate dielectric layer 26 and a metal silicide layer 27 .

[0042] Specifically, a plurality of well regions 22 are formed in the silicon carbide substrate, and a first doping region 23 is formed in the well region 22. The second doping region 24 extends from the first doping region 23 into the well region 22. In the first direction D1, the second doping region 24 separates the first doping region 23 into two independent parts; in the second direction D2, the top surface of the second doping region 24 is lower than the top surface of the first doping region 23. The gate structure 25 is formed on the top surface of the silicon carbide substrate; the gate dielectric layer 26 completely covers the gate structure. The metal silicide layer 27 is formed in a contact hole 50 that penetrates the gate dielectric layer 26 and at least partially exposes the second doping region 24, and the metal silicide layer 27 is in contact with the second doping region 24. The first direction D1 is parallel to the top surface of the silicon carbide substrate, and the second direction D2 is perpendicular to the top surface of the silicon carbide substrate.

[0043] In this embodiment, the silicon carbide substrate (SiC) includes a support substrate 20 and a silicon carbide epitaxial layer 21 formed on the support substrate 20. The well region 22, the first doping region 23, and the second doping region 24 are formed in the silicon carbide epitaxial layer 21; the support substrate 20, the silicon carbide epitaxial layer 21, the well region 22, and the second doping region 24 all have a first conductivity type, and the first doping region 23 has a second conductivity type. The first conductivity type is, for example, P type, and the second conductivity type is, for example, N type.

[0044] In this embodiment, the ion implantation concentration of the second doping region 24 is greater than the ion implantation concentration of the well region 22. The ions implanted into the well region 22 may be Al ions or B ions, the ions implanted into the first doping region 23 may be P ions or N ions at a very high concentration, and the ions implanted into the second doping region 24 may be Al ions or B ions at a very high concentration.

[0045] In this embodiment, in the first direction D1, the first doping region 23 is formed in the top middle area of ​​the well region 22 and has a first distance W1 with the side wall of the well region 22; the second doping region 24 is formed in the middle of the first doping region 23 and separates the first doping region 23 into two independent and basically identical parts 231 and 232.

[0046] In this embodiment, in the second direction D2, the top surface of the silicon carbide substrate, the top surface of the well region 22 and the top surface of the first doping region 23 are basically flush; the top surface of the metal silicide layer 27 is lower than the top surface of the first doping region 23; and there is a second distance W2 between the bottom surface of the second doping region 24 and the bottom surface of the well region 22.

[0047] In the above-mentioned embodiment of the present application, by etching the first doped region formed in the well region to form a groove, and then forming a second doped region extending into the well region at the groove, the regional voltage drop in the first doped region can be reduced, thereby achieving the purpose of effectively reducing the VFSD of the device.

[0048] It should be noted that references to "an embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. in the specification indicate that the described embodiment may include a particular feature, structure or characteristic, but each embodiment may not necessarily include the particular feature, structure or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure or characteristic is described in conjunction with an embodiment, whether or not it is explicitly described, it is within the knowledge of a technician in the relevant field to implement such a feature, structure or characteristic in conjunction with other embodiments. Generally, a term can be understood at least in part from the usage in the context. For example, the term "one or more" as used in this article depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or features in a plural sense. Similarly, depending at least in part on the context, terms such as "one", "a" or "the" can also be understood to express singular usage or to express plural usage. In addition, the term "based on" can be understood to not necessarily be intended to express a set of exclusive factors, but can alternatively, also at least in part on the context, allow the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that “connected / coupled” refers not only to direct coupling of one component to another component but also to indirect coupling of one component to another component via an intermediate component.

[0049] It should be noted that the terms "including" and "having" and their variations involved in the documents of this application are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments in this application and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies has been omitted to avoid unnecessary confusion of the concepts of this application. In the above-mentioned embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0050] The above is only a preferred implementation of the present application. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A method for preparing a silicon carbide transistor structure, characterized in that: The steps include: forming a silicon carbide substrate, wherein a well region is formed in the silicon carbide substrate, and a first doped region is formed in the well region; forming a groove in the first doping region and performing ion implantation to form a second doping region extending into the well region, wherein in a first direction, the second doping region separates the first doping region into two independent parts, and in a second direction, a top surface of the second doping region is lower than a top surface of the first doping region, wherein the first direction is parallel to the top surface of the silicon carbide substrate, and the second direction is perpendicular to the top surface of the silicon carbide substrate; forming a gate structure and a gate dielectric layer completely covering the gate structure on the top surface of the silicon carbide substrate; and A contact hole is formed which penetrates the gate dielectric layer and at least partially exposes the second doped region, and a metal silicide layer which contacts the second doped region is formed in the contact hole.

2. The method according to claim 1, characterized in that The silicon carbide substrate includes a supporting substrate and a silicon carbide epitaxial layer formed on the supporting substrate, the well region is formed in the silicon carbide epitaxial layer, the well region and the second doped region have a first conductivity type, the first doped region has a second conductivity type, and the first conductivity type is different from the second conductivity type.

3. The method according to claim 1, characterized in that The bottom wall of the groove is located in the first doping region, or the bottom wall of the groove is located in the well region.

4. The method according to claim 1, characterized in that In the first direction, the first doped region is formed in the top middle area of ​​the well region and has a first distance from the side wall of the well region, and the second doped region is formed in the middle of the first doped region and separates the first doped region into two independent and basically identical parts.

5. The method according to claim 1, characterized in that In the second direction, the top surface of the silicon carbide substrate, the top surface of the well region and the top surface of the first doped region are basically flush, the top surface of the metal silicide layer is lower than the top surface of the first doped region, and there is a second distance between the bottom surface of the second doped region and the bottom surface of the well region.

6. The method according to claim 1, characterized in that The steps of forming a silicon carbide substrate specifically include: Providing a silicon carbide substrate, wherein the silicon carbide substrate is covered with a first mask layer having a first opening; performing ion implantation using the first mask layer as a shield to form the well region in the silicon carbide substrate corresponding to the first opening region; forming a barrier layer on the sidewall of the first opening of the first mask layer, performing ion implantation under self-alignment of the barrier layer, and forming the first doped region in the well region, wherein the first doped region and the well region are implanted with ions of different conductivity types; and The first mask layer and the barrier layer are removed.

7. The method according to claim 6, characterized in that The step of forming a groove in the first doping region and performing ion implantation to form a second doping region extending into the well region specifically includes: forming a second mask layer having a second opening on the silicon carbide substrate, wherein the second opening partially exposes the first doped region; Using the second mask layer as a shield, etching the first doped region to form the groove in the first doped region corresponding to the second opening area; Ion implantation is performed using the second mask layer as a shield to form the second doped region corresponding to the second opening area and extending into the well region, wherein the second doped region and the well region are implanted with ions of the same conductive type, and the ion implantation concentration of the second doped region is greater than the ion implantation concentration of the well region.

8. The method according to claim 1, characterized in that The step of forming a gate structure on the top surface of the silicon carbide substrate and a gate dielectric layer completely covering the gate structure specifically includes: Forming a patterned gate oxide layer on the top surface of the silicon carbide substrate, wherein the gate oxide layer covers the top surface of the silicon carbide substrate, the top surface of the well region, and a portion of the top surface of the first doped region; forming a gate electrode on the top surface of the gate oxide layer, wherein the gate electrode and the gate oxide layer constitute the gate structure; and The gate dielectric layer is formed to completely cover the gate structure.

9. The method according to claim 8, characterized in that The step of forming a patterned gate oxide layer on the top surface of the silicon carbide substrate specifically includes: Using a thermal oxidation process to form an oxide layer covering the top surface of the silicon carbide substrate, the top surface of the well region, and the top surface of the first doped region; forming a third mask layer on the oxide layer, wherein the third mask layer has a third opening corresponding to a portion of the first doped region; The oxide layer is etched with the third mask layer as a shield to remove the oxide layer in the third opening area, and the third mask layer is removed, and the remaining oxide layer serves as the gate oxide layer.

10. The method according to claim 1 or 8, characterized in that: The gate structure is located on the top surface of the silicon carbide substrate in a region corresponding to a region between two adjacent well regions and extends to above the first doping region.

11. The method according to claim 1, characterized in that: The method further comprises: A lead-out structure is formed which fills the contact hole and contacts the metal silicide layer.

12. A silicon carbide transistor structure, characterized in that: include: A silicon carbide substrate, wherein a well region is formed in the silicon carbide substrate, and a first doped region is formed in the well region; a second doping region extending from the first doping region into the well region, wherein in a first direction, the second doping region separates the first doping region into two independent parts, and in a second direction, a top surface of the second doping region is lower than a top surface of the first doping region, wherein the first direction is parallel to the top surface of the silicon carbide substrate, and the second direction is perpendicular to the top surface of the silicon carbide substrate; A gate structure formed on the top surface of the silicon carbide substrate; a gate dielectric layer, completely covering the gate structure; and A metal silicide layer is formed in a contact hole that penetrates the gate dielectric layer and at least partially exposes the second doped region, and the metal silicide layer is in contact with the second doped region.

13. The silicon carbide transistor structure according to claim 12, characterized in that: The silicon carbide substrate includes a supporting substrate and a silicon carbide epitaxial layer formed on the supporting substrate, the well region is formed in the silicon carbide epitaxial layer, the well region and the second doped region have a first conductivity type, the first doped region has a second conductivity type, the first conductivity type is different from the second conductivity type, and the ion implantation concentration of the second doped region is greater than the ion implantation concentration of the well region.

14. The silicon carbide transistor structure according to claim 12, characterized in that: In the first direction, the first doped region is formed in the middle of the well region and has a distance from the sidewall of the well region, and the second doped region is formed in the middle of the first doped region and separates the first doped region into two independent and substantially identical parts.

15. The silicon carbide transistor structure according to claim 12, characterized in that: In the second direction, the top surface of the silicon carbide substrate, the top surface of the well region and the top surface of the first doped region are basically flush, the top surface of the metal silicide layer is lower than the top surface of the first doped region, and there is a distance between the bottom surface of the second doped region and the bottom surface of the well region.

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