Inverted tube structure of novel 3D nano wall (NWaFET) device

Abstract

The invention mainly aims to provide a novel inverted tube structure of a 3D (three-dimensional) nano-wall (NWaFET) device, the problem that a long-channel device cannot be realized by a traditional NWaFET device is solved, and meanwhile, a new IC (integrated circuit) device structure is provided for a process library based on the 3D nano-wall NWaFET. However, the inverted tube structure is mostly applied to the field of current source bias and low power consumption design for realizing active resistors and cascode tubes.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, in particular to an inverse ratio transistor structure of a novel 3D nano wall field transistor (NWaFET) device. Background Art

[0002] The integrated circuit industry has developed rapidly since the 1950s. According to Moore's Law, the number of components on a chip doubles every six months (changed to every 18 months after 1975), and the performance and capacity of semiconductors will show exponential growth. The basis of Moore's Law is the proportional reduction of integrated circuits. However, according to the prediction of the IEEE International Roadmap for Devices and Systems (IRDS), if the channel length Lch of integrated circuits cannot exceed (be less than) 12nm, Moore's Law will face the dilemma of being unable to move forward. SRAM (Static Random Memory Array), that is, static random memory, as one of the most important memories, is a key part of modern SoC and plays an important role in various types of chips. Its power consumption, stability and other aspects of performance are key factors in the performance of the entire chip. The HVTFET (heterojunction vertical channel field effect transistor) and 3D nanowall NWaFET structures before the present invention adopt a vertical design scheme, which greatly improves the integration of the device and suppresses the DIBL effect through a combination structure of heavy doping in the channel region and light doping in the drift region. The HVT and NWaFET structures achieve a further reduction in Lch by adopting a channel heavy doping method. It has a shorter channel length Lch than existing FINFET, GAA, etc., and has a higher degree of integration. However, the channel length of the HVT and NWaFET device structures themselves is achieved through epitaxial growth technology, and their channel length cannot be large in size. Therefore, it is difficult for NWaFET devices themselves to achieve an inverted transistor structure. This paper proposes a new type of 3D nanowall (NWaFET) device with an inverted transistor structure. On the basis of the original NWaFET device structure, a sidewall structure is retained. The inverted transistor structure is achieved by splitting the source region of the NWaFET and combining it with a lateral design solution.

[0003] References

[0004] [1].Moore,Gordon E."Cramming more components onto integrated circuits".Electronics.Retrieved 2016-07-01.Instruction sheet 1 / 7 page 6CN 116705796A6

[0005] [2]. Thompson S, Packan P, Bohr M. MOS scaling: transistor challenge es for the 21st century. Intel Technology Journal, 1998; pp 1-18.

[0006] [3].Chenming Hu,Lee WC,Kedzierski J,et al.FinFET-a self-alig neddouble-gate MOSFET scalable to 20nm[J].IEEE Transactions on Elec tronDevices,2000,47(12):2320-2325.

[0007] [4]. Liao Yongbo, Li Ping, Tang Ruifeng, et al. Structure of a new digital gate integrated circuit [P]. China, invention patent, application number: CN111048579.1.2020.

[0008] [5]. Li Ping, Tang Ruifeng, Liao Yongbo, et al. A new DRAM structure and implementation method [P]. China, invention patent, application number: CN202110252584.1.2021.

[0009] [6]. Liao Yongbo, Liu Jinming, Li Ping et al. A high-integration nano-wall integrated circuit structure [P]. China, invention patent, application number: CN202210413345.4.2022. Summary of the invention

[0010] The main purpose of the present invention is to propose a new type of inverted transistor structure of 3D nanowall (NWaFET) device, which solves the problem that traditional NWaFET devices cannot realize long channel devices, and provides a new IC device structure for the process library based on 3D nanowall NWaFET. However, the inverted transistor structure is mostly used to realize active resistors, current source bias of common source and common gate transistors, and low power consumption design fields.

[0011] Technical solution 1 of the present invention is a novel 3D nano-wall (NWaFET) inverse transistor structure, here taking NMOS inverse transistor as an example, Figures 1 to 5As shown. The inverse transistor structure is based on the basic structure of 3D nanowall (NWaFET), with part of the source region hollowed out, and the remaining active area is used as the source and drain of the inverse transistor of a new type of 3D nanowall (NWaFET) device. Region (101) is the gate electrode of the inverse transistor device, which is a metal material such as aluminum; region (102) is the drain electrode of the inverse transistor device, which is a metal material such as aluminum; region (103) is the source electrode of the inverse transistor device, which is a metal material such as aluminum; region (104) is the substrate electrode of the inverse transistor device, which is a metal material such as aluminum; region (105) is the gate oxide layer, which is a material of silicon dioxide or other high-K dielectric materials; region (106) is an isolation layer used to isolate the source and drain, which is silicon dioxide or other high-K dielectric materials; region (107) is the active region of the drain, which is an N+ type semiconductor; region (10 8) is the channel layer of the original 3D nanowall (NWaFET) device, which is a P-type doped active region, represented by P1; region (109) is the lightly doped drain region of the original 3D nanowall (NWaFET) device, which is an N-type semiconductor; region (110) is the source active region of the original 3D nanowall (NWaFET) device, which is an N+ type semiconductor; region (111) is the channel region of the inverse ratio transistor device, which is a P-type semiconductor, represented by P2; the channel length of the inverse ratio transistor is the distance from the right side boundary of region (102) to the left side boundary of region (103), and the channel width is the thickness of region (111).

[0012] Technical solution 2 of the present invention is a novel inverse tube structure of a 3D nanowall (NWaFET) device, such as Figures 1 to 5 As shown, the gate oxide layer of the inverse transistor device is made on the sidewall, which is convenient for integration with 3D nano-wall (NWaFET) devices.

[0013] Technical solution 3 of the present invention is a novel inverse transistor structure of a 3D nanowall (NWaFET) device. The channel length of the inverse transistor device is no longer limited by the thickness of epitaxial growth and can be controlled by controlling the etching length, thereby solving the problem that the original 3D nanowall (NWaFET) cannot be made into a long channel device, and its channel width can be controlled by the thickness of epitaxial growth.

[0014] Technical solution 4 of the present invention is a process step of a novel 3D nanowall (NWaFET) device with an inverse ratio tube structure, such as Figures 6 to 20 As shown, a novel 3D nanowall (NWaFET) device with an inverse ratio structure can be realized through the process steps S0 to S14, and the process steps are compatible with the process of 3D nanowall (NWaFET). Figure 6 As shown, prepare N+ single wafer; S1: as Figure 7 As shown, an N-type epitaxial layer is epitaxially grown as an N-region of a lightly doped drain; S2: as Figure 8 As shown, a P-type epitaxial layer is epitaxially grown as a channel isolation layer of the inverse ratio transistor, and the P-type epitaxial layer here is recorded as a P1-type epitaxial layer; S3: as Fig. 9 As shown, a layer of silicon dioxide is deposited; S4: as Fig.10 As shown, part of the silicon dioxide is etched to prepare for subsequent epitaxial growth; S5: as Fig.11 As shown, the N+ type epitaxial layer is selectively grown to form the drain and source active regions of the inverse ratio transistor. The silicon dioxide region cannot grow, but the P1 type epitaxial layer can grow; S6: as Fig.12 As shown, the excess silicon dioxide is etched; S7: as Fig.13 As shown, a P-type epitaxial layer is epitaxially grown as the channel layer of the inverse ratio transistor, and the P-type epitaxial layer here is recorded as a P2-type epitaxial layer; S8: Fig.14 As shown, a layer of silicon dioxide is deposited; S9: as Fig.15 As shown, a chemical mechanical polishing is performed to grind away the excess part; S10: as Fig.16 As shown, etching the gate groove; S11: as Fig.17 As shown, a thin layer of silicon dioxide is deposited to form a gate oxide layer of the inverse ratio transistor; S12: as Fig.18 As shown, etching excess silicon dioxide; S13: as Fig.19 As shown, metal is deposited; S14: as Fig. 20 As shown, the excess metal is etched away to form the leads of the various ports of the inverse ratio tube; BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0016] Figure 1 A front view of the inverted tube structure of a new type of 3D nanowall (NWaFET) device

[0017] Figure 2 A right-side stereoscopic view of the inverted tube structure of a new 3D nanowall (NWaFET) device

[0018] Figure 3 A top view of the inverse tube structure of a new 3D nanowall (NWaFET) device

[0019] Figure 4 A cross-sectional view perpendicular to the main viewing plane of a new type of 3D nanowall (NWaFET) device with an inverse tube structure

[0020] Figure 5 A cross-sectional view parallel to the main viewing plane of a new type of 3D nanowall (NWaFET) device with an inverse tube structure

[0021] Figure 6Schematic diagram of the inverse tube process step S0 of a new 3D nanowall (NWaFET) device

[0022] Figure 7 Schematic diagram of the inverse tube process step S1 of a new 3D nanowall (NWaFET) device

[0023] Figure 8 Schematic diagram of the inverse transistor process step S2 of a new 3D nanowall (NWaFET) device

[0024] Fig. 9 Schematic diagram of the inverse tube process step S3 of a new 3D nanowall (NWaFET) device

[0025] Fig.10 Schematic diagram of the inverse transistor process step S4 of a new 3D nanowall (NWaFET) device

[0026] Fig.11 Schematic diagram of the inverse transistor process step S5 of a new 3D nanowall (NWaFET) device

[0027] Fig.12 Schematic diagram of the inverse transistor process step S6 of a new 3D nanowall (NWaFET) device

[0028] Fig.13 Schematic diagram of the inverse transistor process step S7 of a new 3D nanowall (NWaFET) device

[0029] Fig.14 Schematic diagram of the inverse transistor process step S8 of a new 3D nanowall (NWaFET) device

[0030] Fig.15 Schematic diagram of the inverse transistor process step S9 of a new 3D nanowall (NWaFET) device

[0031] Fig.16 Schematic diagram of the inverse transistor process step S10 of a new 3D nanowall (NWaFET) device

[0032] Fig.17 Schematic diagram of the inverse transistor process step S11 of a new 3D nanowall (NWaFET) device

[0033] Fig.18 Schematic diagram of the inverse transistor process step S12 of a new 3D nanowall (NWaFET) device

[0034] Fig.19 Schematic diagram of the inverse tube process step S13 of a new 3D nanowall (NWaFET) device

[0035] Fig. 20 Schematic diagram of the inverse tube process step S14 of a new 3D nanowall (NWaFET) device DETAILED DESCRIPTION

[0036] [Example]

[0037] The process flow of a new type of 3D nano-wall (NWaFET) device is S0-S14, taking NMOS inverted transistor as an example:

[0038] S0: Figure 6 As shown, prepare an N+ single wafer;

[0039] S1: Figure 7 As shown, an N-type epitaxial layer is epitaxially grown to serve as an N-region of a lightly doped drain;

[0040] S2: Figure 8 As shown, a P-type epitaxial layer is epitaxially grown as a channel isolation layer of the inverse ratio transistor, and the P-type epitaxial layer here is recorded as a P1-type epitaxial layer;

[0041] S3: Fig. 9 As shown, a layer of silicon dioxide is deposited;

[0042] S4: Fig.10 As shown, part of the silicon dioxide is etched to prepare for subsequent epitaxial growth;

[0043] S5: Fig.11 As shown, the N+ type epitaxial layer is selectively grown to form the drain and source active regions of the inverse ratio transistor. The silicon dioxide region cannot grow, but the P1 type epitaxial layer can grow.

[0044] S6: Fig.12 As shown, the excess silicon dioxide is etched away;

[0045] S7: Fig.13 As shown, a P-type epitaxial layer is epitaxially grown as the channel layer of the inverse ratio transistor, and the P-type epitaxial layer here is recorded as a P2-type epitaxial layer;

[0046] S8: Fig.14 As shown, a layer of silicon dioxide is deposited;

[0047] S9: Fig.15 As shown, a chemical mechanical polishing is performed to grind away the excess part;

[0048] S10: Fig.16 As shown, etching a gate groove;

[0049] S11: Fig.17 As shown, a thin layer of silicon dioxide is deposited to form a gate oxide layer of the inverse ratio transistor;

[0050] S12: Fig.18 As shown, the excess silicon dioxide is etched away;

[0051] S13: Fig.19 As shown, metal is deposited;

[0052] S14: Fig. 20 As shown, the excess metal is etched away to form the lead-out ports of the inverse ratio tube.

Claims

1. A novel inverted transistor structure for a 3D nanowall transistor (NWaFET) device, using an NMOS inverted transistor as an example, as shown in Figures 1 to 5. This inverted transistor structure builds on the basic 3D nanowall transistor (NWaFET) structure by hollowing out the source region. The remaining active region serves as the source and drain of the inverted transistor. Region (101) is the gate electrode of the inverse transistor device, which is made of metal materials such as aluminum; region (102) is the drain electrode of the inverse transistor device, which is made of metal materials such as aluminum; region (103) is the source electrode of the inverse transistor device, which is made of metal materials such as aluminum; region (104) is the substrate electrode of the inverse transistor device, which is made of metal materials such as aluminum; region (105) is the gate oxide layer, which is made of silicon dioxide or other high-K dielectric materials; region (106) is the isolation layer used to isolate the source and drain, which is made of silicon dioxide or other high-K dielectric materials; region (107) is the active region of the drain, which is an N+ type semiconductor; region (108) is the channel layer of the original 3D nanowall (NWaFET) device, which is a P-type doped active region, represented by P1; Region (109) is a lightly doped drain region of the original 3D nanowall (NWaFET) device, which is an N-type semiconductor; Region (110) is the source active region of the original 3D nanowall (NWaFET) device, which is an N+ type semiconductor; region (111) is the channel region of the inverted transistor device, which is a P type semiconductor, represented by P2; the channel length of the inverted transistor is the distance from the right boundary of region (102) to the left boundary of region (103), and the channel width is the thickness of region (111). A new inverted transistor structure of a 3D nanowall NWaFET device is characterized by The gate oxide layer is made on the sidewall to facilitate integration with the 3D nanowall NWaFET device.

2. A novel inverted transistor structure of a 3D nanowall transistor (NWaFET) device, as shown in Figures 1 to 5, has a gate oxide layer on the sidewall, making it easy to integrate with the 3D nanowall transistor (NWaFET) device.

3. A new inverted transistor structure for a 3D nanowall transistor (NWaFET) device. The channel length of this inverted transistor device is no longer limited by the thickness of the epitaxial growth and can be controlled by controlling the etching length, solving the problem that the original 3D nanowall transistor (NWaFET) could not make a long channel device. Its channel width can be controlled by the thickness of the epitaxial growth.

4. A novel process step for the inverse transistor structure of a 3D nanowall (NWaFET) device, as shown in Figures 6 to 20, can realize a novel inverse transistor structure of a 3D nanowall (NWaFET) device through process steps S0 to S14, and the process steps are compatible with the process of 3D nanowall (NWaFET). The process steps are as follows: S0: as shown in FIG6, prepare an N+ single wafer; S1: as shown in FIG7, epitaxially grow an N-type epitaxial layer as the N-region of the lightly doped drain; S2: as shown in FIG8, epitaxially grow a P-type epitaxial layer as the channel isolation layer of the inverted transistor, where the P-type epitaxial layer is recorded as the P1-type epitaxial layer; S3: as shown in FIG9, deposit a layer of silicon dioxide; S4: as shown in FIG10, etch part of the silicon dioxide to prepare for subsequent epitaxial growth; S5: as shown in FIG11, selectively grow an N+ type epitaxial layer to form the drain and source active regions of the inverted transistor, where silicon dioxide cannot grow, but can grow on the P1-type epitaxial layer; S6: as shown in FIG12, Etch the excess silicon dioxide; S7: as shown in FIG13, epitaxially grow a P-type epitaxial layer as the channel layer of the inverse ratio transistor, where the P-type epitaxial layer is recorded as a P2-type epitaxial layer; S8: as shown in FIG14, deposit a layer of silicon dioxide; S9: as shown in FIG15, perform a chemical mechanical polishing to grind off the excess part; S10: as shown in FIG16, etch the gate groove; S11: as shown in FIG17, deposit a thin layer of silicon dioxide to form a gate oxide layer of the inverse ratio transistor; S12: as shown in FIG18, etch the excess silicon dioxide; S13: as shown in FIG19, deposit metal; S14: as shown in FIG20, etch the excess metal to form the various port leads of the inverse ratio transistor.

Images