GaN-based transistor and manufacturing method and application thereof

Abstract

The invention discloses a GaN-based transistor and a manufacturing method and application thereof, and belongs to the technical field of semiconductors. The GaN-based transistor sequentially comprises a substrate, an N-GaN layer, a U-GaN layer, an InGaN layer, a source electrode, a drain electrode and a grid electrode, wherein the source electrode, the drain electrode and the grid electrode are arranged on the InGaN layer. Wherein the In component content of the InGaN layer is 1%-2%; the InGaN layer is provided with a P-type source region and a P-type drain region; the source electrode and the drain electrode are respectively arranged on the P-type source region and the P-type drain region, and the grid electrode is arranged between the source electrode and the drain electrode and is separated from the InGaN layer through a grid dielectric layer, so that a high-performance GaN pMOS device structure is constructed and is combined with a PN junction diode structure, and the application of the GaN pMOS device structure in a GaN CMOS logic circuit is realized. According to the manufacturing method, ion implantation is reduced, damage to the surface of the GaN device is activated, and the performance of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors, and in particular relates to a GaN-based transistor and a manufacturing method and application thereof. Background Art

[0002] As a third-generation semiconductor, GaN is the future development direction for solid-state microwave power devices and power electronics due to its advantages, such as high electron saturation drift velocity, wide bandgap, high temperature resistance, and high breakdown field strength. Currently, GaN applications in the power and RF industries are primarily based on GaN HEMTs. This single structure fails to fully demonstrate the advantages of GaN devices at high frequencies and high voltages. Furthermore, current research in academia and industry primarily focuses on n-channel devices. A true GaN complementary logic integrated circuit requires p-channel devices, and achieving high-performance p-channel devices is challenging. Existing p-channel devices are often constructed by forming a p-type doped region within an n-GaN substrate. This suffers from limited doping efficiency, low activation rate, and material damage, making it difficult to achieve high-performance GaN PMOS device structures. This has hindered the development and application of GaN CMOS logic circuits. Summary of the Invention

[0003] In view of the deficiencies in the prior art, the present invention provides a GaN-based transistor and a manufacturing method and application thereof.

[0004] In order to achieve the above objectives, the technical solution of the present invention is:

[0005] A GaN-based transistor comprises, in order, a substrate, an N-GaN layer, a U-GaN layer, and an InGaN layer, as well as a source, a drain, and a gate arranged on the InGaN layer; wherein the In component content of the InGaN layer is 1% to 2%; the InGaN layer has a P-type source region and a P-type drain region; the source and the drain are respectively arranged on the P-type source region and the P-type drain region, and the gate is arranged between the source and the drain and is separated from the InGaN layer by a gate dielectric layer.

[0006] Optionally, the N-type doping concentration of the N-GaN layer is 1E18~3E19 cm -3 The thickness of the N-GaN layer is 1-5 μm, the thickness of the U-GaN layer is 2-4 μm, and the thickness of the InGaN layer is 200-400 nm.

[0007] Optionally, the intrinsic carrier concentration of the U-GaN layer is less than 5E17 cm -3 The intrinsic carrier concentration of the InGaN layer outside the P-type source region and the P-type drain region is less than 1E17 cm -3 The P-type source and drain regions are doped with Mg, and the Mg doping concentration is 1E19~1E20 cm-3 .

[0008] Optionally, the channel length between the P-type source region and the P-type drain region is 200-1000 nm; the gate is located above the channel, with both ends exceeding the channel length by more than 0.5 μm and being more than 4 μm away from the source and drain.

[0009] Optionally, the gate dielectric layer has a thickness of 10 to 30 nm; the gate dielectric layer is made of an aluminum oxide layer, silicon nitride, or silicon oxide.

[0010] Optionally, a back electrode is further included, wherein the back electrode is provided on the etched mesa of the N-GaN layer and forms an ohmic contact with the N-GaN layer.

[0011] A method for manufacturing the above-mentioned GaN-based transistor comprises the following steps:

[0012] 1) Sequentially growing an N-GaN layer, a U-GaN layer, and an InGaN layer on a substrate;

[0013] 2) Forming P-type source and P-type drain regions in the InGaN layer through selective ion implantation and annealing activation;

[0014] 3) Depositing a gate dielectric layer and forming a P-type ohmic contact to form a source electrode and a drain electrode on the P-type source region and the P-type drain region, respectively;

[0015] 4) Forming a gate on the gate dielectric layer between the source and the drain.

[0016] Optionally, the growth temperature of the InGaN layer is greater than 800°C; step 2) includes

[0017] 2.1) Deposit a first dielectric protective layer with a thickness of 20-40 nm on the InGaN layer by selectively implanting Mg ions with an energy of 15-40 KeV and an implantation dose of 1E13 cm -2 ~ 1E14 cm -2 ; forming a P-type source region and a P-type drain region in the InGaN layer, and then removing the first dielectric protective layer;

[0018] 2.2) Deposit a second dielectric protective layer with a thickness of 250-400 nm on the InGaN layer and anneal the layer in a nitrogen atmosphere at a temperature of 1100-1250°C for 1-8 hours. After annealing, remove the second dielectric protective layer.

[0019] Optionally, the first dielectric protection layer is SiN, and the second dielectric protection layer is a stack of 10-30 nm SiO2 and 250-350 nm SiN.

[0020] The In component content is 1%~2%, more preferably about 1%-1.5%. A small amount of In can reduce the activation energy of Mg ion implantation into GaN, and the crystal quality of In-doped GaN at high temperature (800°C) is high. The annealing temperature for activation of Mg-implanted GaN is reduced, and the activation efficiency is improved while ensuring the crystal quality. This can increase the mobility of pMOS and reduce the leakage of pMOS.

[0021] A semiconductor device, wherein the epitaxial structure of the semiconductor device includes a substrate, an N-GaN layer, a U-GaN layer and an InGaN layer in sequence, and is provided with a transistor region and a diode region. The transistor region forms the above-mentioned GaN-based transistor; the InGaN layer in the diode region has an ion-implanted P-type junction region, a P electrode is provided on the P-type junction region, and an N electrode is provided on the etched mesa of the N-GaN layer in the diode region.

[0022] Optionally, a first dielectric layer is further provided on the diode region, and the first dielectric layer and the gate dielectric layer are provided on the same layer.

[0023] Optionally, the InGaN layer of the diode region further has at least one P-type field limiting ring region implanted with ions, and the P-type field limiting ring region is arranged outside the P-type junction region and the distance between the P-type field limiting ring region and the P-type junction region is 200~2000 nm; when multiple P-type field limiting ring regions are arranged at intervals, the distance between adjacent P-type field limiting ring regions is 200~1000 nm.

[0024] A method for manufacturing the above-mentioned semiconductor device includes:

[0025] 1) Sequentially grow N-GaN, U-GaN, and InGaN layers on the substrate, and plan the transistor and diode regions;

[0026] 2) Forming a P-type source region, a P-type drain region, and a P-type junction region in the InGaN layer through selective ion implantation and annealing activation, wherein the P-type source region and the P-type drain region are located in the transistor region, and the P-type junction region is located in the diode region;

[0027] 3) Depositing a dielectric layer and forming a P-type ohmic contact to form a source electrode and a drain electrode on the P-type source region and the P-type drain region, respectively, and forming a P electrode on the P-type junction region; wherein the dielectric layer serves as a gate dielectric layer in the transistor region and as a first dielectric layer in the diode region;

[0028] 4) performing mesa etching and fabricating an N-type ohmic contact on the etched mesa of the N-GaN layer to form an N electrode;

[0029] 5) Forming a gate on the gate dielectric layer between the source and the drain.

[0030] Furthermore, during the ion implantation in step 2), at least one P-type field limiting ring region is also formed outside the P-type junction region in the diode region.

[0031] An integrated circuit comprises the above-mentioned GaN-based transistor or the above-mentioned semiconductor device.

[0032] The beneficial effects of the present invention are:

[0033] Through ion implantation and epitaxial structure construction, a high-performance GaN pMOS device structure is produced and combined with a PN junction diode structure to realize its application in GaN CMOS logic circuits and can be applied to amplifiers and other fields.

[0034] The manufacturing method of the present invention improves the activation rate of GaN p-type selective doping while ensuring the reduction of annealing activation temperature, reduces the damage to the GaN device surface caused by ion implantation and activation, and improves the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of the structure of the GaN-based transistor of Example 1;

[0036] Figure 2(a) to Figure 2(f) Schematic diagram of the process of manufacturing the GaN-based transistor of Example 1;

[0037] Figure 3 Schematic diagram of the structure of the GaN-based transistor of Example 2;

[0038] Figure 4 Schematic diagram of the structure of the semiconductor device of Example 3;

[0039] Figure 5 Schematic diagram of a top view of the semiconductor device of Example 3;

[0040] Figure 6(a) to Figure 6(g) Schematic diagram of the process of manufacturing a semiconductor device according to Example 3;

[0041] Figure 7 This is an application circuit example of the semiconductor device according to Example 3. DETAILED DESCRIPTION

[0042] The present invention is further explained below with reference to the accompanying drawings and specific embodiments. The drawings are provided for illustrative purposes only to facilitate understanding of the present invention, and their specific proportions may be adjusted according to design requirements. Those skilled in the art will understand that the vertical relationships between components and the definitions of front and back in the figures described herein refer to the relative positions of components. Therefore, they can be flipped to present the same components, and all such representations are within the scope of this specification.

[0043] Example 1

[0044] refer to Figure 1 The epitaxial structure of the GaN-based transistor of Example 1 includes, in order, a substrate 1, an N-GaN layer 2, a U-GaN layer 3 (an unintentionally doped GaN layer), and an InGaN layer 4, as well as a gate dielectric layer 5, a source S, a drain D, and a gate G disposed on the InGaN layer 4. The substrate 1 can be made of, for example, Si, SiC, sapphire, or a free-standing substrate; the N-GaN layer 2 has an N-type doping concentration of 1E18 to 3E19 cm -3 , for example, in 5×10 18 cm -3 ~1×10 19 cm -3 The intrinsic carrier concentration of the U-GaN layer 3 is less than 5E17 cm -3 More preferably, the intrinsic carrier concentration of the U-GaN layer 3 is less than 5E16 cm -3 , thickness 2~4μm; the intrinsic carrier concentration of InGaN layer 4 is less than 1E17 cm -3 More preferably, the intrinsic carrier concentration of the InGaN layer 4 is less than 5E16 cm -3 The thickness is 200-400 nm, and the In component content is 1%-2%, more preferably 1%-1.5%. The InGaN layer 4 has a P-type source region a and a P-type drain region b implanted with Mg ions, with an ion implantation dose of 1E13 cm -2 ~ 1E14 cm -2 The P-type source region a and P-type drain region b are doped with Mg, and the Mg doping concentration is 1E19~1E20 cm -3 The source S and drain D are respectively arranged on the P-type source region a and the P-type drain region b and form ohmic contacts. The source S and drain D are arranged opposite to each other. The gate G is arranged between the source S and the drain D and is separated from the InGaN layer 4 by a gate dielectric layer 5. The gate dielectric layer 5 is 10~30 nm of Al2O3.

[0045] The following references Figure 2(a) to Figure 2(f) A method for manufacturing the above-mentioned GaN-based transistor will be described.

[0046] Referring to Figure 2(a), an N-GaN layer 2, a U-GaN layer 3, and an InGaN layer 4 are sequentially grown on a substrate 1 using an epitaxial growth process. The InGaN layer 4 is grown at a temperature greater than 800°C, preferably 800-900°C. The higher growth temperature ensures the quality of InGaN crystal growth and reduces the incorporation of impurity defects. The In composition is preferably 1%-1.5%, and the thickness is, for example, 300 nm. The U-GaN layer 3 is provided to improve the breakdown performance of the pMOS and reduce the gate electron injection effect.

[0047] Referring to Figure 2 (b), a 30 nm thick SiN layer is deposited on the surface of the InGaN layer 4 by ICPCVD as the first dielectric protection layer V1. A P-type source region a and a P-type drain region b are formed by selective Mg ion implantation. The ion implantation energy is 15-40 KeV. For example, the ion implantation energy is 20 KeV and the dose is 6E13 cm -2 The injection depth is equal to the thickness of the InGaN layer 4, with the first dielectric protective layer V1 acting as a buffer. Under these conditions, damage to the GaN is minimal, resulting in fewer defects and less hole compensation after p-type activation. The widths of the P-type source region a and the P-type drain region b are, for example, 100 to 200 μm, with 150 μm being an example. Their spacing, i.e., the channel length, is 200 to 1000 nm, with 1 μm being an example. The channel distance is minimized while avoiding the short channel effect and considering lithography accuracy. This is because GaN holes have low mobility, and the activation rate of injection activation is currently not as high as that of epitaxy. Shortening the distance enhances its gate control effect. The area selection process can be implemented using a patterned shielding layer, for example. After the ion implantation is completed, the first dielectric protective layer V1 is removed.

[0048] Referring to Figure 2(c), a stack of 20 nm ALD-grown SiO2 and 300 nm LPCVD-grown SiN is sequentially deposited on the surface of the InGaN layer 4 as a second dielectric protective layer V2. Annealing is performed in a nitrogen atmosphere at a temperature of 1100-1250°C for 1-8 hours. The second dielectric protective layer V2 protects the GaN from corrosion and decomposition at high temperatures during annealing, and its removal process has minimal impact on the GaN. The small amount of In doping in the InGaN layer 4 reduces the activation energy of Mg ion implantation into the GaN, improving activation efficiency while maintaining high crystal quality. For example, the annealing condition parameters are: temperature 1250°C, N2 atmosphere, time 1h, normal pressure. Under these conditions, the injection lattice damage can be effectively repaired and the holes can be activated. At the same time, this is also the highest temperature that GaN can withstand without decomposition under normal pressure, and it has a high activation rate. In another embodiment, the annealing condition parameters are: 1100°C, N2 atmosphere, 8h, normal pressure. Under these conditions, extending the annealing time at a lower temperature can reduce the damage to the surface caused by high temperature, repair the injection lattice damage, and activate the holes. Thus, a high-performance semiconductor structure is obtained to meet the needs of the device. After the annealing process is completed, the second dielectric protective layer V2 is removed.

[0049] Referring to Figure 2(d), a p-type ohmic contact was prepared using a Ni / Au = 10 / 10 nm metal. Annealing was performed in an oxygen atmosphere at 550°C for 10 minutes. A source electrode S and a drain electrode D were formed on the P-type source region a and P-type drain region b, respectively. On the channel side, the edges of the source electrode S and drain electrode D were retracted relative to the edges of the P-type source region a and P-type drain region b to leave space for the gate.

[0050] Referring to Figure 2(e), a 20 nm thick layer of Al₂O₃ is deposited as the gate dielectric layer 5 using an ALD process at a growth temperature of 350°C. The Al source reacts with ozone to form the gate dielectric layer 5. This gate dielectric layer 5 covers both the source electrode S and the drain electrode D. In subsequent fabrication steps, holes can be selectively opened in these electrodes to facilitate external connections. Al₂O₃ is used as the gate dielectric layer to regulate the pMOS threshold and serves as the gate dielectric for MOS structures. During mass production of devices on a wafer, this step can be followed by insulating implantation to isolate the individual devices on the wafer. In other embodiments, the gate dielectric layer 5 can be made of silicon nitride or silicon oxide.

[0051] Referring to Figure 2(f), a gate metal (Ni / Au = 50 / 150nm) is evaporated on the gate dielectric layer 5 between the source S and drain D. Annealing is performed at 400°C for 5 minutes to reduce gate leakage, thereby forming the gate G and the final GaN p-MOS device. The sides of the gate G extend at least 0.5μm beyond the channel length and are at least 4μm from the source S and drain D. The sides of the gate G overlap above the P-type source region a and the P-type drain region b, enhancing the gate's control over the channel and changing the turn-on voltage.

[0052] In addition, in other embodiments, the gate dielectric layer 5 may be deposited first, the gate dielectric layer 5 located above the P-type source region a and the P-type drain region b may be opened, and then the P ohmic contact may be prepared.

[0053] Example 2

[0054] refer to Figure 3 The GaN-based transistor of Example 2 differs from Example 1 in that it also includes mesa etching, the etching depth reaches the surface of the N-GaN layer 2, and an N-type ohmic contact is made on the N-GaN layer 2 to form a back electrode 6. The back electrode 6 serves as an n-type contact layer for regulating the threshold voltage, thereby preparing a triode device. The metal of the back electrode 6 is Ti / Al / Ni / Au=20 / 20 / 50 / 150 nm. Due to the heavy doping of the N-GaN layer 2, an ohmic contact can be formed without annealing the N-type ohmic. The steps of mesa etching and back electrode 6 production can be performed before the preparation of the gate metal, or can be adjusted according to actual needs. The distance between the back metal 6 and the mesa etching edge is preferably 20~30 μm, which can achieve better regulation performance.

[0055] Example 3

[0056] refer to Figure 4 and Figure 5 The semiconductor device of Example 3 has an epitaxial structure that includes a substrate 1, an N-GaN layer 2, a U-GaN layer 3, and an InGaN layer 4 in sequence, and is provided with a transistor region A and a diode region B. The transistor formed in the transistor region is a pMOS transistor, and the diode formed in the diode region is a PN junction diode. The arrangement of the epitaxial structure is the same as that of Example 1, and a GaN-based transistor structure as in Example 1 is formed in the transistor region A. In the diode region, the InGaN layer 4 has an ion-implanted P-type junction region c and a P-type field limiting ring region d. The P-type field limiting ring region d is arranged outside the P-type junction region c, and a P electrode 7 is provided on the P-type junction region c. An N electrode 8 is provided on the etched mesa of the N-GaN layer 2 of the diode region B. The P-type junction region c and the P-type field limiting ring region d have, for example, the same ion implantation dose as the P-type source region a and the P-type drain region b, and the Mg ion implantation dose is 1E13 cm -2 ~ 1E14 cm -2 A first dielectric layer 9 is provided on the InGaN layer 4 of the diode region B. The first dielectric layer 9 can be provided on the same layer as the gate dielectric layer 5 .

[0057] The following references Figure 6(a) to Figure 6(g) A method for manufacturing the above-mentioned GaN-based transistor will be described.

[0058] Referring to Figure 6(a), an N-GaN layer 2, a U-GaN layer 3, and an InGaN layer 4 are sequentially grown on a substrate 1 using an epitaxial growth process. The InGaN layer 4 is grown at a temperature > 800°C, preferably with an In composition of 1% to 1.5%, and a thickness of 300 nm, for example. Transistor region A and diode region B are then planned.

[0059] Referring to Figure 6 (b), a 30 nm thick SiN layer is deposited on the surface of the InGaN layer 4 by ICPCVD as the first dielectric protective layer V1. A P-type source region a, a P-type drain region b, a P-type junction region c, and a P-type field limiting ring region d are formed by selective Mg ion implantation. The ion implantation energy is 15-40 KeV. For example, the ion implantation energy is 20 KeV and the dose is 6E13 cm -2 The implantation depth is equal to the thickness of the InGaN layer 4. The P-type source region a and the P-type drain region b are located in the transistor region A. The structure can refer to that of Example 1. The P-type junction region c and the P-type field-limiting ring region d are located in the diode region B. The spacing between the P-type junction region and the P-type field-limiting ring region is 200-2000 nm. When multiple P-type field-limiting ring regions d are present, the spacing between adjacent P-type field-limiting ring regions d is 200-1000 nm. After the ion implantation is completed, the first dielectric protective layer V1 is removed.

[0060] Referring to Figure 6(c), a stack of 20 nm ALD-grown SiO2 and 300 nm LPCVD-grown SiN layers is sequentially deposited on the surface of the InGaN layer 4 as the second dielectric protective layer V2. Annealing is performed in a nitrogen atmosphere at a temperature of 1100-1250°C for 1-8 hours. For example, the annealing parameters are: 1250°C, N2 atmosphere, 1 hour, atmospheric pressure. These conditions effectively repair implanted lattice damage and activate holes. This is also the highest temperature GaN can withstand at atmospheric pressure without decomposition, resulting in a high activation rate. In another embodiment, the annealing parameters are: 1100°C, N2 atmosphere, 8 hours, atmospheric pressure. Under these conditions, a lower temperature and longer annealing time minimize high-temperature surface damage, repair implanted lattice damage, and activate holes. After the annealing process is completed, the second dielectric protective layer V2 is removed.

[0061] Referring to FIG6 (d), a p-type ohmic contact is prepared using Ni / Au=10 / 10 nm metal and annealing is performed in an oxygen atmosphere at a temperature of 550°C for 10 min. A source S and a drain D are formed on the P-type source region a and the P-type drain region b, respectively, and a P electrode 7 is formed on the P-type junction region c.

[0062] Referring to Figure 6(e), a 20 nm thick Al2O3 dielectric layer V3 is deposited using an ALD process. This layer serves as the gate dielectric layer 5 in the gate region of transistor region A and as the first dielectric layer 9 on the surface of the InGaN layer 4 in diode region B. The dielectric layer V3 also covers the surfaces of the source S, drain D, and P electrode 7. In subsequent fabrication processes, holes can be selectively opened in these electrodes as needed to facilitate external connections.

[0063] Referring to Figure 6(f), mesa etching is performed to the surface of the N-GaN layer 2, and an N-type ohmic contact is made on the etched mesa in the diode region B to form an N electrode 8. The metal is Ti / Al / Ni / Au = 20 / 20 / 50 / 150 nm. Due to the heavy doping, the N-type ohmic contact can be formed without annealing.

[0064] 6( g ), a gate metal is evaporated on the gate dielectric layer 5 between the source S and the drain D. Ni / Au=50 / 150nm is used and annealed at 400° C. for 5 min to reduce gate leakage, thereby forming a gate G.

[0065] In addition, according to actual needs such as device protection, a passivation layer can be added into the structure or on the surface of the structure. This is a conventional technology.

[0066] The semiconductor device mentioned above simultaneously manufactures a pMOS transistor and a PN junction diode, arranges and connects the devices according to the circuit design, and can be used to combine and connect with other device structures to realize a GaN CMOS logic circuit.

[0067] The semiconductor device of the present invention can be applied to an integrated circuit. In an application circuit in which an integrated circuit includes both a transistor and a diode, for example, Figure 7 In the XOR gate logic circuit, if the levels of the two inputs A and B are different, the output is a high level 1 and the transistor is turned on; if the levels of the two inputs A and B are the same, the output is a low level 0 and the transistor is not turned on.

[0068] The above embodiments are only used to further illustrate a GaN-based transistor and its manufacturing method and application of the present invention, but the present invention is not limited to the embodiments. Any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention fall within the scope of protection of the technical solution of the present invention.

Claims

1. A GaN-based transistor, characterized in that: It includes, in order, a substrate, an N-GaN layer, a U-GaN layer and an InGaN layer, and a source, a drain and a gate arranged on the InGaN layer; wherein the In component content of the InGaN layer is 1% to 2%; the InGaN layer has a P-type source region and a P-type drain region; the source and the drain are arranged on the P-type source region and the P-type drain region respectively, and the gate is arranged between the source and the drain and is separated from the InGaN layer by a gate dielectric layer.

2. The GaN-based transistor according to claim 1, characterized in that: The N-type doping concentration of the N-GaN layer is 1E18~3E19cm -3 ; The thickness of the N-GaN layer is 1~5 μm, the thickness of the U-GaN layer is 2~4 μm, and the thickness of the InGaN layer is 200~400 nm.

3. The GaN-based transistor according to claim 1, characterized in that: The intrinsic carrier concentration of the U-GaN layer is less than 5E17 cm -3 , the intrinsic carrier concentration of the InGaN layer outside the P-type source region and the P-type drain region is less than 1E17 cm -3 ; P-type source region and P-type drain region are doped with Mg, and the Mg doping concentration is 1E19~1E20 cm -3 .

4. The GaN-based transistor according to claim 1, characterized in that: The channel length between the P-type source region and the P-type drain region is 200-1000 nm; the gate is located above the channel, with both ends exceeding the channel length by more than 0.5 μm and being more than 4 μm away from the source and drain.

5. The GaN-based transistor according to claim 1, characterized in that: The gate dielectric layer has a thickness of 10-30 nm; the gate dielectric layer material is an aluminum oxide layer, silicon nitride or silicon oxide.

6. The GaN-based transistor according to claim 1, characterized in that: The invention also includes a back electrode, which is arranged on the etched mesa of the N-GaN layer and forms an ohmic contact with the N-GaN layer.

7. A method for manufacturing a GaN-based transistor according to any one of claims 1 to 6, characterized in that: The following steps are involved: 1) Growing N-GaN layer, U-GaN layer and InGaN layer in sequence on the substrate; 2) Forming a P-type source region and a P-type drain region in the InGaN layer through selective ion implantation and annealing activation; 3) Depositing a gate dielectric layer and fabricating a P-type ohmic contact to form a source electrode and a drain electrode on the P-type source region and the P-type drain region, respectively; 4) A gate is formed on the gate dielectric layer between the source and the drain.

8. The method for manufacturing a GaN-based transistor according to claim 7, characterized in that: The growth temperature of the InGaN layer is greater than 800°C; step 2) comprises 2.1) A first dielectric protective layer with a thickness of 20-40 nm is deposited on the InGaN layer, and Mg ions are selectively implanted with an energy of 15-40 KeV and an implantation dose of 1E13 cm -2 ~ 1E14 cm -2 ; forming a P-type source region and a P-type drain region in the InGaN layer, and then removing the first dielectric protective layer; 2.2) A second dielectric protective layer with a thickness of 250-400 nm is deposited on the InGaN layer, and annealed in a nitrogen atmosphere at a temperature of 1100-1250 °C for 1-8 h. After the annealing is completed, the second dielectric protective layer is removed.

9. The method for manufacturing a GaN-based transistor according to claim 8, characterized in that: The first dielectric protection layer is SiN, and the second dielectric protection layer is a stack of 10-30 nm SiO2 and 250-350 nm SiN.

10. A semiconductor device, characterized in that: The epitaxial structure of the semiconductor device includes a substrate, an N-GaN layer, a U-GaN layer and an InGaN layer in sequence, and is provided with a transistor region and a diode region. The transistor region forms the GaN-based transistor according to any one of claims 1 to 6; the InGaN layer in the diode region has an ion-implanted P-type junction region, a P electrode is provided on the P-type junction region, and an N electrode is provided on the etched table of the N-GaN layer in the diode region.

11. The semiconductor device according to claim 10, wherein: A first dielectric layer is also disposed on the diode region, and the first dielectric layer and the gate dielectric layer are disposed on the same layer.

12. The semiconductor device according to claim 10, wherein: The InGaN layer in the diode region also has at least one P-type field limiting ring region implanted with ions, and the P-type field limiting ring region is arranged outside the P-type junction region and the distance between the P-type junction region and the P-type junction region is 200~2000 nm; when it includes multiple P-type field limiting ring regions arranged at intervals, the distance between adjacent P-type field limiting ring regions is 200~1000 nm.

13. A method for manufacturing a semiconductor device according to claim 10, characterized in that: 1) Grow N-GaN layer, U-GaN layer and InGaN layer in sequence on the substrate, and plan the transistor area and diode area; 2) Forming a P-type source region, a P-type drain region and a P-type junction region in the InGaN layer through selective ion implantation and annealing activation, wherein the P-type source region and the P-type drain region are located in the transistor region, and the P-type junction region is located in the diode region; 3) Depositing a dielectric layer and fabricating a P-type ohmic contact to form a source electrode and a drain electrode on the P-type source region and the P-type drain region, respectively, and forming a P electrode on the P-type junction region; in The dielectric layer serves as a gate dielectric layer in the transistor region and as a first dielectric layer in the diode region; 4) performing mesa etching and fabricating an N-type ohmic contact on the etched mesa of the N-GaN layer to form an N electrode; 5) A gate is formed on the gate dielectric layer between the source and the drain.

14. An integrated circuit, characterized in that: Comprising the GaN-based transistor according to claim 1 or the semiconductor device according to claim 10.

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