Control circuit for PFC circuit and THD optimization method

Abstract

The invention provides a control circuit for a PFC (power factor correction) circuit and a THD (total harmonic distortion) optimization method of the control circuit. The control circuit comprises an input voltage amplitude judgment circuit which is used for obtaining an input voltage amplitude judgment signal used for judging the amplitude of the input voltage of the input end of the PFC circuit; the maximum conduction time control circuit is used for controlling the maximum conduction time of the main power switch tube based on the input voltage amplitude judgment signal, when the input voltage amplitude is a first voltage, the maximum conduction time is a first time, when the input voltage amplitude is a second voltage, the maximum conduction time is a second time, the first voltage is greater than the second voltage, and the second voltage is greater than the first time. The first time is shorter than the second time. According to the control circuit for the PFC circuit and the THD optimization method of the control circuit, the THD performance can be obviously improved by reducing the maximum conduction time in a high input voltage amplitude state.

Description

Technical Field

[0001] The present invention relates to the field of electronics, and in particular but not limited to, to a control circuit for a power factor correction (PFC) circuit and a total harmonic distortion (THD) optimization method thereof. Background Art

[0002] In order to reduce the harmonic current pollution and reactive power increase caused by the non-sinusoidal current waveform distortion generated by the switching power supply, it is generally required to add a power factor correction (PFC) circuit to the power supply design so that the input current follows the sinusoidal changes of the input voltage and reduces distortion.

[0003] In small and medium power switching power supplies, boost PFC circuits are often used. Figure 1 The current operating modes of general PFC circuits include continuous current mode (CCM), critical current mode (CRM) and discontinuous current mode (DCM). Figure 2 As shown. Generally, in the design of power supply of less than 250W, the Boost PFC chip in CRM mode will be selected. In order to take into account the efficiency, the chip will be set to DCM mode. As the power supply becomes more and more high-frequency and full-voltage range design, under the condition of high Vin or high frequency, the PFC chip will work in DCM mode to a deeper extent, resulting in poor total harmonic distortion (THD) performance.

[0004] In view of this, it is necessary to provide an optimized structure or control method in order to solve or improve at least part of the above problems. Summary of the invention

[0005] To at least address one or more problems in the background technology, the present invention proposes a control circuit for a PFC circuit and a THD optimization method thereof.

[0006] According to one aspect of the present invention, a control circuit for a power factor correction (PFC) circuit is provided. The PFC circuit includes a main power switch tube. The control circuit generates a switch control signal for controlling the on and off of the main power switch tube. The control circuit includes: an input voltage amplitude judgment circuit, which obtains an input voltage amplitude judgment signal for judging the amplitude of an input voltage at an input end of the PFC circuit; and a maximum on-time control circuit, which controls the maximum on-time of the main power switch tube based on the input voltage amplitude judgment signal, wherein the on-time of the main power switch tube does not exceed the maximum on-time, when the input voltage amplitude is a first voltage, the maximum on-time is a first time, and when the input voltage amplitude is a second voltage, the maximum on-time is a second time, wherein the first voltage is greater than the second voltage, and the first time is less than the second time.

[0007] Optionally, the input voltage amplitude judgment circuit includes: an input voltage detection circuit, used to obtain an input voltage detection signal representing the input voltage; an amplitude detection circuit, coupled to the input voltage detection circuit, and generating an input voltage amplitude detection signal representing the input voltage amplitude based on the input voltage detection signal; and at least one input voltage amplitude comparison circuit, used to compare the input voltage amplitude detection signal and a threshold signal, and generate an input voltage amplitude judgment signal according to the comparison result; wherein the maximum on-time control circuit selects one of at least two times as the maximum on-time according to the input voltage amplitude judgment signal.

[0008] Optionally, the PFC circuit includes a rectifier circuit and a boost switching circuit, the boost switching circuit includes an inductor, a main power switch tube and a rectifier tube, wherein an input end of the rectifier circuit receives an AC power supply, an output end of the rectifier circuit is coupled to a first end of the inductor, a second end of the inductor is coupled to a first end of the main power switch tube and a first end of the rectifier tube, a second end of the rectifier tube is coupled to an output end of the boost switching circuit, and a control circuit controls the maximum conduction time based on the amplitude of the AC power supply.

[0009] Optionally, the input voltage amplitude judgment circuit includes: an input voltage detection circuit, coupled to the first end of the main power switch tube, to obtain an input voltage detection signal representing the input voltage; and an amplitude detection circuit, coupled to the input voltage detection circuit, to generate an input voltage amplitude detection signal representing the input voltage amplitude based on the input voltage detection signal; the input voltage amplitude judgment circuit generates an input voltage amplitude judgment signal based on the input voltage amplitude detection signal.

[0010] Optionally, the control circuit further includes: an error amplifier circuit, which performs error amplification on an output voltage feedback signal representing the output voltage of the PFC circuit and a voltage reference signal; a compensation circuit, whose input end is coupled to the output end of the error amplifier circuit for generating a compensation feedback signal; and a shutdown comparison circuit, which receives a sawtooth wave signal and a compensation feedback signal, and is used to compare the sawtooth wave signal and the compensation feedback signal to generate a shutdown control signal for shutting down the main power switch tube; wherein when the input voltage amplitude is a first voltage, the slope of the sawtooth wave signal is a first slope, and when the input voltage amplitude is a second voltage, the slope of the sawtooth wave signal is a second slope, and wherein the first slope is greater than the second slope.

[0011] Optionally, the control circuit further includes a sawtooth wave signal generating circuit, the sawtooth wave signal generating circuit including: a current source; a first switch, whose control end is coupled to the switch control signal, whose first end is coupled to the current source, and whose second end is grounded; a capacitor, coupled between the first end and the second end of the first switch, the first end of the first switch providing a sawtooth wave signal; wherein when the input voltage amplitude is a first voltage, the current source has a first current value, and when the input voltage amplitude is a second voltage, the current source has a second current value, wherein the first current value is greater than the second current value.

[0012] Optionally, the control circuit further includes: an error amplifier circuit, which performs error amplification on an output voltage feedback signal representing the output voltage of the PFC circuit and a voltage reference signal; a compensation circuit, whose input end is coupled to the output end of the error amplifier circuit for generating a compensation feedback signal, the compensation feedback signal having an upper limit value of the compensation feedback signal; and a shutdown comparison circuit, which receives a sawtooth wave signal and a compensation feedback signal, and is used to compare the sawtooth wave signal and the compensation feedback signal to generate a shutdown control signal for shutting down the main power switch tube; wherein the maximum on-time control circuit adjusts the maximum on-time by adjusting the upper limit value of the compensation feedback signal based on the input voltage amplitude judgment signal, wherein when the maximum on-time is larger, the corresponding upper limit value of the compensation feedback signal is larger.

[0013] According to another aspect of the present invention, a method for optimizing THD in a PFC circuit is provided, wherein the PFC circuit includes a main power switch tube, and the method includes: controlling a maximum on-time of the main power switch tube based on an input voltage amplitude at an input end of the PFC circuit, wherein the on-time of the main power switch tube does not exceed the maximum on-time, so that when the input voltage amplitude is a first voltage, the maximum on-time is a first time, and when the input voltage amplitude is a second voltage, the maximum on-time is a second time, wherein the first voltage is greater than the second voltage, and the first time is less than the second time.

[0014] Optionally, the method includes: performing an error compensation operation on an output voltage feedback signal representing the output voltage of the PFC circuit and a voltage reference signal to generate a compensation feedback signal; and comparing the sawtooth wave signal and the compensation feedback signal to generate a shutdown control signal for shutting down the main power switch tube; when the input voltage amplitude is greater than a first threshold voltage, controlling the slope of the sawtooth wave signal to be a first slope, and when the input voltage amplitude is less than a second voltage threshold, controlling the slope of the sawtooth wave signal to be a second slope, wherein the first threshold voltage is greater than or equal to the second threshold voltage, and the first slope is greater than the second slope.

[0015] The method comprises: performing an error compensation operation on an output voltage feedback signal representing an output voltage of a PFC circuit and a voltage reference signal to generate a compensation feedback signal; and comparing a sawtooth wave signal with the compensation feedback signal to generate a shutdown control signal for shutting down a main power switch tube; when an input voltage amplitude is greater than a first threshold voltage, setting an upper limit value of the compensation feedback signal to a first value, and when the input voltage amplitude is less than a second voltage threshold, setting the upper limit value of the compensation feedback signal to a second value, wherein the first threshold voltage is greater than or equal to the second threshold voltage, and the first value is less than the second value.

[0016] The control circuit for a PFC circuit and the THD optimization method thereof proposed in the present invention can significantly improve THD performance by reducing the maximum on-time under a high input voltage amplitude state. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide a further understanding of the present invention and are used together with the description to explain the embodiments of the present invention, but do not constitute a limitation of the present invention. In the accompanying drawings:

[0018] Figure 1 A Boost PFC circuit is shown;

[0019] Figure 2 shows the current operating mode of the PFC circuit;

[0020] Figure 3 The switching frequency waveforms under different input voltages in CRM mode are shown;

[0021] Figure 4 shows a frequency limit waveform diagram;

[0022] Figure 5 The current operating mode at higher loads is shown;

[0023] Figure 6 The current operating mode at lower loads is shown;

[0024] Figure 7 The DCM working mode waveform is shown;

[0025] Figure 8 A schematic diagram of a PFC circuit system block diagram according to an embodiment of the present invention is shown.

[0026] Fig. 9 A schematic diagram of a control circuit according to an embodiment of the present invention is shown;

[0027] Fig.10 A waveform diagram of changing the maximum on-time according to an embodiment of the present invention is shown;

[0028] Fig.11A sawtooth wave signal generating circuit according to an embodiment of the present invention is shown;

[0029] Fig.12 A waveform diagram of changing the maximum on-time according to another embodiment of the present invention is shown;

[0030] Fig.13 A comparison diagram of THD improvement effects according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0031] In order to further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0032] The description in this section is only for several typical embodiments, and the present invention is not limited to the scope of the embodiments. The combination of different embodiments, the mutual replacement of some technical features in different embodiments, and the mutual replacement of the same or similar prior art means with some technical features in the embodiments are also within the scope of the description and protection of the present invention.

[0033] "Coupled" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conductive medium such as a conductor, wherein the electrical conductive medium may contain parasitic inductance or parasitic capacitance, or a connection through an intermediate circuit or component described in the embodiments in the specification; indirect connection may also include a connection through other active or passive devices on the basis of achieving the same or similar functions, such as a connection through circuits or components such as switches, signal amplification circuits, and follower circuits. "Multiple" or "many" means two or more.

[0034] Figure 3 The switching frequency waveform of the same PFC circuit in CRM mode at different input voltages in an input sinusoidal voltage cycle is shown. The upper figure is the waveform of the input voltage Vin, and the lower figure is the switching frequency waveform at the corresponding moment. Preferably, the input sinusoidal voltage cycle is the mains frequency cycle, such as 50Hz. The following is an explanation of the following figure. The first curve is the switching frequency when the input voltage amplitude is 265V, the second curve is the switching frequency when the input voltage amplitude is 220V, and the third curve is the switching frequency when the input voltage amplitude is 90V. The loads in this waveform are the same. Figure 1 The CRM mode is theoretically analyzed in the middle mark (the inductor voltage demagnetization time is not considered for the time being). The switching frequency fsw of the main power switch Q in the Boost PFC circuit is expressed as follows (1):

[0035]

[0036] Where Vin(t) is the real-time input voltage, Vin_rms is the amplitude of the input voltage Vin, Vout is the output voltage, Pin_avg is the designed average power, and L is the inductance value. From the above formula (1), it can be seen that the switching frequency fsw is related to the designed power Pin, the output voltage Vout, the inductance L, the Vin at different times, and the input voltage amplitude Vin_rms. When the load power, output voltage, inductance and other parameters are determined, the switching frequency will change with the change of the input voltage Vin.

[0037] from Figure 3 It can be seen that under the same load, as the amplitude of the input voltage increases, the ratio of the switching frequency at the Vin trough (the two ends of the figure) to the switching frequency at the peak (the middle of the figure) increases; at the same time, under the same load, the maximum switching frequency will increase as the input voltage amplitude increases. For example, at time 0, when the input voltage amplitude is 265V, the switching frequency is the highest, and when the input voltage amplitude is 90V, the switching frequency is the lowest.

[0038] Figure 4 The frequency limit waveform is shown. With the high-frequency design of the switching power supply, if the frequency limit is not increased, the switching frequency will be very large closer to the valley of the input voltage, which will greatly increase the switching loss. Therefore, the system needs to limit the frequency according to the load size, and its maximum frequency Fs_limit decreases as the load Comp decreases. When the compensation feedback signal Comp indicating the load is less than the first threshold Comp1, the maximum frequency is limited to a smaller value fslmin, and when the compensation feedback signal Comp is greater than the second threshold Comp2, the maximum frequency is limited to a higher value fslmax. Due to the limitation of the maximum frequency, the PFC circuit may operate in DCM mode at the valley position.

[0039] Figure 5 and Figure 6 shows the working mode under different loads. Figure 5 , its load is high, the compensation feedback signal Comp is higher than the second threshold Comp2, and it can be seen that it works less in DCM mode at the valley position. Figure 6 In the example, the load is low, such as the compensation feedback signal Comp is less than Comp2, and it can be seen that at the valley position, the system operates in a deeper DCM mode. However, a deeper DCM mode will result in poor THD performance.

[0040] Figure 7The waveform of the DCM working mode is shown. The signal Vds is the voltage difference between the two ends of the main power switch tube. In a preferred embodiment, the main power switch tube is a metal oxide semiconductor field effect tube (MOSFET), and its voltage difference Vds is its drain-source voltage. IL is the inductor current flowing through the inductor L. Vout is the output voltage of the PFC circuit, Vin is the input voltage of the PFC circuit, and Td is the oscillation period of the inductor L and the parasitic capacitance Cd of the MOSFET and the rectifier tube. According to the law of conservation of energy, the calculation formula for the negative current value during the DCM oscillation period is as follows:

[0041]

[0042] According to the above formula (2), after the system design parameters and device selection (inductor L, output voltage Vout, parasitic capacitance sum Cd and other parameters are determined), the negative current value IL_avg will increase as the input voltage Vin decreases. Therefore, when Vin is at the valley, the negative current value of the inductor is large, and when it is at the peak, the negative current value of the inductor is small. The formula for calculating the average inductor current is:

[0043]

[0044] From formula (3), we can see that the on-time ton and the freewheeling time tdem are the changes related to the input voltage Vin, and the time tdead from demagnetization to on-time is related to the oscillation period / frequency, which makes the average value ILavg of the inductor current unable to follow Vin and change sinusoidally, causing distortion, and eventually causing THD to deteriorate. Therefore, when the degree of operation in the DCM mode is greater, the number of times the inductor negative current is generated is more, and the inconsistent changes in the parameters ton, tdem, and tdead cause the greater the degree of distortion of the average value of the inductor current, which is equivalent to the greater the degree of input current distortion and the worse the THD effect.

[0045] When the input voltage amplitude increases, the compensation feedback signal Comp value generally decreases with the increase of the input voltage amplitude, and the maximum frequency also decreases, making the DCM deeper and the THD effect worse. By reducing the maximum on-time of the main power switch tube, the Comp value can be equivalently increased, making the system current working mode more in the CRM mode, reducing the working degree of the DCM mode, reducing the input current distortion and optimizing the THD performance.

[0046] Figure 8The schematic diagram of a PFC circuit system 200 according to an embodiment of the present invention is shown. The PFC circuit 200 includes a rectifier circuit 81 and a boost switch circuit 82, wherein the boost switch circuit 82 includes an inductor Lm, a main power switch tube Q1 and a rectifier tube D1, wherein the input end of the rectifier circuit 21 receives an AC power source ACIN, an output end of the rectifier circuit 81 is coupled to the first end of the inductor Lm, the second end of the inductor Lm is coupled to the first end of the main power switch tube Q1 and the first end of the rectifier tube D1, and the second end of the rectifier tube D1 is coupled to the output end of the boost switch circuit 82 for providing an output voltage Vout for a load Road. The PFC circuit may also not include the rectifier circuit 81, but only include the boost switch circuit 82.

[0047] The control circuit 20 generates a switch control signal GATE for controlling the on and off of the main power switch tube Q1, and for implementing PFC control, so that the average current waveform at the input end of the PFC circuit 200 follows or approximately follows the AC input voltage ACIN, or the input current waveform at the first end of the inductor Lm follows or approximately follows the input voltage Vin. The control circuit 20 controls the maximum on time Tonmax of the main power switch tube Q1 based on the amplitude of the AC power source ACIN or the input voltage Vin, and the maximum on time is the upper limit of the time that the main power switch tube Q1 is allowed to be turned on in one switching cycle. The control circuit 20 includes an input voltage amplitude judgment circuit 21, a maximum on time control circuit 22, and a drive control circuit 23. The input voltage amplitude judgment circuit 21 obtains an input voltage amplitude judgment signal PD for judging the amplitude of the input voltage ACIN at the input end of the PFC circuit 200. In one embodiment, the amplitude of the input voltage ACIN is realized by detecting the average voltage value of the voltage Vin at the input end of the boost switch circuit 82. In another embodiment, the amplitude of the input voltage ACIN is obtained by detecting the voltage Vsw at the first end of the main power switch tube Q1 and low-pass filtering the voltage Vsw. In another embodiment, the amplitude of the input voltage ACIN is obtained by detecting the voltage Vsw at the first end of the main power switch tube Q1 and sampling the peak voltage within half or one power frequency cycle of the low-pass filtered signal of the voltage Vsw. Then the obtained input voltage amplitude is compared and its amplitude level is judged, and the input voltage amplitude judgment signal PD is output. In another embodiment, the input voltage amplitude judgment circuit 21 does not detect Vin or Vsw, but after manually judging the input voltage amplitude level, sets external parameters such as voltage, resistance or capacitance at the corresponding port, and judges the input voltage amplitude by detecting the parameters. In one embodiment, when the input voltage ACIN amplitude is 220V, the input voltage amplitude judgment signal PD output by the input voltage amplitude judgment circuit 21 is a signal "1", and when the input voltage ACIN amplitude is 110V, the input voltage amplitude judgment signal PD output by the input voltage amplitude judgment circuit 21 is a signal "0".

[0048] The maximum on-time control circuit 22 controls the maximum on-time Tonmax of the main power switch tube Q1 based on the input voltage amplitude judgment signal PD, so that the on-time of the main power switch tube Q1 does not exceed the maximum on-time Tonmax. When the input voltage amplitude is large, the switching frequency DCM at the input voltage Vin trough is the deepest, and the maximum on-time Tonmax needs to be reduced. In the first way, the maximum on-time Tonmax can be continuously reduced with the input voltage amplitude. In the second way, the input voltage amplitude can be divided into N gears, and the maximum on-time Tonmax is also set to N gears, where N is a natural number greater than or equal to 2, and the larger the input voltage amplitude, the smaller the maximum on-time. Both of the above types of methods for adjusting the maximum on-time can satisfy that when the input voltage amplitude is the first voltage, the maximum on-time of the main power switch tube is the first time, and when the input voltage amplitude is the second voltage, the maximum on-time is the second time, wherein the first voltage is greater than the second voltage, and the first time is less than the second time.

[0049] The drive control circuit 23 controls the main power switch Q1 to be turned on and off based on the maximum on time Tonmax.

[0050] Fig. 9A schematic diagram of a control circuit 300 according to an embodiment of the present invention is shown. The control circuit 300 includes an input voltage amplitude judgment circuit 301, a maximum on-time control circuit 302, a conduction control circuit 31, a shutdown control circuit 32, a trigger circuit 33 and a drive circuit 34. The input voltage amplitude judgment circuit 301 is used to judge the input voltage amplitude, generate an input voltage amplitude judgment signal PD, and further control the maximum on-time of the main power switch tube based on the input voltage amplitude judgment signal PD. The input voltage amplitude judgment circuit 301 is coupled to the shutdown control circuit 32 to achieve control of the maximum on-time of the main power switch tube. In the illustrated embodiment, the input voltage amplitude judgment circuit 301 includes: an input voltage detection circuit 311, an amplitude detection circuit 312 and at least one input voltage amplitude comparison circuit 313. The input voltage detection circuit 311 is used to obtain an input voltage detection signal Vins representing the input voltage Vin. In one embodiment, the input voltage detection circuit 311 is coupled to the first end of the inductor Lm to detect the input voltage Vin, and the input voltage detection circuit 311 may include a voltage divider detection circuit composed of two voltage divider resistors. In another embodiment, the input voltage detection circuit 311 is coupled to the first end of the main power switch tube Q1 to detect the voltage signal Vsw, and the input voltage detection circuit 311 includes a low-pass filter circuit. The input voltage detection circuit 311 uses the low-pass filter signal of the voltage signal Vsw as the input voltage detection signal Vins, thereby obtaining the input voltage detection signal Vins representing the input voltage Vin. The amplitude detection circuit 312 is coupled to the output end of the input voltage detection circuit 311, and generates an input voltage amplitude detection signal Vinpk representing the input voltage amplitude based on the input voltage detection signal Vins. The amplitude comparison circuit 313 is used to compare the input voltage amplitude detection signal Vinpk with the threshold signal Vth, and generate the input voltage amplitude judgment signal PD according to the comparison result. In one embodiment, when the input voltage amplitude detection signal Vinpk is greater than the threshold signal Vth, the judgment signal PD is at a high level, which is used to control the maximum on-time Tonmax to have a smaller first time value; when the input voltage amplitude detection signal Vinpk is less than the threshold signal Vth, the judgment signal PD is at a low level, which is used to control the maximum on-time Tonmax to have a larger second time value, that is, the maximum on-time control circuit selects one of the two times as the corresponding maximum on-time according to the input voltage amplitude judgment signal. In another embodiment, the amplitude comparison circuit 313 includes multiple comparison circuits, compares the input voltage amplitude detection signal Vinpk with multiple thresholds, and outputs an input voltage amplitude judgment signal PD representing multiple input voltage amplitudes according to the comparison results. The input voltage amplitude judgment signal PD representing multiple input voltage amplitudes can be a multi-channel logic signal, or a voltage signal with multiple reference voltage values, or a current signal with multiple reference current values, etc.The maximum on-time control circuit selects one of multiple time values ​​as the maximum on-time according to the gear indicated by the input voltage amplitude judgment signal PD, where the number of selectable time values ​​is the number of amplitude comparison circuits plus 1. The larger the input voltage amplitude Vinpk, the smaller the corresponding gear, and the smaller the maximum on-time Tonmax generated by the control.

[0051] In one embodiment, when the AC input voltage is 220V, the maximum on-time of the main power switch is 18μs; when the AC input voltage is 110V, the maximum on-time of the main power switch is controlled to 35μs.

[0052] In another embodiment, the input voltage amplitude judgment circuit includes an input voltage detection circuit and an amplitude detection circuit, but does not include an amplitude comparison circuit. The input voltage amplitude judgment signal PD provided by the input voltage amplitude judgment circuit is the input voltage amplitude detection signal Vinpk that characterizes the input voltage amplitude. The maximum on-time control circuit continuously adjusts the maximum on-time Tonmax according to the input voltage amplitude detection signal Vinpk.

[0053] Whether it is an embodiment of multi-speed control of Tonmax or an embodiment of continuous adjustment of Tonmax, there is such a situation: when the input voltage amplitude is the first voltage, the maximum on-time is the first time, and when the input voltage amplitude is the second voltage, the maximum on-time is the second time, wherein the first voltage is greater than the second voltage, and the first time is less than the second time.

[0054] The conduction control circuit 31 is used to trigger the trigger circuit 33 to set, and is used to conduct the main power switch tube. In one embodiment, the conduction control circuit 31 controls the conduction time of the main power switch tube based on the demagnetization detection signal and the maximum frequency control signal Fs_limit. This is common knowledge in the art and will not be described in detail here. The shutdown control circuit 32 is used to trigger the reset of the trigger circuit 33 to control the shutdown time of the main power switch tube. The maximum conduction time control circuit 302 controls the shutdown control circuit 32 based on the input voltage amplitude judgment signal PD to adjust the maximum conduction time of the main power switch tube. The trigger circuit 33 outputs the switch control signal PWM, and the drive circuit 34 amplifies and converts the switch control signal PWM and outputs the GATE signal. The output end of the drive circuit 34 is coupled to the control end of the main power switch tube Q1. In the illustrated embodiment, the shutdown control circuit 32 includes a detection circuit 321, an error amplifier circuit 322, a compensation circuit 323, a sawtooth wave signal generation circuit 324 and a shutdown comparison circuit 325. The detection circuit 321 generates an output voltage feedback signal Vfb representing the output voltage Vout of the PFC circuit based on the output voltage Vout of the PFC circuit. The error amplifier circuit 322 amplifies the error between the feedback signal Vfb and the voltage reference signal Vref. The input end of the compensation circuit 323 is coupled to the output end of the error amplifier circuit 322. After compensation by the compensation network of the compensation circuit 323, a compensation feedback signal Comp representing the load size is generated. The shutdown comparison circuit 325 receives the sawtooth wave signal Ramp and the compensation feedback signal Comp, compares the compensation feedback signal Comp with the sawtooth wave signal Ramp, and generates a shutdown control signal GD for controlling the shutdown moment of the main power switch tube.

[0055] Fig. 9 The on-control circuit 31 , the off-control circuit 32 , the trigger circuit 33 and the drive circuit 34 shown may constitute a drive control circuit.

[0056] Fig.10 The waveform diagram of changing the maximum on-time according to an embodiment of the present invention is shown. It can be seen from the figure that when the maximum value Compmax of the compensation feedback signal Comp is fixed, changing the slope of the sawtooth signal Ramp can change the maximum on-time Tonmax. The larger the slope, the smaller Tonmax. The slope of the sawtooth signal Ramp2 is larger than that of the sawtooth signal Ramp1. Tonmax2 <Tonmax1。

[0057] continue Fig. 9In one embodiment, the sawtooth signal generating circuit 324 includes a maximum on-time control circuit. In one embodiment, the sawtooth signal generating circuit 324 changes the slope of the sawtooth signal according to the input voltage amplitude judgment signal PD to adjust the maximum on-time. When the Tonmax corresponding to the input voltage amplitude judgment signal PD is smaller, the slope of the sawtooth signal is larger. That is, there are such a first voltage and a second voltage, when the input voltage amplitude is the first voltage, the slope of the sawtooth signal is the first slope, and when the input voltage amplitude is the second voltage, the slope of the sawtooth signal is the second slope, wherein the first slope is greater than the second slope.

[0058] Fig.11 The sawtooth signal generating circuit 400 according to an embodiment of the present invention is shown. The input end of the sawtooth signal generating circuit 400 is coupled to the maximum on-time control circuit 41. Under the control of the maximum on-time control circuit 41, the output end of the sawtooth signal generating circuit 400 provides a sawtooth signal Ramp. The sawtooth signal generating circuit 400 includes a current source Iramp, a first switch K1 and a capacitor Cramp. The maximum on-time control circuit 41 adjusts the current value of the current source Iramp based on the input voltage amplitude judgment signal PD. The control end of the first switch K1 is coupled to the switch control signal PWM, the first end of the first switch K1 is coupled to the current source Iramp, and the second end of the first switch K1 is grounded. The capacitor Cramp is coupled between the first end and the second end of the first switch K1, and the first end of the first switch K1 provides the sawtooth signal Ramp. When PWM is at a high level, the main power switch tube Q1 is turned on, and when the first switch K1 is turned off, the current source Iramp charges the capacitor Cramp, and the sawtooth wave signal Ramp starts to rise. When the sawtooth wave signal Ramp rises to the compensation feedback signal Comp, the shutdown comparison circuit outputs a valid shutdown control signal GD, which is used to convert the PWM signal to a low level, and is used to turn off the main power switch tube Q1. At this time, the switch K1 is turned on, and the sawtooth wave signal drops to zero. The maximum on-time control circuit 41 controls the input voltage amplitude judgment signal PD. When the input voltage amplitude Vinpk is a first voltage, the current source Iramp has a first current value, and when the input voltage amplitude Vinpk is a second voltage, the current source Iramp has a second current value, wherein the first voltage is greater than the second voltage, and the first current value is greater than the second current value.

[0059] like Fig.11 As shown, the switch on time Ton is determined by comparing the Ramp signal with the Comp signal. Therefore, the maximum on time Tonmax is determined by the upper limit value Compmax of the Comp signal, Iramp and Cramp, and Tonmax can be affected by changing one or more variables. Fig.11The illustrated embodiment adjusts Tonmax by changing Iramp. In another embodiment, the maximum conduction time control circuit can also adjust the maximum conduction time Tonmax by adjusting the capacitance value of the capacitor Cramp based on the input voltage amplitude determination signal PD.

[0060] Fig.12 A waveform schematic diagram of changing the maximum conduction time according to another embodiment of the present invention is shown. As can be seen from the figure, when the slope of the sawtooth wave signal is fixed, the maximum conduction time Tonmax can be increased by increasing the upper limit value Compmax of the Comp signal, and Tonmax can be reduced by reducing Compmax. As shown in the figure, the upper limit value Compmax1 of the compensation feedback signal < Compmax2, and the corresponding maximum conduction time Tonmax1 < Tonmax2. Continue Fig. 9 The description. In one embodiment, the maximum conduction time control circuit controls parameters such as the maximum value Compmax of the compensation feedback signal Comp in the compensation circuit 322 and the gain of the error amplification circuit 322 based on the input voltage amplitude determination signal PD to adjust Tonmax. When the input voltage amplitude is relatively large, such as greater than the first threshold voltage, the upper limit value of the compensation feedback signal is set to the first value Compmax1. When the input voltage amplitude is relatively small, such as less than the second voltage threshold, the upper limit value of the compensation feedback signal is set to the second value Compmax2, where the first threshold voltage is greater than or equal to the second threshold voltage, and the first value is less than the second value. In this way, Tonmax1 when the input voltage amplitude is large is less than Tonmax2 when the input voltage amplitude is small.

[0061] Fig.13 A comparison diagram of the THD improvement effect according to an embodiment of the present invention is shown. In a 100W prototype, the THD performance when the maximum conduction time Tonmax is 10 μs is significantly better than the THD performance when the maximum conduction time Tonmax is 18 μs.

[0062] As can be seen from the above embodiments, the present invention provides a method for optimizing THD in a PFC circuit, which controls the maximum conduction time of the main power switch tube based on the input voltage amplitude at the input end of the PFC circuit. When the input voltage amplitude is relatively high, the maximum conduction time is set relatively low to reduce the depth of the DCM mode and improve the THD performance. So that when the input voltage amplitude is the first voltage, the maximum conduction time is the first time, and when the input voltage amplitude is the second voltage, the maximum conduction time is the second time, where the first voltage is greater than the second voltage, and the first time is less than the second time.

[0063] In one embodiment, the method for adjusting the maximum on-time includes performing an error compensation operation on an output voltage feedback signal representing the output voltage of the PFC circuit and a voltage reference signal to generate a compensation feedback signal; and comparing a sawtooth wave signal with the compensation feedback signal to generate a shutdown control signal for shutting down a main power switch tube; when the input voltage amplitude is greater than a first threshold voltage, controlling the slope of the sawtooth wave signal to be a first slope, and when the input voltage amplitude is less than a second voltage threshold, controlling the slope of the sawtooth wave signal to be a second slope, wherein the first threshold voltage is greater than or equal to the second threshold voltage, and the first slope is greater than the second slope.

[0064] In another embodiment, the method for adjusting the maximum on-time includes performing an error compensation operation on an output voltage feedback signal representing the output voltage of the PFC circuit and a voltage reference signal to generate a compensation feedback signal; and comparing the sawtooth wave signal with the compensation feedback signal to generate a shutdown control signal for shutting down the main power switch tube; when the input voltage amplitude is greater than a first threshold voltage, setting the upper limit value of the compensation feedback signal to a first value, and when the input voltage amplitude is less than a second voltage threshold, setting the upper limit value of the compensation feedback signal to a second value, wherein the first threshold voltage is greater than or equal to the second threshold voltage, and the first value is less than the second value.

[0065] Those skilled in the art should know that the logic controls such as "high level" and "low level", "set" and "reset", "AND gate" and "OR gate", "non-inverting input terminal" and "inverting input terminal" in the logic controls involved in the specification or drawings can be interchanged or changed with each other, and the same function or purpose as the above embodiment can be achieved by adjusting the subsequent logic controls.

[0066] The description and application of the present invention here are illustrative, and it is not intended to limit the scope of the present invention to the above-mentioned embodiments. The effects or advantages involved in the specification may not be reflected in the actual experimental examples due to the uncertainty of specific condition parameters or other factors, and the effects or advantages are not used to limit the scope of the invention. The deformation and change of the embodiments disclosed here are possible, and the replacement of the embodiments and the various equivalent parts are well known to those of ordinary skill in the art. It should be clear to those skilled in the art that the present invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials and parts without departing from the spirit or essential features of the present invention. Other deformations and changes can be made to the embodiments disclosed here without departing from the scope and spirit of the present invention.

Claims

1. A control circuit for a power factor correction (PFC) circuit, the PFC circuit comprising a main power switch tube, the control circuit generating a switch control signal for controlling the on and off of the main power switch tube, the control circuit comprising: An input voltage amplitude judgment circuit is used to obtain an input voltage amplitude judgment signal for judging the amplitude of the input voltage at the input end of the PFC circuit; as well as A maximum on-time control circuit controls the maximum on-time of a main power switch tube based on an input voltage amplitude judgment signal, wherein the on-time of the main power switch tube does not exceed the maximum on-time, when the input voltage amplitude is a first voltage, the maximum on-time is a first time, and when the input voltage amplitude is a second voltage, the maximum on-time is a second time, wherein the first voltage is greater than the second voltage, and the first time is less than the second time.

2. The control circuit as claimed in claim 1, wherein the input voltage amplitude judgment circuit comprises: An input voltage detection circuit, used for obtaining an input voltage detection signal representing an input voltage; An amplitude detection circuit is coupled to the input voltage detection circuit, and generates an input voltage amplitude detection signal representing the input voltage amplitude based on the input voltage detection signal; as well as At least one input voltage amplitude comparison circuit, used for comparing the input voltage amplitude detection signal with the threshold signal, and generating an input voltage amplitude determination signal according to the comparison result; The maximum on-time control circuit selects one of at least two times as the maximum on-time according to the input voltage amplitude judgment signal.

3. The control circuit as claimed in claim 1, wherein the PFC circuit includes a rectifier circuit and a boost switch circuit, the boost switch circuit includes an inductor, a main power switch tube and a rectifier tube, wherein an input end of the rectifier circuit receives an AC power supply, an output end of the rectifier circuit is coupled to a first end of the inductor, a second end of the inductor is coupled to a first end of the main power switch tube and a first end of the rectifier tube, a second end of the rectifier tube is coupled to an output end of the boost switch circuit, and the control circuit controls the maximum conduction time based on the amplitude of the AC power supply.

4. The control circuit as claimed in claim 3, wherein the input voltage amplitude judgment circuit comprises: An input voltage detection circuit is coupled to the first end of the main power switch tube to obtain an input voltage detection signal representing the input voltage; as well as An amplitude detection circuit is coupled to the input voltage detection circuit, and generates an input voltage amplitude detection signal representing the input voltage amplitude based on the input voltage detection signal; The input voltage amplitude determination circuit generates an input voltage amplitude determination signal based on the input voltage amplitude detection signal.

5. The control circuit of claim 1, further comprising: An error amplifier circuit, wherein the error amplifier circuit performs error amplification on an output voltage feedback signal representing an output voltage of the PFC circuit and a voltage reference signal; A compensation circuit, whose input terminal is coupled to the output terminal of the error amplifier circuit for generating a compensation feedback signal; as well as A shutdown comparison circuit receives a sawtooth wave signal and a compensation feedback signal, and is used to compare the sawtooth wave signal and the compensation feedback signal, and generate a shutdown control signal for shutting down the main power switch tube; When the input voltage amplitude is a first voltage, the slope of the sawtooth wave signal is a first slope, and when the input voltage amplitude is a second voltage, the slope of the sawtooth wave signal is a second slope, wherein the first slope is greater than the second slope.

6. The control circuit as claimed in claim 5, further comprising a sawtooth wave signal generating circuit, the sawtooth wave signal generating circuit comprising: Current source; A first switch, a control end of which is coupled to a switch control signal, a first end of which is coupled to a current source, and a second end of which is grounded; A capacitor coupled between a first terminal and a second terminal of the first switch, wherein the first terminal of the first switch provides a sawtooth wave signal; When the input voltage amplitude is a first voltage, the current source has a first current value, and when the input voltage amplitude is a second voltage, the current source has a second current value, wherein the first current value is greater than the second current value.

7. The control circuit of claim 1, further comprising: An error amplifier circuit, wherein the error amplifier circuit performs error amplification on an output voltage feedback signal representing an output voltage of the PFC circuit and a voltage reference signal; A compensation circuit, whose input terminal is coupled to the output terminal of the error amplifier circuit for generating a compensation feedback signal, wherein the compensation feedback signal has an upper limit value of the compensation feedback signal; as well as A shutdown comparison circuit receives a sawtooth wave signal and a compensation feedback signal, and is used to compare the sawtooth wave signal and the compensation feedback signal, and generate a shutdown control signal for shutting down the main power switch tube; The maximum on-time control circuit adjusts the maximum on-time by adjusting the upper limit value of the compensation feedback signal based on the input voltage amplitude judgment signal. When the maximum on-time is larger, the corresponding upper limit value of the compensation feedback signal is larger.

8. A method for optimizing total harmonic distortion (THD) in a PFC circuit, wherein the PFC circuit includes a main power switch tube, the method comprising: The maximum on-time of the main power switch tube is controlled based on the input voltage amplitude at the input end of the PFC circuit, wherein the on-time of the main power switch tube does not exceed the maximum on-time, so that when the input voltage amplitude is a first voltage, the maximum on-time is a first time, and when the input voltage amplitude is a second voltage, the maximum on-time is a second time, wherein the first voltage is greater than the second voltage, and the first time is less than the second time.

9. The method of claim 8, comprising: An output voltage feedback signal representing the output voltage of the PFC circuit is subjected to an error compensation operation with a voltage reference signal to generate a compensation feedback signal; as well as Compare the sawtooth wave signal with the compensation feedback signal to generate a shutdown control signal for shutting down the main power switch tube; When the input voltage amplitude is greater than the first threshold voltage, the slope of the sawtooth wave signal is controlled to be the first slope, and when the input voltage amplitude is less than the second voltage threshold, the slope of the sawtooth wave signal is controlled to be the second slope, wherein the first threshold voltage is greater than or equal to the second threshold voltage, and the first slope is greater than the second slope.

10. The method of claim 8, comprising: An output voltage feedback signal representing the output voltage of the PFC circuit is subjected to an error compensation operation with a voltage reference signal to generate a compensation feedback signal; as well as Compare the sawtooth wave signal with the compensation feedback signal to generate a shutdown control signal for shutting down the main power switch tube; When the input voltage amplitude is greater than the first threshold voltage, the upper limit value of the compensation feedback signal is set to the first value, and when the input voltage amplitude is less than the second voltage threshold, the upper limit value of the compensation feedback signal is set to the second value, wherein the first threshold voltage is greater than or equal to the second threshold voltage, and the first value is less than the second value.

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