Power management integrated circuit and method of operating power management integrated circuit

Abstract

A power management integrated circuit and a method of operating a power management integrated circuit are disclosed. The power management integrated circuit includes: an upper regulator circuit receiving a system voltage as an input and outputting a first output voltage; a lower regulator circuit having a first output voltage as an input; and a Kelvin switching circuit connected between the upper regulator circuit and the lower regulator circuit. The Kelvin switching circuit includes a plurality of switches that connect any one of a plurality of upper regulators included in the upper regulator circuit to any one of a plurality of lower regulators included in the lower regulator circuit.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0075070 filed in the Korean Intellectual Property Office on June 12, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The inventive concept relates to a power management integrated circuit and a method of operating the power management integrated circuit. More particularly, the inventive concept relates to a power management integrated circuit having a sub-regulation structure. Background Art

[0003] Recently, due to the increasing demand for efficient power management of mobile devices such as smart phones and tablet personal computers (PCs), power management integrated circuits (PMICs) have become an important issue. For example, minimizing power consumption of mobile devices and improving the efficiency of mobile devices have become key issues for PMICs. Switching regulators such as pulse width modulation (PWM) direct current to direct current (DC-DC) converters that can provide power with high driving voltage and high power efficiency are used in PMICs.

[0004] For example, a PMIC having a sub-regulator structure capable of improving efficiency by combining a switching regulator and a linear regulator may be used. Recently, as the capacity of a linear regulator increases, there is a concern that performance degradation may occur due to a voltage drop caused by power wiring. Summary of the invention

[0005] The inventive concept provides a power management integrated circuit capable of ensuring a high voltage drop.

[0006] An embodiment of the inventive concept provides a power management integrated circuit, the power management integrated circuit comprising: an upper regulator circuit receiving a system voltage as an input and outputting a first output voltage; a lower regulator circuit having the first output voltage as an input; and a Kelvin switch circuit connected between the upper regulator circuit and the lower regulator circuit. The Kelvin switch circuit comprises a plurality of switches, the plurality of switches connecting any one of a plurality of upper regulators included in the upper regulator circuit to any one of a plurality of lower regulators included in the lower regulator circuit.

[0007] An embodiment of the inventive concept also provides a power management integrated circuit, which includes: a first switching regulator and a second switching regulator, both of which receive a system voltage as an input; a first low dropout output (LDO) regulator and a second LDO regulator, the first LDO regulator and the second LDO regulator being connected to an output terminal of the first switching regulator or an output terminal of the second switching regulator, respectively; a first Kelvin sensing circuit connected between a feedback voltage terminal of the first switching regulator and a feedback voltage terminal of the second switching regulator and a power supply node of the first LDO regulator; and a second Kelvin sensing circuit connected between the feedback voltage terminal of the first switching regulator and the feedback voltage terminal of the second switching regulator and a power supply node of the second LDO regulator.

[0008] An embodiment of the inventive concept still further provides a method for operating a power management integrated circuit, the method comprising: applying a system voltage to an upper regulator circuit; generating a primary output voltage through the upper regulator circuit; and feedback sensing the primary output voltage by controlling a Kelvin switch circuit connected between the upper regulator circuit and a lower regulator circuit to which the primary output voltage is applied. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating an electronic device including a power management integrated circuit according to some example embodiments;

[0011] Figure 2 is a block diagram illustrating a power management integrated circuit according to some example embodiments;

[0012] Figure 3 is a block diagram illustrating a power management integrated circuit according to some example embodiments;

[0013] Figure 4 is a block diagram illustrating a power management integrated circuit according to some example embodiments;

[0014] Figure 5 is a block diagram illustrating a power management integrated circuit according to some example embodiments;

[0015] Figure 6 is a block diagram illustrating a power management integrated circuit according to some example embodiments;

[0016] Figure 7 is a circuit diagram illustrating a power management integrated circuit according to some example embodiments;

[0017] Figure 8is a circuit diagram illustrating a power management integrated circuit according to some example embodiments;

[0018] Fig. 9 is a circuit diagram illustrating a power management integrated circuit according to some example embodiments;

[0019] Fig.10 is a circuit diagram illustrating a power management integrated circuit according to some example embodiments;

[0020] Fig.11 is a circuit diagram illustrating a power management integrated circuit according to some example embodiments;

[0021] Fig.12 is a circuit diagram illustrating a power management integrated circuit according to some example embodiments; and

[0022] Fig.13 is a flow chart illustrating a method of operating a power management integrated circuit according to some example embodiments. DETAILED DESCRIPTION

[0023] Hereinafter, various embodiments of the inventive concept are described with reference to the accompanying drawings.

[0024] Figure 1 is a block diagram illustrating an electronic device 1000 including a power management integrated circuit (PMIC) 1100 according to some example embodiments.

[0025] Reference Figure 1, the electronic device 1000 includes a PMIC 1100 , an application processor (AP) 1200 , an input device 1300 , a display 1400 , a memory 1500 , and a battery 1600 . For example, the electronic device 1000 may be a device included in a vehicle, or the electronic device 1000 may be a smart phone, a personal computer (PC), a tablet PC, a netbook, an electronic reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, an ultra-mobile PC (UMPC), a workstation, a portable computer, a network tablet computer, a tablet computer, a wireless phone, a mobile phone, a smart phone, an electronic book, a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional TV, a smart TV, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, a storage device constituting a data center, one of various components of a device for sending and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, a radio frequency identification (RFID) device, or a computing system. In addition, the electronic device 1000 may be a wearable device (such as an electronic bracelet or an electronic neckband).

[0026] The PMIC 1100 may receive power from the battery 1600, supply power to the AP 1200, the input device 1300, the display 1400, or the memory 1500, and manage power of the AP 1200, the input device 1300, the display 1400, or the memory 1500. The electronic device 1000 may include at least one PMIC 1100. For example, the electronic device 1000 may supply power to the AP 1200, the input device 1300, the display 1400, or the memory 1500 using one PMIC 1100. For example, the electronic device 1000 may include a plurality of PMICs 1100 for independently supplying power to each of the AP 1200, the input device 1300, the display 1400, and the memory 1500.

[0027] The PMIC 1100 according to some example embodiments may ensure a voltage drop of a lower regulator included in a lower regulator circuit through an upper regulator circuit, a lower regulator circuit, and a Kelvin switch circuit connecting the upper regulator circuit to the lower regulator circuit. The PMIC 1100 according to some example embodiments may increase (and / or maximize) the efficiency of the lower regulator circuit through feedback control of the output voltage of the upper regulator circuit taking into account the current-resistance (IR) drop between the upper regulator circuit and the lower regulator circuit. The PMIC 1100 according to some example embodiments may be applied to all power integrated circuit (IC) products including a PMIC or a serial power wiring structure. The following reference is made to Figure 2 A more detailed example of the PMIC 1100 is described.

[0028] The AP 1200 may control the overall operation of the electronic device 1000. For example, the AP 1200 may display data stored in the memory 1500 through the display 1400 according to an input signal generated by the input device 1300. For example, the input device 1300 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

[0029] Figure 2 is a block diagram illustrating a PMIC 10 according to some example embodiments. Figure 2 The PMIC 10 can be Figure 1 An example of a PMIC 1100 and a PMIC generally described in the disclosure may be shown as Figure 1 Any of the various embodiments of the PMIC 1100.

[0030] The PMIC 10 can supply the required power to the electronic device 1000 (refer to Figure 1 ). The PMIC 10 may receive power from the outside, convert and rectify the power into a stable voltage or current, and may distribute and control the voltage and current. The PMIC 10 may be implemented as a single semiconductor chip or an assembly of a plurality of semiconductor chips.

[0031] Figure 2 The PMIC 10 may include an upper regulator circuit 11 , a lower regulator circuit 12 , a Kelvin switch circuit 13 , and a controller 14 .

[0032] According to some example embodiments, the upper regulator circuit 11 and the lower regulator circuit 12 may be direct current to direct current (DC-DC) converters. The upper regulator circuit 11 according to some example embodiments includes a buck converter that generates a power level less than the input power, a boost converter that generates a power level greater than the input power, and a buck-boost converter that generates a power level greater than or less than the input power. However, example embodiments are not limited thereto, and various types of DC conversion may be performed by the upper regulator circuit 11.

[0033] According to some example embodiments, the upper regulator circuit 11 and the lower regulator circuit 12 may convert a specific level of DC power into another level of DC power. In some example embodiments, the DC power input to the upper regulator circuit 11 may be supplied by a battery 1600 (see Figure 1 ) supply. In some example embodiments, it is assumed that the DC power is converted into DC power of different levels. However, in some example embodiments, it is understood that even when alternating current (AC) is supplied from the outside, DC power can be supplied to the upper regulator circuit 11 through appropriate AC-DC conversion (for example, using an AC-DC transformer).

[0034] Reference Figure 2 , the upper regulator circuit 11 may receive a system voltage Vsys as an input. The system voltage Vsys may represent a voltage initially applied to the PMIC 10. The upper regulator circuit 11 may include a plurality of upper regulators. According to some example embodiments, the upper regulator circuit 11 may include a plurality of switching regulators. The switching regulator included in the upper regulator circuit 11 may generate DC power by adjusting a switching period of a switching element. For example, the switching regulator may generate a pulse width modulation (PWM) signal using a ramp signal, and generate a desired output voltage by increasing or decreasing an input voltage based on the PWM signal.

[0035] The system voltage Vsys may be applied as an input voltage to each of the plurality of upper regulators included in the upper regulator circuit 11. The upper regulator circuit 11 may first adjust the system voltage Vsys. The upper regulator circuit 11 may output a first output voltage Va having a level lower than that of the system voltage Vsys as an input voltage.

[0036] The first output voltage Va may be connected to (eg, applied to) a power supply node of the lower regulator circuit 12. Figure 2, although the first output voltage Va is shown as being directly connected to the down regulator circuit 12, the first output voltage Va may be connected to a plurality of down regulators included in the down regulator circuit 12 through a power supply node. For example, the down regulator circuit 12 may have the first output voltage Va as an input. According to some example embodiments, the down regulator circuit 12 may include a plurality of down regulators. According to some example embodiments, the down regulator may be a low dropout output (LDO) regulator. The LDO regulator may calculate the voltage difference applied to the power switch included in the LDO regulator as efficiency. The efficiency of the LDO regulator is determined by the difference between the input voltage and the output voltage, and therefore, the voltage difference should be small to achieve high efficiency. In some example embodiments, the second output voltage Vb output from the down regulator circuit 12 may be provided to other components connected to the PMIC 10. According to some example embodiments, the second output voltage Vb output from the down regulator circuit 12 may have a level less than that of the first output voltage Va.

[0037] In the description of example embodiments, a switching regulator may refer to an upper regulator included in an upper regulator circuit, and a linear regulator or an LDO regulator may refer to a lower regulator included in a lower regulator circuit.

[0038] The Kelvin switch circuit 13 may include a plurality of switches. According to some example embodiments, the Kelvin switch circuit 13 may include a Kelvin sensing circuit corresponding to the number of lower regulators included in the lower regulator circuit 12. According to some example embodiments, the number of switches included in each Kelvin sensing circuit may correspond to the number of upper regulators included in the upper regulator circuit 11. The Kelvin switch circuit 13 may include a plurality of switches configured to connect any one of the plurality of upper regulators included in the upper regulator circuit 11 to any one of the plurality of lower regulators included in the lower regulator circuit 12.

[0039] According to some example embodiments, when the upper regulator circuit 11 includes two upper regulators and the lower regulator circuit 12 includes four lower regulators, the Kelvin switch circuit 13 may include four Kelvin sensing circuits, and each Kelvin sensing circuit may include two switches. Each of the plurality of Kelvin sensing circuits included in the Kelvin switch circuit 13 may be respectively connected to each of the lower regulators included in the lower regulator circuit 12, and each of the plurality of switches included in the Kelvin sensing circuit may be connected to each of the plurality of upper regulators included in the upper regulator circuit 11. For example, the four Kelvin sensing circuits may be connected to corresponding different regulators of the four lower regulators, and the two switches in the Kelvin sensing circuit may be connected to different corresponding regulators of the two upper regulators.

[0040] In some example embodiments, in the process of detecting the voltage at a specific point, when the voltage at a point connected to the specific point is measured without measuring the specific point, an IR drop may occur through the current. Kelvin sensing may mean accurately measuring the voltage at the corresponding point without an IR drop by additionally placing a sensing line. In an example embodiment, the Kelvin switch circuit 13 may mean a circuit including a switch for applying Kelvin sensing as described above. In some example embodiments, the Kelvin switch circuit 13 may mean a switch circuit provided between the lower regulator circuit 12 and the upper regulator circuit 11 to assist in voltage sensing in order to apply Kelvin sensing. Depending on which switch is selected among the multiple switches included in the Kelvin switch circuit 13, the output voltage of any one of the multiple upper regulators included in the upper regulator circuit 11 may be feedback-sense. By the control of the switch included in the Kelvin switch circuit 13, the feedback voltage Vf applied to the first output voltage Va of the lower regulator circuit 12 may be sensed, and by reflecting the sensing result, the voltage applied to the lower regulator circuit 12 may be improved or optimized. According to some example embodiments, a voltage terminal to which the feedback voltage Vf is applied may be referred to as a feedback voltage terminal. In the PMIC 10 according to some example embodiments, the influence of parasitic resistance may be reduced by feedback sensing using the Kelvin switch circuit 13 .

[0041] The PMIC 10 according to some example embodiments may include a reconfigurable Kelvin switch circuit 13 and a controller 14 capable of controlling the Kelvin switch circuit 13. In some example embodiments, reconfigurable may mean that a desired voltage may be output according to the specification of a power rail of an electronic device connected to the PMIC without changing the hardware. For example, it may mean that an upper regulator included in a different upper regulator circuit 11 and a lower regulator included in a lower regulator circuit 12 may be connected only by controlling a switch included in the Kelvin switch circuit 13. Figure 2 , a feedback voltage Vf for controlling the first output voltage Va of the upper regulator circuit 11 may be connected from the Kelvin switch circuit 13 to the upper regulator circuit 11 .

[0042] The controller 14 may control signals applied to a plurality of switches included in the Kelvin switch circuit 13. Figure 2, although the controller 14 is shown as being included inside the PMIC 10, the controller 14 may also be provided outside the PMIC 10. According to some example embodiments, the controller 14 may control “some of the plurality of switches included in the Kelvin switch circuit 13” to be closed and control other switches to be opened. According to example embodiments, the controller 14 may control the connection structure between the upper regulator circuit 11 and the lower regulator circuit 12 according to the power required by other components to which the PMIC 10 is connected. According to some example embodiments, the controller 14 may control “a switch determined by information stored in a one-time programmable (OTP) memory device (not shown)” to be closed. According to some example embodiments, the PMIC 10 may be connected to various components to apply power to the various components, and the configuration of the upper regulator circuit 11 and the lower regulator circuit 12 applied to each component may be different. According to some example embodiments, power supply information corresponding to each component and the connection structure of the regulator circuit may be included in the OTP memory device. The code information included in the OTP memory device may include information about the configuration of the upper regulator circuit 11 and the lower regulator circuit 12, and by applying the information, a connection structure suitable for each component may be controlled. The controller 14 may control signals applied to the plurality of switches in response to power supply information corresponding to the components connected to the PMIC 10. According to some example embodiments, the power supply information may be power value information of the electronic device connected to the PMIC 10. According to some example embodiments, the power supply information may be information related to a power range that changes according to the arrangement of power rails included in the electronic device.

[0043] When the power rail of the electronic device to which the PMIC 10 is connected is determined, the controller 14 can fix the power information corresponding to the power rail by using the information included in the OTP memory device, and can perform switch control for connecting the upper regulator circuit 11 and the lower regulator circuit 12 by setting the connection structure of the upper regulator circuit 11 and the lower regulator circuit 12 corresponding to the power information.

[0044] It is understood that the controller 14 may be implemented as a central processing unit (CPU), an arithmetic logic unit (ALU) that performs arithmetic and logical operations, bit shifting, etc., a digital signal processor (DSP), a microprocessor, an application specific integrated circuit (ASIC), control logic, etc., but the controller 14 is not limited thereto. In some example embodiments, the controller 14 may include a state machine composed of a plurality of logic gates, and include a processor and a memory that stores instructions executed by the processor.

[0045] According to some example embodiments, the controller 14 may generally control the PMIC 10 itself or components (eg, the upper regulator circuit 11, the lower regulator circuit 12, and the Kelvin switch circuit 13) included in the PMIC 10. Figure 7 and Figure 8 Detailed description and Figure 2 An example of a corresponding PMIC 10 .

[0046] Figure 3 is a block diagram illustrating the PMIC 20 according to some example embodiments.

[0047] Figure 3 The PMIC 20 may include an upper regulator circuit 21 , a lower regulator circuit 22 , a Kelvin switch circuit 23 , a controller 24 , and a detection gain control circuit 25 . Figure 3 The upper regulator circuit 21, the lower regulator circuit 22, the Kelvin switch circuit 23 and the controller 24 can be respectively connected to Figure 2 The upper regulator circuit 11, the lower regulator circuit 12, the Kelvin switch circuit 13 and the controller 14 correspond to each other. Figure 3 In the description of Figure 2 Descriptions of components identical to those described above will be omitted.

[0048] Reference Figure 3 , the detection gain control circuit 25 is provided between the Kelvin switch circuit 23 and the lower regulator circuit 22. The detection gain control circuit 25 may have a structure in which a plurality of resistors are connected in series. According to some example embodiments, the Kelvin switch circuit 23 may be connected between a plurality of resistors included in the detection gain control circuit 25. The gain value of the voltage may be controlled by adjusting the value of the resistor included in the detection gain control circuit 25. For example, the detection gain control circuit 25 may adjust the gain value of the feedback voltage output from the Kelvin switch circuit 23 to the upper regulator circuit 21. Therefore, the voltage of the lower regulator circuit 22 may be more easily controlled. Referring to Fig. 9 The voltage control of the lower regulator circuit 22 is described in detail.

[0049] Figure 4 is a block diagram illustrating a PMIC 30 according to some example embodiments.

[0050] Figure 4 The PMIC 30 may include an upper regulator circuit 31 , a lower regulator circuit 32 , a Kelvin switch circuit 33 , a controller 34 , and a detection gain control circuit 35 . Figure 4 The upper regulator circuit 31, the lower regulator circuit 32, the Kelvin switch circuit 33 and the controller 34 can be respectively connected to Figure 2The upper regulator circuit 11, the lower regulator circuit 12, the Kelvin switch circuit 13 and the controller 14 correspond to each other. Figure 4 In the description of Figure 2 Descriptions of components identical to those described above will be omitted.

[0051] Reference Figure 4 The detection gain control circuit 35 is arranged between the Kelvin switch circuit 33 and the upper regulator circuit 31. Figure 3 In contrast, the location of the detection gain control circuit 35 in the PMIC 30 may be different from the location of the detection gain control circuit 25 in the PMIC 20. The detection gain control circuit 35 is connected to the feedback voltage terminal of the upper regulator circuit 31 to adjust the detection gain of the feedback voltage, which will refer to Fig.10 For example, the detection gain control circuit 35 may adjust the gain value of the feedback voltage output from the Kelvin switch circuit 33 to the upper regulator circuit 31 .

[0052] Figure 5 is a block diagram illustrating a PMIC 40 according to some example embodiments. Figure 5 The PMIC 40 may include an upper regulator circuit 41 , a lower regulator circuit 42 , a Kelvin switch circuit 43 , a controller 44 , and a minimum voltage selection circuit 46 . Figure 5 The upper regulator circuit 41, the lower regulator circuit 42, the Kelvin switch circuit 43 and the controller 44 can be respectively connected to Figure 2 The upper regulator circuit 11, the lower regulator circuit 12, the Kelvin switch circuit 13 and the controller 14 correspond to each other. Figure 5 In the description of Figure 2 Descriptions of components identical to those described above will be omitted.

[0053] The minimum voltage selection circuit 46 may be disposed between the Kelvin switch circuit 43 and the upper regulator circuit 41. Figure 5 In the PMIC 40 of FIG. 4 , a plurality of down regulators may be connected to at least one up regulator included in the up regulator circuit 41. According to some example embodiments, the minimum voltage selection circuit 46 may select a down regulator having a highest voltage drop among the plurality of down regulators.

[0054] When multiple down regulators are connected to one up regulator, the values ​​of the load current flowing through the down regulators may all be different. As the value of the load current increases, the parasitic resistance value increases and the voltage drop may increase. Therefore, the minimum voltage selection circuit 46 can improve or optimize the dropout voltage (or voltage drop) by selecting the lowest voltage (e.g., the voltage with the most voltage drop), which will refer to Fig.11 Detailed description.

[0055] Figure 6 is a block diagram illustrating a PMIC 50 according to some example embodiments.

[0056] Figure 6 The PMIC 50 may include an upper regulator circuit 51 , a lower regulator circuit 52 , a Kelvin switch circuit 53 , a controller 54 , a detection gain control circuit 55 , and a minimum voltage selection circuit 56 . Figure 6 The upper regulator circuit 51, the lower regulator circuit 52, the Kelvin switch circuit 53 and the controller 54 can be respectively connected to Figure 2 The upper regulator circuit 11, the lower regulator circuit 12, the Kelvin switch circuit 13, and the controller 14 correspond to: Figure 6 The detection gain control circuit 55 can be connected with Figure 4 The detection gain control circuit 35 corresponds to, and Figure 6 The minimum voltage selection circuit 56 can be connected with Figure 5 The minimum voltage selection circuit 46 corresponds to. Figure 6 In the description of FIG. 1 , descriptions of components identical to those described in previous drawings are omitted.

[0057] Reference Figure 6 , the PMIC 50 may include both a detection gain control circuit 55 and a minimum voltage selection circuit 56. The PMIC 50 according to some example embodiments may adjust the detection gain of the output voltage of the upper regulator circuit 51 fed back through the detection gain control circuit 55, and may select a lower regulator having the lowest voltage among a plurality of lower regulators using the minimum voltage selection circuit 56.

[0058] In order to feedback sense the output voltage of the upper regulator circuit, the minimum voltage selection circuit 56 included in the PMIC 50 according to example embodiments may maintain the voltage level by adjusting the voltage at the input terminal of the lower regulator circuit connected to the load terminal based on the lowest voltage. The PMIC 50 according to some example embodiments may perform voltage control to reduce (and / or minimize) power loss due to IR drop, and perform a compensation operation based on a voltage having a maximum loss.

[0059] Figure 7 is a circuit diagram illustrating a PMIC 60 according to some example embodiments.

[0060] Reference Figure 7, shows an example of a circuit diagram of a PMIC 60 including an upper regulator circuit 61, a lower regulator circuit 62, a Kelvin switch circuit 63, and a controller 64, wherein the upper regulator circuit 61 may include a first switch regulator 61a and a second switch regulator 61b. The lower regulator circuit 62 may include a first LDO regulator (L1) 62a, a second LDO regulator (L2) 62b, a third LDO regulator (L3) 62c, and a fourth LDO regulator (L4) 62d. The Kelvin switch circuit 63 may include a first Kelvin sensing circuit 63a, a second Kelvin sensing circuit 63b, a third Kelvin sensing circuit 63c, and a fourth Kelvin sensing circuit 63d. The first Kelvin sensing circuit 63a may include a first switch S1 and a second switch S2. The second Kelvin sensing circuit 63b may include a third switch S3 and a fourth switch S4. The third Kelvin sensing circuit 63c may include a fifth switch S5 and a sixth switch S6. The fourth Kelvin sensing circuit 63d may include a seventh switch S7 and an eighth switch S8.

[0061] Reference Figure 7 , the system voltage Vsys may be applied to each of the first switching regulator 61a and the second switching regulator 61b included in the upper regulator circuit 61. According to some example embodiments, although the same system voltage Vsys is shown as being applied to the first switching regulator 61a and the second switching regulator 61b included in the upper regulator circuit 61, system voltages having different levels from each other may be applied to each of the first switching regulator 61a and the second switching regulator 61b. The first switching regulator 61a and the second switching regulator 61b may output first output voltages Vo1 and Vo2, respectively, through pins PIN1 and PIN2 connected to the corresponding switching regulators and a filter selectively set. For example, the filter may be an inductor or a capacitor. The first output voltages Vo1 and Vo2 may be applied to the power supply node VN of the lower regulator included in the lower regulator circuit 62 via pins PIN3 and PIN4 for connecting to the lower regulator circuit 62.

[0062] exist Figure 7 As described above, Optional may mean that the connection structure of the upper regulator circuit and the lower regulator circuit may be different according to the power rail of the electronic device connected to the PMIC 60, and the feedback loops in the connection process may be different. Optional may mean that the connection structure between the upper regulator circuit 61 and the lower regulator circuit 62 may be selectively determined.

[0063] According to some example embodiments, the first Kelvin sensing circuit 63a connected to the first LDO regulator 62a may include a first switch S1 and a second switch S2. The first switch S1 may be connected to the second switching regulator 61b to provide feedback fb2, and the second switch S2 may be connected to the first switching regulator 61a to provide feedback fb1. The first switch control signal C1 and the second switch control signal C2 may be applied to the first switch S1 and the second switch S2, respectively. The first switch control signal C1 and the second switch control signal C2 may be output by the controller 64. The first output voltage Vo1 of the first switching regulator 61a or the first output voltage Vo2 of the second switching regulator 61b may be feedback-controlled by controlling to turn on any one of the first switch S1 and the second switch S2 included in the first Kelvin sensing circuit 63a.

[0064] According to some example embodiments, the operation of the first Kelvin sensing circuit 63a may be similarly applied to a second Kelvin sensing circuit 63b including a third switch S3 and a fourth switch S4 and a third switch control signal C3 and a fourth switch control signal C4, a third Kelvin sensing circuit 63c including a fifth switch S5 and a sixth switch S6 and a fifth switch control signal C5 and a sixth switch control signal C6, and a fourth Kelvin sensing circuit 63d including a seventh switch S7 and an eighth switch S8 and a seventh switch control signal C7 and an eighth switch control signal C8.

[0065] Reference Figure 7 , a PMIC 60 having a sub-regulator structure capable of improving efficiency by combining a switching regulator and a linear regulator is disclosed. The LDO regulator included in the lower regulator circuit 62 according to the example embodiment needs to reduce the voltage difference between the two ends of the LDO regulator in order to obtain high efficiency. When the system voltage Vsys is directly connected to the LDO regulator for use, power loss occurs. Therefore, the overall efficiency can be improved by using a switching regulator (i.e., an upper regulator circuit) with relatively high efficiency to reduce the system voltage Vsys to supply power to the lower regulator. In some example embodiments, the sub-regulator structure may represent a structure in which the system voltage Vsys is sequentially converted and output by the switching regulator and the LDO regulator. According to some example embodiments, the sub-regulator structure may represent a structure in which the voltage is controlled by the switching regulator to improve efficiency instead of directly connecting the system voltage Vsys through the LDO regulator. In this way, the voltage difference of the first LDO regulator 62a to the fourth LDO regulator 62d included in the lower regulator circuit 62 can be improved or optimized.

[0066] According to some example embodiments, as the output current capacity of the LDO regulator continues to increase, there is a possibility that the power supply voltage decreases and deteriorates due to parasitic resistance, and therefore, improvement or optimization of the voltage difference of the LDO regulator may be required. According to some example embodiments, the voltage difference may be improved or optimized and the number of pins PIN may be reduced by controlling the structure of the Kelvin switch circuit 63 and the signal applied to the Kelvin switch circuit 63. The structure of the PMIC 60 according to some example embodiments may reduce the number of pins and reconfiguration of power rails, and therefore may be advantageous in a PMIC using a limited number of pins PIN.

[0067] Reference Figure 7 , through the Kelvin switch circuit 63, the output voltage of the upper regulator circuit 61 can be detected inside the PMIC 60 instead of outside. Therefore, in the PMIC 60 according to some example embodiments, even if the voltage reduced by the printed circuit board (PCB) pattern resistors Rp3 and Rp4 and the pin resistors R_pin3 and R_pin4 is supplied to the lower regulator circuit 62, the voltage is transferred to the upper regulator circuit 61 through the Kelvin switch circuit 63 and the voltage reduction is compensated. A signal capable of controlling whether the plurality of switches S1 to S8 included in the Kelvin switch circuit 63 are closed may be applied from the controller 64. The structure of the Kelvin switch circuit 63 may be selected from a structure including a plurality of switching regulators and an LDO regulator (including Figure 7 Therefore, regardless of the magnitude of the output current of the LDO regulator, the PMIC 60 according to some example embodiments can receive an accurate power supply voltage and can ensure relatively high efficiency.

[0068] When the electronic device connected to the PMIC 60 is determined and the specification of the corresponding electronic device is determined, the controller 64 may fix the connection structure between the upper regulator circuit and the lower regulator circuit corresponding to the electronic device connected to the PMIC 60, and not control the switch included in the Kelvin switch circuit 63 to be closed or opened according to a separate operation. For example, in the case of the electronic device A, the first switching regulator 61a, the first LDO regulator 62a, and the second LDO regulator 62b may be connected, and in the case of the electronic device B, the first switching regulator 61a, the third LDO regulator 62c, and the fourth LDO regulator 62d may be connected. The controller 64 may control the switch included in the Kelvin switch circuit 63 to be closed or opened according to the connection structure between the upper regulator circuit and the lower regulator circuit corresponding to each electronic device.

[0069] Figure 8 is a circuit diagram showing a PMIC 70 according to some example embodiments. Figure 8 In the description of Figure 7The description given is omitted. For example, something like Figure 7 , the PMIC 70 may include a controller 74; the upper regulator circuit 71 may include a first switching regulator 71a and a second switching regulator 71b; the Kelvin switch circuit 73 may include a first Kelvin sensing circuit 73a, a second Kelvin sensing circuit 73b, a third Kelvin sensing circuit 73c and a fourth Kelvin sensing circuit 73d; and a lower regulator circuit 72.

[0070] Reference Figure 8 The number of pins PIN1 to PIN6 between the output terminal of the upper regulator circuit 71 and the power supply node VN of the lower regulator circuit 72 is equal to Figure 7 The embodiments are different, and the number of PCB pattern resistors Rp3 to Rp6 is also different.

[0071] Reference Figure 8 , each of the first LDO regulator 72a, the second LDO regulator 72b, the third LDO regulator 72c, and the fourth LDO regulator 72d included in the lower regulator circuit 72 may have a pin corresponding to each feedback loop of the upper regulator circuit 71. Figure 8 , showing the structure of the PMIC 70, in which the power supply pins of each of the first LDO regulator 72a, the second LDO regulator 72b, the third LDO regulator 72c, and the fourth LDO regulator 72d are separated from each other. Figure 7 In comparison, although the number of pins increases, a pin corresponding to each LDO regulator is included, and thus clearer voltage detection control is possible.

[0072] Fig. 9 is a circuit diagram showing a PMIC 80 according to some example embodiments. Fig. 9 In the description of Figure 7 and Figure 8 The description already given is omitted. Fig. 9, the detection gain control circuit 85 is arranged between the Kelvin switch circuit 83 and the down regulator circuit 82, and the Kelvin switch circuit 83 includes a first Kelvin sensing circuit 83a, a second Kelvin sensing circuit 83b, a third Kelvin sensing circuit 83c, and a fourth Kelvin sensing circuit 83d. The controller 84 controls the first Kelvin sensing circuit 83a, the second Kelvin sensing circuit 83b, the third Kelvin sensing circuit 83c, and the fourth Kelvin sensing circuit 83d. The detection gain control circuit 85 may include a plurality of detection gain circuits (e.g., first to fourth detection gain circuits 85a, 85b, 85c, and 85d). Each of the plurality of detection gain circuits 85a, 85b, 85c, and 85d may be arranged to correspond to the LDO regulators 82a, 82b, 82c, and 82d included in the down regulator circuit 82.

[0073] According to some example embodiments, the first detection gain circuit 85a may be provided between the first Kelvin sensing circuit 83a and the first LDO regulator 82a. The first detection gain circuit 85a may generate a feedback voltage Vfs proportional to the voltage of the power supply node VN of the first LDO regulator 82a, and transmit the feedback voltage Vfs to the upper regulator circuit 81 including the first switching regulator 81a and the second switching regulator 81b through the first Kelvin sensing circuit 83a. For example, Fig. 9 As shown in , the first detection gain circuit 85a may provide the feedback voltage Vfs corresponding to the ratio of the resistance values ​​to the upper regulator circuit 81 using the distribution resistors Rs1 and Rs2, but the configuration of the first detection gain circuit 85a is not limited thereto.

[0074] exist Fig. 9 , the relationship of Vfs=VN×Rs2 / (Rs1+Rs2) is satisfied. Here, VN may represent the voltage of the power supply node VN, and Rs1 and Rs2 may represent the resistance value of the distribution resistor Rs1 and the resistance value of the distribution resistor Rs2, respectively. The distribution resistors Rs1 and Rs2 may be connected in series between the power supply node VN and the ground voltage, and may be connected to each other at the feedback node Vs. The first detection gain circuit 85a may provide a feedback voltage Vfs at the feedback node Vs. According to some example embodiments, the distribution resistors Rs1 and Rs2 may be a voltage divider that generates a feedback voltage Vfs by dividing the voltage of the power supply node VN. According to some example embodiments, in the case of a specific LDO regulator, operations such as increasing or decreasing the detection gain may be required. When the detection gain control circuit 85 is provided between the Kelvin switch circuit 83 and the lower regulator circuit 82, it may be determined which upper regulator in the upper regulator circuit 81 is reflected with reference to the feedback voltage Vfs.

[0075] Although only described as Fig. 9The present invention relates to a first detection gain circuit 85a which is one of the multiple detection gain circuits 85a, 85b, 85c and 85d in the present invention, but it can be understood that the description of the first detection gain circuit 85a can be similarly applied to the remaining second detection gain circuit 85b including the distribution resistors Rs3 and Rs4, the third detection gain circuit 85c including the distribution resistors Rs5 and Rs6, and the fourth detection gain circuit 85d including the distribution resistors Rs7 and Rs8.

[0076] Fig.10 is a circuit diagram showing a PMIC 90 according to some example embodiments. Fig.10 , the PMIC 90 may include a detection gain control circuit 95 disposed between a Kelvin switch circuit 93 (including a first Kelvin sensing circuit 93a, a second Kelvin sensing circuit 93b, a third Kelvin sensing circuit 93c, and a fourth Kelvin sensing circuit 93d) and an upper regulator circuit 91, and may also include a lower regulator circuit 92 (including a first LDO regulator 92a, a second LDO regulator 92b, a third LDO regulator 92c, and a fourth LDO regulator 92d). The detection gain control circuit 95 may include a plurality of detection gain circuits (e.g., first to eighth detection gain circuits 95a1, 95a2, 95b1, 95b2, 95c1, 95c2, 95d1, and 95d2). Fig.10 , the connection of the controller 94 is not shown as being directly connected to the Kelvin switch circuit 93, but Fig.10 The controller 94 in can be connected to the switches included in the Kelvin switch circuit 93 as shown in the above figures.

[0077] Reference Fig.10 , a first detection gain circuit 95a1 and a second detection gain circuit 95a2 corresponding to the first Kelvin sensing circuit 93a may be provided. According to some example embodiments, a first switch S1 included in the first Kelvin sensing circuit 93a may be connected to the first switching regulator 91a via the first detection gain circuit 95a1, and a second switch S2 included in the first Kelvin sensing circuit 93a may be connected to the second switching regulator 91b via the second detection gain circuit 95a2.

[0078] The first detection gain circuit 85a corresponding to the first Kelvin sensing circuit 83a is disclosed as a Fig. 9 In comparison, Fig.10 In the embodiment, the detection gain circuits 95a1 and 95a2 corresponding to the first Kelvin sensing circuit 93a are disclosed as two. Fig. 9 The configuration of the detection gain circuit is the same, so its detailed description is omitted.

[0079] As in Fig.10 In the embodiment, when the detection gain circuits 95a1 and 95a2 are provided in front of the Kelvin switch circuit 93, since the outputs corresponding to the first switch S1 and the second switch S2 included in the first Kelvin sensing circuit 93a are respectively determined, the gain can be adjusted in more detail. According to some example embodiments, the voltage detected by the Kelvin switch circuit 93 may be transmitted to the upper regulator circuit 91 after the detection gain is adjusted.

[0080] Although only described Fig.10 Some of the multiple detection gain circuits 95a1 and 95a2 are described above, but it can be understood that the description of the detection gain circuits 95a1 and 95a2 can be similarly applied to the remaining detection gain circuits 95b1, 95b2, 95c1, 95c2, 95d1 and 95d2.

[0081] Fig.11 is a circuit diagram illustrating a PMIC 100 according to some example embodiments. Fig.11 , the connection of the controller 104 is shown as not being directly connected to the Kelvin switch circuit 103, but Fig.11 The controller 104 may be connected to the switches included in the Kelvin sensing circuits 103a, 103b, 103c, and 103d of the Kelvin switch circuit 103 as shown in the above figures.

[0082] Reference Fig.11 , showing a minimum voltage selection circuit 106. According to some example embodiments, the minimum voltage selection circuit 106 includes a first minimum voltage selector 106a, a second minimum voltage selector 106b, a third minimum voltage selector 106c, and a fourth minimum voltage selector 106d. According to some example embodiments, the minimum voltage selection circuit 106 may be provided between the upper regulator circuit 101 and the Kelvin switch circuit 103. According to some example embodiments, each of the first to fourth minimum voltage selectors 106a, 106b, 106c, and 106d included in the minimum voltage selection circuit 106 may be connected between: any one of the plurality of first switching regulators 101a and the second switching regulator 101b and a switch connected to at least two or more lower regulators among the plurality of switches S1, S2, S3, S4, S5, S6, S7, and S8 included in the Kelvin switch circuit 103.

[0083] according to Fig.11In some example embodiments, assuming that a plurality of down regulators including LDO regulators 102a, 102b, 102c, and 102d use the output voltage of the same switching regulator 101a or 101b, the magnitude of the voltage dropped by the PCB resistors Rp3 to Rp6 and the pin resistors R_pin3 to R_pin6 may be proportional to the output current of each down regulator including the LDO regulators 102a, 102b, 102c, and 102d. Therefore, when only the Kelvin switch circuit 103 is used, the average voltage of the detected voltage is fed back to the up regulator circuit 101, and thus, the accuracy of the voltage compensation may be reduced.

[0084] According to some example embodiments, when both power supply voltages of the first LDO regulator 102a and the second LDO regulator 102b are connected to the second switching regulator 101b, the first switch S1 and the third switch S3 included in the Kelvin switch circuit 103 may be connected to the first minimum voltage selector 106a. In some example embodiments, any one of the plurality of upper regulators (i.e., the plurality of switching regulators) may form a feedback loop with at least two or more of the plurality of lower regulators (i.e., the plurality of LDO regulators). In some example embodiments, the second switching regulator 101b may form a feedback loop with the first LDO regulator 102a and the second LDO regulator 102b. The first minimum voltage selector 106a may be connected to the second switching regulator 101b by controlling whether the first switch S1 and the third switch S3 are closed to select an LDO regulator with a large voltage drop among the first LDO regulator 102a and the second LDO regulator 102b. The first LDO regulator 102a and the third switch S3 may be controlled to be disconnected.

[0085] exist Fig.11 In the description of FIG. 1 , only the first minimum voltage selector 106 a is described, but the mechanism of the first minimum voltage selector 106 a may also be applied to the second minimum voltage selector 106 b , the third minimum voltage selector 106 c , and the fourth minimum voltage selector 106 d .

[0086] Fig.12 is a circuit diagram illustrating the PMIC 110 according to some example embodiments.

[0087] according to Fig.12The PMIC 110 includes an upper regulator circuit 111 including a first switching regulator 111a and a second switching regulator 111b, a lower regulator circuit 112 including LDO regulators 112a, 112b, 112c, and 112d, a Kelvin switch circuit 113 including Kelvin sensing circuits 113a, 113b, 113c, and 113d, a controller 114, a detection gain control circuit 115 including detection gain circuits 115a, 115b, 115c, and 115d, and a minimum voltage selection circuit 116 including minimum voltage selectors 116a, 116b, 116c, and 116d. Fig.12 , the connection of the controller 114 is shown as not being directly connected to the Kelvin switch circuit 113, but Fig.12 The controller 114 may be connected to the switches included in the Kelvin switch circuit 113 as shown in the above figures.

[0088] The output voltages Vo1 and Vo2 of the upper regulator circuit 111 may be fed back through the Kelvin switch circuit 113, the detection gain control circuit 115, and the minimum voltage selection circuit 116. Fig.12 , it is described that the upper regulator circuit 111 includes two switching regulators and the lower regulator circuit 112 includes four LDO regulators, but the number of switching regulators and the number of LDO regulators applicable to some example embodiments are not limited thereto.

[0089] Fig.13 is a flowchart illustrating a method of operating a PMIC according to some example embodiments.

[0090] In operation S100, a system voltage may be applied to a PMIC. According to some example embodiments, the system voltage may be applied to an upper regulator circuit (such as, for example, Figures 2 to 6 Any of the upper regulator circuits 11, 21, 31, 41 or 51 shown in FIG. 1 ).

[0091] In operation S200, a primary output voltage may be generated by an upper regulator circuit. The primary output voltage may be a voltage output from a system voltage via the upper regulator circuit. The primary output voltage may be at a level less than that of the system voltage.

[0092] In operation S300, a Kelvin switch circuit (such as, for example, a Kelvin switch circuit provided between a lower regulator circuit (such as, for example, any one of the lower regulator circuits 12, 22, 32, 42, or 52) and an upper regulator circuit may be controlled. Figures 2 to 6Any one of the Kelvin switch circuits 13, 23, 33, 43 or 53 shown in ). Some of the multiple switches included in the Kelvin switch circuit can be controlled to be closed, and some of the switches can be controlled to be opened, so that the lower regulator circuit and the upper regulator circuit are controlled to be feedback sensed. Through the control of the Kelvin switch circuit, any one of the multiple lower regulators included in the lower regulator circuit can be controlled to be connected to any one of the multiple upper regulators included in the upper regulator circuit, so that the primary output voltage of the upper regulator circuit can be feedback sensed. According to some example embodiments, when the gain of the detection voltage is adjusted or multiple lower regulators are connected to the upper regulator, the lower regulator with the largest voltage drop can be selected. The control of the Kelvin switch circuit can be performed by a controller. The controller can control the multiple switches included in the Kelvin switch circuit in response to the power supply information corresponding to the component connected to the PMIC.

[0093] In operation S400, the output voltage of the upper regulator may be adjusted by feeding back a parasitic resistance. Here, the parasitic resistance may refer to a parasitic resistance generated between a primary output voltage and a power supply node of the lower regulator circuit.

[0094] According to some example embodiments, the output voltage of the upper regulator circuit may be detected by connecting the Kelvin switch circuit to the power supply node of the lower regulator circuit, and the output voltage may be feedback controlled. According to some example embodiments, the Kelvin switch circuit may be controlled by digital logic or internal and external switch regulation circuits, or may be controlled by a controller according to some example embodiments. According to some example embodiments, the power supply voltage of the lower regulator may be sequentially connected to the upper regulator via the Kelvin switch circuit and the detection gain control circuit, or the power supply voltage of the lower regulator may be sequentially connected to the upper regulator via the detection gain control circuit and the Kelvin switch circuit. According to some example embodiments, the power supply voltage of the lower regulator using the same upper regulator may be connected to the upper regulator through the minimum voltage selection circuit after the Kelvin switch circuit, or the power supply voltage of the lower regulator using the same upper regulator may be connected to the upper regulator through the Kelvin switch circuit after the minimum voltage selection circuit.

[0095] According to the PMIC of the comparative example, due to the parasitic resistance (e.g., PCB pattern resistance) existing between the output voltage of the upper regulator and the input voltage of the lower regulator, the power supply voltage may be reduced by the IR drop voltage and provided to the linear regulator. According to the comparative example, since the voltage reduced by the parasitic resistance on the PCB is not detected, the actual voltage provided to the linear regulator is reduced. Therefore, it is necessary to set the output voltage of the switching regulator to high, and therefore, the efficiency may be reduced except for the part with the largest output current.

[0096] A PMIC according to some example embodiments may ensure a voltage difference of a regulator included in a lower regulator circuit regardless of a high-capacity current, and may be reconfigured without developing hardware even if an upper regulator in a previous stage is changed.

[0097] One or more of the elements disclosed above may include a processing circuit (such as hardware including a logic circuit; a hardware / software combination (such as a processor that executes software); or a combination thereof), or be implemented in a processing circuit (such as hardware including a logic circuit; a hardware / software combination (such as a processor that executes software); or a combination thereof). For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0098] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A power management integrated circuit, include: an upper regulator circuit configured to: receive a system voltage as an input and output a first output voltage; a down regulator circuit having the first output voltage as an input; as well as Kelvin switch circuit, connected between the upper regulator circuit and the lower regulator circuit, The Kelvin switch circuit includes a plurality of switches configured to connect any one of a plurality of upper regulators included in the upper regulator circuit to any one of a plurality of lower regulators included in the lower regulator circuit.

2. The power management integrated circuit according to claim 1 further comprises a detection gain control circuit, which is connected between the down-regulator circuit and the Kelvin switch circuit and is configured to adjust the gain value of the feedback voltage output from the Kelvin switch circuit to the up-regulator circuit.

3. The power management integrated circuit according to claim 1 further comprises a detection gain control circuit, which is connected between the Kelvin switch circuit and the upper regulator circuit and is configured to adjust the gain value of the feedback voltage output from the Kelvin switch circuit to the upper regulator circuit.

4. The power management integrated circuit of claim 1 , further comprising a minimum voltage selection circuit connected between the Kelvin switch circuit and the upper regulator circuit and configured to select a lower regulator having a highest voltage drop from among the plurality of lower regulators.

5. The power management integrated circuit according to claim 4, wherein Any one of the plurality of up regulators is configured to form a feedback loop with at least two or more down regulators among the plurality of down regulators, and The minimum voltage selection circuit is connected between the any one of the plurality of upper regulators and a switch connected to the at least two or more lower regulators among the plurality of switches included in the Kelvin switch circuit. 6 . The power management integrated circuit of claim 1 , further comprising a controller configured to output a control signal to close or open the plurality of switches.

7. The power management integrated circuit according to claim 6, in, The controller is configured to apply the control signal to the plurality of switches in response to power supply information corresponding to a component connected to the power management integrated circuit.

8. The power management integrated circuit according to any one of claims 1 to 7, wherein Kelvin switch circuit include: Kelvin sensing circuits corresponding to the number of down regulators included in the down regulator circuit, and Each of the Kelvin sensing circuits includes: a number of switches of the plurality of switches corresponding to the number of upper regulators included in the upper regulator circuit.

9. A power management integrated circuit, include: a first switching regulator and a second switching regulator, wherein the first switching regulator and the second switching regulator both receive a system voltage as an input; A first low dropout output (LDO) regulator and a second LDO regulator, the first LDO regulator and the second LDO regulator being connected to an output terminal of the first switching regulator or an output terminal of the second switching regulator, respectively; a first Kelvin sensing circuit connected between a feedback voltage terminal of the first switching regulator and a feedback voltage terminal of the second switching regulator and a power supply node of the first LDO regulator; as well as The second Kelvin sensing circuit is connected between the feedback voltage terminal of the first switching regulator, the feedback voltage terminal of the second switching regulator, and the power supply node of the second LDO regulator.

10. The power management integrated circuit of claim 9, wherein The first Kelvin sensing circuit include: a first switch connected between a feedback voltage terminal of the first switching regulator and a power supply node of the first LDO regulator; and a second switch connected between the feedback voltage terminal of the second switching regulator and the power supply node of the first LDO regulator, and The second Kelvin sensing circuit includes: a third switch connected between a feedback voltage terminal of the first switching regulator and a power supply node of the second LDO regulator; and a fourth switch connected between the feedback voltage terminal of the second switching regulator and the power supply node of the second LDO regulator.

11. The power management integrated circuit according to claim 10, further comprising: include: a first minimum voltage selector connected between the feedback voltage terminal of the first switching regulator and the first switch and the third switch; as well as a second minimum voltage selector connected between the feedback voltage terminal of the second switching regulator and the second switch and the fourth switch, The first minimum voltage selector and the second minimum voltage selector are configured to select the LDO regulator having the highest voltage drop from among the first LDO regulator and the second LDO regulator.

12. The power management integrated circuit according to claim 10, further comprising: include: a first detection gain control circuit connected between the first Kelvin sensing circuit and a power supply node of the first LDO regulator and including a plurality of first resistors; as well as The second detection gain control circuit is connected between the second Kelvin sensing circuit and the power supply node of the second LDO regulator and includes a plurality of second resistors.

13. The power management integrated circuit according to claim 10, further comprising: include: a first detection gain control circuit connected between the first Kelvin sensing circuit and each of the feedback voltage terminal of the first switching regulator and the feedback voltage terminal of the second switching regulator, respectively, and configured to: adjust a gain value of a feedback voltage output from the first LDO regulator to the feedback voltage terminal of the first switching regulator and the feedback voltage terminal of the second switching regulator; as well as The second detection gain control circuit is connected between the second Kelvin sensing circuit and each of the feedback voltage terminal of the first switching regulator and the feedback voltage terminal of the second switching regulator, respectively, and is configured to: adjust the gain value of the feedback voltage output from the second LDO regulator to the feedback voltage terminal of the first switching regulator and the feedback voltage terminal of the second switching regulator.

14. The power management integrated circuit according to any one of claims 10 to 13, further comprising a controller, wherein the controller is configured to output switch control signals to the first switch, the second switch, the third switch and the fourth switch respectively to control the first switch, the second switch, the third switch and the fourth switch to be closed or opened.

15. The power management integrated circuit according to claim 14, in, The controller is configured to output a switch control signal in response to power supply information corresponding to a component connected to the power management integrated circuit.

16. The power management integrated circuit according to claim 14, further comprising: include: a first minimum voltage selector connected between the feedback voltage terminal of the first switching regulator and the first switch and the third switch; as well as a second minimum voltage selector connected between the feedback voltage terminal of the second switching regulator and the second switch and the fourth switch, Wherein, the controller is configured to control the first switch, the second switch, the third switch and the fourth switch, and the first minimum voltage selector and the second minimum voltage selector are configured to compare the voltage drop value at each of the first LDO regulator and the second LDO regulator, and select the LDO regulator with the larger voltage drop value from among the first LDO regulator and the second LDO regulator.

17. A method of operating a power management integrated circuit, the method include: applying a system voltage to the upper regulator circuit; generating a primary output voltage through an upper regulator circuit; as well as The primary output voltage is feedback sensed by controlling a Kelvin switch circuit connected between an upper regulator circuit and a lower regulator circuit to which the primary output voltage is applied.

18. The method according to claim 17, in, The step of feedback sensing the primary output voltage includes performing feedback sensing by controlling to connect any one of a plurality of down regulators included in the down regulator circuit to any one of a plurality of up regulators included in the up regulator circuit.

19. The method according to claim 18, in, The step of controlling connecting any one of the plurality of down regulators included in the down regulator circuit to any one of the plurality of up regulators included in the up regulator circuit comprises: controlling a plurality of switches included in a Kelvin switch circuit, and The step of controlling the plurality of switches is responsive to power supply information corresponding to a component to which the power management integrated circuit is connected.

20. The method according to claim 17, in, The step of feedback sensing the primary output voltage includes sensing by feedback of a parasitic resistance existing between the upper regulator circuit and the lower regulator circuit.

Images