Dynamic minimum cut-off time for switching regulator

Abstract

The invention relates to a dynamic minimum deadtime for a switching regulator. A circuit is configured to adjust a minimum off-time of a switching element in a power converter. In an example, a controller (106) includes a pulse width modulation (PWM) circuit (202) and a timing adjustment circuit (206). The PWM circuit (202) is configured to determine an off-time of the switching element based on the received feedback signal and a minimum off-time control signal. The received feedback signal is proportional to an output voltage of the power converter. The timing adjustment circuit (206) includes a comparator (308) in which a first comparator input is configured to receive a sampled voltage that varies based on the output voltage of the power converter and a second comparator input is configured to receive a reference voltage. The comparator (308) provides the minimum deadtime control signal at its output and is configured to adjust the minimum deadtime control signal based on a length of time during which the sampled voltage is less than the reference voltage.

Description

Technical Field

[0001] The present description relates to power converters, and more particularly, to adjusting a minimum off-time of a switching element in a switching regulator. Background Art

[0002] Power converters (e.g., DC-DC converters) are widely used in electronic systems such as consumer electronics, automotive systems, industrial equipment, lighting systems, etc. to convert an input voltage into an output voltage that is higher or lower than the input voltage. These converters utilize switching transistors (e.g., metal oxide semiconductor field effect transistors or MOSFETs) that are turned on and off to regulate the output voltage. A feedback loop along with a controller is also used to determine the on or off time of the transistor in each switching cycle based on the feedback voltage and a reference voltage, thereby regulating the output voltage of the power converter. There are many important problems in providing a stable output voltage in view of the transistor switching time. Summary of the invention

[0003] According to an embodiment, a controller designed to determine the cut-off time of a switching element of a power converter circuit is described. The controller includes: a pulse width modulation circuit configured to determine the cut-off time of the switching element based on a received feedback signal and a minimum cut-off time control signal; and a timing adjustment circuit including a comparator having a first and a second comparator input and a comparator output. The received feedback signal is proportional to the voltage at the output voltage terminal of the power converter circuit. The first comparator input is configured to receive a sampled voltage that changes based on the voltage at the output voltage terminal of the power converter circuit, and the second comparator input is configured to receive a reference voltage. The comparator output provides the minimum cut-off time control signal. The comparator is configured to adjust the minimum cut-off time control signal based on the length of time that the sampled voltage is less than the reference voltage.

[0004] According to another embodiment, a voltage regulator includes: a first voltage rail; a second voltage rail; a ground rail; a first transistor coupled between the first voltage rail and a switch node terminal; a first driver coupled to a control terminal of the first transistor and configured to receive a voltage on the second voltage rail; a second transistor coupled between the switch node terminal and the ground rail; a second driver coupled to a control terminal of the second transistor; and a timing adjustment circuit configured to generate a minimum off-time control signal for dynamically adjusting a minimum off-time of the first transistor. The timing adjustment circuit includes a comparator having: a first input configured to receive a sampled voltage that changes based on a voltage at the switch node terminal; a second input configured to receive a reference voltage; and an output that provides the minimum off-time control signal. The minimum off-time control signal has a state based on a length of time that the sampled voltage is less than the reference voltage.

[0005] According to another embodiment, a timing adjustment circuit for use in a voltage converter is described. The timing adjustment circuit includes: a filter circuit configured to receive a switch node terminal voltage of the voltage converter and generate a direct current (DC) voltage proportional to the output voltage of the voltage converter; an operational amplifier (op-amp) having an op-amp output and first and second op-amp inputs. The first op-amp input is configured to receive the DC voltage. The timing adjustment circuit also includes a first transistor having a control terminal coupled to the output of the operational amplifier, a first current terminal coupled to the second op-amp input, and a second current terminal. The timing adjustment circuit also includes: a capacitor having a first terminal and a second terminal; a current mirror circuit coupled between a voltage supply terminal and the second current terminal of the first transistor, and also coupled between the voltage supply terminal and the first terminal of the capacitor; a second transistor coupled between the first and second terminals of the capacitor; and a comparator having a comparator output and first and second comparator inputs. The first comparator input is coupled to the first terminal of the capacitor and the second comparator input is coupled to a reference voltage source such that the comparator output provides a logic high in response to a voltage at the first comparator input being higher than a voltage at the second comparator input and the comparator output provides a logic low in response to a voltage at the first comparator input being lower than the voltage at the second comparator input. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the example, Figure 1 is the block diagram of a voltage regulator.

[0007] In the example, Figure 2A It is a display Figure 1 A block diagram of a controller of a voltage regulator is shown in FIG.

[0008] In the example, Figure 2B is with Figure 2A 0048 is a timing diagram of various signals associated with the pulse control block of the controller shown in FIG.

[0009] In the example, Figure 3 yes Figure 2A A block diagram of the timing adjustment circuit of the controller shown in FIG.

[0010] In the example, Figure 4 yes Figure 3 Schematic diagram of the timing adjustment circuit shown in .

[0011] In the example, Figure 5 Provide with Figure 4 0048] A timing diagram of various signals associated with the timing adjustment circuit shown in FIG.

[0012] In the example, Figure 6 Provides graphs of different minimum off-times produced by the timing adjustment circuit for different output voltages.

[0013] Fig. 7A Graphs of output voltage and output current are provided for different parasitic capacitance values ​​without using a timing adjustment circuit.

[0014] In the example, Figure 7B Graphs of output voltage and output current for different parasitic capacitance values ​​are provided when using a timing adjustment circuit. DETAILED DESCRIPTION

[0015] A technique for adjusting the minimum cut-off time of a switching element in a power converter is described. According to some embodiments, the technique may be implemented in a timing adjustment system. In some such instances, the system is configured to adjust the minimum allowable cut-off time of a high-side switching element of a power converter (e.g., a DC-DC buck converter). The timing adjustment system may include a timing adjustment circuit within a controller, the controller generating a pulse width modulation (PWM) signal for turning on and off both the high-side switching element and the low-side switching element. The high-side and low-side switching elements regulate whether the switch node terminal is coupled to an input power rail or to a ground rail, and their respective on-times indicate an output voltage level. The high-side and low-side switching elements are alternately activated so that the high-side switching element is turned on, while the low-side switching element is turned off, and vice versa. A feedback loop is provided to sample the output voltage and provide it back to the controller, and the controller may use the feedback to set the appropriate on-time of the high-side switching element to bring the output voltage to a desired voltage output.

[0016] According to some such embodiments, the timing adjustment circuit samples the output switch voltage of the power converter and converts this sampled voltage into a sampled current. The current mirror can be used to provide a mirror current (e.g., approximately equal to the sampled current) for charging the capacitor during the time period when the high-side switch element is turned off. The voltage on the capacitor is compared with the reference voltage by a comparator, wherein the output of the comparator remains low, and the capacitor voltage is less than the reference voltage. In response to the capacitor charging long enough so that the capacitor voltage exceeds the reference voltage, the output of the comparator switches to high. The comparator output can be used to override the feedback operation used by the controller by forcing the high-side switch element to remain turned off at least until the voltage on the capacitor exceeds the reference voltage, and the feedback operation determines when to turn on the high-side switch element. Therefore, the minimum cut-off time of the high-side switch element can be dynamically adjusted based on the output voltage level. For example, in order to reduce the output voltage, the minimum cut-off time can be increased respectively.

[0017] General Overview

[0018] As described above, a number of important issues are associated with providing a stable output voltage in view of the transistor (e.g., MOSFET) switching time within the power converter. For example, the controller typically uses a minimum cut-off time to control the PWM signals of the high-side and low-side MOSFET switches to support a large duty cycle and improve load transient performance. Therefore, the minimum cut-off time is set as low as possible (e.g., about 50ns). However, in the case where a lower output voltage is required, the problem of a lower minimum cut-off time is generated. For example, a desired output voltage of less than two volts may cause the output voltage terminal to be charged insufficiently due to parasitic capacitance within the circuit or circuit package. This parasitic capacitance may, for example, exist between the output terminal and the feedback terminal of the power converter. Since the feedback voltage is also affected, the feedback voltage also drops and cannot be recovered due to the short minimum cut-off time. As a result, the high-side switch is turned on for too long and the output voltage becomes unstable. A longer minimum cut-off time of the high-side switch can correct this problem, but this causes noise and other instability problems when the desired output voltage is higher (e.g., closer to the input voltage of the power converter). In such cases, it may be advantageous to keep the minimum cut-off time short.

[0019] Thus, described herein are techniques for dynamically adjusting the off time of a power converter switching element (e.g., a MOSFET). In an example, a timing adjustment system is described that can be integrated with a controller of a power converter to dynamically change the minimum off time of a high-side switch based at least in part on an output voltage. The timing adjustment system can include circuitry within the controller itself or coupled to the controller, the timing adjustment system including a sampling block, an amplifier block, a charging block, and a comparator block at the output. According to some embodiments, the sampling block can be designed to sample the switch node voltage of the power converter, and use any number of resistor-capacitor (RC) filters to average the switch node voltage and provide an average output voltage (V CSN The average output voltage can be fed into the input of an amplifier block (e.g., an operational amplifier) ​​to generate a drive voltage (V DRV According to some embodiments, the charging block may include a MOSFET having a receiving V DRV The gate terminal of the high-side switch is connected to generate a related current (I1) through a resistor (R). A current mirror within the charging block can be used to provide a mirror current (I2) substantially the same as I1 to charge the capacitor (C) only during the time when the high-side switch is turned off (and the low-side switch is respectively turned on). The voltage on the capacitor can be received by a first input of a comparator block, and a second input of the comparator block receives a reference voltage. The output of the comparator block determines the minimum off time of the high-side switch and remains low as long as the voltage on the capacitor remains below the reference voltage. The comparator block output can be used to override the output of a feedback loop used by a controller to determine the on time of the high-side switch (for example, by using logic such as an AND gate). Based on the embodiments described herein, many other variations will be apparent.

[0020] Electronic Systems

[0021] Figure 1 At least a portion of an exemplary electronic system 100 is shown. In some cases, the electronic system 100 is implemented as a system on a chip, or as a chipset populated on a printed circuit board (PCB), or as a set of discrete components populated on a PCB, which in turn can be populated into a chassis of a multi-chassis system or other higher-level system, but any number of implementations can be used. The electronic system 100 can be part of a switching regulator or a power converter (e.g., a DC-DC step-down switching converter).

[0022] According to some embodiments, electronic system 100 includes power converter circuit 102, which may be implemented as a chip within a chip package and may have various input / output (I / O) terminals, such as an enable terminal (EN), a power input terminal (PVIN), a bootstrap terminal (BST), a switch node terminal (SW), a ground terminal (GND), and a feedback terminal (FB). Any number of other I / O terminals may be provided.

[0023] According to some embodiments, the power converter circuit 102 includes a high-side switching element (HSD) together with an associated high-side driver (HS), and a low-side switching element (LSD) together with an associated low-side driver (LS). Figure 1 As shown in , both the high-side switch element HSD and the low-side switch element LSD can be n-channel MOSFETs, but other suitable switch elements can be used. The high-side switch element HSD has a first terminal coupled to an input power rail (e.g., a PVIN terminal) and a second terminal coupled to a switch node SW of a power converter. Therefore, the state of the high-side driver HS controls the gate terminal of the high-side switch element HSD, and the high-side switch element HSD provides the input voltage on PVIN to the switch node SW when the high-side switch element HSD is turned on. The low-side switch element LSD has a first terminal coupled to the switch node SW and a second terminal coupled to a ground rail (e.g., at a ground terminal GND). Therefore, the state of the low-side driver LS controls the gate terminal of the low-side switch element LSD, and the low-side switch element LSD provides the ground voltage to the switch node SW when the low-side switch element LSD is turned on. Only one of the HSD and LSD is turned on at any given time, and whenever the HSD is turned on, the LSD is turned off, and vice versa.

[0024] A boost capacitor Cb may be coupled between the switch node SW and a bootstrap terminal BST (or bootstrap voltage rail) and may be used in conjunction with a bootstrap charging circuit 104 between the bootstrap terminal BST and the input voltage terminal PVIN (e.g., for charging Cb) to provide a boosted voltage higher than the output switch voltage at SW. This boosted voltage may then be provided to the positive supply rail of the high-side driver HS.

[0025] An inductor LOUT may be provided at the switch node SW to smooth the varying voltage and provide a more stable output voltage as VOUT. In some cases, the inductor LOUT may be, for example, part of a transformer, or any other suitable energy storage element. A voltage divider including resistors R1 and R2 may be provided at the output to generate a feedback voltage that is fed to a feedback terminal FB of the power converter circuit 102.

[0026] The controller 106 sends a control signal (eg, HS PWM and LSPWM ) are provided to the inputs of the high-side driver HS and the low-side driver LS, respectively. These control signals may be pulse width modulation signals that drive the corresponding high-side switching elements and low-side switching elements. The controller 106 may also receive various inputs (e.g., feedback voltage FB, switch node voltage SW, and enable signal EN) to facilitate the generation of control signals.

[0027] According to some embodiments, a parasitic capacitance Cp may exist between the switch node SW and the feedback terminal FB. This parasitic capacitance may cause problems by causing the feedback voltage to drop too quickly and cause an unstable output voltage VOUT, which may be more pronounced for lower VOUT values ​​(e.g., less than 2 volts). Therefore, according to some embodiments, the controller 106 may include (or be coupled to) a timing adjustment system designed to dynamically change the minimum off-time of the high-side switching element HSD, thus giving the feedback voltage at FB more time to recover during the lower VOUT operation.

[0028] Figure 2A 1 shows a diagram of a controller 106 according to some embodiments. The controller 106 includes a pulse width modulation circuit 202, which may include a pulse control block 204 that generates PWM control signals for both the high-side driver and the low-side driver. The controller 106 also includes a timing adjustment circuit that generates a Minoff signal to control the HS PWM Minimum off time of the control signal.

[0029] The pulse control block 204 determines the on-time and duty cycle of the PWM control signal based at least in part on the state of the ONESHOT signal and the drive signal. Figure 2B An exemplary timing diagram is shown, which shows how these signals are used to generate a PWM control signal. According to some embodiments, when the drive signal pulse is high, HS PWM The signal is asserted high to turn on the high-side switching element HSD. PWM The signal will remain high until the one-shot pulse is low, at which time HS PWM The signal is asserted low to turn off the high-side switching element HSD. PWM The signal will remain low until the drive signal pulses high again, thus repeating the cycle. Thus, the drive signal controls when the high-side switching element is turned on, and the one-shot switches on by controlling the HS PWM How long LS remains high determines the duty cycle. PWM The signal is HS PWM The inversion of the signal ensures correct switching operation of the high-side and low-side switching elements.

[0030] Return to Figure 2AIn the case where the Minoff signal is asserted to be high, the feedback voltage at FB is compared with the first reference voltage (V REF1 ) to determine the state of the drive signal. Therefore, when the feedback voltage is lower than V REF1 , the drive signal will pulse high, thereby turning the high-side switch element HSD back on. According to some embodiments, the output of the comparator 208 from the feedback loop can be effectively overwritten (or otherwise neutralized) by the Minoff signal via the use of AND gate 210. In this way, as long as the Minoff signal is asserted to be low, the output of the comparator 208 will not matter and the drive signal will remain low. According to some embodiments, the output of the comparator 208 can control the state of the drive signal only when the Minoff signal is high.

[0031] According to some embodiments, the timing adjustment circuit 206 receives the switch node voltage at the terminal SW and may be LS PWM The inverted LSD signal OFF signal so that when the low-side switch element is turned off, LS PWM Low and LSD OFF Therefore, the timing adjustment circuit 206 can adjust the length of time that Minoff remains low based on the output switch voltage at terminal SW. LSD OFF The signal may be used by the timing adjustment circuit 206 to indicate the current state of the high-side and low-side switching elements so that adjustments are made to the Minoff signal during the time period when the high-side switching element HSD is turned off.

[0032] Timing adjustment circuit

[0033] Figure 3 2 shows a block diagram of the timing adjustment circuit 206 according to some embodiments. The timing adjustment circuit 206 includes a sampling block 302, an amplifier 304, a charging block 306, and a comparator 308. According to some embodiments, the sampling block 302 receives the output switch voltage at the SW terminal and filters the switch voltage to generate an average output voltage value V CSN The voltage V is received at the input terminal of the amplifier 304 (which may be an operational amplifier). CSN To generate a driving voltage V DRV According to some embodiments, the driving voltage V DRVis converted into a drive current within the charging block 306. This drive current can be used to generate a feedback voltage V1, which is also received by another input terminal of the amplifier 304. According to some embodiments, the drive current is mirrored to generate a similar current that charges the capacitor during the time when the high-side switching element is off. The voltage Vc on the capacitor can be fed to a first input of a comparator 308, while a second input of the comparator 308 receives a second reference voltage V REF2 The output of the comparator 308 is generated when the capacitor voltage Vc is less than the second reference voltage V REF2 The time period is the low Minoff signal.

[0034] Figure 4 Schematic diagram of timing adjustment circuit 206 according to an embodiment is shown. Sampling block 302 may include a voltage divider having resistors R3 and R4 together with any number of RC filters to generate a voltage V proportional to output voltage VOUT CSN Voltage V CSN V may be a DC (or nearly DC) voltage representing the average value of the voltage at the switch node terminal SW. In some embodiments, the RC filter network is a ripple filter. In some embodiments, the RC filter includes any number of low-pass filters. Due to the presence of the voltage divider, V CSN Approximately equal to VOUT / N (or at least proportional to it), where N=(R3+R4) / R4.

[0035] According to some embodiments, the amplifier 304 receives V at a first input. CSN The output of amplifier 304 is coupled to the gate terminal of first FET 402. In some embodiments, first FET 402 is an n-channel device. Therefore, the output voltage of amplifier 304 is converted into a drive current I1 that flows through the source terminal and the drain terminal of first FET 402. According to some embodiments, feedback voltage V1 can be generated from drive current I1 through resistor R5. Feedback voltage V1 can then be fed into a second input of amplifier 304. According to some embodiments, feedback voltage V1 is approximately equal to V CSN Furthermore, the drive current I1 is approximately equal to VOUT / (N*R5). In some embodiments, the amplifier 304 acts as a unity gain buffer with a gain of approximately 1.

[0036] According to some embodiments, the charging block 306 includes a current mirror 404 to generate a mirror current I2 that is approximately equal to I1. In some examples, the current mirror 404 includes a p-channel FET. According to some embodiments, the mirror current I2 charges the capacitor C during the time period when the high-side switch element HSD is turned off. Therefore, a second FET 406 can be coupled across the terminals of the capacitor C, wherein the gate of the second FET 406 is configured to receive LSD.OFF In some embodiments, the second FET 406 is an n-channel device. If the low-side switch element LSD is turned off (eg, LSD OFF is high), then the second FET 406 is turned on and the capacitor C is bypassed because the high-side switch element HSD is turned on. However, whenever the high-side switch element HSD is turned off, LSD OFF will be low, and the mirror current I2 can charge the capacitor C. It should be understood that any number of other circuits can be used to bypass the capacitor C during the period when the high-side switch element HSD is turned on. For example, the control terminal of the second FET 406 can be configured to receive HSD ON A signal may be used to indicate when the high-side switch element HSD is turned on, or a p-channel device may be used together with a corresponding control signal to indicate when the high-side switch element HSD is turned on.

[0037] According to some embodiments, a sample voltage V is generated at capacitor C due to charging from mirror current I2. C Therefore, as capacitor C charges, the sampled voltage V C The comparator 308 receives the sampled voltage V at the positive input terminal. C , and receives a second reference voltage V at the negative input terminal REF2 According to some embodiments, the output (Minoff) of comparator 308 is C Towards V REF2 The level is charged while remaining low, and at V C Beyond V REF2 As long as Minoff remains low, the high-side switch element HSD cannot be turned on, thereby setting the minimum off-time of the high-side switch element HSD. According to some embodiments, the length of time that Minoff remains low (e.g., the minimum off-time) is approximately equal to (N*R*C)*(V REF2 / VOUT). Therefore, the minimum off time changes dynamically in response to changes in VOUT. According to some embodiments, the second reference voltage V REF2 It can be a static value that affects the maximum length of time for Minoff for a given output voltage, or V REF2 The maximum level may be configurable (eg, by a user) to adjust the minimum off time for a given output voltage.

[0038] Figure 5 2 shows a timing diagram of various signals within the timing adjustment circuit 206 according to some embodiments. Until the first time T1, the high-side switching element HSD turns on and VOUT increases, causing a corresponding increase in I2. During this time, the capacitor C is due to LSD OFF is bypassed because it is high, so V CGND and Minoff is low. At time T1, the high-side switch element HSD turns off, which starts to reduce VOUT and allows capacitor C to charge. Therefore, V C Starts to increase and continues to increase until the high-side switch element HSD is turned on again. At time T2, V C Increased beyond V REF2 At time T3, the high-side switch element HSD is turned on again, thereby turning Minoff back to a lower level and V C Pull to ground.

[0039] According to some embodiments, the time between T1 and T2 is equivalent to the minimum off time of the high-side switch element HSD. During this time, the high-side switch element HSD is forced to remain off and can be turned on only when Minoff is asserted high.

[0040] Figure 6 A graph showing some exemplary values ​​of the minimum off time (Tminoff) provided by the timing adjustment circuit 206 based on different output voltages VOUT is shown. As the output voltage decreases due to a slower charging speed across the capacitor C, the minimum off time increases. Conversely, a higher voltage results in faster charging of the capacitor C and a lower minimum off time. In some embodiments, the minimum off time may not be less than a threshold value, such as approximately 50ns.

[0041] Fig. 7A Graphs of various power converter output signals are shown that highlight the problem when the timing adjustment circuit 206 is not used. The various graphs show the current output (I), DC output voltage (VOUT), and switch node voltage (SW) of the power converter. As can be seen, for high parasitic capacitance (e.g., Cp is 12F or greater), the output of the power converter becomes unstable because the high-side switch element HSD is turned back on too quickly and the feedback cannot keep up. This causes the DC output voltage to swing too much.

[0042] Figure 7B The display highlights the improved performance when the timing adjustment circuit 206 is used. Fig. 7A Same graph of various power converter output signals. Here, parasitic capacitance values ​​up to 50F are used and exhibit stable operation. The output voltage VOUT is kept stable by preventing the high-side switching element HSD from turning on too quickly during the lower VOUT operation.

[0043] Other Examples

[0044] Example 1 is a controller configured to determine the cut-off time of a switching element of a power converter circuit. The controller includes a pulse width modulation circuit and a timing adjustment circuit. The pulse width modulation circuit is designed to determine the cut-off time of the switching element based on a received feedback signal and a minimum cut-off time control signal. The received feedback signal is proportional to the voltage at the output voltage terminal of the power converter circuit. The timing adjustment circuit includes a comparator having a first and a second comparator input and a comparator output. The first comparator input is configured to receive a sampled voltage that changes based on the voltage at the output voltage terminal of the power converter circuit, and the second comparator input is configured to receive a reference voltage. The comparator output provides the minimum cut-off time control signal. The comparator is configured to adjust the minimum cut-off time control signal based on the length of time that the sampled voltage is less than the reference voltage.

[0045] Example 2 includes the controller of Example 1, wherein the timing adjustment circuit further includes a sampling block configured to generate an intermediate voltage proportional to an average value of a voltage at a switch node terminal of the power converter circuit.

[0046] Example 3 includes the controller of Example 2, wherein the comparator is a first comparator and the reference voltage is a first reference voltage, and the pulse width modulation circuit includes a second comparator having a first input configured to receive the feedback signal, a second input configured to receive a second reference voltage, and an output.

[0047] Example 4 includes the controller of Example 3, wherein the pulse width modulation circuit further includes an AND gate having a first AND gate input coupled to the output of the second comparator, a second AND gate input coupled to the output of the first comparator, and an AND gate output coupled to a pulse control block.

[0048] Example 5 includes the controller of any of Examples 2-4, wherein the sampling block comprises one or more low-pass filter stages.

[0049] Example 6 includes the controller of any of Examples 2 to 5, wherein the timing adjustment circuit further includes an amplifier configured to generate a drive current proportional to the intermediate voltage.

[0050] Example 7 includes the controller of Example 6, wherein the timing adjustment circuit further includes a current mirror arrangement configured to generate a mirror current based on the drive current.

[0051] Example 8 includes the controller of Example 7, wherein the timing adjustment circuit further includes a capacitor configured to be charged by the mirror current, and wherein a first terminal of the capacitor is coupled to both the current mirror arrangement and the first input of the comparator, and a second terminal of the capacitor is coupled to a ground terminal.

[0052] Example 9 includes the controller of Example 8, wherein the timing adjustment circuit further includes a transistor coupled across the first and second terminals of the capacitor.

[0053] Example 10 includes the controller of Example 8 or 9, wherein a charging rate of the capacitor is proportional to the voltage at the output voltage terminal.

[0054] Example 11 is an integrated circuit comprising the controller of any one of Examples 1 to 10.

[0055] Example 12 is a power converter circuit comprising the controller of any of Examples 1 to 10, a switching element, and a driver having an output coupled to a control terminal of the switching element.

[0056] Example 13 includes the power converter circuit of Example 12, wherein the timing adjustment circuit further includes a sampling block, an amplifier, a current mirror arrangement, a capacitor, and a transistor. The sampling block is configured to generate an intermediate voltage proportional to the average value of the voltage at the switch node terminal of the power converter circuit. The amplifier is configured to generate a drive current proportional to the intermediate voltage. The current mirror arrangement is configured to generate a mirror current based on the drive current. The capacitor is configured to be charged by the mirror current. The first terminal of the capacitor is coupled to both the current mirror arrangement and the first input of the comparator, and the second terminal of the capacitor is coupled to a ground terminal. The transistor is coupled across the first and second terminals of the capacitor. The transistor bypasses the capacitor during the period when the switch element is turned on, and the transistor does not bypass the capacitor during the period when the switch element is turned off.

[0057] Example 14 includes the power converter circuit of example 12 or 13, wherein the switch element is a high-side switch element and the driver is a first driver. The power converter circuit further includes a low-side switch element coupled in series with the high-side switch element, and a second driver having an output coupled to a control terminal of the low-side switch element.

[0058] Example 15 includes the power converter circuit of Example 14, wherein an on-time of the low-side switching element is substantially equal to an off-time of the high-side switching element.

[0059] Example 16 is a voltage regulator comprising: a first voltage rail; a second voltage rail; a ground rail; a first transistor coupled between the first voltage rail and a switch node terminal; a first driver coupled to a control terminal of the first transistor and configured to receive a voltage on the second voltage rail; a second transistor coupled between the switch node terminal and the ground rail; a second driver coupled to a control terminal of the second transistor; and a timing adjustment circuit. The timing adjustment circuit is configured to generate a minimum off-time control signal for dynamically adjusting a minimum off-time of the first transistor. The timing adjustment circuit includes a comparator having: a first input configured to receive a sampled voltage that changes based on a voltage at the switch node terminal; a second input configured to receive a reference voltage; and an output that provides the minimum off-time control signal. The minimum off-time control signal has a state based on a length of time that the sampled voltage is less than the reference voltage.

[0060] Example 17 includes the voltage regulator of Example 16, wherein the timing adjustment circuit further includes a sampling block configured to generate an intermediate voltage proportional to an average value of the voltage at the switch node terminal.

[0061] Example 18 includes the voltage regulator of Example 17, wherein the sampling block comprises one or more resistor-capacitor (RC) filter stages.

[0062] Example 19 includes the voltage regulator of Example 17 or 18, wherein the timing adjustment circuit further includes an amplifier configured to generate a drive current proportional to the intermediate voltage.

[0063] Example 20 includes the voltage regulator of Example 19, wherein the timing adjustment circuit further includes a current mirror circuit configured to generate a mirror current based on the drive current.

[0064] Example 21 includes the voltage regulator of Example 20, wherein the timing adjustment circuit further includes a capacitor configured to be charged by the mirror current at a first terminal, and wherein the first terminal of the capacitor is coupled to the first input of the comparator and a second terminal of the capacitor is coupled to the ground rail.

[0065] Example 22 includes the voltage regulator of Example 21, wherein the timing adjustment circuit further includes a third transistor coupled across the first terminal of the capacitor and the second terminal of the capacitor.

[0066] Example 23 includes the voltage regulator of Example 21 or 22, wherein a charging rate of the capacitor is proportional to the voltage at the switch node terminal.

[0067] Example 24 includes the voltage regulator of any of Examples 16-23, wherein an on-time of the first transistor is substantially equal to an off-time of the second transistor.

[0068] Example 25 includes the voltage regulator of any one of Examples 16 to 24, further comprising a pulse width modulation circuit configured to determine a cut-off time of the first transistor based on a received feedback signal proportional to the voltage at the switch node terminal and based on the output of the comparator, wherein the cut-off time cannot be lower than the minimum cut-off time.

[0069] Example 26 includes the voltage regulator of any of Examples 16-25, wherein the first voltage rail is an input voltage rail, the second voltage rail is a bootstrap voltage rail, the first transistor is a high-side transistor, and the second transistor is a low-side transistor.

[0070] Example 27 is a timing adjustment circuit for use in a voltage converter. The timing adjustment circuit includes: a filter circuit; an operational amplifier (op-amp) having an op-amp output and first and second op-amp inputs; a first transistor having a control terminal and first and second current terminals; a capacitor having a first terminal and a second terminal; a current mirror circuit; a second transistor coupled between the first and second terminals of the capacitor; and a comparator having a comparator output and first and second comparator inputs. The filter circuit is configured to receive a switch node terminal voltage of the voltage converter and generate a direct current (DC) voltage. The first op-amp input is configured to receive the DC voltage. The control terminal of the first transistor is coupled to the output of the operational amplifier, and the first current terminal of the first transistor is coupled to the second op-amp input. The current mirror circuit is coupled between a voltage supply terminal and the second current terminal of the first transistor, and is also coupled between the voltage supply terminal and the first terminal of the capacitor. The first comparator input is coupled to the first terminal of the capacitor, and the second comparator input is coupled to a reference voltage source. The comparator output provides a logic high in response to a voltage at the first comparator input being higher than a voltage at the second comparator input, and the comparator output provides a logic low in response to a voltage at the first comparator input being lower than the voltage at the second comparator input.

[0071] Example 28 includes the timing adjustment circuit of Example 27, wherein the DC voltage is proportional to an output voltage of the voltage converter. In one such example, the DC voltage is proportional to an average level of the switch node terminal voltage.

[0072] Example 29 includes the timing adjustment circuit of Example 27 or 28, wherein the filter circuit comprises one or more resistor-capacitor (RC) filter stages arranged in a low-pass filter configuration.

[0073] Example 30 includes the timing adjustment circuit of any of Examples 27-29, wherein the second terminal of the capacitor is coupled to a ground terminal, the timing adjustment circuit further comprising a resistor coupled between the second op-amp input and the ground terminal.

[0074] Example 31 includes the timing adjustment circuit of any of Examples 27-30, wherein the first transistor is a p-channel device and the second transistor is an n-channel device.

[0075] Example 32 includes the timing adjustment circuit of any one of Examples 27 to 31, wherein: the second transistor is turned on in response to the voltage converter being in a high-side turn-on phase, thereby bypassing the capacitor; and the second transistor is turned off in response to the voltage converter being in a low-side turn-on phase.

[0076] In this specification, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B so that device B is controlled by device A via the control signal generated by device A.

[0077] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0078] As used herein, the terms "terminal", "node", "interconnect", "pin", and "lead" may be used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnect between device elements, circuit elements, integrated circuits, devices, or semiconductor components, or their terminations. In addition, a voltage rail or more simply a "rail" may also be referred to as a voltage terminal, and may generally mean a common node or set of coupled nodes in a circuit that are at the same potential.

[0079] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0080] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively. For example, a p-channel field effect transistor (PFET) may be used instead of an n-channel field effect transistor (NFET) with little or no change to the circuit. In addition, other types of transistors (e.g., bipolar junction transistors (BJTs)) may be used. In addition, the device may be implemented in / above a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs). In addition, references to transistor features such as a gate, source, or drain are not intended to exclude any suitable transistor technology. For example, features such as a source, drain, and gate are commonly used to refer to a FET, while an emitter, collector, and base are commonly used to refer to a BJT. Such features may be used interchangeably herein. For example, a reference to the gate of a transistor may refer to the gate of a FET or the base of a BJT, and vice versa. In some instances, a control terminal may refer to the gate of a FET or the base of a BJT. Any other suitable transistor technology may be used. Any such transistor may be used as a switch, with the gate or base or other comparable feature acting as a switch select input that can be driven to connect the source and drain (or emitter and collector as the case may be).

[0081] Reference herein to a field effect transistor (FET) being "on" (or the switch being closed) means that there is a conductive channel of the FET and drain current can flow through the FET. Reference herein to a FET being "off" (or the switch being open) means that there is no conductive channel and drain current does not flow through the FET. However, an off FET may have current flowing through the body diode of the transistor.

[0082] The circuits described herein may be reconfigured to include additional or different components to provide functionality at least partially similar to functionality available before component replacement. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0083] The use of the phrase "ground" in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise specified, "about", "substantially", "approximately" or "substantially" before a parameter means within + / -10% of the parameter.

[0084] Modifications are possible in the examples described, and other examples are possible within the scope of the claims.

Claims

1. A controller configured to determine a turn-off time of a switching element of a power converter circuit, the controller include: a pulse width modulation circuit configured to determine the off-time of the switching element based on a received feedback signal and a minimum off-time control signal, wherein the received feedback signal is proportional to a voltage at an output voltage terminal of the power converter circuit; and A timing adjustment circuit comprising a comparator having first and second comparator inputs and a comparator output, wherein the first comparator input is configured to receive a sampled voltage that varies based on the voltage at the output voltage terminal of the power converter circuit, the second comparator input is configured to receive a reference voltage, and the comparator output provides the minimum off-time control signal, the comparator being configured to adjust the minimum off-time control signal based on a length of time that the sampled voltage is less than the reference voltage. 2 . The controller of claim 1 , wherein the timing adjustment circuit further comprises a sampling block configured to generate an intermediate voltage proportional to an average value of a voltage at a switch node terminal of the power converter circuit.

3. The controller of claim 2 , wherein the comparator is a first comparator and the reference voltage is a first reference voltage, and the pulse width modulation circuit comprises a second comparator having a first input configured to receive the received feedback signal, a second input configured to receive a second reference voltage, and an output.

4. The controller of claim 3 , wherein the pulse width modulation circuit further comprises an AND gate having a first AND gate input coupled to the output of the second comparator, a second AND gate input coupled to the output of the first comparator, and an AND gate output coupled to a pulse control block. 5 . The controller of claim 2 , wherein the timing adjustment circuit further comprises an amplifier configured to generate a drive current proportional to the intermediate voltage. 6 . The controller of claim 5 , wherein the timing adjustment circuit further comprises a current mirror arrangement configured to generate a mirror current based on the drive current.

7. The controller according to claim 6, wherein the timing adjustment circuit further include: a capacitor configured to be charged by the mirror current, and wherein a first terminal of the capacitor is coupled to both the current mirror arrangement and the first comparator input, and a second terminal of the capacitor is coupled to a ground terminal; as well as A transistor is coupled across the first and second terminals of the capacitor.

8. An integrated circuit comprising the controller according to claim 1.

9. A voltage regulator, include: A first voltage rail; A second voltage rail; Ground rail; a first transistor coupled between the first voltage rail and a switch node terminal; a first driver coupled to a control terminal of the first transistor and configured to receive a voltage on the second voltage rail; a second transistor coupled between the switch node terminal and the ground rail; a second driver coupled to a control terminal of the second transistor; as well as a timing adjustment circuit configured to generate a minimum off-time control signal for dynamically adjusting a minimum off-time of the first transistor, the timing adjustment circuit comprising a comparator having: a first input configured to receive a sampled voltage that changes based on a voltage at the switch node terminal; a second input configured to receive a reference voltage; and an output that provides the minimum off-time control signal, the minimum off-time control signal having a state based on a length of time that the sampled voltage is less than the reference voltage. 10 . The voltage regulator of claim 9 , wherein the timing adjustment circuit further comprises a sampling block configured to generate an intermediate voltage proportional to an average value of the voltage at the switch node terminal. 11 . The voltage regulator of claim 10 , wherein the timing adjustment circuit further comprises an amplifier configured to generate a drive current proportional to the intermediate voltage. 12 . The voltage regulator of claim 11 , wherein the timing adjustment circuit further comprises a current mirror circuit configured to generate a mirror current based on the drive current.

13. The voltage regulator of claim 12, wherein the timing adjustment circuit further comprises a capacitor configured to be charged by the mirror current at a first terminal, and wherein the first terminal of the capacitor is coupled to the first input of the comparator and a second terminal of the capacitor is coupled to the ground rail.

14. The voltage regulator of claim 13, wherein the timing adjustment circuit further comprises a third transistor coupled across the first terminal of the capacitor and the second terminal of the capacitor.

15. The voltage regulator of claim 9, wherein the first voltage rail is an input voltage rail, the second voltage rail is a bootstrap voltage rail, the first transistor is a high-side transistor, and the second transistor is a low-side transistor.

16. A timing adjustment circuit for use in a voltage converter, the timing adjustment circuit include: a filter circuit configured to receive a switch node terminal voltage of the voltage converter and generate a direct current (DC) voltage; an operational amplifier, op-amp, having an op-amp output and first and second op-amp inputs, the first op-amp input being configured to receive the DC voltage; a first transistor having a control terminal and first and second current terminals, the control terminal coupled to the op-amp output and the first current terminal coupled to the second op-amp input; a capacitor having a first terminal and a second terminal; a current mirror circuit coupled between a voltage supply terminal and the second current terminal of the first transistor and also coupled between the voltage supply terminal and the first terminal of the capacitor; a second transistor coupled between the first and second terminals of the capacitor; as well as A comparator having a comparator output and first and second comparator inputs, the first comparator input coupled to the first terminal of the capacitor and the second comparator input coupled to a reference voltage source, such that the comparator output provides a logic high in response to a voltage at the first comparator input being higher than a voltage at the second comparator input and the comparator output provides a logic low in response to a voltage at the first comparator input being lower than the voltage at the second comparator input. 17 . The timing adjustment circuit of claim 16 , wherein the DC voltage is proportional to an average level of the switch node terminal voltage.

18. The timing adjustment circuit of claim 16, wherein the filter circuit comprises one or more resistor-capacitor (RC) filter stages arranged in a low pass filter configuration.

19. The timing adjustment circuit of claim 16, wherein the second terminal of the capacitor is coupled to a ground terminal, the timing adjustment circuit further comprising a resistor coupled between the second op-amp input and the ground terminal.

20. The timing adjustment circuit according to claim 16, in: The second transistor is turned on in response to the voltage converter being in a high-side on phase, thereby bypassing the capacitor; and the second transistor is turned off in response to the voltage converter being in a low-side on phase.

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